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34 //! \addtogroup analog_group
35 //! @{
36 //! \section sec_analog Introduction
37 //!
38 //! Access to registers in the analog domain of the device goes through master modules controlling slave
39 //! modules which contain the actual registers. The master module is located in the digital domain of the
40 //! device. The interfaces between master and slave modules are called ADI (Analog-to-Digital Interface)
41 //! and DDI (Digital-to-Digital Interface) depending on the type of module to access and thus the slave
42 //! modules are referred to as ADI slave and DDI slave.
43 //!
44 //! The ADI and DDI APIs provide access to these registers:
45 //! - <a href="../register_descriptions/ANATOP_MMAP/ADI_2_REFSYS.html" target="_blank">ADI_2_REFSYS</a> : Reference System for generating reference voltages and reference currents.
46 //!   - Reference system control
47 //!   - SOC LDO control
48 //! - <a href="../register_descriptions/ANATOP_MMAP/ADI_3_REFSYS.html" target="_blank">ADI_3_REFSYS</a> : Reference System for generating reference voltages and reference currents.
49 //!   - Reference system control
50 //!   - DC/DC control
51 //! - <a href="../register_descriptions/ANATOP_MMAP/ADI_4_AUX.html" target="_blank">ADI_4_AUX</a> : Controlling analog peripherals of AUX.
52 //!   - Multiplexers
53 //!   - Current source
54 //!   - Comparators
55 //!   - ADCs
56 //! - <a href="../register_descriptions/ANATOP_MMAP/DDI_0_OSC.html" target="_blank">DDI_0_OSC</a> : Controlling the oscillators (via AUX domain)
57 //!
58 //! The register descriptions of CPU memory map document the ADI/DDI masters. The register descriptions of
59 //! analog memory map document the ADI/DDI slaves. The ADI/DDI APIs allow the programmer to focus on the
60 //! slave registers of interest without being concerned with the ADI/DDI master part of the interface.
61 //!
62 //! Although the ADI/DDI APIs make the master "transparent" it can be useful to know a few details about
63 //! the ADI/DDI protocol and how the master handles transactions as it can affect how the system CPU performs.
64 //! - ADI protocol uses 8-bit write bus compared to 32-bit write bus in DDI. ADI protocol uses 4-bit read
65 //!   bus compared to 16-bit read bus in DDI. Hence a 32-bit read from an ADI register is translated into 8
66 //!   transactions in the ADI protocol.
67 //! - One transaction on the ADI/DDI protocol takes several clock cycles for the master to complete.
68 //! - ADI slave registers are 8-bit wide.
69 //! - DDI slave registers are 32-bit wide.
70 //! - ADI/DDI master supports multiple data width accesses seen from the system CPU
71 //!   (however, not all bit width accesses are supported by the APIs):
72 //!   - Read: 8, 16, 32-bit
73 //!   - Write
74 //!     - Direct (write, set, clear): 8, 16, 32-bit
75 //!     - Masked: 4, 8, 16-bit
76 //!
77 //! Making posted/buffered writes from the system CPU (default) to the ADI/DDI allows the system CPU to continue
78 //! while the ADI/DDI master handles the transactions on the ADI/DDI protocol. If using non-posted/non-buffered
79 //! writes the system CPU will wait for ADI/DDI master to complete the transactions to the slave before continuing
80 //! execution.
81 //!
82 //! Reading from ADI/DDI requires that all transactions on the ADI/DDI protocol have completed before the system CPU
83 //! receives the response thus the programmer must understand that the response time depends on the number of bytes
84 //! read. However, due to the 'set', 'clear' and 'masked write' features of the ADI/DDI most writes can be done
85 //! without the typical read-modify-write sequence thus reducing the need for reads to a minimum.
86 //!
87 //! Consequently, if making posted/buffered writes then the written value will not take effect in the
88 //! analog domain until some point later in time. An alternative to non-posted/non-buffered writes - in order to make
89 //! sure a written value has taken effect - is to read from the same ADI/DDI as the write as this will keep the system CPU
90 //! waiting until both the write and the read have completed.
91 //!
92 //! \note
93 //! Do NOT use masked write when writing bit fields spanning the "masked write boundary" i.e. the widest possible
94 //! masked write that the protocol supports (ADI = 4 bits, DDI = 16 bits). This will put the device into a
95 //! temporary state - which is potentially harmful to the device - as the bit field will be written over two transactions.
96 //! Thus to use masked writes:
97 //! - For ADI the bit field(s) must be within bit 0 to 3 (REG[3:0]) or bit 4 to 7 (REG[7:4]).
98 //! - For DDI the bit field(s) must be within bit 0 to 15 (REG[15:0]) or bit 16 to 31 (REG[31:16]).
99 //!
100 //! \note
101 //! If masked write is not allowed, a regular read-modify-write is necessary.
102 //!
103 //! @}
104