1 /****************************************************************************** 2 * Filename: hw_udma_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_UDMA_H__ 38 #define __HW_UDMA_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // UDMA component 44 // 45 //***************************************************************************** 46 // Status 47 #define UDMA_O_STATUS 0x00000000 48 49 // Configuration 50 #define UDMA_O_CFG 0x00000004 51 52 // Channel Control Data Base Pointer 53 #define UDMA_O_CTRL 0x00000008 54 55 // Channel Alternate Control Data Base Pointer 56 #define UDMA_O_ALTCTRL 0x0000000C 57 58 // Channel Wait On Request Status 59 #define UDMA_O_WAITONREQ 0x00000010 60 61 // Channel Software Request 62 #define UDMA_O_SOFTREQ 0x00000014 63 64 // Channel Set UseBurst 65 #define UDMA_O_SETBURST 0x00000018 66 67 // Channel Clear UseBurst 68 #define UDMA_O_CLEARBURST 0x0000001C 69 70 // Channel Set Request Mask 71 #define UDMA_O_SETREQMASK 0x00000020 72 73 // Clear Channel Request Mask 74 #define UDMA_O_CLEARREQMASK 0x00000024 75 76 // Set Channel Enable 77 #define UDMA_O_SETCHANNELEN 0x00000028 78 79 // Clear Channel Enable 80 #define UDMA_O_CLEARCHANNELEN 0x0000002C 81 82 // Channel Set Primary-Alternate 83 #define UDMA_O_SETCHNLPRIALT 0x00000030 84 85 // Channel Clear Primary-Alternate 86 #define UDMA_O_CLEARCHNLPRIALT 0x00000034 87 88 // Set Channel Priority 89 #define UDMA_O_SETCHNLPRIORITY 0x00000038 90 91 // Clear Channel Priority 92 #define UDMA_O_CLEARCHNLPRIORITY 0x0000003C 93 94 // Error Status and Clear 95 #define UDMA_O_ERROR 0x0000004C 96 97 // Channel Request Done 98 #define UDMA_O_REQDONE 0x00000504 99 100 // Channel Request Done Mask 101 #define UDMA_O_DONEMASK 0x00000520 102 103 //***************************************************************************** 104 // 105 // Register: UDMA_O_STATUS 106 // 107 //***************************************************************************** 108 // Field: [31:28] TEST 109 // 110 // 111 // 0x0: Controller does not include the integration test logic 112 // 0x1: Controller includes the integration test logic 113 // 0x2: Undefined 114 // ... 115 // 0xF: Undefined 116 #define UDMA_STATUS_TEST_W 4 117 #define UDMA_STATUS_TEST_M 0xF0000000 118 #define UDMA_STATUS_TEST_S 28 119 120 // Field: [20:16] TOTALCHANNELS 121 // 122 // Register value returns number of available uDMA channels minus one. For 123 // example a read out value of: 124 // 125 // 0x00: Show that the controller is configured to use 1 uDMA channel 126 // 0x01: Shows that the controller is configured to use 2 uDMA channels 127 // ... 128 // 0x1F: Shows that the controller is configured to use 32 uDMA channels 129 // (32-1=31=0x1F) 130 #define UDMA_STATUS_TOTALCHANNELS_W 5 131 #define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 132 #define UDMA_STATUS_TOTALCHANNELS_S 16 133 134 // Field: [7:4] STATE 135 // 136 // Current state of the control state machine. State can be one of the 137 // following: 138 // 139 // 0x0: Idle 140 // 0x1: Reading channel controller data 141 // 0x2: Reading source data end pointer 142 // 0x3: Reading destination data end pointer 143 // 0x4: Reading source data 144 // 0x5: Writing destination data 145 // 0x6: Waiting for uDMA request to clear 146 // 0x7: Writing channel controller data 147 // 0x8: Stalled 148 // 0x9: Done 149 // 0xA: Peripheral scatter-gather transition 150 // 0xB: Undefined 151 // ... 152 // 0xF: Undefined. 153 #define UDMA_STATUS_STATE_W 4 154 #define UDMA_STATUS_STATE_M 0x000000F0 155 #define UDMA_STATUS_STATE_S 4 156 157 // Field: [0] MASTERENABLE 158 // 159 // Shows the enable status of the controller as configured by CFG.MASTERENABLE: 160 // 161 // 0: Controller is disabled 162 // 1: Controller is enabled 163 #define UDMA_STATUS_MASTERENABLE 0x00000001 164 #define UDMA_STATUS_MASTERENABLE_BITN 0 165 #define UDMA_STATUS_MASTERENABLE_M 0x00000001 166 #define UDMA_STATUS_MASTERENABLE_S 0 167 168 //***************************************************************************** 169 // 170 // Register: UDMA_O_CFG 171 // 172 //***************************************************************************** 173 // Field: [7:5] PRTOCTRL 174 // 175 // Sets the AHB-Lite bus protocol protection state by controlling the AHB 176 // signal HProt[3:1] as follows: 177 // 178 // Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. 179 // Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. 180 // Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. 181 // 182 // When bit [n] = 1 then the corresponding HProt bit is high. 183 // When bit [n] = 0 then the corresponding HProt bit is low. 184 // 185 // This field controls HProt[3:1] signal for all transactions initiated by uDMA 186 // except two transactions below: 187 // - the read from the address indicated by source address pointer 188 // - the write to the address indicated by destination address pointer 189 // HProt[3:1] for these two exceptions can be controlled by dedicated fields in 190 // the channel configutation descriptor. 191 #define UDMA_CFG_PRTOCTRL_W 3 192 #define UDMA_CFG_PRTOCTRL_M 0x000000E0 193 #define UDMA_CFG_PRTOCTRL_S 5 194 195 // Field: [0] MASTERENABLE 196 // 197 // Enables the controller: 198 // 199 // 0: Disables the controller 200 // 1: Enables the controller 201 #define UDMA_CFG_MASTERENABLE 0x00000001 202 #define UDMA_CFG_MASTERENABLE_BITN 0 203 #define UDMA_CFG_MASTERENABLE_M 0x00000001 204 #define UDMA_CFG_MASTERENABLE_S 0 205 206 //***************************************************************************** 207 // 208 // Register: UDMA_O_CTRL 209 // 210 //***************************************************************************** 211 // Field: [31:10] BASEPTR 212 // 213 // This register point to the base address for the primary data structures of 214 // each DMA channel. This is not stored in module, but in system memory, thus 215 // space must be allocated for this usage when DMA is in usage 216 #define UDMA_CTRL_BASEPTR_W 22 217 #define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 218 #define UDMA_CTRL_BASEPTR_S 10 219 220 //***************************************************************************** 221 // 222 // Register: UDMA_O_ALTCTRL 223 // 224 //***************************************************************************** 225 // Field: [31:0] BASEPTR 226 // 227 // This register shows the base address for the alternate data structures and 228 // is calculated by module, thus read only 229 #define UDMA_ALTCTRL_BASEPTR_W 32 230 #define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF 231 #define UDMA_ALTCTRL_BASEPTR_S 0 232 233 //***************************************************************************** 234 // 235 // Register: UDMA_O_WAITONREQ 236 // 237 //***************************************************************************** 238 // Field: [31:0] CHNLSTATUS 239 // 240 // Channel wait on request status: 241 // 242 // Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, 243 // this channel may come out of active state even if request is still present. 244 // Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it 245 // keeps channel Ch in active state until the requests are deasserted. This 246 // handshake is necessary for channels where the requester is in an 247 // asynchronous domain or can run at slower clock speed than uDMA 248 #define UDMA_WAITONREQ_CHNLSTATUS_W 32 249 #define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF 250 #define UDMA_WAITONREQ_CHNLSTATUS_S 0 251 252 //***************************************************************************** 253 // 254 // Register: UDMA_O_SOFTREQ 255 // 256 //***************************************************************************** 257 // Field: [31:0] CHNLS 258 // 259 // Set the appropriate bit to generate a software uDMA request on the 260 // corresponding uDMA channel 261 // 262 // Bit [Ch] = 0: Does not create a uDMA request for channel Ch 263 // Bit [Ch] = 1: Creates a uDMA request for channel Ch 264 // 265 // Writing to a bit where a uDMA channel is not implemented does not create a 266 // uDMA request for that channel 267 #define UDMA_SOFTREQ_CHNLS_W 32 268 #define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF 269 #define UDMA_SOFTREQ_CHNLS_S 0 270 271 //***************************************************************************** 272 // 273 // Register: UDMA_O_SETBURST 274 // 275 //***************************************************************************** 276 // Field: [31:0] CHNLS 277 // 278 // Returns the useburst status, or disables individual channels from generating 279 // single uDMA requests. The value R is the arbitration rate and stored in the 280 // controller data structure. 281 // 282 // Read as: 283 // 284 // Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on 285 // channel C. The controller performs 2^R, or single, bus transfers. 286 // 287 // Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. 288 // The controller only responds to burst transfer requests and performs 2^R 289 // transfers. 290 // 291 // Write as: 292 // Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. 293 // Bit [Ch] = 1: Disables single transfer requests on channel Ch. The 294 // controller performs 2^R transfers for burst requests. 295 // 296 // Writing to a bit where a uDMA channel is not implemented has no effect 297 #define UDMA_SETBURST_CHNLS_W 32 298 #define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF 299 #define UDMA_SETBURST_CHNLS_S 0 300 301 //***************************************************************************** 302 // 303 // Register: UDMA_O_CLEARBURST 304 // 305 //***************************************************************************** 306 // Field: [31:0] CHNLS 307 // 308 // Set the appropriate bit to enable single transfer requests. 309 // 310 // Write as: 311 // 312 // Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer 313 // requests. 314 // 315 // Bit [Ch] = 1: Enables single transfer requests on channel Ch. 316 // 317 // Writing to a bit where a DMA channel is not implemented has no effect. 318 #define UDMA_CLEARBURST_CHNLS_W 32 319 #define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF 320 #define UDMA_CLEARBURST_CHNLS_S 0 321 322 //***************************************************************************** 323 // 324 // Register: UDMA_O_SETREQMASK 325 // 326 //***************************************************************************** 327 // Field: [31:0] CHNLS 328 // 329 // Returns the burst and single request mask status, or disables the 330 // corresponding channel from generating uDMA requests. 331 // 332 // Read as: 333 // Bit [Ch] = 0: External requests are enabled for channel Ch. 334 // Bit [Ch] = 1: External requests are disabled for channel Ch. 335 // 336 // Write as: 337 // Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. 338 // Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single 339 // request channel [C] input from generating uDMA requests. 340 // 341 // Writing to a bit where a uDMA channel is not implemented has no effect 342 #define UDMA_SETREQMASK_CHNLS_W 32 343 #define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF 344 #define UDMA_SETREQMASK_CHNLS_S 0 345 346 //***************************************************************************** 347 // 348 // Register: UDMA_O_CLEARREQMASK 349 // 350 //***************************************************************************** 351 // Field: [31:0] CHNLS 352 // 353 // Set the appropriate bit to enable DMA request for the channel. 354 // 355 // Write as: 356 // Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from 357 // generating requests. 358 // Bit [Ch] = 1: Enables channel [C] to generate DMA requests. 359 // 360 // Writing to a bit where a DMA channel is not implemented has no effect. 361 #define UDMA_CLEARREQMASK_CHNLS_W 32 362 #define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF 363 #define UDMA_CLEARREQMASK_CHNLS_S 0 364 365 //***************************************************************************** 366 // 367 // Register: UDMA_O_SETCHANNELEN 368 // 369 //***************************************************************************** 370 // Field: [31:0] CHNLS 371 // 372 // Returns the enable status of the channels, or enables the corresponding 373 // channels. 374 // 375 // Read as: 376 // Bit [Ch] = 0: Channel Ch is disabled. 377 // Bit [Ch] = 1: Channel Ch is enabled. 378 // 379 // Write as: 380 // Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel 381 // Bit [Ch] = 1: Enables channel Ch 382 // 383 // Writing to a bit where a DMA channel is not implemented has no effect 384 #define UDMA_SETCHANNELEN_CHNLS_W 32 385 #define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF 386 #define UDMA_SETCHANNELEN_CHNLS_S 0 387 388 //***************************************************************************** 389 // 390 // Register: UDMA_O_CLEARCHANNELEN 391 // 392 //***************************************************************************** 393 // Field: [31:0] CHNLS 394 // 395 // Set the appropriate bit to disable the corresponding uDMA channel. 396 // 397 // Write as: 398 // Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. 399 // Bit [Ch] = 1: Disables channel Ch 400 // 401 // Writing to a bit where a uDMA channel is not implemented has no effect 402 #define UDMA_CLEARCHANNELEN_CHNLS_W 32 403 #define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF 404 #define UDMA_CLEARCHANNELEN_CHNLS_S 0 405 406 //***************************************************************************** 407 // 408 // Register: UDMA_O_SETCHNLPRIALT 409 // 410 //***************************************************************************** 411 // Field: [31:0] CHNLS 412 // 413 // Returns the channel control data structure status, or selects the alternate 414 // data structure for the corresponding uDMA channel. 415 // 416 // Read as: 417 // Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. 418 // Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. 419 // 420 // Write as: 421 // Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel 422 // Bit [Ch] = 1: Selects the alternate data structure for channel Ch 423 // 424 // Writing to a bit where a uDMA channel is not implemented has no effect 425 #define UDMA_SETCHNLPRIALT_CHNLS_W 32 426 #define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF 427 #define UDMA_SETCHNLPRIALT_CHNLS_S 0 428 429 //***************************************************************************** 430 // 431 // Register: UDMA_O_CLEARCHNLPRIALT 432 // 433 //***************************************************************************** 434 // Field: [31:0] CHNLS 435 // 436 // Clears the appropriate bit to select the primary data structure for the 437 // corresponding uDMA channel. 438 // 439 // Write as: 440 // Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate 441 // data structure. 442 // Bit [Ch] = 1: Selects the primary data structure for channel Ch. 443 // 444 // Writing to a bit where a uDMA channel is not implemented has no effect 445 #define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 446 #define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF 447 #define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 448 449 //***************************************************************************** 450 // 451 // Register: UDMA_O_SETCHNLPRIORITY 452 // 453 //***************************************************************************** 454 // Field: [31:0] CHNLS 455 // 456 // Returns the channel priority mask status, or sets the channel priority to 457 // high. 458 // 459 // Read as: 460 // Bit [Ch] = 0: uDMA channel Ch is using the default priority level. 461 // Bit [Ch] = 1: uDMA channel Ch is using a high priority level. 462 // 463 // Write as: 464 // Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch 465 // to the default priority level. 466 // Bit [Ch] = 1: Channel Ch uses the high priority level. 467 // 468 // Writing to a bit where a uDMA channel is not implemented has no effect 469 #define UDMA_SETCHNLPRIORITY_CHNLS_W 32 470 #define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF 471 #define UDMA_SETCHNLPRIORITY_CHNLS_S 0 472 473 //***************************************************************************** 474 // 475 // Register: UDMA_O_CLEARCHNLPRIORITY 476 // 477 //***************************************************************************** 478 // Field: [31:0] CHNLS 479 // 480 // Clear the appropriate bit to select the default priority level for the 481 // specified uDMA channel. 482 // 483 // Write as: 484 // Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to 485 // the high priority level. 486 // Bit [Ch] = 1: Channel Ch uses the default priority level. 487 // 488 // Writing to a bit where a uDMA channel is not implemented has no effect 489 #define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 490 #define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF 491 #define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 492 493 //***************************************************************************** 494 // 495 // Register: UDMA_O_ERROR 496 // 497 //***************************************************************************** 498 // Field: [0] STATUS 499 // 500 // Returns the status of bus error flag in uDMA, or clears this bit 501 // 502 // Read as: 503 // 504 // 0: No bus error detected 505 // 1: Bus error detected 506 // 507 // Write as: 508 // 509 // 0: No effect, status of bus error flag is unchanged. 510 // 1: Clears the bus error flag. 511 #define UDMA_ERROR_STATUS 0x00000001 512 #define UDMA_ERROR_STATUS_BITN 0 513 #define UDMA_ERROR_STATUS_M 0x00000001 514 #define UDMA_ERROR_STATUS_S 0 515 516 //***************************************************************************** 517 // 518 // Register: UDMA_O_REQDONE 519 // 520 //***************************************************************************** 521 // Field: [31:0] CHNLS 522 // 523 // Reflects the uDMA done status for the given channel, channel [Ch]. It's a 524 // sticky done bit. Unless cleared by writing a 1, it holds the value of 1. 525 // 526 // Read as: 527 // Bit [Ch] = 0: Request has not completed for channel Ch 528 // Bit [Ch] = 1: Request has completed for the channel Ch 529 // 530 // Writing a 1 to individual bits would clear the corresponding bit. 531 // 532 // Write as: 533 // Bit [Ch] = 0: No effect. 534 // Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 535 #define UDMA_REQDONE_CHNLS_W 32 536 #define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF 537 #define UDMA_REQDONE_CHNLS_S 0 538 539 //***************************************************************************** 540 // 541 // Register: UDMA_O_DONEMASK 542 // 543 //***************************************************************************** 544 // Field: [31:0] CHNLS 545 // 546 // Controls the propagation of the uDMA done and active state to the assigned 547 // peripheral. Specifically used for software channels. 548 // 549 // Read as: 550 // Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from 551 // reaching to the peripherals. 552 // Note that the uDMA done state for channel [Ch] is blocked from contributing 553 // to generation of combined uDMA done signal 554 // 555 // Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from 556 // reaching to the peripherals. 557 // Note that the uDMA done state for channel [Ch] is not blocked from 558 // contributing to generation of combined uDMA done signal 559 // 560 // Write as: 561 // Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the 562 // peripherals. 563 // Note that this disables uDMA done state for channel [Ch] from contributing 564 // to generation of combined uDMA done signal 565 // 566 // Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the 567 // peripherals. 568 // Note that this enables uDMA done for channel [Ch] to contribute to 569 // generation of combined uDMA done signal. 570 #define UDMA_DONEMASK_CHNLS_W 32 571 #define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF 572 #define UDMA_DONEMASK_CHNLS_S 0 573 574 575 #endif // __UDMA__ 576
