1 /****************************************************************************** 2 * Filename: hw_uart_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_UART_H__ 38 #define __HW_UART_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // UART component 44 // 45 //***************************************************************************** 46 // Data 47 #define UART_O_DR 0x00000000 48 49 // Status 50 #define UART_O_RSR 0x00000004 51 52 // Error Clear 53 #define UART_O_ECR 0x00000004 54 55 // Flag 56 #define UART_O_FR 0x00000018 57 58 // Integer Baud-Rate Divisor 59 #define UART_O_IBRD 0x00000024 60 61 // Fractional Baud-Rate Divisor 62 #define UART_O_FBRD 0x00000028 63 64 // Line Control 65 #define UART_O_LCRH 0x0000002C 66 67 // Control 68 #define UART_O_CTL 0x00000030 69 70 // Interrupt FIFO Level Select 71 #define UART_O_IFLS 0x00000034 72 73 // Interrupt Mask Set/Clear 74 #define UART_O_IMSC 0x00000038 75 76 // Raw Interrupt Status 77 #define UART_O_RIS 0x0000003C 78 79 // Masked Interrupt Status 80 #define UART_O_MIS 0x00000040 81 82 // Interrupt Clear 83 #define UART_O_ICR 0x00000044 84 85 // DMA Control 86 #define UART_O_DMACTL 0x00000048 87 88 //***************************************************************************** 89 // 90 // Register: UART_O_DR 91 // 92 //***************************************************************************** 93 // Field: [11] OE 94 // 95 // UART Overrun Error: 96 // This bit is set to 1 if data is received and the receive FIFO is already 97 // full. The FIFO contents remain valid because no more data is written when 98 // the FIFO is full, , only the contents of the shift register are overwritten. 99 // This is cleared to 0 once there is an empty space in the FIFO and a new 100 // character can be written to it. 101 #define UART_DR_OE 0x00000800 102 #define UART_DR_OE_BITN 11 103 #define UART_DR_OE_M 0x00000800 104 #define UART_DR_OE_S 11 105 106 // Field: [10] BE 107 // 108 // UART Break Error: 109 // This bit is set to 1 if a break condition was detected, indicating that the 110 // received data input (UARTRXD input pin) was held LOW for longer than a 111 // full-word transmission time (defined as start, data, parity and stop bits). 112 // In FIFO mode, this error is associated with the character at the top of the 113 // FIFO (that is., the oldest received data character since last read). When a 114 // break occurs, a 0 character is loaded into the FIFO. The next character is 115 // enabled after the receive data input (UARTRXD input pin) goes to a 1 116 // (marking state), and the next valid start bit is received. 117 #define UART_DR_BE 0x00000400 118 #define UART_DR_BE_BITN 10 119 #define UART_DR_BE_M 0x00000400 120 #define UART_DR_BE_S 10 121 122 // Field: [9] PE 123 // 124 // UART Parity Error: 125 // When set to 1, it indicates that the parity of the received data character 126 // does not match the parity that the LCRH.EPS and LCRH.SPS select. 127 // In FIFO mode, this error is associated with the character at the top of the 128 // FIFO (that is, the oldest received data character since last read). 129 #define UART_DR_PE 0x00000200 130 #define UART_DR_PE_BITN 9 131 #define UART_DR_PE_M 0x00000200 132 #define UART_DR_PE_S 9 133 134 // Field: [8] FE 135 // 136 // UART Framing Error: 137 // When set to 1, it indicates that the received character did not have a valid 138 // stop bit (a valid stop bit is 1). 139 // In FIFO mode, this error is associated with the character at the top of the 140 // FIFO (that is., the oldest received data character since last read). 141 #define UART_DR_FE 0x00000100 142 #define UART_DR_FE_BITN 8 143 #define UART_DR_FE_M 0x00000100 144 #define UART_DR_FE_S 8 145 146 // Field: [7:0] DATA 147 // 148 // Data transmitted or received: 149 // On writes, the transmit data character is pushed into the FIFO. 150 // On reads, the oldest received data character since the last read is 151 // returned. 152 #define UART_DR_DATA_W 8 153 #define UART_DR_DATA_M 0x000000FF 154 #define UART_DR_DATA_S 0 155 156 //***************************************************************************** 157 // 158 // Register: UART_O_RSR 159 // 160 //***************************************************************************** 161 // Field: [3] OE 162 // 163 // UART Overrun Error: 164 // This bit is set to 1 if data is received and the receive FIFO is already 165 // full. The FIFO contents remain valid because no more data is written when 166 // the FIFO is full, , only the contents of the shift register are overwritten. 167 // This is cleared to 0 once there is an empty space in the FIFO and a new 168 // character can be written to it. 169 #define UART_RSR_OE 0x00000008 170 #define UART_RSR_OE_BITN 3 171 #define UART_RSR_OE_M 0x00000008 172 #define UART_RSR_OE_S 3 173 174 // Field: [2] BE 175 // 176 // UART Break Error: 177 // This bit is set to 1 if a break condition was detected, indicating that the 178 // received data input (UARTRXD input pin) was held LOW for longer than a 179 // full-word transmission time (defined as start, data, parity and stop bits). 180 // When a break occurs, a 0 character is loaded into the FIFO. The next 181 // character is enabled after the receive data input (UARTRXD input pin) goes 182 // to a 1 (marking state), and the next valid start bit is received. 183 #define UART_RSR_BE 0x00000004 184 #define UART_RSR_BE_BITN 2 185 #define UART_RSR_BE_M 0x00000004 186 #define UART_RSR_BE_S 2 187 188 // Field: [1] PE 189 // 190 // UART Parity Error: 191 // When set to 1, it indicates that the parity of the received data character 192 // does not match the parity that the LCRH.EPS and LCRH.SPS select. 193 #define UART_RSR_PE 0x00000002 194 #define UART_RSR_PE_BITN 1 195 #define UART_RSR_PE_M 0x00000002 196 #define UART_RSR_PE_S 1 197 198 // Field: [0] FE 199 // 200 // UART Framing Error: 201 // When set to 1, it indicates that the received character did not have a valid 202 // stop bit (a valid stop bit is 1). 203 #define UART_RSR_FE 0x00000001 204 #define UART_RSR_FE_BITN 0 205 #define UART_RSR_FE_M 0x00000001 206 #define UART_RSR_FE_S 0 207 208 //***************************************************************************** 209 // 210 // Register: UART_O_ECR 211 // 212 //***************************************************************************** 213 // Field: [3] OE 214 // 215 // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are 216 // cleared to 0 by any write to this register. 217 #define UART_ECR_OE 0x00000008 218 #define UART_ECR_OE_BITN 3 219 #define UART_ECR_OE_M 0x00000008 220 #define UART_ECR_OE_S 3 221 222 // Field: [2] BE 223 // 224 // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are 225 // cleared to 0 by any write to this register. 226 #define UART_ECR_BE 0x00000004 227 #define UART_ECR_BE_BITN 2 228 #define UART_ECR_BE_M 0x00000004 229 #define UART_ECR_BE_S 2 230 231 // Field: [1] PE 232 // 233 // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are 234 // cleared to 0 by any write to this register. 235 #define UART_ECR_PE 0x00000002 236 #define UART_ECR_PE_BITN 1 237 #define UART_ECR_PE_M 0x00000002 238 #define UART_ECR_PE_S 1 239 240 // Field: [0] FE 241 // 242 // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are 243 // cleared to 0 by any write to this register. 244 #define UART_ECR_FE 0x00000001 245 #define UART_ECR_FE_BITN 0 246 #define UART_ECR_FE_M 0x00000001 247 #define UART_ECR_FE_S 0 248 249 //***************************************************************************** 250 // 251 // Register: UART_O_FR 252 // 253 //***************************************************************************** 254 // Field: [7] TXFE 255 // 256 // UART Transmit FIFO Empty: 257 // The meaning of this bit depends on the state of LCRH.FEN . 258 // - If the FIFO is disabled, this bit is set when the transmit holding 259 // register is empty. 260 // - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. 261 // This bit does not indicate if there is data in the transmit shift register. 262 #define UART_FR_TXFE 0x00000080 263 #define UART_FR_TXFE_BITN 7 264 #define UART_FR_TXFE_M 0x00000080 265 #define UART_FR_TXFE_S 7 266 267 // Field: [6] RXFF 268 // 269 // UART Receive FIFO Full: 270 // The meaning of this bit depends on the state of LCRH.FEN. 271 // - If the FIFO is disabled, this bit is set when the receive holding 272 // register is full. 273 // - If the FIFO is enabled, this bit is set when the receive FIFO is full. 274 #define UART_FR_RXFF 0x00000040 275 #define UART_FR_RXFF_BITN 6 276 #define UART_FR_RXFF_M 0x00000040 277 #define UART_FR_RXFF_S 6 278 279 // Field: [5] TXFF 280 // 281 // UART Transmit FIFO Full: 282 // Transmit FIFO full. The meaning of this bit depends on the state of 283 // LCRH.FEN. 284 // - If the FIFO is disabled, this bit is set when the transmit holding 285 // register is full. 286 // - If the FIFO is enabled, this bit is set when the transmit FIFO is full. 287 #define UART_FR_TXFF 0x00000020 288 #define UART_FR_TXFF_BITN 5 289 #define UART_FR_TXFF_M 0x00000020 290 #define UART_FR_TXFF_S 5 291 292 // Field: [4] RXFE 293 // 294 // UART Receive FIFO Empty: 295 // Receive FIFO empty. The meaning of this bit depends on the state of 296 // LCRH.FEN. 297 // - If the FIFO is disabled, this bit is set when the receive holding 298 // register is empty. 299 // - If the FIFO is enabled, this bit is set when the receive FIFO is empty. 300 #define UART_FR_RXFE 0x00000010 301 #define UART_FR_RXFE_BITN 4 302 #define UART_FR_RXFE_M 0x00000010 303 #define UART_FR_RXFE_S 4 304 305 // Field: [3] BUSY 306 // 307 // UART Busy: 308 // If this bit is set to 1, the UART is busy transmitting data. This bit 309 // remains set until the complete byte, including all the stop bits, has been 310 // sent from the shift register. 311 // This bit is set as soon as the transmit FIFO becomes non-empty, regardless 312 // of whether the UART is enabled or not. 313 #define UART_FR_BUSY 0x00000008 314 #define UART_FR_BUSY_BITN 3 315 #define UART_FR_BUSY_M 0x00000008 316 #define UART_FR_BUSY_S 3 317 318 // Field: [0] CTS 319 // 320 // Clear To Send: 321 // This bit is the complement of the active-low UART CTS input pin. 322 // That is, the bit is 1 when CTS input pin is LOW. 323 #define UART_FR_CTS 0x00000001 324 #define UART_FR_CTS_BITN 0 325 #define UART_FR_CTS_M 0x00000001 326 #define UART_FR_CTS_S 0 327 328 //***************************************************************************** 329 // 330 // Register: UART_O_IBRD 331 // 332 //***************************************************************************** 333 // Field: [15:0] DIVINT 334 // 335 // The integer baud rate divisor: 336 // The baud rate divisor is calculated using the formula below: 337 // Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) 338 // Baud rate divisor must be minimum 1 and maximum 65535. 339 // That is, DIVINT=0 does not give a valid baud rate. 340 // Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be 341 // illegal. 342 // A valid value must be written to this field before the UART can be used for 343 // RX or TX operations. 344 #define UART_IBRD_DIVINT_W 16 345 #define UART_IBRD_DIVINT_M 0x0000FFFF 346 #define UART_IBRD_DIVINT_S 0 347 348 //***************************************************************************** 349 // 350 // Register: UART_O_FBRD 351 // 352 //***************************************************************************** 353 // Field: [5:0] DIVFRAC 354 // 355 // Fractional Baud-Rate Divisor: 356 // The baud rate divisor is calculated using the formula below: 357 // Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) 358 // Baud rate divisor must be minimum 1 and maximum 65535. 359 // That is, IBRD.DIVINT=0 does not give a valid baud rate. 360 // Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be 361 // illegal. 362 // A valid value must be written to this field before the UART can be used for 363 // RX or TX operations. 364 #define UART_FBRD_DIVFRAC_W 6 365 #define UART_FBRD_DIVFRAC_M 0x0000003F 366 #define UART_FBRD_DIVFRAC_S 0 367 368 //***************************************************************************** 369 // 370 // Register: UART_O_LCRH 371 // 372 //***************************************************************************** 373 // Field: [7] SPS 374 // 375 // UART Stick Parity Select: 376 // 377 // 0: Stick parity is disabled 378 // 1: The parity bit is transmitted and checked as invert of EPS field (i.e. 379 // the parity bit is transmitted and checked as 1 when EPS = 0). 380 // 381 // This bit has no effect when PEN disables parity checking and generation. 382 #define UART_LCRH_SPS 0x00000080 383 #define UART_LCRH_SPS_BITN 7 384 #define UART_LCRH_SPS_M 0x00000080 385 #define UART_LCRH_SPS_S 7 386 387 // Field: [6:5] WLEN 388 // 389 // UART Word Length: 390 // These bits indicate the number of data bits transmitted or received in a 391 // frame. 392 // ENUMs: 393 // 8 Word Length 8 bits 394 // 7 Word Length 7 bits 395 // 6 Word Length 6 bits 396 // 5 Word Length 5 bits 397 #define UART_LCRH_WLEN_W 2 398 #define UART_LCRH_WLEN_M 0x00000060 399 #define UART_LCRH_WLEN_S 5 400 #define UART_LCRH_WLEN_8 0x00000060 401 #define UART_LCRH_WLEN_7 0x00000040 402 #define UART_LCRH_WLEN_6 0x00000020 403 #define UART_LCRH_WLEN_5 0x00000000 404 405 // Field: [4] FEN 406 // 407 // UART Enable FIFOs 408 // ENUMs: 409 // EN Transmit and receive FIFO buffers are enabled 410 // (FIFO mode) 411 // DIS FIFOs are disabled (character mode) that is, the 412 // FIFOs become 1-byte-deep holding registers. 413 #define UART_LCRH_FEN 0x00000010 414 #define UART_LCRH_FEN_BITN 4 415 #define UART_LCRH_FEN_M 0x00000010 416 #define UART_LCRH_FEN_S 4 417 #define UART_LCRH_FEN_EN 0x00000010 418 #define UART_LCRH_FEN_DIS 0x00000000 419 420 // Field: [3] STP2 421 // 422 // UART Two Stop Bits Select: 423 // If this bit is set to 1, two stop bits are transmitted at the end of the 424 // frame. The receive logic does not check for two stop bits being received. 425 #define UART_LCRH_STP2 0x00000008 426 #define UART_LCRH_STP2_BITN 3 427 #define UART_LCRH_STP2_M 0x00000008 428 #define UART_LCRH_STP2_S 3 429 430 // Field: [2] EPS 431 // 432 // UART Even Parity Select 433 // ENUMs: 434 // EVEN Even parity: The UART generates or checks for an 435 // even number of 1s in the data and parity bits. 436 // ODD Odd parity: The UART generates or checks for an 437 // odd number of 1s in the data and parity bits. 438 #define UART_LCRH_EPS 0x00000004 439 #define UART_LCRH_EPS_BITN 2 440 #define UART_LCRH_EPS_M 0x00000004 441 #define UART_LCRH_EPS_S 2 442 #define UART_LCRH_EPS_EVEN 0x00000004 443 #define UART_LCRH_EPS_ODD 0x00000000 444 445 // Field: [1] PEN 446 // 447 // UART Parity Enable 448 // This bit controls generation and checking of parity bit. 449 // ENUMs: 450 // EN Parity checking and generation is enabled. 451 // DIS Parity is disabled and no parity bit is added to 452 // the data frame 453 #define UART_LCRH_PEN 0x00000002 454 #define UART_LCRH_PEN_BITN 1 455 #define UART_LCRH_PEN_M 0x00000002 456 #define UART_LCRH_PEN_S 1 457 #define UART_LCRH_PEN_EN 0x00000002 458 #define UART_LCRH_PEN_DIS 0x00000000 459 460 // Field: [0] BRK 461 // 462 // UART Send Break 463 // If this bit is set to 1, a low-level is continually output on the UARTTXD 464 // output pin, after completing transmission of the current character. For the 465 // proper execution of the break command, the 466 // software must set this bit for at least two complete frames. For normal use, 467 // this bit must be cleared to 0. 468 #define UART_LCRH_BRK 0x00000001 469 #define UART_LCRH_BRK_BITN 0 470 #define UART_LCRH_BRK_M 0x00000001 471 #define UART_LCRH_BRK_S 0 472 473 //***************************************************************************** 474 // 475 // Register: UART_O_CTL 476 // 477 //***************************************************************************** 478 // Field: [15] CTSEN 479 // 480 // CTS hardware flow control enable 481 // ENUMs: 482 // EN CTS hardware flow control enabled 483 // DIS CTS hardware flow control disabled 484 #define UART_CTL_CTSEN 0x00008000 485 #define UART_CTL_CTSEN_BITN 15 486 #define UART_CTL_CTSEN_M 0x00008000 487 #define UART_CTL_CTSEN_S 15 488 #define UART_CTL_CTSEN_EN 0x00008000 489 #define UART_CTL_CTSEN_DIS 0x00000000 490 491 // Field: [14] RTSEN 492 // 493 // RTS hardware flow control enable 494 // ENUMs: 495 // EN RTS hardware flow control enabled 496 // DIS RTS hardware flow control disabled 497 #define UART_CTL_RTSEN 0x00004000 498 #define UART_CTL_RTSEN_BITN 14 499 #define UART_CTL_RTSEN_M 0x00004000 500 #define UART_CTL_RTSEN_S 14 501 #define UART_CTL_RTSEN_EN 0x00004000 502 #define UART_CTL_RTSEN_DIS 0x00000000 503 504 // Field: [11] RTS 505 // 506 // Request to Send 507 // This bit is the complement of the active-low UART RTS output. That is, when 508 // the bit is programmed to a 1 then RTS output on the pins is LOW. 509 #define UART_CTL_RTS 0x00000800 510 #define UART_CTL_RTS_BITN 11 511 #define UART_CTL_RTS_M 0x00000800 512 #define UART_CTL_RTS_S 11 513 514 // Field: [9] RXE 515 // 516 // UART Receive Enable 517 // If the UART is disabled in the middle of reception, it completes the current 518 // character before stopping. 519 // ENUMs: 520 // EN UART Receive enabled 521 // DIS UART Receive disabled 522 #define UART_CTL_RXE 0x00000200 523 #define UART_CTL_RXE_BITN 9 524 #define UART_CTL_RXE_M 0x00000200 525 #define UART_CTL_RXE_S 9 526 #define UART_CTL_RXE_EN 0x00000200 527 #define UART_CTL_RXE_DIS 0x00000000 528 529 // Field: [8] TXE 530 // 531 // UART Transmit Enable 532 // If the UART is disabled in the middle of transmission, it completes the 533 // current character before stopping. 534 // ENUMs: 535 // EN UART Transmit enabled 536 // DIS UART Transmit disabled 537 #define UART_CTL_TXE 0x00000100 538 #define UART_CTL_TXE_BITN 8 539 #define UART_CTL_TXE_M 0x00000100 540 #define UART_CTL_TXE_S 8 541 #define UART_CTL_TXE_EN 0x00000100 542 #define UART_CTL_TXE_DIS 0x00000000 543 544 // Field: [7] LBE 545 // 546 // UART Loop Back Enable: 547 // Enabling the loop-back mode connects the UARTTXD output from the UART to 548 // UARTRXD input of the UART. 549 // ENUMs: 550 // EN Loop Back enabled 551 // DIS Loop Back disabled 552 #define UART_CTL_LBE 0x00000080 553 #define UART_CTL_LBE_BITN 7 554 #define UART_CTL_LBE_M 0x00000080 555 #define UART_CTL_LBE_S 7 556 #define UART_CTL_LBE_EN 0x00000080 557 #define UART_CTL_LBE_DIS 0x00000000 558 559 // Field: [0] UARTEN 560 // 561 // UART Enable 562 // ENUMs: 563 // EN UART enabled 564 // DIS UART disabled 565 #define UART_CTL_UARTEN 0x00000001 566 #define UART_CTL_UARTEN_BITN 0 567 #define UART_CTL_UARTEN_M 0x00000001 568 #define UART_CTL_UARTEN_S 0 569 #define UART_CTL_UARTEN_EN 0x00000001 570 #define UART_CTL_UARTEN_DIS 0x00000000 571 572 //***************************************************************************** 573 // 574 // Register: UART_O_IFLS 575 // 576 //***************************************************************************** 577 // Field: [5:3] RXSEL 578 // 579 // Receive interrupt FIFO level select: 580 // This field sets the trigger points for the receive interrupt. Values 581 // 0b101-0b111 are reserved. 582 // ENUMs: 583 // 7_8 Receive FIFO becomes >= 7/8 full 584 // 6_8 Receive FIFO becomes >= 3/4 full 585 // 4_8 Receive FIFO becomes >= 1/2 full 586 // 2_8 Receive FIFO becomes >= 1/4 full 587 // 1_8 Receive FIFO becomes >= 1/8 full 588 #define UART_IFLS_RXSEL_W 3 589 #define UART_IFLS_RXSEL_M 0x00000038 590 #define UART_IFLS_RXSEL_S 3 591 #define UART_IFLS_RXSEL_7_8 0x00000020 592 #define UART_IFLS_RXSEL_6_8 0x00000018 593 #define UART_IFLS_RXSEL_4_8 0x00000010 594 #define UART_IFLS_RXSEL_2_8 0x00000008 595 #define UART_IFLS_RXSEL_1_8 0x00000000 596 597 // Field: [2:0] TXSEL 598 // 599 // Transmit interrupt FIFO level select: 600 // This field sets the trigger points for the transmit interrupt. Values 601 // 0b101-0b111 are reserved. 602 // ENUMs: 603 // 7_8 Transmit FIFO becomes <= 7/8 full 604 // 6_8 Transmit FIFO becomes <= 3/4 full 605 // 4_8 Transmit FIFO becomes <= 1/2 full 606 // 2_8 Transmit FIFO becomes <= 1/4 full 607 // 1_8 Transmit FIFO becomes <= 1/8 full 608 #define UART_IFLS_TXSEL_W 3 609 #define UART_IFLS_TXSEL_M 0x00000007 610 #define UART_IFLS_TXSEL_S 0 611 #define UART_IFLS_TXSEL_7_8 0x00000004 612 #define UART_IFLS_TXSEL_6_8 0x00000003 613 #define UART_IFLS_TXSEL_4_8 0x00000002 614 #define UART_IFLS_TXSEL_2_8 0x00000001 615 #define UART_IFLS_TXSEL_1_8 0x00000000 616 617 //***************************************************************************** 618 // 619 // Register: UART_O_IMSC 620 // 621 //***************************************************************************** 622 // Field: [11] EOTIM 623 // 624 // End of Transmission interrupt mask. A read returns the current mask for 625 // UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set 626 // which means the interrupt state will be reflected in MIS.EOTMIS. A write of 627 // 0 clears the mask which means MIS.EOTMIS will not reflect the interrupt. 628 #define UART_IMSC_EOTIM 0x00000800 629 #define UART_IMSC_EOTIM_BITN 11 630 #define UART_IMSC_EOTIM_M 0x00000800 631 #define UART_IMSC_EOTIM_S 11 632 633 // Field: [10] OEIM 634 // 635 // Overrun error interrupt mask. A read returns the current mask for UART's 636 // overrun error interrupt. On a write of 1, the mask of the overrun error 637 // interrupt is set which means the interrupt state will be reflected in 638 // MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not 639 // reflect the interrupt. 640 #define UART_IMSC_OEIM 0x00000400 641 #define UART_IMSC_OEIM_BITN 10 642 #define UART_IMSC_OEIM_M 0x00000400 643 #define UART_IMSC_OEIM_S 10 644 645 // Field: [9] BEIM 646 // 647 // Break error interrupt mask. A read returns the current mask for UART's break 648 // error interrupt. On a write of 1, the mask of the overrun error interrupt is 649 // set which means the interrupt state will be reflected in MIS.BEMIS. A write 650 // of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. 651 #define UART_IMSC_BEIM 0x00000200 652 #define UART_IMSC_BEIM_BITN 9 653 #define UART_IMSC_BEIM_M 0x00000200 654 #define UART_IMSC_BEIM_S 9 655 656 // Field: [8] PEIM 657 // 658 // Parity error interrupt mask. A read returns the current mask for UART's 659 // parity error interrupt. On a write of 1, the mask of the overrun error 660 // interrupt is set which means the interrupt state will be reflected in 661 // MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not 662 // reflect the interrupt. 663 #define UART_IMSC_PEIM 0x00000100 664 #define UART_IMSC_PEIM_BITN 8 665 #define UART_IMSC_PEIM_M 0x00000100 666 #define UART_IMSC_PEIM_S 8 667 668 // Field: [7] FEIM 669 // 670 // Framing error interrupt mask. A read returns the current mask for UART's 671 // framing error interrupt. On a write of 1, the mask of the overrun error 672 // interrupt is set which means the interrupt state will be reflected in 673 // MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not 674 // reflect the interrupt. 675 #define UART_IMSC_FEIM 0x00000080 676 #define UART_IMSC_FEIM_BITN 7 677 #define UART_IMSC_FEIM_M 0x00000080 678 #define UART_IMSC_FEIM_S 7 679 680 // Field: [6] RTIM 681 // 682 // Receive timeout interrupt mask. A read returns the current mask for UART's 683 // receive timeout interrupt. On a write of 1, the mask of the overrun error 684 // interrupt is set which means the interrupt state will be reflected in 685 // MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not 686 // reflect the interrupt. 687 // The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the 688 // mask is set (RTIM = 1). This is because the mask acts as an enable for power 689 // saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. 690 #define UART_IMSC_RTIM 0x00000040 691 #define UART_IMSC_RTIM_BITN 6 692 #define UART_IMSC_RTIM_M 0x00000040 693 #define UART_IMSC_RTIM_S 6 694 695 // Field: [5] TXIM 696 // 697 // Transmit interrupt mask. A read returns the current mask for UART's transmit 698 // interrupt. On a write of 1, the mask of the overrun error interrupt is set 699 // which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 700 // clears the mask which means MIS.TXMIS will not reflect the interrupt. 701 #define UART_IMSC_TXIM 0x00000020 702 #define UART_IMSC_TXIM_BITN 5 703 #define UART_IMSC_TXIM_M 0x00000020 704 #define UART_IMSC_TXIM_S 5 705 706 // Field: [4] RXIM 707 // 708 // Receive interrupt mask. A read returns the current mask for UART's receive 709 // interrupt. On a write of 1, the mask of the overrun error interrupt is set 710 // which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 711 // clears the mask which means MIS.RXMIS will not reflect the interrupt. 712 #define UART_IMSC_RXIM 0x00000010 713 #define UART_IMSC_RXIM_BITN 4 714 #define UART_IMSC_RXIM_M 0x00000010 715 #define UART_IMSC_RXIM_S 4 716 717 // Field: [1] CTSMIM 718 // 719 // Clear to Send (CTS) modem interrupt mask. A read returns the current mask 720 // for UART's clear to send interrupt. On a write of 1, the mask of the overrun 721 // error interrupt is set which means the interrupt state will be reflected in 722 // MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not 723 // reflect the interrupt. 724 #define UART_IMSC_CTSMIM 0x00000002 725 #define UART_IMSC_CTSMIM_BITN 1 726 #define UART_IMSC_CTSMIM_M 0x00000002 727 #define UART_IMSC_CTSMIM_S 1 728 729 //***************************************************************************** 730 // 731 // Register: UART_O_RIS 732 // 733 //***************************************************************************** 734 // Field: [11] EOTRIS 735 // 736 // End of Transmission interrupt status: 737 // This field returns the raw interrupt state of UART's end of transmission 738 // interrupt. End of transmission flag is set when all the Transmit data in the 739 // FIFO and on the TX Line is tranmitted. 740 #define UART_RIS_EOTRIS 0x00000800 741 #define UART_RIS_EOTRIS_BITN 11 742 #define UART_RIS_EOTRIS_M 0x00000800 743 #define UART_RIS_EOTRIS_S 11 744 745 // Field: [10] OERIS 746 // 747 // Overrun error interrupt status: 748 // This field returns the raw interrupt state of UART's overrun error 749 // interrupt. Overrun error occurs if data is received and the receive FIFO is 750 // full. 751 #define UART_RIS_OERIS 0x00000400 752 #define UART_RIS_OERIS_BITN 10 753 #define UART_RIS_OERIS_M 0x00000400 754 #define UART_RIS_OERIS_S 10 755 756 // Field: [9] BERIS 757 // 758 // Break error interrupt status: 759 // This field returns the raw interrupt state of UART's break error interrupt. 760 // Break error is set when a break condition is detected, indicating that the 761 // received data input (UARTRXD input pin) was held LOW for longer than a 762 // full-word transmission time (defined as start, data, parity and stop bits). 763 #define UART_RIS_BERIS 0x00000200 764 #define UART_RIS_BERIS_BITN 9 765 #define UART_RIS_BERIS_M 0x00000200 766 #define UART_RIS_BERIS_S 9 767 768 // Field: [8] PERIS 769 // 770 // Parity error interrupt status: 771 // This field returns the raw interrupt state of UART's parity error interrupt. 772 // Parity error is set if the parity of the received data character does not 773 // match the parity that the LCRH.EPS and LCRH.SPS select. 774 #define UART_RIS_PERIS 0x00000100 775 #define UART_RIS_PERIS_BITN 8 776 #define UART_RIS_PERIS_M 0x00000100 777 #define UART_RIS_PERIS_S 8 778 779 // Field: [7] FERIS 780 // 781 // Framing error interrupt status: 782 // This field returns the raw interrupt state of UART's framing error 783 // interrupt. Framing error is set if the received character does not have a 784 // valid stop bit (a valid stop bit is 1). 785 #define UART_RIS_FERIS 0x00000080 786 #define UART_RIS_FERIS_BITN 7 787 #define UART_RIS_FERIS_M 0x00000080 788 #define UART_RIS_FERIS_S 7 789 790 // Field: [6] RTRIS 791 // 792 // Receive timeout interrupt status: 793 // This field returns the raw interrupt state of UART's receive timeout 794 // interrupt. The receive timeout interrupt is asserted when the receive FIFO 795 // is not empty, and no more data is received during a 32-bit period. The 796 // receive timeout interrupt is cleared either when the FIFO becomes empty 797 // through reading all the data, or when a 1 is written to ICR.RTIC. 798 // The raw interrupt for receive timeout cannot be set unless the mask is set 799 // (IMSC.RTIM = 1). This is because the mask acts as an enable for power 800 // saving. That is, the same status can be read from MIS.RTMIS and RTRIS. 801 #define UART_RIS_RTRIS 0x00000040 802 #define UART_RIS_RTRIS_BITN 6 803 #define UART_RIS_RTRIS_M 0x00000040 804 #define UART_RIS_RTRIS_S 6 805 806 // Field: [5] TXRIS 807 // 808 // Transmit interrupt status: 809 // This field returns the raw interrupt state of UART's transmit interrupt. 810 // When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if 811 // the number of bytes in transmit FIFO is equal to or lower than the 812 // programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by 813 // writing data to the transmit FIFO until it becomes greater than the trigger 814 // level, or by clearing the interrupt through ICR.TXIC. 815 // When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one 816 // location, the transmit interrupt is asserted if there is no data present in 817 // the transmitters single location. It is cleared by performing a single write 818 // to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. 819 #define UART_RIS_TXRIS 0x00000020 820 #define UART_RIS_TXRIS_BITN 5 821 #define UART_RIS_TXRIS_M 0x00000020 822 #define UART_RIS_TXRIS_S 5 823 824 // Field: [4] RXRIS 825 // 826 // Receive interrupt status: 827 // This field returns the raw interrupt state of UART's receive interrupt. 828 // When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if 829 // the receive FIFO reaches the programmed trigger 830 // level (IFLS.RXSEL). The receive interrupt is cleared by reading data from 831 // the receive FIFO until it becomes less than the trigger level, or by 832 // clearing the interrupt through ICR.RXIC. 833 // When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one 834 // location, the receive interrupt is asserted if data is received 835 // thereby filling the location. The receive interrupt is cleared by performing 836 // a single read of the receive FIFO, or by clearing the interrupt through 837 // ICR.RXIC. 838 #define UART_RIS_RXRIS 0x00000010 839 #define UART_RIS_RXRIS_BITN 4 840 #define UART_RIS_RXRIS_M 0x00000010 841 #define UART_RIS_RXRIS_S 4 842 843 // Field: [1] CTSRMIS 844 // 845 // Clear to Send (CTS) modem interrupt status: 846 // This field returns the raw interrupt state of UART's clear to send 847 // interrupt. 848 #define UART_RIS_CTSRMIS 0x00000002 849 #define UART_RIS_CTSRMIS_BITN 1 850 #define UART_RIS_CTSRMIS_M 0x00000002 851 #define UART_RIS_CTSRMIS_S 1 852 853 //***************************************************************************** 854 // 855 // Register: UART_O_MIS 856 // 857 //***************************************************************************** 858 // Field: [11] EOTMIS 859 // 860 // End of Transmission interrupt status: 861 // This field returns the masked interrupt state of the overrun interrupt which 862 // is the AND product of raw interrupt state RIS.EOTRIS and the mask setting 863 // IMSC.EOTIM. 864 #define UART_MIS_EOTMIS 0x00000800 865 #define UART_MIS_EOTMIS_BITN 11 866 #define UART_MIS_EOTMIS_M 0x00000800 867 #define UART_MIS_EOTMIS_S 11 868 869 // Field: [10] OEMIS 870 // 871 // Overrun error masked interrupt status: 872 // This field returns the masked interrupt state of the overrun interrupt which 873 // is the AND product of raw interrupt state RIS.OERIS and the mask setting 874 // IMSC.OEIM. 875 #define UART_MIS_OEMIS 0x00000400 876 #define UART_MIS_OEMIS_BITN 10 877 #define UART_MIS_OEMIS_M 0x00000400 878 #define UART_MIS_OEMIS_S 10 879 880 // Field: [9] BEMIS 881 // 882 // Break error masked interrupt status: 883 // This field returns the masked interrupt state of the break error interrupt 884 // which is the AND product of raw interrupt state RIS.BERIS and the mask 885 // setting IMSC.BEIM. 886 #define UART_MIS_BEMIS 0x00000200 887 #define UART_MIS_BEMIS_BITN 9 888 #define UART_MIS_BEMIS_M 0x00000200 889 #define UART_MIS_BEMIS_S 9 890 891 // Field: [8] PEMIS 892 // 893 // Parity error masked interrupt status: 894 // This field returns the masked interrupt state of the parity error interrupt 895 // which is the AND product of raw interrupt state RIS.PERIS and the mask 896 // setting IMSC.PEIM. 897 #define UART_MIS_PEMIS 0x00000100 898 #define UART_MIS_PEMIS_BITN 8 899 #define UART_MIS_PEMIS_M 0x00000100 900 #define UART_MIS_PEMIS_S 8 901 902 // Field: [7] FEMIS 903 // 904 // Framing error masked interrupt status: Returns the masked interrupt state of 905 // the framing error interrupt which is the AND product of raw interrupt state 906 // RIS.FERIS and the mask setting IMSC.FEIM. 907 #define UART_MIS_FEMIS 0x00000080 908 #define UART_MIS_FEMIS_BITN 7 909 #define UART_MIS_FEMIS_M 0x00000080 910 #define UART_MIS_FEMIS_S 7 911 912 // Field: [6] RTMIS 913 // 914 // Receive timeout masked interrupt status: 915 // Returns the masked interrupt state of the receive timeout interrupt. 916 // The raw interrupt for receive timeout cannot be set unless the mask is set 917 // (IMSC.RTIM = 1). This is because the mask acts as an enable for power 918 // saving. That is, the same status can be read from RTMIS and RIS.RTRIS. 919 #define UART_MIS_RTMIS 0x00000040 920 #define UART_MIS_RTMIS_BITN 6 921 #define UART_MIS_RTMIS_M 0x00000040 922 #define UART_MIS_RTMIS_S 6 923 924 // Field: [5] TXMIS 925 // 926 // Transmit masked interrupt status: 927 // This field returns the masked interrupt state of the transmit interrupt 928 // which is the AND product of raw interrupt state RIS.TXRIS and the mask 929 // setting IMSC.TXIM. 930 #define UART_MIS_TXMIS 0x00000020 931 #define UART_MIS_TXMIS_BITN 5 932 #define UART_MIS_TXMIS_M 0x00000020 933 #define UART_MIS_TXMIS_S 5 934 935 // Field: [4] RXMIS 936 // 937 // Receive masked interrupt status: 938 // This field returns the masked interrupt state of the receive interrupt 939 // which is the AND product of raw interrupt state RIS.RXRIS and the mask 940 // setting IMSC.RXIM. 941 #define UART_MIS_RXMIS 0x00000010 942 #define UART_MIS_RXMIS_BITN 4 943 #define UART_MIS_RXMIS_M 0x00000010 944 #define UART_MIS_RXMIS_S 4 945 946 // Field: [1] CTSMMIS 947 // 948 // Clear to Send (CTS) modem masked interrupt status: 949 // This field returns the masked interrupt state of the clear to send interrupt 950 // which is the AND product of raw interrupt state RIS.CTSRMIS and the mask 951 // setting IMSC.CTSMIM. 952 #define UART_MIS_CTSMMIS 0x00000002 953 #define UART_MIS_CTSMMIS_BITN 1 954 #define UART_MIS_CTSMMIS_M 0x00000002 955 #define UART_MIS_CTSMMIS_S 1 956 957 //***************************************************************************** 958 // 959 // Register: UART_O_ICR 960 // 961 //***************************************************************************** 962 // Field: [11] EOTIC 963 // 964 // End of Transmission interrupt clear: 965 // Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS). 966 // Writing 0 has no effect. 967 #define UART_ICR_EOTIC 0x00000800 968 #define UART_ICR_EOTIC_BITN 11 969 #define UART_ICR_EOTIC_M 0x00000800 970 #define UART_ICR_EOTIC_S 11 971 972 // Field: [10] OEIC 973 // 974 // Overrun error interrupt clear: 975 // Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). 976 // Writing 0 has no effect. 977 #define UART_ICR_OEIC 0x00000400 978 #define UART_ICR_OEIC_BITN 10 979 #define UART_ICR_OEIC_M 0x00000400 980 #define UART_ICR_OEIC_S 10 981 982 // Field: [9] BEIC 983 // 984 // Break error interrupt clear: 985 // Writing 1 to this field clears the break error interrupt (RIS.BERIS). 986 // Writing 0 has no effect. 987 #define UART_ICR_BEIC 0x00000200 988 #define UART_ICR_BEIC_BITN 9 989 #define UART_ICR_BEIC_M 0x00000200 990 #define UART_ICR_BEIC_S 9 991 992 // Field: [8] PEIC 993 // 994 // Parity error interrupt clear: 995 // Writing 1 to this field clears the parity error interrupt (RIS.PERIS). 996 // Writing 0 has no effect. 997 #define UART_ICR_PEIC 0x00000100 998 #define UART_ICR_PEIC_BITN 8 999 #define UART_ICR_PEIC_M 0x00000100 1000 #define UART_ICR_PEIC_S 8 1001 1002 // Field: [7] FEIC 1003 // 1004 // Framing error interrupt clear: 1005 // Writing 1 to this field clears the framing error interrupt (RIS.FERIS). 1006 // Writing 0 has no effect. 1007 #define UART_ICR_FEIC 0x00000080 1008 #define UART_ICR_FEIC_BITN 7 1009 #define UART_ICR_FEIC_M 0x00000080 1010 #define UART_ICR_FEIC_S 7 1011 1012 // Field: [6] RTIC 1013 // 1014 // Receive timeout interrupt clear: 1015 // Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). 1016 // Writing 0 has no effect. 1017 #define UART_ICR_RTIC 0x00000040 1018 #define UART_ICR_RTIC_BITN 6 1019 #define UART_ICR_RTIC_M 0x00000040 1020 #define UART_ICR_RTIC_S 6 1021 1022 // Field: [5] TXIC 1023 // 1024 // Transmit interrupt clear: 1025 // Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 1026 // has no effect. 1027 #define UART_ICR_TXIC 0x00000020 1028 #define UART_ICR_TXIC_BITN 5 1029 #define UART_ICR_TXIC_M 0x00000020 1030 #define UART_ICR_TXIC_S 5 1031 1032 // Field: [4] RXIC 1033 // 1034 // Receive interrupt clear: 1035 // Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 1036 // has no effect. 1037 #define UART_ICR_RXIC 0x00000010 1038 #define UART_ICR_RXIC_BITN 4 1039 #define UART_ICR_RXIC_M 0x00000010 1040 #define UART_ICR_RXIC_S 4 1041 1042 // Field: [1] CTSMIC 1043 // 1044 // Clear to Send (CTS) modem interrupt clear: 1045 // Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). 1046 // Writing 0 has no effect. 1047 #define UART_ICR_CTSMIC 0x00000002 1048 #define UART_ICR_CTSMIC_BITN 1 1049 #define UART_ICR_CTSMIC_M 0x00000002 1050 #define UART_ICR_CTSMIC_S 1 1051 1052 //***************************************************************************** 1053 // 1054 // Register: UART_O_DMACTL 1055 // 1056 //***************************************************************************** 1057 // Field: [2] DMAONERR 1058 // 1059 // DMA on error. If this bit is set to 1, the DMA receive request outputs (for 1060 // single and burst requests) are disabled when the UART error interrupt is 1061 // asserted (more specifically if any of the error interrupts RIS.PERIS, 1062 // RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). 1063 #define UART_DMACTL_DMAONERR 0x00000004 1064 #define UART_DMACTL_DMAONERR_BITN 2 1065 #define UART_DMACTL_DMAONERR_M 0x00000004 1066 #define UART_DMACTL_DMAONERR_S 2 1067 1068 // Field: [1] TXDMAE 1069 // 1070 // Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is 1071 // enabled. 1072 #define UART_DMACTL_TXDMAE 0x00000002 1073 #define UART_DMACTL_TXDMAE_BITN 1 1074 #define UART_DMACTL_TXDMAE_M 0x00000002 1075 #define UART_DMACTL_TXDMAE_S 1 1076 1077 // Field: [0] RXDMAE 1078 // 1079 // Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is 1080 // enabled. 1081 #define UART_DMACTL_RXDMAE 0x00000001 1082 #define UART_DMACTL_RXDMAE_BITN 0 1083 #define UART_DMACTL_RXDMAE_M 0x00000001 1084 #define UART_DMACTL_RXDMAE_S 0 1085 1086 1087 #endif // __UART__ 1088
