1 /******************************************************************************
2 *  Filename:       hw_sram_mmr_h
3 *  Revised:        2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
4 *  Revision:       51990
5 *
6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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35 ******************************************************************************/
36 
37 #ifndef __HW_SRAM_MMR_H__
38 #define __HW_SRAM_MMR_H__
39 
40 //*****************************************************************************
41 //
42 // This section defines the register offsets of
43 // SRAM_MMR component
44 //
45 //*****************************************************************************
46 // Parity Error Control
47 #define SRAM_MMR_O_PER_CTL                                          0x00000000
48 
49 // Parity Error Check
50 #define SRAM_MMR_O_PER_CHK                                          0x00000004
51 
52 // Parity Error Debug
53 #define SRAM_MMR_O_PER_DBG                                          0x00000008
54 
55 // Memory Control
56 #define SRAM_MMR_O_MEM_CTL                                          0x0000000C
57 
58 //*****************************************************************************
59 //
60 // Register: SRAM_MMR_O_PER_CTL
61 //
62 //*****************************************************************************
63 // Field:     [8] PER_DISABLE
64 //
65 // Parity Status Disable
66 //
67 // 0: A parity error will update PER_CHK.PER_ADDR field
68 // 1: Parity error does not update PER_CHK.PER_ADDR field
69 #define SRAM_MMR_PER_CTL_PER_DISABLE                                0x00000100
70 #define SRAM_MMR_PER_CTL_PER_DISABLE_BITN                                    8
71 #define SRAM_MMR_PER_CTL_PER_DISABLE_M                              0x00000100
72 #define SRAM_MMR_PER_CTL_PER_DISABLE_S                                       8
73 
74 // Field:     [0] PER_DEBUG_ENABLE
75 //
76 // Parity Error Debug Enable
77 //
78 // 0: Normal operation
79 // 1: An address offset can be written to PER_DBG.PER_DEBUG_ADDR and parity
80 // errors will be generated on reads from within this offset
81 #define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE                           0x00000001
82 #define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_BITN                               0
83 #define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_M                         0x00000001
84 #define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_S                                  0
85 
86 //*****************************************************************************
87 //
88 // Register: SRAM_MMR_O_PER_CHK
89 //
90 //*****************************************************************************
91 // Field:  [23:0] PER_ADDR
92 //
93 // Parity Error Address Offset
94 // Returns the last address offset which resulted in a parity error during an
95 // SRAM read. The address offset returned is always the word-aligned address
96 // that contains the location with the parity error. For parity faults on non
97 // word-aligned accesses, CPU_SCS:BFAR.ADDRESS will hold the address of the
98 // location that resulted in parity error.
99 #define SRAM_MMR_PER_CHK_PER_ADDR_W                                         24
100 #define SRAM_MMR_PER_CHK_PER_ADDR_M                                 0x00FFFFFF
101 #define SRAM_MMR_PER_CHK_PER_ADDR_S                                          0
102 
103 //*****************************************************************************
104 //
105 // Register: SRAM_MMR_O_PER_DBG
106 //
107 //*****************************************************************************
108 // Field:  [23:0] PER_DEBUG_ADDR
109 //
110 // Debug Parity Error Address Offset
111 // When PER_CTL.PER_DEBUG is 1, this field is used to set a parity debug
112 // address offset. The address offset must be a word-aligned address. Writes
113 // within this address offset will force incorrect parity bits to be stored
114 // together with the data written. The following reads within this same address
115 // offset will thus result in parity errors to be generated.
116 #define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_W                                   24
117 #define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_M                           0x00FFFFFF
118 #define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_S                                    0
119 
120 //*****************************************************************************
121 //
122 // Register: SRAM_MMR_O_MEM_CTL
123 //
124 //*****************************************************************************
125 // Field:     [1] MEM_BUSY
126 //
127 // Memory Busy status
128 //
129 // 0: Memory accepts transfers
130 // 1: Memory controller is busy during initialization. Read and write transfers
131 // are not performed.
132 #define SRAM_MMR_MEM_CTL_MEM_BUSY                                   0x00000002
133 #define SRAM_MMR_MEM_CTL_MEM_BUSY_BITN                                       1
134 #define SRAM_MMR_MEM_CTL_MEM_BUSY_M                                 0x00000002
135 #define SRAM_MMR_MEM_CTL_MEM_BUSY_S                                          1
136 
137 // Field:     [0] MEM_CLR_EN
138 //
139 // Memory Contents Initialization enable
140 //
141 // Writing 1 to MEM_CLR_EN will start memory initialization. The contents of
142 // all byte locations will be initialized to 0x00. MEM_BUSY will be 1 until
143 // memory initialization has completed.
144 #define SRAM_MMR_MEM_CTL_MEM_CLR_EN                                 0x00000001
145 #define SRAM_MMR_MEM_CTL_MEM_CLR_EN_BITN                                     0
146 #define SRAM_MMR_MEM_CTL_MEM_CLR_EN_M                               0x00000001
147 #define SRAM_MMR_MEM_CTL_MEM_CLR_EN_S                                        0
148 
149 
150 #endif // __SRAM_MMR__
151