1 /****************************************************************************** 2 * Filename: hw_pka_int_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_PKA_INT_H__ 38 #define __HW_PKA_INT_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // PKA_INT component 44 // 45 //***************************************************************************** 46 // PKA Options register 47 #define PKA_INT_O_OPTIONS 0x00000FF8 48 49 // PKA hardware revision register 50 #define PKA_INT_O_REVISION 0x00000FFC 51 52 //***************************************************************************** 53 // 54 // Register: PKA_INT_O_OPTIONS 55 // 56 //***************************************************************************** 57 // Field: [10] AIC_PRESENT 58 // 59 // When set to '1', indicates that an EIP201 AIC is included in the EIP150 60 #define PKA_INT_OPTIONS_AIC_PRESENT 0x00000400 61 #define PKA_INT_OPTIONS_AIC_PRESENT_BITN 10 62 #define PKA_INT_OPTIONS_AIC_PRESENT_M 0x00000400 63 #define PKA_INT_OPTIONS_AIC_PRESENT_S 10 64 65 // Field: [9] EIP76_PRESENT 66 // 67 // When set to '1', indicates that the EIP76 TRNG is included in the EIP150 68 #define PKA_INT_OPTIONS_EIP76_PRESENT 0x00000200 69 #define PKA_INT_OPTIONS_EIP76_PRESENT_BITN 9 70 #define PKA_INT_OPTIONS_EIP76_PRESENT_M 0x00000200 71 #define PKA_INT_OPTIONS_EIP76_PRESENT_S 9 72 73 // Field: [8] EIP28_PRESENT 74 // 75 // When set to '1', indicates that the EIP28 PKA is included in the EIP150 76 #define PKA_INT_OPTIONS_EIP28_PRESENT 0x00000100 77 #define PKA_INT_OPTIONS_EIP28_PRESENT_BITN 8 78 #define PKA_INT_OPTIONS_EIP28_PRESENT_M 0x00000100 79 #define PKA_INT_OPTIONS_EIP28_PRESENT_S 8 80 81 // Field: [3] AXI_INTERFACE 82 // 83 // When set to '1', indicates that the EIP150 is equipped with a AXI interface 84 #define PKA_INT_OPTIONS_AXI_INTERFACE 0x00000008 85 #define PKA_INT_OPTIONS_AXI_INTERFACE_BITN 3 86 #define PKA_INT_OPTIONS_AXI_INTERFACE_M 0x00000008 87 #define PKA_INT_OPTIONS_AXI_INTERFACE_S 3 88 89 // Field: [2] AHB_IS_ASYNC 90 // 91 // When set to '1', indicates that AHB interface is asynchronous Only 92 // applicable when AHB_INTERFACE is 1 93 #define PKA_INT_OPTIONS_AHB_IS_ASYNC 0x00000004 94 #define PKA_INT_OPTIONS_AHB_IS_ASYNC_BITN 2 95 #define PKA_INT_OPTIONS_AHB_IS_ASYNC_M 0x00000004 96 #define PKA_INT_OPTIONS_AHB_IS_ASYNC_S 2 97 98 // Field: [1] AHB_INTERFACE 99 // 100 // When set to '1', indicates that the EIP150 is equipped with a AHB interface 101 #define PKA_INT_OPTIONS_AHB_INTERFACE 0x00000002 102 #define PKA_INT_OPTIONS_AHB_INTERFACE_BITN 1 103 #define PKA_INT_OPTIONS_AHB_INTERFACE_M 0x00000002 104 #define PKA_INT_OPTIONS_AHB_INTERFACE_S 1 105 106 // Field: [0] PLB_INTERFACE 107 // 108 // When set to '1', indicates that the EIP150 is equipped with a PLB interface 109 #define PKA_INT_OPTIONS_PLB_INTERFACE 0x00000001 110 #define PKA_INT_OPTIONS_PLB_INTERFACE_BITN 0 111 #define PKA_INT_OPTIONS_PLB_INTERFACE_M 0x00000001 112 #define PKA_INT_OPTIONS_PLB_INTERFACE_S 0 113 114 //***************************************************************************** 115 // 116 // Register: PKA_INT_O_REVISION 117 // 118 //***************************************************************************** 119 // Field: [27:24] MAJOR_REVISION 120 // 121 // These bits encode the major version number for this module 122 #define PKA_INT_REVISION_MAJOR_REVISION_W 4 123 #define PKA_INT_REVISION_MAJOR_REVISION_M 0x0F000000 124 #define PKA_INT_REVISION_MAJOR_REVISION_S 24 125 126 // Field: [23:20] MINOR_REVISION 127 // 128 // These bits encode the minor version number for this module 129 #define PKA_INT_REVISION_MINOR_REVISION_W 4 130 #define PKA_INT_REVISION_MINOR_REVISION_M 0x00F00000 131 #define PKA_INT_REVISION_MINOR_REVISION_S 20 132 133 // Field: [19:16] PATCH_LEVEL 134 // 135 // These bits encode the hardware patch level for this module they start at 136 // value 0 on the first release 137 #define PKA_INT_REVISION_PATCH_LEVEL_W 4 138 #define PKA_INT_REVISION_PATCH_LEVEL_M 0x000F0000 139 #define PKA_INT_REVISION_PATCH_LEVEL_S 16 140 141 // Field: [15:8] COMP_EIP_NUM 142 // 143 // These bits simply contain the complement of bits [7:0], used by a driver to 144 // ascertain that the EIP150 revision register is indeed read 145 #define PKA_INT_REVISION_COMP_EIP_NUM_W 8 146 #define PKA_INT_REVISION_COMP_EIP_NUM_M 0x0000FF00 147 #define PKA_INT_REVISION_COMP_EIP_NUM_S 8 148 149 // Field: [7:0] EIP_NUM 150 // 151 // These bits encode the AuthenTec EIP number for the EIP150 152 #define PKA_INT_REVISION_EIP_NUM_W 8 153 #define PKA_INT_REVISION_EIP_NUM_M 0x000000FF 154 #define PKA_INT_REVISION_EIP_NUM_S 0 155 156 157 #endif // __PKA_INT__ 158
