1 /****************************************************************************** 2 * Filename: hw_fcfg1_h 3 * Revised: 2020-09-04 11:58:29 +0200 (Fri, 04 Sep 2020) 4 * Revision: 58475 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_FCFG1_H__ 38 #define __HW_FCFG1_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // FCFG1 component 44 // 45 //***************************************************************************** 46 // Misc configurations 47 #define FCFG1_O_MISC_CONF_1 0x000000A0 48 49 // Internal 50 #define FCFG1_O_MISC_CONF_2 0x000000A4 51 52 // Internal 53 #define FCFG1_O_HPOSC_MEAS_5 0x000000B0 54 55 // Internal 56 #define FCFG1_O_HPOSC_MEAS_4 0x000000B4 57 58 // Internal 59 #define FCFG1_O_HPOSC_MEAS_3 0x000000B8 60 61 // Internal 62 #define FCFG1_O_HPOSC_MEAS_2 0x000000BC 63 64 // Internal 65 #define FCFG1_O_HPOSC_MEAS_1 0x000000C0 66 67 // Internal 68 #define FCFG1_O_CONFIG_CC26_FE 0x000000C4 69 70 // Internal 71 #define FCFG1_O_CONFIG_CC13_FE 0x000000C8 72 73 // Internal 74 #define FCFG1_O_CONFIG_RF_COMMON 0x000000CC 75 76 // Internal 77 #define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 0x000000D0 78 79 // Internal 80 #define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 0x000000D4 81 82 // Internal 83 #define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G 0x000000D8 84 85 // Internal 86 #define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G 0x000000DC 87 88 // Internal 89 #define FCFG1_O_CONFIG_SYNTH_DIV4_CC26 0x000000E0 90 91 // Internal 92 #define FCFG1_O_CONFIG_SYNTH_DIV4_CC13 0x000000E4 93 94 // Internal 95 #define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000E8 96 97 // Internal 98 #define FCFG1_O_CONFIG_SYNTH_DIV6_CC26 0x000000EC 99 100 // Internal 101 #define FCFG1_O_CONFIG_SYNTH_DIV6_CC13 0x000000F0 102 103 // Internal 104 #define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000F4 105 106 // Internal 107 #define FCFG1_O_CONFIG_SYNTH_DIV12_CC26 0x000000F8 108 109 // Internal 110 #define FCFG1_O_CONFIG_SYNTH_DIV12_CC13 0x000000FC 111 112 // Internal 113 #define FCFG1_O_CONFIG_SYNTH_DIV15 0x00000100 114 115 // Internal 116 #define FCFG1_O_CONFIG_SYNTH_DIV30 0x00000104 117 118 // Flash information 119 #define FCFG1_O_FLASH_NUMBER 0x00000164 120 121 // Flash information 122 #define FCFG1_O_FLASH_COORDINATE 0x0000016C 123 124 // Internal 125 #define FCFG1_O_FLASH_E_P 0x00000170 126 127 // Internal 128 #define FCFG1_O_FLASH_C_E_P_R 0x00000174 129 130 // Internal 131 #define FCFG1_O_FLASH_P_R_PV 0x00000178 132 133 // Internal 134 #define FCFG1_O_FLASH_EH_SEQ 0x0000017C 135 136 // Internal 137 #define FCFG1_O_FLASH_VHV_E 0x00000180 138 139 // Internal 140 #define FCFG1_O_FLASH_PP 0x00000184 141 142 // Internal 143 #define FCFG1_O_FLASH_PROG_EP 0x00000188 144 145 // Internal 146 #define FCFG1_O_FLASH_ERA_PW 0x0000018C 147 148 // Internal 149 #define FCFG1_O_FLASH_VHV 0x00000190 150 151 // Internal 152 #define FCFG1_O_FLASH_VHV_PV 0x00000194 153 154 // Internal 155 #define FCFG1_O_FLASH_V 0x00000198 156 157 // User Identification. 158 #define FCFG1_O_USER_ID 0x00000294 159 160 // Internal 161 #define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 162 163 // Internal 164 #define FCFG1_O_ANA2_TRIM 0x000002B4 165 166 // Internal 167 #define FCFG1_O_LDO_TRIM 0x000002B8 168 169 // MAC BLE Address 0 170 #define FCFG1_O_MAC_BLE_0 0x000002E8 171 172 // MAC BLE Address 1 173 #define FCFG1_O_MAC_BLE_1 0x000002EC 174 175 // MAC IEEE 802.15.4 Address 0 176 #define FCFG1_O_MAC_15_4_0 0x000002F0 177 178 // MAC IEEE 802.15.4 Address 1 179 #define FCFG1_O_MAC_15_4_1 0x000002F4 180 181 // Internal 182 #define FCFG1_O_FLASH_OTP_DATA4 0x00000308 183 184 // Miscellaneous Trim Parameters 185 #define FCFG1_O_MISC_TRIM 0x0000030C 186 187 // Internal 188 #define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 189 190 // IcePick Device Identification 191 #define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 192 193 // Factory Configuration (FCFG1) Revision 194 #define FCFG1_O_FCFG1_REVISION 0x0000031C 195 196 // Misc OTP Data 197 #define FCFG1_O_MISC_OTP_DATA 0x00000320 198 199 // IO Configuration 200 #define FCFG1_O_IOCONF 0x00000344 201 202 // Internal 203 #define FCFG1_O_CONFIG_IF_ADC 0x0000034C 204 205 // Internal 206 #define FCFG1_O_CONFIG_OSC_TOP 0x00000350 207 208 // AUX_ADC Gain in Absolute Reference Mode 209 #define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C 210 211 // AUX_ADC Gain in Relative Reference Mode 212 #define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 213 214 // AUX_ADC Temperature Offsets in Absolute Reference Mode 215 #define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 216 217 // Internal 218 #define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C 219 220 // Internal 221 #define FCFG1_O_AMPCOMP_TH1 0x00000370 222 223 // Internal 224 #define FCFG1_O_AMPCOMP_TH2 0x00000374 225 226 // Internal 227 #define FCFG1_O_AMPCOMP_CTRL1 0x00000378 228 229 // Internal 230 #define FCFG1_O_ANABYPASS_VALUE2 0x0000037C 231 232 // Internal 233 #define FCFG1_O_VOLT_TRIM 0x00000388 234 235 // OSC Configuration 236 #define FCFG1_O_OSC_CONF 0x0000038C 237 238 // Internal 239 #define FCFG1_O_FREQ_OFFSET 0x00000390 240 241 // Internal 242 #define FCFG1_O_MISC_OTP_DATA_1 0x00000398 243 244 // Shadow of EFUSE:DIE_ID_0 register 245 #define FCFG1_O_SHDW_DIE_ID_0 0x000003D0 246 247 // Shadow of EFUSE:DIE_ID_1 register 248 #define FCFG1_O_SHDW_DIE_ID_1 0x000003D4 249 250 // Shadow of EFUSE:DIE_ID_2 register 251 #define FCFG1_O_SHDW_DIE_ID_2 0x000003D8 252 253 // Shadow of EFUSE:DIE_ID_3 register 254 #define FCFG1_O_SHDW_DIE_ID_3 0x000003DC 255 256 // Internal 257 #define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x000003F8 258 259 // Internal 260 #define FCFG1_O_SHDW_ANA_TRIM 0x000003FC 261 262 // Oscillator configuration 263 #define FCFG1_O_OSC_CONF1 0x00000408 264 265 // Internal 266 #define FCFG1_O_DAC_BIAS_CNF 0x0000040C 267 268 // Internal 269 #define FCFG1_O_TFW_PROBE 0x00000418 270 271 // Internal 272 #define FCFG1_O_TFW_FT 0x0000041C 273 274 // Internal 275 #define FCFG1_O_DAC_CAL0 0x00000420 276 277 // Internal 278 #define FCFG1_O_DAC_CAL1 0x00000424 279 280 // Internal 281 #define FCFG1_O_DAC_CAL2 0x00000428 282 283 // Internal 284 #define FCFG1_O_DAC_CAL3 0x0000042C 285 286 //***************************************************************************** 287 // 288 // Register: FCFG1_O_MISC_CONF_1 289 // 290 //***************************************************************************** 291 // Field: [7:0] DEVICE_MINOR_REV 292 // 293 // HW minor revision number (a value of 0xFF shall be treated equally to 0x00). 294 // Any test of this field by SW should be implemented as a 'greater or equal' 295 // comparison as signed integer. 296 // Value may change without warning. 297 #define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 298 #define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF 299 #define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 300 301 //***************************************************************************** 302 // 303 // Register: FCFG1_O_MISC_CONF_2 304 // 305 //***************************************************************************** 306 // Field: [7:0] HPOSC_COMP_P3 307 // 308 // Internal. Only to be used through TI provided API. 309 #define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 310 #define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF 311 #define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 312 313 //***************************************************************************** 314 // 315 // Register: FCFG1_O_HPOSC_MEAS_5 316 // 317 //***************************************************************************** 318 // Field: [31:16] HPOSC_D5 319 // 320 // Internal. Only to be used through TI provided API. 321 #define FCFG1_HPOSC_MEAS_5_HPOSC_D5_W 16 322 #define FCFG1_HPOSC_MEAS_5_HPOSC_D5_M 0xFFFF0000 323 #define FCFG1_HPOSC_MEAS_5_HPOSC_D5_S 16 324 325 // Field: [15:8] HPOSC_T5 326 // 327 // Internal. Only to be used through TI provided API. 328 #define FCFG1_HPOSC_MEAS_5_HPOSC_T5_W 8 329 #define FCFG1_HPOSC_MEAS_5_HPOSC_T5_M 0x0000FF00 330 #define FCFG1_HPOSC_MEAS_5_HPOSC_T5_S 8 331 332 // Field: [7:0] HPOSC_DT5 333 // 334 // Internal. Only to be used through TI provided API. 335 #define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_W 8 336 #define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_M 0x000000FF 337 #define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_S 0 338 339 //***************************************************************************** 340 // 341 // Register: FCFG1_O_HPOSC_MEAS_4 342 // 343 //***************************************************************************** 344 // Field: [31:16] HPOSC_D4 345 // 346 // Internal. Only to be used through TI provided API. 347 #define FCFG1_HPOSC_MEAS_4_HPOSC_D4_W 16 348 #define FCFG1_HPOSC_MEAS_4_HPOSC_D4_M 0xFFFF0000 349 #define FCFG1_HPOSC_MEAS_4_HPOSC_D4_S 16 350 351 // Field: [15:8] HPOSC_T4 352 // 353 // Internal. Only to be used through TI provided API. 354 #define FCFG1_HPOSC_MEAS_4_HPOSC_T4_W 8 355 #define FCFG1_HPOSC_MEAS_4_HPOSC_T4_M 0x0000FF00 356 #define FCFG1_HPOSC_MEAS_4_HPOSC_T4_S 8 357 358 // Field: [7:0] HPOSC_DT4 359 // 360 // Internal. Only to be used through TI provided API. 361 #define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_W 8 362 #define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_M 0x000000FF 363 #define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_S 0 364 365 //***************************************************************************** 366 // 367 // Register: FCFG1_O_HPOSC_MEAS_3 368 // 369 //***************************************************************************** 370 // Field: [31:16] HPOSC_D3 371 // 372 // Internal. Only to be used through TI provided API. 373 #define FCFG1_HPOSC_MEAS_3_HPOSC_D3_W 16 374 #define FCFG1_HPOSC_MEAS_3_HPOSC_D3_M 0xFFFF0000 375 #define FCFG1_HPOSC_MEAS_3_HPOSC_D3_S 16 376 377 // Field: [15:8] HPOSC_T3 378 // 379 // Internal. Only to be used through TI provided API. 380 #define FCFG1_HPOSC_MEAS_3_HPOSC_T3_W 8 381 #define FCFG1_HPOSC_MEAS_3_HPOSC_T3_M 0x0000FF00 382 #define FCFG1_HPOSC_MEAS_3_HPOSC_T3_S 8 383 384 // Field: [7:0] HPOSC_DT3 385 // 386 // Internal. Only to be used through TI provided API. 387 #define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_W 8 388 #define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_M 0x000000FF 389 #define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_S 0 390 391 //***************************************************************************** 392 // 393 // Register: FCFG1_O_HPOSC_MEAS_2 394 // 395 //***************************************************************************** 396 // Field: [31:16] HPOSC_D2 397 // 398 // Internal. Only to be used through TI provided API. 399 #define FCFG1_HPOSC_MEAS_2_HPOSC_D2_W 16 400 #define FCFG1_HPOSC_MEAS_2_HPOSC_D2_M 0xFFFF0000 401 #define FCFG1_HPOSC_MEAS_2_HPOSC_D2_S 16 402 403 // Field: [15:8] HPOSC_T2 404 // 405 // Internal. Only to be used through TI provided API. 406 #define FCFG1_HPOSC_MEAS_2_HPOSC_T2_W 8 407 #define FCFG1_HPOSC_MEAS_2_HPOSC_T2_M 0x0000FF00 408 #define FCFG1_HPOSC_MEAS_2_HPOSC_T2_S 8 409 410 // Field: [7:0] HPOSC_DT2 411 // 412 // Internal. Only to be used through TI provided API. 413 #define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_W 8 414 #define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_M 0x000000FF 415 #define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_S 0 416 417 //***************************************************************************** 418 // 419 // Register: FCFG1_O_HPOSC_MEAS_1 420 // 421 //***************************************************************************** 422 // Field: [31:16] HPOSC_D1 423 // 424 // Internal. Only to be used through TI provided API. 425 #define FCFG1_HPOSC_MEAS_1_HPOSC_D1_W 16 426 #define FCFG1_HPOSC_MEAS_1_HPOSC_D1_M 0xFFFF0000 427 #define FCFG1_HPOSC_MEAS_1_HPOSC_D1_S 16 428 429 // Field: [15:8] HPOSC_T1 430 // 431 // Internal. Only to be used through TI provided API. 432 #define FCFG1_HPOSC_MEAS_1_HPOSC_T1_W 8 433 #define FCFG1_HPOSC_MEAS_1_HPOSC_T1_M 0x0000FF00 434 #define FCFG1_HPOSC_MEAS_1_HPOSC_T1_S 8 435 436 // Field: [7:0] HPOSC_DT1 437 // 438 // Internal. Only to be used through TI provided API. 439 #define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_W 8 440 #define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_M 0x000000FF 441 #define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_S 0 442 443 //***************************************************************************** 444 // 445 // Register: FCFG1_O_CONFIG_CC26_FE 446 // 447 //***************************************************************************** 448 // Field: [31:28] IFAMP_IB 449 // 450 // Internal. Only to be used through TI provided API. 451 #define FCFG1_CONFIG_CC26_FE_IFAMP_IB_W 4 452 #define FCFG1_CONFIG_CC26_FE_IFAMP_IB_M 0xF0000000 453 #define FCFG1_CONFIG_CC26_FE_IFAMP_IB_S 28 454 455 // Field: [27:24] LNA_IB 456 // 457 // Internal. Only to be used through TI provided API. 458 #define FCFG1_CONFIG_CC26_FE_LNA_IB_W 4 459 #define FCFG1_CONFIG_CC26_FE_LNA_IB_M 0x0F000000 460 #define FCFG1_CONFIG_CC26_FE_LNA_IB_S 24 461 462 // Field: [23:19] IFAMP_TRIM 463 // 464 // Internal. Only to be used through TI provided API. 465 #define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_W 5 466 #define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_M 0x00F80000 467 #define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_S 19 468 469 // Field: [18:14] CTL_PA0_TRIM 470 // 471 // Internal. Only to be used through TI provided API. 472 #define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_W 5 473 #define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_M 0x0007C000 474 #define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_S 14 475 476 // Field: [13] PATRIMCOMPLETE_N 477 // 478 // Internal. Only to be used through TI provided API. 479 #define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N 0x00002000 480 #define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_BITN 13 481 #define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_M 0x00002000 482 #define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_S 13 483 484 // Field: [12] RSSITRIMCOMPLETE_N 485 // 486 // Internal. Only to be used through TI provided API. 487 #define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N 0x00001000 488 #define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_BITN 12 489 #define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_M 0x00001000 490 #define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_S 12 491 492 // Field: [7:0] RSSI_OFFSET 493 // 494 // Internal. Only to be used through TI provided API. 495 #define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_W 8 496 #define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_M 0x000000FF 497 #define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_S 0 498 499 //***************************************************************************** 500 // 501 // Register: FCFG1_O_CONFIG_CC13_FE 502 // 503 //***************************************************************************** 504 // Field: [31:28] IFAMP_IB 505 // 506 // Internal. Only to be used through TI provided API. 507 #define FCFG1_CONFIG_CC13_FE_IFAMP_IB_W 4 508 #define FCFG1_CONFIG_CC13_FE_IFAMP_IB_M 0xF0000000 509 #define FCFG1_CONFIG_CC13_FE_IFAMP_IB_S 28 510 511 // Field: [27:24] LNA_IB 512 // 513 // Internal. Only to be used through TI provided API. 514 #define FCFG1_CONFIG_CC13_FE_LNA_IB_W 4 515 #define FCFG1_CONFIG_CC13_FE_LNA_IB_M 0x0F000000 516 #define FCFG1_CONFIG_CC13_FE_LNA_IB_S 24 517 518 // Field: [23:19] IFAMP_TRIM 519 // 520 // Internal. Only to be used through TI provided API. 521 #define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_W 5 522 #define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_M 0x00F80000 523 #define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_S 19 524 525 // Field: [18:14] CTL_PA0_TRIM 526 // 527 // Internal. Only to be used through TI provided API. 528 #define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_W 5 529 #define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_M 0x0007C000 530 #define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_S 14 531 532 // Field: [13] PATRIMCOMPLETE_N 533 // 534 // Internal. Only to be used through TI provided API. 535 #define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N 0x00002000 536 #define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_BITN 13 537 #define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_M 0x00002000 538 #define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_S 13 539 540 // Field: [12] RSSITRIMCOMPLETE_N 541 // 542 // Internal. Only to be used through TI provided API. 543 #define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N 0x00001000 544 #define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_BITN 12 545 #define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_M 0x00001000 546 #define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_S 12 547 548 // Field: [7:0] RSSI_OFFSET 549 // 550 // Internal. Only to be used through TI provided API. 551 #define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_W 8 552 #define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_M 0x000000FF 553 #define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_S 0 554 555 //***************************************************************************** 556 // 557 // Register: FCFG1_O_CONFIG_RF_COMMON 558 // 559 //***************************************************************************** 560 // Field: [31] DISABLE_CORNER_CAP 561 // 562 // Internal. Only to be used through TI provided API. 563 #define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP 0x80000000 564 #define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_BITN 31 565 #define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_M 0x80000000 566 #define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_S 31 567 568 // Field: [30:25] SLDO_TRIM_OUTPUT 569 // 570 // Internal. Only to be used through TI provided API. 571 #define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_W 6 572 #define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_M 0x7E000000 573 #define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_S 25 574 575 // Field: [21] PA20DBMTRIMCOMPLETE_N 576 // 577 // Internal. Only to be used through TI provided API. 578 #define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N 0x00200000 579 #define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_BITN 21 580 #define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_M 0x00200000 581 #define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_S 21 582 583 // Field: [20:16] CTL_PA_20DBM_TRIM 584 // 585 // Internal. Only to be used through TI provided API. 586 #define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_W 5 587 #define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_M 0x001F0000 588 #define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_S 16 589 590 // Field: [15:9] RFLDO_TRIM_OUTPUT 591 // 592 // Internal. Only to be used through TI provided API. 593 #define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_W 7 594 #define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_M 0x0000FE00 595 #define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_S 9 596 597 // Field: [8:6] QUANTCTLTHRES 598 // 599 // Internal. Only to be used through TI provided API. 600 #define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_W 3 601 #define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_M 0x000001C0 602 #define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_S 6 603 604 // Field: [5:0] DACTRIM 605 // 606 // Internal. Only to be used through TI provided API. 607 #define FCFG1_CONFIG_RF_COMMON_DACTRIM_W 6 608 #define FCFG1_CONFIG_RF_COMMON_DACTRIM_M 0x0000003F 609 #define FCFG1_CONFIG_RF_COMMON_DACTRIM_S 0 610 611 //***************************************************************************** 612 // 613 // Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 614 // 615 //***************************************************************************** 616 // Field: [31:28] MIN_ALLOWED_RTRIM 617 // 618 // Internal. Only to be used through TI provided API. 619 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_W 4 620 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 621 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_S 28 622 623 // Field: [27:12] RFC_MDM_DEMIQMC0 624 // 625 // Internal. Only to be used through TI provided API. 626 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_W 16 627 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 628 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_S 12 629 630 // Field: [11:6] LDOVCO_TRIM_OUTPUT 631 // 632 // Internal. Only to be used through TI provided API. 633 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_W 6 634 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 635 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_S 6 636 637 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 638 // 639 // Internal. Only to be used through TI provided API. 640 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 641 0x00000020 642 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 643 5 644 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 645 0x00000020 646 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 647 5 648 649 //***************************************************************************** 650 // 651 // Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 652 // 653 //***************************************************************************** 654 // Field: [31:28] MIN_ALLOWED_RTRIM 655 // 656 // Internal. Only to be used through TI provided API. 657 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_W 4 658 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 659 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_S 28 660 661 // Field: [27:12] RFC_MDM_DEMIQMC0 662 // 663 // Internal. Only to be used through TI provided API. 664 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_W 16 665 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 666 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_S 12 667 668 // Field: [11:6] LDOVCO_TRIM_OUTPUT 669 // 670 // Internal. Only to be used through TI provided API. 671 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_W 6 672 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 673 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_S 6 674 675 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 676 // 677 // Internal. Only to be used through TI provided API. 678 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 679 0x00000020 680 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 681 5 682 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 683 0x00000020 684 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 685 5 686 687 //***************************************************************************** 688 // 689 // Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G 690 // 691 //***************************************************************************** 692 // Field: [31:28] MIN_ALLOWED_RTRIM 693 // 694 // Internal. Only to be used through TI provided API. 695 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_W 4 696 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 697 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_S 28 698 699 // Field: [27:12] RFC_MDM_DEMIQMC0 700 // 701 // Internal. Only to be used through TI provided API. 702 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_W 16 703 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 704 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_S 12 705 706 // Field: [11:6] LDOVCO_TRIM_OUTPUT 707 // 708 // Internal. Only to be used through TI provided API. 709 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_W 6 710 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 711 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_S 6 712 713 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 714 // 715 // Internal. Only to be used through TI provided API. 716 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 717 0x00000020 718 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 719 5 720 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 721 0x00000020 722 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 723 5 724 725 //***************************************************************************** 726 // 727 // Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G 728 // 729 //***************************************************************************** 730 // Field: [31:28] MIN_ALLOWED_RTRIM 731 // 732 // Internal. Only to be used through TI provided API. 733 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_W 4 734 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 735 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_S 28 736 737 // Field: [27:12] RFC_MDM_DEMIQMC0 738 // 739 // Internal. Only to be used through TI provided API. 740 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_W 16 741 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 742 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_S 12 743 744 // Field: [11:6] LDOVCO_TRIM_OUTPUT 745 // 746 // Internal. Only to be used through TI provided API. 747 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_W 6 748 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 749 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_S 6 750 751 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 752 // 753 // Internal. Only to be used through TI provided API. 754 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 755 0x00000020 756 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 757 5 758 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 759 0x00000020 760 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 761 5 762 763 //***************************************************************************** 764 // 765 // Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC26 766 // 767 //***************************************************************************** 768 // Field: [31:28] MIN_ALLOWED_RTRIM 769 // 770 // Internal. Only to be used through TI provided API. 771 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_W 4 772 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 773 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_S 28 774 775 // Field: [27:12] RFC_MDM_DEMIQMC0 776 // 777 // Internal. Only to be used through TI provided API. 778 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_W 16 779 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 780 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_S 12 781 782 // Field: [11:6] LDOVCO_TRIM_OUTPUT 783 // 784 // Internal. Only to be used through TI provided API. 785 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_W 6 786 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 787 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_S 6 788 789 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 790 // 791 // Internal. Only to be used through TI provided API. 792 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 793 0x00000020 794 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 795 5 796 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 797 0x00000020 798 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 799 5 800 801 //***************************************************************************** 802 // 803 // Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC13 804 // 805 //***************************************************************************** 806 // Field: [31:28] MIN_ALLOWED_RTRIM 807 // 808 // Internal. Only to be used through TI provided API. 809 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_W 4 810 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 811 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_S 28 812 813 // Field: [27:12] RFC_MDM_DEMIQMC0 814 // 815 // Internal. Only to be used through TI provided API. 816 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_W 16 817 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 818 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_S 12 819 820 // Field: [11:6] LDOVCO_TRIM_OUTPUT 821 // 822 // Internal. Only to be used through TI provided API. 823 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_W 6 824 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 825 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_S 6 826 827 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 828 // 829 // Internal. Only to be used through TI provided API. 830 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 831 0x00000020 832 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 833 5 834 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 835 0x00000020 836 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 837 5 838 839 //***************************************************************************** 840 // 841 // Register: FCFG1_O_CONFIG_SYNTH_DIV5 842 // 843 //***************************************************************************** 844 // Field: [31:28] MIN_ALLOWED_RTRIM 845 // 846 // Internal. Only to be used through TI provided API. 847 #define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_W 4 848 #define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_M 0xF0000000 849 #define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_S 28 850 851 // Field: [27:12] RFC_MDM_DEMIQMC0 852 // 853 // Internal. Only to be used through TI provided API. 854 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 855 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 856 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 857 858 // Field: [11:6] LDOVCO_TRIM_OUTPUT 859 // 860 // Internal. Only to be used through TI provided API. 861 #define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 862 #define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 863 #define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 864 865 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 866 // 867 // Internal. Only to be used through TI provided API. 868 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 0x00000020 869 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 870 5 871 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 872 0x00000020 873 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 874 5 875 876 //***************************************************************************** 877 // 878 // Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC26 879 // 880 //***************************************************************************** 881 // Field: [31:28] MIN_ALLOWED_RTRIM 882 // 883 // Internal. Only to be used through TI provided API. 884 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_W 4 885 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 886 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_S 28 887 888 // Field: [27:12] RFC_MDM_DEMIQMC0 889 // 890 // Internal. Only to be used through TI provided API. 891 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_W 16 892 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 893 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_S 12 894 895 // Field: [11:6] LDOVCO_TRIM_OUTPUT 896 // 897 // Internal. Only to be used through TI provided API. 898 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_W 6 899 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 900 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_S 6 901 902 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 903 // 904 // Internal. Only to be used through TI provided API. 905 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 906 0x00000020 907 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 908 5 909 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 910 0x00000020 911 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 912 5 913 914 //***************************************************************************** 915 // 916 // Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC13 917 // 918 //***************************************************************************** 919 // Field: [31:28] MIN_ALLOWED_RTRIM 920 // 921 // Internal. Only to be used through TI provided API. 922 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_W 4 923 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 924 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_S 28 925 926 // Field: [27:12] RFC_MDM_DEMIQMC0 927 // 928 // Internal. Only to be used through TI provided API. 929 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_W 16 930 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 931 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_S 12 932 933 // Field: [11:6] LDOVCO_TRIM_OUTPUT 934 // 935 // Internal. Only to be used through TI provided API. 936 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_W 6 937 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 938 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_S 6 939 940 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 941 // 942 // Internal. Only to be used through TI provided API. 943 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 944 0x00000020 945 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 946 5 947 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 948 0x00000020 949 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 950 5 951 952 //***************************************************************************** 953 // 954 // Register: FCFG1_O_CONFIG_SYNTH_DIV10 955 // 956 //***************************************************************************** 957 // Field: [31:28] MIN_ALLOWED_RTRIM 958 // 959 // Internal. Only to be used through TI provided API. 960 #define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_W 4 961 #define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_M 0xF0000000 962 #define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_S 28 963 964 // Field: [27:12] RFC_MDM_DEMIQMC0 965 // 966 // Internal. Only to be used through TI provided API. 967 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 968 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 969 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 970 971 // Field: [11:6] LDOVCO_TRIM_OUTPUT 972 // 973 // Internal. Only to be used through TI provided API. 974 #define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 975 #define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 976 #define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 977 978 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 979 // 980 // Internal. Only to be used through TI provided API. 981 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 982 0x00000020 983 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 984 5 985 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 986 0x00000020 987 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 988 5 989 990 //***************************************************************************** 991 // 992 // Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC26 993 // 994 //***************************************************************************** 995 // Field: [31:28] MIN_ALLOWED_RTRIM 996 // 997 // Internal. Only to be used through TI provided API. 998 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_W 4 999 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 1000 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_S 28 1001 1002 // Field: [27:12] RFC_MDM_DEMIQMC0 1003 // 1004 // Internal. Only to be used through TI provided API. 1005 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_W 16 1006 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 1007 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_S 12 1008 1009 // Field: [11:6] LDOVCO_TRIM_OUTPUT 1010 // 1011 // Internal. Only to be used through TI provided API. 1012 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_W 6 1013 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 1014 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_S 6 1015 1016 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 1017 // 1018 // Internal. Only to be used through TI provided API. 1019 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 1020 0x00000020 1021 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 1022 5 1023 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 1024 0x00000020 1025 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 1026 5 1027 1028 //***************************************************************************** 1029 // 1030 // Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC13 1031 // 1032 //***************************************************************************** 1033 // Field: [31:28] MIN_ALLOWED_RTRIM 1034 // 1035 // Internal. Only to be used through TI provided API. 1036 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_W 4 1037 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 1038 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_S 28 1039 1040 // Field: [27:12] RFC_MDM_DEMIQMC0 1041 // 1042 // Internal. Only to be used through TI provided API. 1043 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_W 16 1044 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 1045 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_S 12 1046 1047 // Field: [11:6] LDOVCO_TRIM_OUTPUT 1048 // 1049 // Internal. Only to be used through TI provided API. 1050 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_W 6 1051 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 1052 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_S 6 1053 1054 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 1055 // 1056 // Internal. Only to be used through TI provided API. 1057 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 1058 0x00000020 1059 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 1060 5 1061 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 1062 0x00000020 1063 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 1064 5 1065 1066 //***************************************************************************** 1067 // 1068 // Register: FCFG1_O_CONFIG_SYNTH_DIV15 1069 // 1070 //***************************************************************************** 1071 // Field: [31:28] MIN_ALLOWED_RTRIM 1072 // 1073 // Internal. Only to be used through TI provided API. 1074 #define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_W 4 1075 #define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_M 0xF0000000 1076 #define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_S 28 1077 1078 // Field: [27:12] RFC_MDM_DEMIQMC0 1079 // 1080 // Internal. Only to be used through TI provided API. 1081 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 1082 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 1083 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 1084 1085 // Field: [11:6] LDOVCO_TRIM_OUTPUT 1086 // 1087 // Internal. Only to be used through TI provided API. 1088 #define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 1089 #define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 1090 #define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 1091 1092 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 1093 // 1094 // Internal. Only to be used through TI provided API. 1095 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 1096 0x00000020 1097 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 1098 5 1099 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 1100 0x00000020 1101 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 1102 5 1103 1104 //***************************************************************************** 1105 // 1106 // Register: FCFG1_O_CONFIG_SYNTH_DIV30 1107 // 1108 //***************************************************************************** 1109 // Field: [31:28] MIN_ALLOWED_RTRIM 1110 // 1111 // Internal. Only to be used through TI provided API. 1112 #define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_W 4 1113 #define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_M 0xF0000000 1114 #define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_S 28 1115 1116 // Field: [27:12] RFC_MDM_DEMIQMC0 1117 // 1118 // Internal. Only to be used through TI provided API. 1119 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 1120 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 1121 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 1122 1123 // Field: [11:6] LDOVCO_TRIM_OUTPUT 1124 // 1125 // Internal. Only to be used through TI provided API. 1126 #define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 1127 #define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 1128 #define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 1129 1130 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 1131 // 1132 // Internal. Only to be used through TI provided API. 1133 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 1134 0x00000020 1135 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 1136 5 1137 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 1138 0x00000020 1139 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 1140 5 1141 1142 //***************************************************************************** 1143 // 1144 // Register: FCFG1_O_FLASH_NUMBER 1145 // 1146 //***************************************************************************** 1147 // Field: [31:0] LOT_NUMBER 1148 // 1149 // Number of the manufacturing lot that produced this unit. 1150 #define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 1151 #define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF 1152 #define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 1153 1154 //***************************************************************************** 1155 // 1156 // Register: FCFG1_O_FLASH_COORDINATE 1157 // 1158 //***************************************************************************** 1159 // Field: [31:16] XCOORDINATE 1160 // 1161 // X coordinate of this unit on the wafer. 1162 #define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 1163 #define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 1164 #define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 1165 1166 // Field: [15:0] YCOORDINATE 1167 // 1168 // Y coordinate of this unit on the wafer. 1169 #define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 1170 #define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF 1171 #define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 1172 1173 //***************************************************************************** 1174 // 1175 // Register: FCFG1_O_FLASH_E_P 1176 // 1177 //***************************************************************************** 1178 // Field: [31:24] PSU 1179 // 1180 // Internal. Only to be used through TI provided API. 1181 #define FCFG1_FLASH_E_P_PSU_W 8 1182 #define FCFG1_FLASH_E_P_PSU_M 0xFF000000 1183 #define FCFG1_FLASH_E_P_PSU_S 24 1184 1185 // Field: [23:16] ESU 1186 // 1187 // Internal. Only to be used through TI provided API. 1188 #define FCFG1_FLASH_E_P_ESU_W 8 1189 #define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 1190 #define FCFG1_FLASH_E_P_ESU_S 16 1191 1192 // Field: [15:8] PVSU 1193 // 1194 // Internal. Only to be used through TI provided API. 1195 #define FCFG1_FLASH_E_P_PVSU_W 8 1196 #define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 1197 #define FCFG1_FLASH_E_P_PVSU_S 8 1198 1199 // Field: [7:0] EVSU 1200 // 1201 // Internal. Only to be used through TI provided API. 1202 #define FCFG1_FLASH_E_P_EVSU_W 8 1203 #define FCFG1_FLASH_E_P_EVSU_M 0x000000FF 1204 #define FCFG1_FLASH_E_P_EVSU_S 0 1205 1206 //***************************************************************************** 1207 // 1208 // Register: FCFG1_O_FLASH_C_E_P_R 1209 // 1210 //***************************************************************************** 1211 // Field: [31:24] RVSU 1212 // 1213 // Internal. Only to be used through TI provided API. 1214 #define FCFG1_FLASH_C_E_P_R_RVSU_W 8 1215 #define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 1216 #define FCFG1_FLASH_C_E_P_R_RVSU_S 24 1217 1218 // Field: [23:16] PV_ACCESS 1219 // 1220 // Internal. Only to be used through TI provided API. 1221 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 1222 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 1223 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 1224 1225 // Field: [15:12] A_EXEZ_SETUP 1226 // 1227 // Internal. Only to be used through TI provided API. 1228 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 1229 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 1230 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 1231 1232 // Field: [11:0] CVSU 1233 // 1234 // Internal. Only to be used through TI provided API. 1235 #define FCFG1_FLASH_C_E_P_R_CVSU_W 12 1236 #define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF 1237 #define FCFG1_FLASH_C_E_P_R_CVSU_S 0 1238 1239 //***************************************************************************** 1240 // 1241 // Register: FCFG1_O_FLASH_P_R_PV 1242 // 1243 //***************************************************************************** 1244 // Field: [31:24] PH 1245 // 1246 // Internal. Only to be used through TI provided API. 1247 #define FCFG1_FLASH_P_R_PV_PH_W 8 1248 #define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 1249 #define FCFG1_FLASH_P_R_PV_PH_S 24 1250 1251 // Field: [23:16] RH 1252 // 1253 // Internal. Only to be used through TI provided API. 1254 #define FCFG1_FLASH_P_R_PV_RH_W 8 1255 #define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 1256 #define FCFG1_FLASH_P_R_PV_RH_S 16 1257 1258 // Field: [15:8] PVH 1259 // 1260 // Internal. Only to be used through TI provided API. 1261 #define FCFG1_FLASH_P_R_PV_PVH_W 8 1262 #define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 1263 #define FCFG1_FLASH_P_R_PV_PVH_S 8 1264 1265 // Field: [7:0] PVH2 1266 // 1267 // Internal. Only to be used through TI provided API. 1268 #define FCFG1_FLASH_P_R_PV_PVH2_W 8 1269 #define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF 1270 #define FCFG1_FLASH_P_R_PV_PVH2_S 0 1271 1272 //***************************************************************************** 1273 // 1274 // Register: FCFG1_O_FLASH_EH_SEQ 1275 // 1276 //***************************************************************************** 1277 // Field: [31:24] EH 1278 // 1279 // Internal. Only to be used through TI provided API. 1280 #define FCFG1_FLASH_EH_SEQ_EH_W 8 1281 #define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 1282 #define FCFG1_FLASH_EH_SEQ_EH_S 24 1283 1284 // Field: [23:16] SEQ 1285 // 1286 // Internal. Only to be used through TI provided API. 1287 #define FCFG1_FLASH_EH_SEQ_SEQ_W 8 1288 #define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 1289 #define FCFG1_FLASH_EH_SEQ_SEQ_S 16 1290 1291 // Field: [15:12] VSTAT 1292 // 1293 // Internal. Only to be used through TI provided API. 1294 #define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 1295 #define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 1296 #define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 1297 1298 // Field: [11:0] SM_FREQUENCY 1299 // 1300 // Internal. Only to be used through TI provided API. 1301 #define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 1302 #define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF 1303 #define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 1304 1305 //***************************************************************************** 1306 // 1307 // Register: FCFG1_O_FLASH_VHV_E 1308 // 1309 //***************************************************************************** 1310 // Field: [31:16] VHV_E_START 1311 // 1312 // Internal. Only to be used through TI provided API. 1313 #define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 1314 #define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 1315 #define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 1316 1317 // Field: [15:0] VHV_E_STEP_HIGHT 1318 // 1319 // Internal. Only to be used through TI provided API. 1320 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 1321 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF 1322 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 1323 1324 //***************************************************************************** 1325 // 1326 // Register: FCFG1_O_FLASH_PP 1327 // 1328 //***************************************************************************** 1329 // Field: [31:24] PUMP_SU 1330 // 1331 // Internal. Only to be used through TI provided API. 1332 #define FCFG1_FLASH_PP_PUMP_SU_W 8 1333 #define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 1334 #define FCFG1_FLASH_PP_PUMP_SU_S 24 1335 1336 // Field: [23:16] TRIM3P4 1337 // 1338 // Internal. Only to be used through TI provided API. 1339 #define FCFG1_FLASH_PP_TRIM3P4_W 8 1340 #define FCFG1_FLASH_PP_TRIM3P4_M 0x00FF0000 1341 #define FCFG1_FLASH_PP_TRIM3P4_S 16 1342 1343 // Field: [15:0] MAX_PP 1344 // 1345 // Internal. Only to be used through TI provided API. 1346 #define FCFG1_FLASH_PP_MAX_PP_W 16 1347 #define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF 1348 #define FCFG1_FLASH_PP_MAX_PP_S 0 1349 1350 //***************************************************************************** 1351 // 1352 // Register: FCFG1_O_FLASH_PROG_EP 1353 // 1354 //***************************************************************************** 1355 // Field: [31:16] MAX_EP 1356 // 1357 // Internal. Only to be used through TI provided API. 1358 #define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 1359 #define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 1360 #define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 1361 1362 // Field: [15:0] PROGRAM_PW 1363 // 1364 // Internal. Only to be used through TI provided API. 1365 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 1366 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF 1367 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 1368 1369 //***************************************************************************** 1370 // 1371 // Register: FCFG1_O_FLASH_ERA_PW 1372 // 1373 //***************************************************************************** 1374 // Field: [31:0] ERASE_PW 1375 // 1376 // Internal. Only to be used through TI provided API. 1377 #define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 1378 #define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF 1379 #define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 1380 1381 //***************************************************************************** 1382 // 1383 // Register: FCFG1_O_FLASH_VHV 1384 // 1385 //***************************************************************************** 1386 // Field: [27:24] TRIM13_P 1387 // 1388 // Internal. Only to be used through TI provided API. 1389 #define FCFG1_FLASH_VHV_TRIM13_P_W 4 1390 #define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 1391 #define FCFG1_FLASH_VHV_TRIM13_P_S 24 1392 1393 // Field: [19:16] VHV_P 1394 // 1395 // Internal. Only to be used through TI provided API. 1396 #define FCFG1_FLASH_VHV_VHV_P_W 4 1397 #define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 1398 #define FCFG1_FLASH_VHV_VHV_P_S 16 1399 1400 // Field: [11:8] TRIM13_E 1401 // 1402 // Internal. Only to be used through TI provided API. 1403 #define FCFG1_FLASH_VHV_TRIM13_E_W 4 1404 #define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 1405 #define FCFG1_FLASH_VHV_TRIM13_E_S 8 1406 1407 // Field: [3:0] VHV_E 1408 // 1409 // Internal. Only to be used through TI provided API. 1410 #define FCFG1_FLASH_VHV_VHV_E_W 4 1411 #define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F 1412 #define FCFG1_FLASH_VHV_VHV_E_S 0 1413 1414 //***************************************************************************** 1415 // 1416 // Register: FCFG1_O_FLASH_VHV_PV 1417 // 1418 //***************************************************************************** 1419 // Field: [27:24] TRIM13_PV 1420 // 1421 // Internal. Only to be used through TI provided API. 1422 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 1423 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 1424 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 1425 1426 // Field: [19:16] VHV_PV 1427 // 1428 // Internal. Only to be used through TI provided API. 1429 #define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 1430 #define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 1431 #define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 1432 1433 // Field: [15:8] VCG2P5 1434 // 1435 // Internal. Only to be used through TI provided API. 1436 #define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 1437 #define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 1438 #define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 1439 1440 // Field: [7:0] VINH 1441 // 1442 // Internal. Only to be used through TI provided API. 1443 #define FCFG1_FLASH_VHV_PV_VINH_W 8 1444 #define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF 1445 #define FCFG1_FLASH_VHV_PV_VINH_S 0 1446 1447 //***************************************************************************** 1448 // 1449 // Register: FCFG1_O_FLASH_V 1450 // 1451 //***************************************************************************** 1452 // Field: [31:24] VSL_P 1453 // 1454 // Internal. Only to be used through TI provided API. 1455 #define FCFG1_FLASH_V_VSL_P_W 8 1456 #define FCFG1_FLASH_V_VSL_P_M 0xFF000000 1457 #define FCFG1_FLASH_V_VSL_P_S 24 1458 1459 // Field: [23:16] VWL_P 1460 // 1461 // Internal. Only to be used through TI provided API. 1462 #define FCFG1_FLASH_V_VWL_P_W 8 1463 #define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 1464 #define FCFG1_FLASH_V_VWL_P_S 16 1465 1466 // Field: [15:8] V_READ 1467 // 1468 // Internal. Only to be used through TI provided API. 1469 #define FCFG1_FLASH_V_V_READ_W 8 1470 #define FCFG1_FLASH_V_V_READ_M 0x0000FF00 1471 #define FCFG1_FLASH_V_V_READ_S 8 1472 1473 // Field: [7:0] TRIM0P8 1474 // 1475 // Internal. Only to be used through TI provided API. 1476 #define FCFG1_FLASH_V_TRIM0P8_W 8 1477 #define FCFG1_FLASH_V_TRIM0P8_M 0x000000FF 1478 #define FCFG1_FLASH_V_TRIM0P8_S 0 1479 1480 //***************************************************************************** 1481 // 1482 // Register: FCFG1_O_USER_ID 1483 // 1484 //***************************************************************************** 1485 // Field: [31:28] PG_REV 1486 // 1487 // Field used to distinguish revisions of the device 1488 #define FCFG1_USER_ID_PG_REV_W 4 1489 #define FCFG1_USER_ID_PG_REV_M 0xF0000000 1490 #define FCFG1_USER_ID_PG_REV_S 28 1491 1492 // Field: [27:26] VER 1493 // 1494 // Version number. 1495 // 1496 // 0x0: Bits [25:12] of this register has the stated meaning. 1497 // 1498 // Any other setting indicate a different encoding of these bits. 1499 #define FCFG1_USER_ID_VER_W 2 1500 #define FCFG1_USER_ID_VER_M 0x0C000000 1501 #define FCFG1_USER_ID_VER_S 26 1502 1503 // Field: [25] PA 1504 // 1505 // 0: Does not support 20dBm PA 1506 // 1: Supports 20dBM PA 1507 #define FCFG1_USER_ID_PA 0x02000000 1508 #define FCFG1_USER_ID_PA_BITN 25 1509 #define FCFG1_USER_ID_PA_M 0x02000000 1510 #define FCFG1_USER_ID_PA_S 25 1511 1512 // Field: [23] CC13 1513 // 1514 // 0: CC26xx device type 1515 // 1: CC13xx device type 1516 #define FCFG1_USER_ID_CC13 0x00800000 1517 #define FCFG1_USER_ID_CC13_BITN 23 1518 #define FCFG1_USER_ID_CC13_M 0x00800000 1519 #define FCFG1_USER_ID_CC13_S 23 1520 1521 // Field: [22:19] SEQUENCE 1522 // 1523 // Sequence. 1524 // 1525 // Used to differentiate between marketing/orderable product where other fields 1526 // of this register are the same (temp range, flash size, voltage range etc) 1527 #define FCFG1_USER_ID_SEQUENCE_W 4 1528 #define FCFG1_USER_ID_SEQUENCE_M 0x00780000 1529 #define FCFG1_USER_ID_SEQUENCE_S 19 1530 1531 // Field: [18:16] PKG 1532 // 1533 // Package type. 1534 // 1535 // 0x0: 4x4mm QFN (RHB) package 1536 // 0x1: 5x5mm QFN (RSM) package 1537 // 0x2: 7x7mm QFN (RGZ) package 1538 // 0x3: Wafer sale package (naked die) 1539 // 0x4: WCSP (YFV) 1540 // 0x5: 7x7mm QFN package with Wettable Flanks 1541 // 1542 // Other values are reserved for future use. 1543 // Packages available for a specific device are shown in the device datasheet. 1544 #define FCFG1_USER_ID_PKG_W 3 1545 #define FCFG1_USER_ID_PKG_M 0x00070000 1546 #define FCFG1_USER_ID_PKG_S 16 1547 1548 // Field: [15:12] PROTOCOL 1549 // 1550 // Protocols supported. 1551 // 1552 // 0x1: BLE 1553 // 0x2: RF4CE 1554 // 0x4: Zigbee/6lowpan 1555 // 0x8: Proprietary 1556 // 1557 // More than one protocol can be supported on same device - values above are 1558 // then combined. 1559 #define FCFG1_USER_ID_PROTOCOL_W 4 1560 #define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 1561 #define FCFG1_USER_ID_PROTOCOL_S 12 1562 1563 //***************************************************************************** 1564 // 1565 // Register: FCFG1_O_FLASH_OTP_DATA3 1566 // 1567 //***************************************************************************** 1568 // Field: [31:23] EC_STEP_SIZE 1569 // 1570 // Internal. Only to be used through TI provided API. 1571 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 1572 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 1573 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 1574 1575 // Field: [22] DO_PRECOND 1576 // 1577 // Internal. Only to be used through TI provided API. 1578 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 1579 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 1580 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 1581 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 1582 1583 // Field: [21:18] MAX_EC_LEVEL 1584 // 1585 // Internal. Only to be used through TI provided API. 1586 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 1587 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 1588 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 1589 1590 // Field: [17:16] TRIM_1P7 1591 // 1592 // Internal. Only to be used through TI provided API. 1593 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 1594 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 1595 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 1596 1597 // Field: [15:8] FLASH_SIZE 1598 // 1599 // Internal. Only to be used through TI provided API. 1600 #define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 1601 #define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 1602 #define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 1603 1604 // Field: [7:0] WAIT_SYSCODE 1605 // 1606 // Internal. Only to be used through TI provided API. 1607 #define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 1608 #define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF 1609 #define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 1610 1611 //***************************************************************************** 1612 // 1613 // Register: FCFG1_O_ANA2_TRIM 1614 // 1615 //***************************************************************************** 1616 // Field: [31] RCOSCHFCTRIMFRACT_EN 1617 // 1618 // Internal. Only to be used through TI provided API. 1619 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 1620 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 1621 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 1622 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 1623 1624 // Field: [30:26] RCOSCHFCTRIMFRACT 1625 // 1626 // Internal. Only to be used through TI provided API. 1627 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 1628 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 1629 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 1630 1631 // Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR 1632 // 1633 // Internal. Only to be used through TI provided API. 1634 #define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 1635 #define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 1636 #define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 1637 1638 // Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM 1639 // 1640 // Internal. Only to be used through TI provided API. 1641 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 1642 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 1643 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 1644 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 1645 1646 // Field: [21:15] NANOAMP_RES_TRIM 1647 // 1648 // Internal. Only to be used through TI provided API. 1649 #define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 7 1650 #define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F8000 1651 #define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 15 1652 1653 // Field: [11] DITHER_EN 1654 // 1655 // Internal. Only to be used through TI provided API. 1656 #define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 1657 #define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 1658 #define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 1659 #define FCFG1_ANA2_TRIM_DITHER_EN_S 11 1660 1661 // Field: [10:8] DCDC_IPEAK 1662 // 1663 // Internal. Only to be used through TI provided API. 1664 #define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 1665 #define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 1666 #define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 1667 1668 // Field: [7:6] DEAD_TIME_TRIM 1669 // 1670 // Internal. Only to be used through TI provided API. 1671 #define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 1672 #define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 1673 #define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 1674 1675 // Field: [5:3] DCDC_LOW_EN_SEL 1676 // 1677 // Internal. Only to be used through TI provided API. 1678 #define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 1679 #define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 1680 #define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 1681 1682 // Field: [2:0] DCDC_HIGH_EN_SEL 1683 // 1684 // Internal. Only to be used through TI provided API. 1685 #define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 1686 #define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 1687 #define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 1688 1689 //***************************************************************************** 1690 // 1691 // Register: FCFG1_O_LDO_TRIM 1692 // 1693 //***************************************************************************** 1694 // Field: [28:24] VDDR_TRIM_SLEEP 1695 // 1696 // Internal. Only to be used through TI provided API. 1697 #define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 1698 #define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 1699 #define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 1700 1701 // Field: [18:16] GLDO_CURSRC 1702 // 1703 // Internal. Only to be used through TI provided API. 1704 #define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 1705 #define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 1706 #define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 1707 1708 // Field: [12:11] ITRIM_DIGLDO_LOAD 1709 // 1710 // Internal. Only to be used through TI provided API. 1711 #define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 1712 #define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 1713 #define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 1714 1715 // Field: [10:8] ITRIM_UDIGLDO 1716 // 1717 // Internal. Only to be used through TI provided API. 1718 #define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 1719 #define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 1720 #define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 1721 1722 // Field: [2:0] VTRIM_DELTA 1723 // 1724 // Internal. Only to be used through TI provided API. 1725 #define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 1726 #define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 1727 #define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 1728 1729 //***************************************************************************** 1730 // 1731 // Register: FCFG1_O_MAC_BLE_0 1732 // 1733 //***************************************************************************** 1734 // Field: [31:0] ADDR_0_31 1735 // 1736 // The first 32-bits of the 64-bit MAC BLE address 1737 #define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 1738 #define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF 1739 #define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 1740 1741 //***************************************************************************** 1742 // 1743 // Register: FCFG1_O_MAC_BLE_1 1744 // 1745 //***************************************************************************** 1746 // Field: [31:0] ADDR_32_63 1747 // 1748 // The last 32-bits of the 64-bit MAC BLE address 1749 #define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 1750 #define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF 1751 #define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 1752 1753 //***************************************************************************** 1754 // 1755 // Register: FCFG1_O_MAC_15_4_0 1756 // 1757 //***************************************************************************** 1758 // Field: [31:0] ADDR_0_31 1759 // 1760 // The first 32-bits of the 64-bit MAC 15.4 address 1761 #define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 1762 #define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF 1763 #define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 1764 1765 //***************************************************************************** 1766 // 1767 // Register: FCFG1_O_MAC_15_4_1 1768 // 1769 //***************************************************************************** 1770 // Field: [31:0] ADDR_32_63 1771 // 1772 // The last 32-bits of the 64-bit MAC 15.4 address 1773 #define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 1774 #define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF 1775 #define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 1776 1777 //***************************************************************************** 1778 // 1779 // Register: FCFG1_O_FLASH_OTP_DATA4 1780 // 1781 //***************************************************************************** 1782 // Field: [31] STANDBY_MODE_SEL_INT_WRT 1783 // 1784 // Internal. Only to be used through TI provided API. 1785 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 1786 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 1787 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 1788 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 1789 1790 // Field: [30:29] STANDBY_PW_SEL_INT_WRT 1791 // 1792 // Internal. Only to be used through TI provided API. 1793 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 1794 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 1795 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 1796 1797 // Field: [28] DIS_STANDBY_INT_WRT 1798 // 1799 // Internal. Only to be used through TI provided API. 1800 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 1801 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 1802 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 1803 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 1804 1805 // Field: [27] DIS_IDLE_INT_WRT 1806 // 1807 // Internal. Only to be used through TI provided API. 1808 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 1809 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 1810 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 1811 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 1812 1813 // Field: [26:24] VIN_AT_X_INT_WRT 1814 // 1815 // Internal. Only to be used through TI provided API. 1816 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 1817 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 1818 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 1819 1820 // Field: [23] STANDBY_MODE_SEL_EXT_WRT 1821 // 1822 // Internal. Only to be used through TI provided API. 1823 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 1824 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 1825 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 1826 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 1827 1828 // Field: [22:21] STANDBY_PW_SEL_EXT_WRT 1829 // 1830 // Internal. Only to be used through TI provided API. 1831 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 1832 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 1833 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 1834 1835 // Field: [20] DIS_STANDBY_EXT_WRT 1836 // 1837 // Internal. Only to be used through TI provided API. 1838 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 1839 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 1840 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 1841 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 1842 1843 // Field: [19] DIS_IDLE_EXT_WRT 1844 // 1845 // Internal. Only to be used through TI provided API. 1846 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 1847 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 1848 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 1849 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 1850 1851 // Field: [18:16] VIN_AT_X_EXT_WRT 1852 // 1853 // Internal. Only to be used through TI provided API. 1854 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 1855 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 1856 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 1857 1858 // Field: [15] STANDBY_MODE_SEL_INT_RD 1859 // 1860 // Internal. Only to be used through TI provided API. 1861 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 1862 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 1863 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 1864 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 1865 1866 // Field: [14:13] STANDBY_PW_SEL_INT_RD 1867 // 1868 // Internal. Only to be used through TI provided API. 1869 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 1870 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 1871 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 1872 1873 // Field: [12] DIS_STANDBY_INT_RD 1874 // 1875 // Internal. Only to be used through TI provided API. 1876 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 1877 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 1878 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 1879 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 1880 1881 // Field: [11] DIS_IDLE_INT_RD 1882 // 1883 // Internal. Only to be used through TI provided API. 1884 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 1885 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 1886 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 1887 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 1888 1889 // Field: [10:8] VIN_AT_X_INT_RD 1890 // 1891 // Internal. Only to be used through TI provided API. 1892 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 1893 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 1894 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 1895 1896 // Field: [7] STANDBY_MODE_SEL_EXT_RD 1897 // 1898 // Internal. Only to be used through TI provided API. 1899 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 1900 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 1901 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 1902 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 1903 1904 // Field: [6:5] STANDBY_PW_SEL_EXT_RD 1905 // 1906 // Internal. Only to be used through TI provided API. 1907 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 1908 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 1909 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 1910 1911 // Field: [4] DIS_STANDBY_EXT_RD 1912 // 1913 // Internal. Only to be used through TI provided API. 1914 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 1915 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 1916 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 1917 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 1918 1919 // Field: [3] DIS_IDLE_EXT_RD 1920 // 1921 // Internal. Only to be used through TI provided API. 1922 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 1923 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 1924 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 1925 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 1926 1927 // Field: [2:0] VIN_AT_X_EXT_RD 1928 // 1929 // Internal. Only to be used through TI provided API. 1930 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 1931 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 1932 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 1933 1934 //***************************************************************************** 1935 // 1936 // Register: FCFG1_O_MISC_TRIM 1937 // 1938 //***************************************************************************** 1939 // Field: [16:12] TRIM_RECHARGE_COMP_OFFSET 1940 // 1941 // Internal. Only to be used through TI provided API. 1942 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_W 5 1943 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_M 0x0001F000 1944 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_S 12 1945 1946 // Field: [11:8] TRIM_RECHARGE_COMP_REFLEVEL 1947 // 1948 // Internal. Only to be used through TI provided API. 1949 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_W 4 1950 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M 0x00000F00 1951 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S 8 1952 1953 // Field: [7:0] TEMPVSLOPE 1954 // 1955 // Signed byte value representing the TEMP slope with battery voltage, in 1956 // degrees C / V, with four fractional bits. 1957 #define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 1958 #define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF 1959 #define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 1960 1961 //***************************************************************************** 1962 // 1963 // Register: FCFG1_O_RCOSC_HF_TEMPCOMP 1964 // 1965 //***************************************************************************** 1966 // Field: [31:24] FINE_RESISTOR 1967 // 1968 // Internal. Only to be used through TI provided API. 1969 #define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 1970 #define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 1971 #define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 1972 1973 // Field: [23:16] CTRIM 1974 // 1975 // Internal. Only to be used through TI provided API. 1976 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 1977 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 1978 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 1979 1980 // Field: [15:8] CTRIMFRACT_QUAD 1981 // 1982 // Internal. Only to be used through TI provided API. 1983 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 1984 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 1985 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 1986 1987 // Field: [7:0] CTRIMFRACT_SLOPE 1988 // 1989 // Internal. Only to be used through TI provided API. 1990 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 1991 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF 1992 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 1993 1994 //***************************************************************************** 1995 // 1996 // Register: FCFG1_O_ICEPICK_DEVICE_ID 1997 // 1998 //***************************************************************************** 1999 // Field: [31:28] PG_REV 2000 // 2001 // Field used to distinguish revisions of the device. 2002 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 2003 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 2004 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 2005 2006 // Field: [27:12] WAFER_ID 2007 // 2008 // Field used to identify silicon die. 2009 #define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 2010 #define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 2011 #define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 2012 2013 // Field: [11:0] MANUFACTURER_ID 2014 // 2015 // Manufacturer code. 2016 // 2017 // 0x02F: Texas Instruments 2018 #define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 2019 #define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF 2020 #define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 2021 2022 //***************************************************************************** 2023 // 2024 // Register: FCFG1_O_FCFG1_REVISION 2025 // 2026 //***************************************************************************** 2027 // Field: [31:0] REV 2028 // 2029 // The revision number of the FCFG1 layout. This value will be read by 2030 // application SW in order to determine which FCFG1 parameters that have valid 2031 // values. This revision number must be incremented by 1 before any devices are 2032 // to be produced if the FCFG1 layout has changed since the previous production 2033 // of devices. 2034 // Value migth change without warning. 2035 #define FCFG1_FCFG1_REVISION_REV_W 32 2036 #define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF 2037 #define FCFG1_FCFG1_REVISION_REV_S 0 2038 2039 //***************************************************************************** 2040 // 2041 // Register: FCFG1_O_MISC_OTP_DATA 2042 // 2043 //***************************************************************************** 2044 // Field: [31:28] RCOSC_HF_ITUNE 2045 // 2046 // Internal. Only to be used through TI provided API. 2047 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 2048 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 2049 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 2050 2051 // Field: [27:20] RCOSC_HF_CRIM 2052 // 2053 // Internal. Only to be used through TI provided API. 2054 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 2055 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 2056 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 2057 2058 // Field: [19:15] PER_M 2059 // 2060 // Internal. Only to be used through TI provided API. 2061 #define FCFG1_MISC_OTP_DATA_PER_M_W 5 2062 #define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 2063 #define FCFG1_MISC_OTP_DATA_PER_M_S 15 2064 2065 // Field: [14:12] PER_E 2066 // 2067 // Internal. Only to be used through TI provided API. 2068 #define FCFG1_MISC_OTP_DATA_PER_E_W 3 2069 #define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 2070 #define FCFG1_MISC_OTP_DATA_PER_E_S 12 2071 2072 //***************************************************************************** 2073 // 2074 // Register: FCFG1_O_IOCONF 2075 // 2076 //***************************************************************************** 2077 // Field: [6:0] GPIO_CNT 2078 // 2079 // Number of available DIOs. 2080 #define FCFG1_IOCONF_GPIO_CNT_W 7 2081 #define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F 2082 #define FCFG1_IOCONF_GPIO_CNT_S 0 2083 2084 //***************************************************************************** 2085 // 2086 // Register: FCFG1_O_CONFIG_IF_ADC 2087 // 2088 //***************************************************************************** 2089 // Field: [31:28] FF2ADJ 2090 // 2091 // Internal. Only to be used through TI provided API. 2092 #define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 2093 #define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 2094 #define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 2095 2096 // Field: [27:24] FF3ADJ 2097 // 2098 // Internal. Only to be used through TI provided API. 2099 #define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 2100 #define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 2101 #define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 2102 2103 // Field: [23:20] INT3ADJ 2104 // 2105 // Internal. Only to be used through TI provided API. 2106 #define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 2107 #define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 2108 #define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 2109 2110 // Field: [19:16] FF1ADJ 2111 // 2112 // Internal. Only to be used through TI provided API. 2113 #define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 2114 #define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 2115 #define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 2116 2117 // Field: [15:14] AAFCAP 2118 // 2119 // Internal. Only to be used through TI provided API. 2120 #define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 2121 #define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 2122 #define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 2123 2124 // Field: [13:10] INT2ADJ 2125 // 2126 // Internal. Only to be used through TI provided API. 2127 #define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 2128 #define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 2129 #define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 2130 2131 // Field: [9:5] IFDIGLDO_TRIM_OUTPUT 2132 // 2133 // Internal. Only to be used through TI provided API. 2134 #define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 2135 #define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 2136 #define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 2137 2138 // Field: [4:0] IFANALDO_TRIM_OUTPUT 2139 // 2140 // Internal. Only to be used through TI provided API. 2141 #define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 2142 #define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F 2143 #define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 2144 2145 //***************************************************************************** 2146 // 2147 // Register: FCFG1_O_CONFIG_OSC_TOP 2148 // 2149 //***************************************************************************** 2150 // Field: [29:26] XOSC_HF_ROW_Q12 2151 // 2152 // Internal. Only to be used through TI provided API. 2153 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 2154 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 2155 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 2156 2157 // Field: [25:10] XOSC_HF_COLUMN_Q12 2158 // 2159 // Internal. Only to be used through TI provided API. 2160 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 2161 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 2162 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 2163 2164 // Field: [9:2] RCOSCLF_CTUNE_TRIM 2165 // 2166 // Internal. Only to be used through TI provided API. 2167 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 2168 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC 2169 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 2170 2171 // Field: [1:0] RCOSCLF_RTUNE_TRIM 2172 // 2173 // Internal. Only to be used through TI provided API. 2174 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 2175 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 2176 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 2177 2178 //***************************************************************************** 2179 // 2180 // Register: FCFG1_O_SOC_ADC_ABS_GAIN 2181 // 2182 //***************************************************************************** 2183 // Field: [15:0] SOC_ADC_ABS_GAIN_TEMP1 2184 // 2185 // SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated 2186 // in production test.. 2187 #define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 2188 #define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF 2189 #define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 2190 2191 //***************************************************************************** 2192 // 2193 // Register: FCFG1_O_SOC_ADC_REL_GAIN 2194 // 2195 //***************************************************************************** 2196 // Field: [15:0] SOC_ADC_REL_GAIN_TEMP1 2197 // 2198 // SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated 2199 // in production test.. 2200 #define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 2201 #define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF 2202 #define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 2203 2204 //***************************************************************************** 2205 // 2206 // Register: FCFG1_O_SOC_ADC_OFFSET_INT 2207 // 2208 //***************************************************************************** 2209 // Field: [23:16] SOC_ADC_REL_OFFSET_TEMP1 2210 // 2211 // SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed 2212 // 8-bit number. Calculated in production test.. 2213 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 2214 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 2215 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 2216 2217 // Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 2218 // 2219 // SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed 2220 // 8-bit number. Calculated in production test.. 2221 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 2222 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF 2223 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 2224 2225 //***************************************************************************** 2226 // 2227 // Register: FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 2228 // 2229 //***************************************************************************** 2230 // Field: [5:0] SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 2231 // 2232 // Internal. Only to be used through TI provided API. 2233 #define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_W \ 2234 6 2235 #define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_M \ 2236 0x0000003F 2237 #define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S \ 2238 0 2239 2240 //***************************************************************************** 2241 // 2242 // Register: FCFG1_O_AMPCOMP_TH1 2243 // 2244 //***************************************************************************** 2245 // Field: [23:18] HPMRAMP3_LTH 2246 // 2247 // Internal. Only to be used through TI provided API. 2248 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 2249 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 2250 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 2251 2252 // Field: [15:10] HPMRAMP3_HTH 2253 // 2254 // Internal. Only to be used through TI provided API. 2255 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 2256 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 2257 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 2258 2259 // Field: [9:6] IBIASCAP_LPTOHP_OL_CNT 2260 // 2261 // Internal. Only to be used through TI provided API. 2262 #define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 2263 #define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 2264 #define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 2265 2266 // Field: [5:0] HPMRAMP1_TH 2267 // 2268 // Internal. Only to be used through TI provided API. 2269 #define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 2270 #define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F 2271 #define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 2272 2273 //***************************************************************************** 2274 // 2275 // Register: FCFG1_O_AMPCOMP_TH2 2276 // 2277 //***************************************************************************** 2278 // Field: [31:26] LPMUPDATE_LTH 2279 // 2280 // Internal. Only to be used through TI provided API. 2281 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 2282 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 2283 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 2284 2285 // Field: [23:18] LPMUPDATE_HTM 2286 // 2287 // Internal. Only to be used through TI provided API. 2288 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 2289 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 2290 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 2291 2292 // Field: [15:10] ADC_COMP_AMPTH_LPM 2293 // 2294 // Internal. Only to be used through TI provided API. 2295 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 2296 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 2297 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 2298 2299 // Field: [7:2] ADC_COMP_AMPTH_HPM 2300 // 2301 // Internal. Only to be used through TI provided API. 2302 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 2303 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC 2304 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 2305 2306 //***************************************************************************** 2307 // 2308 // Register: FCFG1_O_AMPCOMP_CTRL1 2309 // 2310 //***************************************************************************** 2311 // Field: [30] AMPCOMP_REQ_MODE 2312 // 2313 // Internal. Only to be used through TI provided API. 2314 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 2315 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 2316 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 2317 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 2318 2319 // Field: [23:20] IBIAS_OFFSET 2320 // 2321 // Internal. Only to be used through TI provided API. 2322 #define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 2323 #define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 2324 #define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 2325 2326 // Field: [19:16] IBIAS_INIT 2327 // 2328 // Internal. Only to be used through TI provided API. 2329 #define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 2330 #define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 2331 #define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 2332 2333 // Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL 2334 // 2335 // Internal. Only to be used through TI provided API. 2336 #define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 2337 #define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 2338 #define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 2339 2340 // Field: [7:4] CAP_STEP 2341 // 2342 // Internal. Only to be used through TI provided API. 2343 #define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 2344 #define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 2345 #define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 2346 2347 // Field: [3:0] IBIASCAP_HPTOLP_OL_CNT 2348 // 2349 // Internal. Only to be used through TI provided API. 2350 #define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 2351 #define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F 2352 #define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 2353 2354 //***************************************************************************** 2355 // 2356 // Register: FCFG1_O_ANABYPASS_VALUE2 2357 // 2358 //***************************************************************************** 2359 // Field: [13:0] XOSC_HF_IBIASTHERM 2360 // 2361 // Internal. Only to be used through TI provided API. 2362 #define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 2363 #define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF 2364 #define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 2365 2366 //***************************************************************************** 2367 // 2368 // Register: FCFG1_O_VOLT_TRIM 2369 // 2370 //***************************************************************************** 2371 // Field: [28:24] VDDR_TRIM_HH 2372 // 2373 // Internal. Only to be used through TI provided API. 2374 #define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 2375 #define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 2376 #define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 2377 2378 // Field: [20:16] VDDR_TRIM_H 2379 // 2380 // Internal. Only to be used through TI provided API. 2381 #define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 2382 #define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 2383 #define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 2384 2385 // Field: [12:8] VDDR_TRIM_SLEEP_H 2386 // 2387 // Internal. Only to be used through TI provided API. 2388 #define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 2389 #define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 2390 #define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 2391 2392 // Field: [4:0] TRIMBOD_H 2393 // 2394 // Internal. Only to be used through TI provided API. 2395 #define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 2396 #define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F 2397 #define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 2398 2399 //***************************************************************************** 2400 // 2401 // Register: FCFG1_O_OSC_CONF 2402 // 2403 //***************************************************************************** 2404 // Field: [29] ADC_SH_VBUF_EN 2405 // 2406 // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. 2407 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 2408 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 2409 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 2410 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 2411 2412 // Field: [28] ADC_SH_MODE_EN 2413 // 2414 // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. 2415 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 2416 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 2417 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 2418 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 2419 2420 // Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM 2421 // 2422 // Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. 2423 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 2424 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 2425 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 2426 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 2427 2428 // Field: [26:25] XOSCLF_REGULATOR_TRIM 2429 // 2430 // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. 2431 #define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 2432 #define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 2433 #define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 2434 2435 // Field: [24:21] XOSCLF_CMIRRWR_RATIO 2436 // 2437 // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. 2438 #define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 2439 #define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 2440 #define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 2441 2442 // Field: [20:19] XOSC_HF_FAST_START 2443 // 2444 // Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. 2445 #define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 2446 #define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 2447 #define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 2448 2449 // Field: [18] XOSC_OPTION 2450 // 2451 // 0: XOSC_HF unavailable (may not be bonded out) 2452 // 1: XOSC_HF available (default) 2453 #define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 2454 #define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 2455 #define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 2456 #define FCFG1_OSC_CONF_XOSC_OPTION_S 18 2457 2458 // Field: [17] HPOSC_OPTION 2459 // 2460 // Internal. Only to be used through TI provided API. 2461 #define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 2462 #define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 2463 #define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 2464 #define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 2465 2466 // Field: [16] HPOSC_BIAS_HOLD_MODE_EN 2467 // 2468 // Internal. Only to be used through TI provided API. 2469 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 2470 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 2471 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 2472 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 2473 2474 // Field: [15:12] HPOSC_CURRMIRR_RATIO 2475 // 2476 // Internal. Only to be used through TI provided API. 2477 #define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 2478 #define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 2479 #define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 2480 2481 // Field: [11:8] HPOSC_BIAS_RES_SET 2482 // 2483 // Internal. Only to be used through TI provided API. 2484 #define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 2485 #define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 2486 #define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 2487 2488 // Field: [7] HPOSC_FILTER_EN 2489 // 2490 // Internal. Only to be used through TI provided API. 2491 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 2492 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 2493 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 2494 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 2495 2496 // Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY 2497 // 2498 // Internal. Only to be used through TI provided API. 2499 #define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 2500 #define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 2501 #define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 2502 2503 // Field: [2:1] HPOSC_SERIES_CAP 2504 // 2505 // Internal. Only to be used through TI provided API. 2506 #define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 2507 #define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 2508 #define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 2509 2510 // Field: [0] HPOSC_DIV3_BYPASS 2511 // 2512 // Internal. Only to be used through TI provided API. 2513 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 2514 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 2515 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 2516 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 2517 2518 //***************************************************************************** 2519 // 2520 // Register: FCFG1_O_FREQ_OFFSET 2521 // 2522 //***************************************************************************** 2523 // Field: [31:16] HPOSC_COMP_P0 2524 // 2525 // Internal. Only to be used through TI provided API. 2526 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 2527 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 2528 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 2529 2530 // Field: [15:8] HPOSC_COMP_P1 2531 // 2532 // Internal. Only to be used through TI provided API. 2533 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 2534 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 2535 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 2536 2537 // Field: [7:0] HPOSC_COMP_P2 2538 // 2539 // Internal. Only to be used through TI provided API. 2540 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 2541 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF 2542 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 2543 2544 //***************************************************************************** 2545 // 2546 // Register: FCFG1_O_MISC_OTP_DATA_1 2547 // 2548 //***************************************************************************** 2549 // Field: [28:27] PEAK_DET_ITRIM 2550 // 2551 // Internal. Only to be used through TI provided API. 2552 #define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 2553 #define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 2554 #define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 2555 2556 // Field: [26:24] HP_BUF_ITRIM 2557 // 2558 // Internal. Only to be used through TI provided API. 2559 #define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 2560 #define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 2561 #define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 2562 2563 // Field: [23:22] LP_BUF_ITRIM 2564 // 2565 // Internal. Only to be used through TI provided API. 2566 #define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 2567 #define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 2568 #define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 2569 2570 // Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE 2571 // 2572 // Internal. Only to be used through TI provided API. 2573 #define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 2574 #define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 2575 #define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 2576 2577 // Field: [19:10] HPM_IBIAS_WAIT_CNT 2578 // 2579 // Internal. Only to be used through TI provided API. 2580 #define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 2581 #define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 2582 #define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 2583 2584 // Field: [9:4] LPM_IBIAS_WAIT_CNT 2585 // 2586 // Internal. Only to be used through TI provided API. 2587 #define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 2588 #define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 2589 #define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 2590 2591 // Field: [3:0] IDAC_STEP 2592 // 2593 // Internal. Only to be used through TI provided API. 2594 #define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 2595 #define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F 2596 #define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 2597 2598 //***************************************************************************** 2599 // 2600 // Register: FCFG1_O_SHDW_DIE_ID_0 2601 // 2602 //***************************************************************************** 2603 // Field: [31:0] ID_31_0 2604 // 2605 // Shadow of DIE_ID_0 register in eFuse row number 5 2606 #define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 2607 #define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF 2608 #define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 2609 2610 //***************************************************************************** 2611 // 2612 // Register: FCFG1_O_SHDW_DIE_ID_1 2613 // 2614 //***************************************************************************** 2615 // Field: [31:0] ID_63_32 2616 // 2617 // Shadow of DIE_ID_1 register in eFuse row number 6 2618 #define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 2619 #define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF 2620 #define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 2621 2622 //***************************************************************************** 2623 // 2624 // Register: FCFG1_O_SHDW_DIE_ID_2 2625 // 2626 //***************************************************************************** 2627 // Field: [31:0] ID_95_64 2628 // 2629 // Shadow of DIE_ID_2 register in eFuse row number 7 2630 #define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 2631 #define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF 2632 #define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 2633 2634 //***************************************************************************** 2635 // 2636 // Register: FCFG1_O_SHDW_DIE_ID_3 2637 // 2638 //***************************************************************************** 2639 // Field: [31:0] ID_127_96 2640 // 2641 // Shadow of DIE_ID_3 register in eFuse row number 8 2642 #define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 2643 #define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF 2644 #define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 2645 2646 //***************************************************************************** 2647 // 2648 // Register: FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 2649 // 2650 //***************************************************************************** 2651 // Field: [26:23] TRIMMAG 2652 // 2653 // Internal. Only to be used through TI provided API. 2654 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 2655 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 2656 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 2657 2658 // Field: [22:18] TRIMIREF 2659 // 2660 // Internal. Only to be used through TI provided API. 2661 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 2662 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 2663 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 2664 2665 // Field: [17:16] ITRIM_DIG_LDO 2666 // 2667 // Internal. Only to be used through TI provided API. 2668 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 2669 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 2670 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 2671 2672 // Field: [15:12] VTRIM_DIG 2673 // 2674 // Internal. Only to be used through TI provided API. 2675 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 2676 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 2677 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 2678 2679 // Field: [11:8] VTRIM_COARSE 2680 // 2681 // Internal. Only to be used through TI provided API. 2682 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 2683 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 2684 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 2685 2686 // Field: [7:0] RCOSCHF_CTRIM 2687 // 2688 // Internal. Only to be used through TI provided API. 2689 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 2690 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF 2691 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 2692 2693 //***************************************************************************** 2694 // 2695 // Register: FCFG1_O_SHDW_ANA_TRIM 2696 // 2697 //***************************************************************************** 2698 // Field: [30] ALT_VDDR_TRIM 2699 // 2700 // Internal. Only to be used through TI provided API. 2701 #define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM 0x40000000 2702 #define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_BITN 30 2703 #define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_M 0x40000000 2704 #define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_S 30 2705 2706 // Field: [29] DET_LOGIC_DIS 2707 // 2708 // Internal. Only to be used through TI provided API. 2709 #define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS 0x20000000 2710 #define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_BITN 29 2711 #define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_M 0x20000000 2712 #define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_S 29 2713 2714 // Field: [28:27] BOD_BANDGAP_TRIM_CNF_EXT 2715 // 2716 // Internal. Only to be used through TI provided API. 2717 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_W 2 2718 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_M 0x18000000 2719 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_S 27 2720 2721 // Field: [26:25] BOD_BANDGAP_TRIM_CNF 2722 // 2723 // Internal. Only to be used through TI provided API. 2724 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 2725 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 2726 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 2727 2728 // Field: [24] VDDR_ENABLE_PG1 2729 // 2730 // Internal. Only to be used through TI provided API. 2731 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 2732 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 2733 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 2734 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 2735 2736 // Field: [23] VDDR_OK_HYS 2737 // 2738 // Internal. Only to be used through TI provided API. 2739 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 2740 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 2741 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 2742 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 2743 2744 // Field: [22:21] IPTAT_TRIM 2745 // 2746 // Internal. Only to be used through TI provided API. 2747 #define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 2748 #define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 2749 #define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 2750 2751 // Field: [20:16] VDDR_TRIM 2752 // 2753 // Internal. Only to be used through TI provided API. 2754 #define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 2755 #define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 2756 #define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 2757 2758 // Field: [15:11] TRIMBOD_INTMODE 2759 // 2760 // Internal. Only to be used through TI provided API. 2761 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 2762 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 2763 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 2764 2765 // Field: [10:6] TRIMBOD_EXTMODE 2766 // 2767 // Internal. Only to be used through TI provided API. 2768 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 2769 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 2770 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 2771 2772 // Field: [5:0] TRIMTEMP 2773 // 2774 // Internal. Only to be used through TI provided API. 2775 #define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 2776 #define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F 2777 #define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 2778 2779 //***************************************************************************** 2780 // 2781 // Register: FCFG1_O_OSC_CONF1 2782 // 2783 //***************************************************************************** 2784 // Field: [31:28] RCOSC_MF_BIAS_HTEMP 2785 // 2786 // Internal. Only to be used through TI provided API. 2787 #define FCFG1_OSC_CONF1_RCOSC_MF_BIAS_HTEMP_W 4 2788 #define FCFG1_OSC_CONF1_RCOSC_MF_BIAS_HTEMP_M 0xF0000000 2789 #define FCFG1_OSC_CONF1_RCOSC_MF_BIAS_HTEMP_S 28 2790 2791 // Field: [27] RCOSC_MF_TEMP_DEPEND_MODE 2792 // 2793 // Internal. Only to be used through TI provided API. 2794 #define FCFG1_OSC_CONF1_RCOSC_MF_TEMP_DEPEND_MODE 0x08000000 2795 #define FCFG1_OSC_CONF1_RCOSC_MF_TEMP_DEPEND_MODE_BITN 27 2796 #define FCFG1_OSC_CONF1_RCOSC_MF_TEMP_DEPEND_MODE_M 0x08000000 2797 #define FCFG1_OSC_CONF1_RCOSC_MF_TEMP_DEPEND_MODE_S 27 2798 2799 // Field: [26] RCOSC_MF_SINGLE_TRIM_METHOD 2800 // 2801 // Internal. Only to be used through TI provided API. 2802 #define FCFG1_OSC_CONF1_RCOSC_MF_SINGLE_TRIM_METHOD 0x04000000 2803 #define FCFG1_OSC_CONF1_RCOSC_MF_SINGLE_TRIM_METHOD_BITN 26 2804 #define FCFG1_OSC_CONF1_RCOSC_MF_SINGLE_TRIM_METHOD_M 0x04000000 2805 #define FCFG1_OSC_CONF1_RCOSC_MF_SINGLE_TRIM_METHOD_S 26 2806 2807 // Field: [3:0] RCOSC_MF_BIAS_ADJ 2808 // 2809 // Internal. Only to be used through TI provided API. 2810 #define FCFG1_OSC_CONF1_RCOSC_MF_BIAS_ADJ_W 4 2811 #define FCFG1_OSC_CONF1_RCOSC_MF_BIAS_ADJ_M 0x0000000F 2812 #define FCFG1_OSC_CONF1_RCOSC_MF_BIAS_ADJ_S 0 2813 2814 //***************************************************************************** 2815 // 2816 // Register: FCFG1_O_DAC_BIAS_CNF 2817 // 2818 //***************************************************************************** 2819 // Field: [17:12] LPM_TRIM_IOUT 2820 // 2821 // Internal. Only to be used through TI provided API. 2822 #define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_W 6 2823 #define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M 0x0003F000 2824 #define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S 12 2825 2826 // Field: [11:9] LPM_BIAS_WIDTH_TRIM 2827 // 2828 // Internal. Only to be used through TI provided API. 2829 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_W 3 2830 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M 0x00000E00 2831 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S 9 2832 2833 // Field: [8] LPM_BIAS_BACKUP_EN 2834 // 2835 // Internal. Only to be used through TI provided API. 2836 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN 0x00000100 2837 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_BITN 8 2838 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_M 0x00000100 2839 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_S 8 2840 2841 //***************************************************************************** 2842 // 2843 // Register: FCFG1_O_TFW_PROBE 2844 // 2845 //***************************************************************************** 2846 // Field: [31:0] REV 2847 // 2848 // Internal. Only to be used through TI provided API. 2849 #define FCFG1_TFW_PROBE_REV_W 32 2850 #define FCFG1_TFW_PROBE_REV_M 0xFFFFFFFF 2851 #define FCFG1_TFW_PROBE_REV_S 0 2852 2853 //***************************************************************************** 2854 // 2855 // Register: FCFG1_O_TFW_FT 2856 // 2857 //***************************************************************************** 2858 // Field: [31:0] REV 2859 // 2860 // Internal. Only to be used through TI provided API. 2861 #define FCFG1_TFW_FT_REV_W 32 2862 #define FCFG1_TFW_FT_REV_M 0xFFFFFFFF 2863 #define FCFG1_TFW_FT_REV_S 0 2864 2865 //***************************************************************************** 2866 // 2867 // Register: FCFG1_O_DAC_CAL0 2868 // 2869 //***************************************************************************** 2870 // Field: [31:16] SOC_DAC_VOUT_CAL_DECOUPLE_C2 2871 // 2872 // Internal. Only to be used through TI provided API. 2873 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_W 16 2874 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_M 0xFFFF0000 2875 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_S 16 2876 2877 // Field: [15:0] SOC_DAC_VOUT_CAL_DECOUPLE_C1 2878 // 2879 // Internal. Only to be used through TI provided API. 2880 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_W 16 2881 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_M 0x0000FFFF 2882 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_S 0 2883 2884 //***************************************************************************** 2885 // 2886 // Register: FCFG1_O_DAC_CAL1 2887 // 2888 //***************************************************************************** 2889 // Field: [31:16] SOC_DAC_VOUT_CAL_PRECH_C2 2890 // 2891 // Internal. Only to be used through TI provided API. 2892 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_W 16 2893 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_M 0xFFFF0000 2894 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_S 16 2895 2896 // Field: [15:0] SOC_DAC_VOUT_CAL_PRECH_C1 2897 // 2898 // Internal. Only to be used through TI provided API. 2899 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_W 16 2900 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_M 0x0000FFFF 2901 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_S 0 2902 2903 //***************************************************************************** 2904 // 2905 // Register: FCFG1_O_DAC_CAL2 2906 // 2907 //***************************************************************************** 2908 // Field: [31:16] SOC_DAC_VOUT_CAL_ADCREF_C2 2909 // 2910 // Internal. Only to be used through TI provided API. 2911 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_W 16 2912 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_M 0xFFFF0000 2913 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_S 16 2914 2915 // Field: [15:0] SOC_DAC_VOUT_CAL_ADCREF_C1 2916 // 2917 // Internal. Only to be used through TI provided API. 2918 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_W 16 2919 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_M 0x0000FFFF 2920 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_S 0 2921 2922 //***************************************************************************** 2923 // 2924 // Register: FCFG1_O_DAC_CAL3 2925 // 2926 //***************************************************************************** 2927 // Field: [31:16] SOC_DAC_VOUT_CAL_VDDS_C2 2928 // 2929 // Internal. Only to be used through TI provided API. 2930 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_W 16 2931 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_M 0xFFFF0000 2932 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_S 16 2933 2934 // Field: [15:0] SOC_DAC_VOUT_CAL_VDDS_C1 2935 // 2936 // Internal. Only to be used through TI provided API. 2937 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_W 16 2938 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_M 0x0000FFFF 2939 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_S 0 2940 2941 2942 #endif // __FCFG1__ 2943
