1 /****************************************************************************** 2 * Filename: hw_event_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_EVENT_H__ 38 #define __HW_EVENT_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // EVENT component 44 // 45 //***************************************************************************** 46 // Output Selection for CPU Interrupt 0 47 #define EVENT_O_CPUIRQSEL0 0x00000000 48 49 // Output Selection for CPU Interrupt 1 50 #define EVENT_O_CPUIRQSEL1 0x00000004 51 52 // Output Selection for CPU Interrupt 2 53 #define EVENT_O_CPUIRQSEL2 0x00000008 54 55 // Output Selection for CPU Interrupt 3 56 #define EVENT_O_CPUIRQSEL3 0x0000000C 57 58 // Output Selection for CPU Interrupt 4 59 #define EVENT_O_CPUIRQSEL4 0x00000010 60 61 // Output Selection for CPU Interrupt 5 62 #define EVENT_O_CPUIRQSEL5 0x00000014 63 64 // Output Selection for CPU Interrupt 6 65 #define EVENT_O_CPUIRQSEL6 0x00000018 66 67 // Output Selection for CPU Interrupt 7 68 #define EVENT_O_CPUIRQSEL7 0x0000001C 69 70 // Output Selection for CPU Interrupt 8 71 #define EVENT_O_CPUIRQSEL8 0x00000020 72 73 // Output Selection for CPU Interrupt 9 74 #define EVENT_O_CPUIRQSEL9 0x00000024 75 76 // Output Selection for CPU Interrupt 10 77 #define EVENT_O_CPUIRQSEL10 0x00000028 78 79 // Output Selection for CPU Interrupt 11 80 #define EVENT_O_CPUIRQSEL11 0x0000002C 81 82 // Output Selection for CPU Interrupt 12 83 #define EVENT_O_CPUIRQSEL12 0x00000030 84 85 // Output Selection for CPU Interrupt 13 86 #define EVENT_O_CPUIRQSEL13 0x00000034 87 88 // Output Selection for CPU Interrupt 14 89 #define EVENT_O_CPUIRQSEL14 0x00000038 90 91 // Output Selection for CPU Interrupt 15 92 #define EVENT_O_CPUIRQSEL15 0x0000003C 93 94 // Output Selection for CPU Interrupt 16 95 #define EVENT_O_CPUIRQSEL16 0x00000040 96 97 // Output Selection for CPU Interrupt 17 98 #define EVENT_O_CPUIRQSEL17 0x00000044 99 100 // Output Selection for CPU Interrupt 18 101 #define EVENT_O_CPUIRQSEL18 0x00000048 102 103 // Output Selection for CPU Interrupt 19 104 #define EVENT_O_CPUIRQSEL19 0x0000004C 105 106 // Output Selection for CPU Interrupt 20 107 #define EVENT_O_CPUIRQSEL20 0x00000050 108 109 // Output Selection for CPU Interrupt 21 110 #define EVENT_O_CPUIRQSEL21 0x00000054 111 112 // Output Selection for CPU Interrupt 22 113 #define EVENT_O_CPUIRQSEL22 0x00000058 114 115 // Output Selection for CPU Interrupt 23 116 #define EVENT_O_CPUIRQSEL23 0x0000005C 117 118 // Output Selection for CPU Interrupt 24 119 #define EVENT_O_CPUIRQSEL24 0x00000060 120 121 // Output Selection for CPU Interrupt 25 122 #define EVENT_O_CPUIRQSEL25 0x00000064 123 124 // Output Selection for CPU Interrupt 26 125 #define EVENT_O_CPUIRQSEL26 0x00000068 126 127 // Output Selection for CPU Interrupt 27 128 #define EVENT_O_CPUIRQSEL27 0x0000006C 129 130 // Output Selection for CPU Interrupt 28 131 #define EVENT_O_CPUIRQSEL28 0x00000070 132 133 // Output Selection for CPU Interrupt 29 134 #define EVENT_O_CPUIRQSEL29 0x00000074 135 136 // Output Selection for CPU Interrupt 30 137 #define EVENT_O_CPUIRQSEL30 0x00000078 138 139 // Output Selection for CPU Interrupt 31 140 #define EVENT_O_CPUIRQSEL31 0x0000007C 141 142 // Output Selection for CPU Interrupt 32 143 #define EVENT_O_CPUIRQSEL32 0x00000080 144 145 // Output Selection for CPU Interrupt 33 146 #define EVENT_O_CPUIRQSEL33 0x00000084 147 148 // Output Selection for CPU Interrupt 34 149 #define EVENT_O_CPUIRQSEL34 0x00000088 150 151 // Output Selection for CPU Interrupt 35 152 #define EVENT_O_CPUIRQSEL35 0x0000008C 153 154 // Output Selection for CPU Interrupt 36 155 #define EVENT_O_CPUIRQSEL36 0x00000090 156 157 // Output Selection for CPU Interrupt 37 158 #define EVENT_O_CPUIRQSEL37 0x00000094 159 160 // Output Selection for RFC Event 0 161 #define EVENT_O_RFCSEL0 0x00000100 162 163 // Output Selection for RFC Event 1 164 #define EVENT_O_RFCSEL1 0x00000104 165 166 // Output Selection for RFC Event 2 167 #define EVENT_O_RFCSEL2 0x00000108 168 169 // Output Selection for RFC Event 3 170 #define EVENT_O_RFCSEL3 0x0000010C 171 172 // Output Selection for RFC Event 4 173 #define EVENT_O_RFCSEL4 0x00000110 174 175 // Output Selection for RFC Event 5 176 #define EVENT_O_RFCSEL5 0x00000114 177 178 // Output Selection for RFC Event 6 179 #define EVENT_O_RFCSEL6 0x00000118 180 181 // Output Selection for RFC Event 7 182 #define EVENT_O_RFCSEL7 0x0000011C 183 184 // Output Selection for RFC Event 8 185 #define EVENT_O_RFCSEL8 0x00000120 186 187 // Output Selection for RFC Event 9 188 #define EVENT_O_RFCSEL9 0x00000124 189 190 // Output Selection for GPT0 0 191 #define EVENT_O_GPT0ACAPTSEL 0x00000200 192 193 // Output Selection for GPT0 1 194 #define EVENT_O_GPT0BCAPTSEL 0x00000204 195 196 // Output Selection for GPT1 0 197 #define EVENT_O_GPT1ACAPTSEL 0x00000300 198 199 // Output Selection for GPT1 1 200 #define EVENT_O_GPT1BCAPTSEL 0x00000304 201 202 // Output Selection for GPT2 0 203 #define EVENT_O_GPT2ACAPTSEL 0x00000400 204 205 // Output Selection for GPT2 1 206 #define EVENT_O_GPT2BCAPTSEL 0x00000404 207 208 // Output Selection for DMA Channel 1 SREQ 209 #define EVENT_O_UDMACH1SSEL 0x00000508 210 211 // Output Selection for DMA Channel 1 REQ 212 #define EVENT_O_UDMACH1BSEL 0x0000050C 213 214 // Output Selection for DMA Channel 2 SREQ 215 #define EVENT_O_UDMACH2SSEL 0x00000510 216 217 // Output Selection for DMA Channel 2 REQ 218 #define EVENT_O_UDMACH2BSEL 0x00000514 219 220 // Output Selection for DMA Channel 3 SREQ 221 #define EVENT_O_UDMACH3SSEL 0x00000518 222 223 // Output Selection for DMA Channel 3 REQ 224 #define EVENT_O_UDMACH3BSEL 0x0000051C 225 226 // Output Selection for DMA Channel 4 SREQ 227 #define EVENT_O_UDMACH4SSEL 0x00000520 228 229 // Output Selection for DMA Channel 4 REQ 230 #define EVENT_O_UDMACH4BSEL 0x00000524 231 232 // Output Selection for DMA Channel 5 SREQ 233 #define EVENT_O_UDMACH5SSEL 0x00000528 234 235 // Output Selection for DMA Channel 5 REQ 236 #define EVENT_O_UDMACH5BSEL 0x0000052C 237 238 // Output Selection for DMA Channel 6 SREQ 239 #define EVENT_O_UDMACH6SSEL 0x00000530 240 241 // Output Selection for DMA Channel 6 REQ 242 #define EVENT_O_UDMACH6BSEL 0x00000534 243 244 // Output Selection for DMA Channel 7 SREQ 245 #define EVENT_O_UDMACH7SSEL 0x00000538 246 247 // Output Selection for DMA Channel 7 REQ 248 #define EVENT_O_UDMACH7BSEL 0x0000053C 249 250 // Output Selection for DMA Channel 8 SREQ 251 #define EVENT_O_UDMACH8SSEL 0x00000540 252 253 // Output Selection for DMA Channel 8 REQ 254 #define EVENT_O_UDMACH8BSEL 0x00000544 255 256 // Output Selection for DMA Channel 9 SREQ 257 #define EVENT_O_UDMACH9SSEL 0x00000548 258 259 // Output Selection for DMA Channel 9 REQ 260 #define EVENT_O_UDMACH9BSEL 0x0000054C 261 262 // Output Selection for DMA Channel 10 SREQ 263 #define EVENT_O_UDMACH10SSEL 0x00000550 264 265 // Output Selection for DMA Channel 10 REQ 266 #define EVENT_O_UDMACH10BSEL 0x00000554 267 268 // Output Selection for DMA Channel 11 SREQ 269 #define EVENT_O_UDMACH11SSEL 0x00000558 270 271 // Output Selection for DMA Channel 11 REQ 272 #define EVENT_O_UDMACH11BSEL 0x0000055C 273 274 // Output Selection for DMA Channel 12 SREQ 275 #define EVENT_O_UDMACH12SSEL 0x00000560 276 277 // Output Selection for DMA Channel 12 REQ 278 #define EVENT_O_UDMACH12BSEL 0x00000564 279 280 // Output Selection for DMA Channel 13 REQ 281 #define EVENT_O_UDMACH13BSEL 0x0000056C 282 283 // Output Selection for DMA Channel 14 REQ 284 #define EVENT_O_UDMACH14BSEL 0x00000574 285 286 // Output Selection for DMA Channel 15 REQ 287 #define EVENT_O_UDMACH15BSEL 0x0000057C 288 289 // Output Selection for DMA Channel 16 SREQ 290 #define EVENT_O_UDMACH16SSEL 0x00000580 291 292 // Output Selection for DMA Channel 16 REQ 293 #define EVENT_O_UDMACH16BSEL 0x00000584 294 295 // Output Selection for DMA Channel 17 SREQ 296 #define EVENT_O_UDMACH17SSEL 0x00000588 297 298 // Output Selection for DMA Channel 17 REQ 299 #define EVENT_O_UDMACH17BSEL 0x0000058C 300 301 // Output Selection for DMA Channel 21 SREQ 302 #define EVENT_O_UDMACH21SSEL 0x000005A8 303 304 // Output Selection for DMA Channel 21 REQ 305 #define EVENT_O_UDMACH21BSEL 0x000005AC 306 307 // Output Selection for DMA Channel 22 SREQ 308 #define EVENT_O_UDMACH22SSEL 0x000005B0 309 310 // Output Selection for DMA Channel 22 REQ 311 #define EVENT_O_UDMACH22BSEL 0x000005B4 312 313 // Output Selection for DMA Channel 23 SREQ 314 #define EVENT_O_UDMACH23SSEL 0x000005B8 315 316 // Output Selection for DMA Channel 23 REQ 317 #define EVENT_O_UDMACH23BSEL 0x000005BC 318 319 // Output Selection for DMA Channel 24 SREQ 320 #define EVENT_O_UDMACH24SSEL 0x000005C0 321 322 // Output Selection for DMA Channel 24 REQ 323 #define EVENT_O_UDMACH24BSEL 0x000005C4 324 325 // Output Selection for GPT3 0 326 #define EVENT_O_GPT3ACAPTSEL 0x00000600 327 328 // Output Selection for GPT3 1 329 #define EVENT_O_GPT3BCAPTSEL 0x00000604 330 331 // Output Selection for AUX Subscriber 0 332 #define EVENT_O_AUXSEL0 0x00000700 333 334 // Output Selection for NMI Subscriber 0 335 #define EVENT_O_CM3NMISEL0 0x00000800 336 337 // Output Selection for I2S Subscriber 0 338 #define EVENT_O_I2SSTMPSEL0 0x00000900 339 340 // Output Selection for FRZ Subscriber 341 #define EVENT_O_FRZSEL0 0x00000A00 342 343 // Set or Clear Software Events 344 #define EVENT_O_SWEV 0x00000F00 345 346 //***************************************************************************** 347 // 348 // Register: EVENT_O_CPUIRQSEL0 349 // 350 //***************************************************************************** 351 // Field: [6:0] EV 352 // 353 // Read only selection value 354 // ENUMs: 355 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 356 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 357 // settings 358 #define EVENT_CPUIRQSEL0_EV_W 7 359 #define EVENT_CPUIRQSEL0_EV_M 0x0000007F 360 #define EVENT_CPUIRQSEL0_EV_S 0 361 #define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 362 363 //***************************************************************************** 364 // 365 // Register: EVENT_O_CPUIRQSEL1 366 // 367 //***************************************************************************** 368 // Field: [6:0] EV 369 // 370 // Read only selection value 371 // ENUMs: 372 // I2C_IRQ Interrupt event from I2C 373 #define EVENT_CPUIRQSEL1_EV_W 7 374 #define EVENT_CPUIRQSEL1_EV_M 0x0000007F 375 #define EVENT_CPUIRQSEL1_EV_S 0 376 #define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 377 378 //***************************************************************************** 379 // 380 // Register: EVENT_O_CPUIRQSEL2 381 // 382 //***************************************************************************** 383 // Field: [6:0] EV 384 // 385 // Read only selection value 386 // ENUMs: 387 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 388 // Corresponding flags are here 389 // RFC_DBELL:RFCPEIFG. Only interrupts selected 390 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 391 // RFC_CPE_1 event 392 #define EVENT_CPUIRQSEL2_EV_W 7 393 #define EVENT_CPUIRQSEL2_EV_M 0x0000007F 394 #define EVENT_CPUIRQSEL2_EV_S 0 395 #define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E 396 397 //***************************************************************************** 398 // 399 // Register: EVENT_O_CPUIRQSEL3 400 // 401 //***************************************************************************** 402 // Field: [6:0] EV 403 // 404 // Read only selection value 405 // ENUMs: 406 // PKA_IRQ PKA Interrupt event 407 #define EVENT_CPUIRQSEL3_EV_W 7 408 #define EVENT_CPUIRQSEL3_EV_M 0x0000007F 409 #define EVENT_CPUIRQSEL3_EV_S 0 410 #define EVENT_CPUIRQSEL3_EV_PKA_IRQ 0x0000001F 411 412 //***************************************************************************** 413 // 414 // Register: EVENT_O_CPUIRQSEL4 415 // 416 //***************************************************************************** 417 // Field: [6:0] EV 418 // 419 // Read only selection value 420 // ENUMs: 421 // AON_RTC_COMB Event from AON_RTC, controlled by the 422 // AON_RTC:CTL.COMB_EV_MASK setting 423 #define EVENT_CPUIRQSEL4_EV_W 7 424 #define EVENT_CPUIRQSEL4_EV_M 0x0000007F 425 #define EVENT_CPUIRQSEL4_EV_S 0 426 #define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 427 428 //***************************************************************************** 429 // 430 // Register: EVENT_O_CPUIRQSEL5 431 // 432 //***************************************************************************** 433 // Field: [6:0] EV 434 // 435 // Read only selection value 436 // ENUMs: 437 // UART0_COMB UART0 combined interrupt, interrupt flags are 438 // found here UART0:MIS 439 #define EVENT_CPUIRQSEL5_EV_W 7 440 #define EVENT_CPUIRQSEL5_EV_M 0x0000007F 441 #define EVENT_CPUIRQSEL5_EV_S 0 442 #define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 443 444 //***************************************************************************** 445 // 446 // Register: EVENT_O_CPUIRQSEL6 447 // 448 //***************************************************************************** 449 // Field: [6:0] EV 450 // 451 // Read only selection value 452 // ENUMs: 453 // AUX_SWEV0 AUX software event 0, triggered by 454 // AUX_EVCTL:SWEVSET.SWEV0, also available as 455 // AUX_EVENT0 AON wake up event. 456 // MCU domain wakeup control 457 // AON_EVENT:MCUWUSEL 458 #define EVENT_CPUIRQSEL6_EV_W 7 459 #define EVENT_CPUIRQSEL6_EV_M 0x0000007F 460 #define EVENT_CPUIRQSEL6_EV_S 0 461 #define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C 462 463 //***************************************************************************** 464 // 465 // Register: EVENT_O_CPUIRQSEL7 466 // 467 //***************************************************************************** 468 // Field: [6:0] EV 469 // 470 // Read only selection value 471 // ENUMs: 472 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 473 // here SSI0:MIS 474 #define EVENT_CPUIRQSEL7_EV_W 7 475 #define EVENT_CPUIRQSEL7_EV_M 0x0000007F 476 #define EVENT_CPUIRQSEL7_EV_S 0 477 #define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 478 479 //***************************************************************************** 480 // 481 // Register: EVENT_O_CPUIRQSEL8 482 // 483 //***************************************************************************** 484 // Field: [6:0] EV 485 // 486 // Read only selection value 487 // ENUMs: 488 // SSI1_COMB SSI1 combined interrupt, interrupt flags are found 489 // here SSI1:MIS 490 #define EVENT_CPUIRQSEL8_EV_W 7 491 #define EVENT_CPUIRQSEL8_EV_M 0x0000007F 492 #define EVENT_CPUIRQSEL8_EV_S 0 493 #define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 494 495 //***************************************************************************** 496 // 497 // Register: EVENT_O_CPUIRQSEL9 498 // 499 //***************************************************************************** 500 // Field: [6:0] EV 501 // 502 // Read only selection value 503 // ENUMs: 504 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 505 // Corresponding flags are here 506 // RFC_DBELL:RFCPEIFG. Only interrupts selected 507 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 508 // RFC_CPE_0 event 509 #define EVENT_CPUIRQSEL9_EV_W 7 510 #define EVENT_CPUIRQSEL9_EV_M 0x0000007F 511 #define EVENT_CPUIRQSEL9_EV_S 0 512 #define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B 513 514 //***************************************************************************** 515 // 516 // Register: EVENT_O_CPUIRQSEL10 517 // 518 //***************************************************************************** 519 // Field: [6:0] EV 520 // 521 // Read only selection value 522 // ENUMs: 523 // RFC_HW_COMB Combined RFC hardware interrupt, corresponding 524 // flag is here RFC_DBELL:RFHWIFG 525 #define EVENT_CPUIRQSEL10_EV_W 7 526 #define EVENT_CPUIRQSEL10_EV_M 0x0000007F 527 #define EVENT_CPUIRQSEL10_EV_S 0 528 #define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A 529 530 //***************************************************************************** 531 // 532 // Register: EVENT_O_CPUIRQSEL11 533 // 534 //***************************************************************************** 535 // Field: [6:0] EV 536 // 537 // Read only selection value 538 // ENUMs: 539 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 540 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 541 #define EVENT_CPUIRQSEL11_EV_W 7 542 #define EVENT_CPUIRQSEL11_EV_M 0x0000007F 543 #define EVENT_CPUIRQSEL11_EV_S 0 544 #define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 545 546 //***************************************************************************** 547 // 548 // Register: EVENT_O_CPUIRQSEL12 549 // 550 //***************************************************************************** 551 // Field: [6:0] EV 552 // 553 // Read only selection value 554 // ENUMs: 555 // I2S_IRQ Interrupt event from I2S 556 #define EVENT_CPUIRQSEL12_EV_W 7 557 #define EVENT_CPUIRQSEL12_EV_M 0x0000007F 558 #define EVENT_CPUIRQSEL12_EV_S 0 559 #define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 560 561 //***************************************************************************** 562 // 563 // Register: EVENT_O_CPUIRQSEL13 564 // 565 //***************************************************************************** 566 // Field: [6:0] EV 567 // 568 // Read only selection value 569 // ENUMs: 570 // AUX_SWEV1 AUX software event 1, triggered by 571 // AUX_EVCTL:SWEVSET.SWEV1, also available as 572 // AUX_EVENT2 AON wake up event. 573 // MCU domain wakeup control 574 // AON_EVENT:MCUWUSEL 575 #define EVENT_CPUIRQSEL13_EV_W 7 576 #define EVENT_CPUIRQSEL13_EV_M 0x0000007F 577 #define EVENT_CPUIRQSEL13_EV_S 0 578 #define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D 579 580 //***************************************************************************** 581 // 582 // Register: EVENT_O_CPUIRQSEL14 583 // 584 //***************************************************************************** 585 // Field: [6:0] EV 586 // 587 // Read only selection value 588 // ENUMs: 589 // WDT_IRQ Watchdog interrupt event, controlled by 590 // WDT:CTL.INTEN 591 #define EVENT_CPUIRQSEL14_EV_W 7 592 #define EVENT_CPUIRQSEL14_EV_M 0x0000007F 593 #define EVENT_CPUIRQSEL14_EV_S 0 594 #define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 595 596 //***************************************************************************** 597 // 598 // Register: EVENT_O_CPUIRQSEL15 599 // 600 //***************************************************************************** 601 // Field: [6:0] EV 602 // 603 // Read only selection value 604 // ENUMs: 605 // GPT0A GPT0A interrupt event, controlled by GPT0:TAMR 606 #define EVENT_CPUIRQSEL15_EV_W 7 607 #define EVENT_CPUIRQSEL15_EV_M 0x0000007F 608 #define EVENT_CPUIRQSEL15_EV_S 0 609 #define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 610 611 //***************************************************************************** 612 // 613 // Register: EVENT_O_CPUIRQSEL16 614 // 615 //***************************************************************************** 616 // Field: [6:0] EV 617 // 618 // Read only selection value 619 // ENUMs: 620 // GPT0B GPT0B interrupt event, controlled by GPT0:TBMR 621 #define EVENT_CPUIRQSEL16_EV_W 7 622 #define EVENT_CPUIRQSEL16_EV_M 0x0000007F 623 #define EVENT_CPUIRQSEL16_EV_S 0 624 #define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 625 626 //***************************************************************************** 627 // 628 // Register: EVENT_O_CPUIRQSEL17 629 // 630 //***************************************************************************** 631 // Field: [6:0] EV 632 // 633 // Read only selection value 634 // ENUMs: 635 // GPT1A GPT1A interrupt event, controlled by GPT1:TAMR 636 #define EVENT_CPUIRQSEL17_EV_W 7 637 #define EVENT_CPUIRQSEL17_EV_M 0x0000007F 638 #define EVENT_CPUIRQSEL17_EV_S 0 639 #define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 640 641 //***************************************************************************** 642 // 643 // Register: EVENT_O_CPUIRQSEL18 644 // 645 //***************************************************************************** 646 // Field: [6:0] EV 647 // 648 // Read only selection value 649 // ENUMs: 650 // GPT1B GPT1B interrupt event, controlled by GPT1:TBMR 651 #define EVENT_CPUIRQSEL18_EV_W 7 652 #define EVENT_CPUIRQSEL18_EV_M 0x0000007F 653 #define EVENT_CPUIRQSEL18_EV_S 0 654 #define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 655 656 //***************************************************************************** 657 // 658 // Register: EVENT_O_CPUIRQSEL19 659 // 660 //***************************************************************************** 661 // Field: [6:0] EV 662 // 663 // Read only selection value 664 // ENUMs: 665 // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR 666 #define EVENT_CPUIRQSEL19_EV_W 7 667 #define EVENT_CPUIRQSEL19_EV_M 0x0000007F 668 #define EVENT_CPUIRQSEL19_EV_S 0 669 #define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C 670 671 //***************************************************************************** 672 // 673 // Register: EVENT_O_CPUIRQSEL20 674 // 675 //***************************************************************************** 676 // Field: [6:0] EV 677 // 678 // Read only selection value 679 // ENUMs: 680 // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR 681 #define EVENT_CPUIRQSEL20_EV_W 7 682 #define EVENT_CPUIRQSEL20_EV_M 0x0000007F 683 #define EVENT_CPUIRQSEL20_EV_S 0 684 #define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D 685 686 //***************************************************************************** 687 // 688 // Register: EVENT_O_CPUIRQSEL21 689 // 690 //***************************************************************************** 691 // Field: [6:0] EV 692 // 693 // Read only selection value 694 // ENUMs: 695 // GPT3A GPT3A interrupt event, controlled by GPT3:TAMR 696 #define EVENT_CPUIRQSEL21_EV_W 7 697 #define EVENT_CPUIRQSEL21_EV_M 0x0000007F 698 #define EVENT_CPUIRQSEL21_EV_S 0 699 #define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E 700 701 //***************************************************************************** 702 // 703 // Register: EVENT_O_CPUIRQSEL22 704 // 705 //***************************************************************************** 706 // Field: [6:0] EV 707 // 708 // Read only selection value 709 // ENUMs: 710 // GPT3B GPT3B interrupt event, controlled by GPT3:TBMR 711 #define EVENT_CPUIRQSEL22_EV_W 7 712 #define EVENT_CPUIRQSEL22_EV_M 0x0000007F 713 #define EVENT_CPUIRQSEL22_EV_S 0 714 #define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F 715 716 //***************************************************************************** 717 // 718 // Register: EVENT_O_CPUIRQSEL23 719 // 720 //***************************************************************************** 721 // Field: [6:0] EV 722 // 723 // Read only selection value 724 // ENUMs: 725 // CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the 726 // corresponding flag is found here 727 // CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by 728 // CRYPTO:IRQSTAT.RESULT_AVAIL 729 #define EVENT_CPUIRQSEL23_EV_W 7 730 #define EVENT_CPUIRQSEL23_EV_M 0x0000007F 731 #define EVENT_CPUIRQSEL23_EV_S 0 732 #define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D 733 734 //***************************************************************************** 735 // 736 // Register: EVENT_O_CPUIRQSEL24 737 // 738 //***************************************************************************** 739 // Field: [6:0] EV 740 // 741 // Read only selection value 742 // ENUMs: 743 // DMA_DONE_COMB Combined DMA done, corresponding flags are here 744 // UDMA0:REQDONE 745 #define EVENT_CPUIRQSEL24_EV_W 7 746 #define EVENT_CPUIRQSEL24_EV_M 0x0000007F 747 #define EVENT_CPUIRQSEL24_EV_S 0 748 #define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 749 750 //***************************************************************************** 751 // 752 // Register: EVENT_O_CPUIRQSEL25 753 // 754 //***************************************************************************** 755 // Field: [6:0] EV 756 // 757 // Read only selection value 758 // ENUMs: 759 // DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS 760 #define EVENT_CPUIRQSEL25_EV_W 7 761 #define EVENT_CPUIRQSEL25_EV_M 0x0000007F 762 #define EVENT_CPUIRQSEL25_EV_S 0 763 #define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 764 765 //***************************************************************************** 766 // 767 // Register: EVENT_O_CPUIRQSEL26 768 // 769 //***************************************************************************** 770 // Field: [6:0] EV 771 // 772 // Read only selection value 773 // ENUMs: 774 // FLASH FLASH controller error event, the status flags 775 // are FLASH:FEDACSTAT.FSM_DONE and 776 // FLASH:FEDACSTAT.RVF_INT 777 #define EVENT_CPUIRQSEL26_EV_W 7 778 #define EVENT_CPUIRQSEL26_EV_M 0x0000007F 779 #define EVENT_CPUIRQSEL26_EV_S 0 780 #define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 781 782 //***************************************************************************** 783 // 784 // Register: EVENT_O_CPUIRQSEL27 785 // 786 //***************************************************************************** 787 // Field: [6:0] EV 788 // 789 // Read only selection value 790 // ENUMs: 791 // SWEV0 Software event 0, triggered by SWEV.SWEV0 792 #define EVENT_CPUIRQSEL27_EV_W 7 793 #define EVENT_CPUIRQSEL27_EV_M 0x0000007F 794 #define EVENT_CPUIRQSEL27_EV_S 0 795 #define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 796 797 //***************************************************************************** 798 // 799 // Register: EVENT_O_CPUIRQSEL28 800 // 801 //***************************************************************************** 802 // Field: [6:0] EV 803 // 804 // Read only selection value 805 // ENUMs: 806 // AUX_COMB AUX combined event, the corresponding flag 807 // register is here AUX_EVCTL:EVTOMCUFLAGS 808 #define EVENT_CPUIRQSEL28_EV_W 7 809 #define EVENT_CPUIRQSEL28_EV_M 0x0000007F 810 #define EVENT_CPUIRQSEL28_EV_S 0 811 #define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B 812 813 //***************************************************************************** 814 // 815 // Register: EVENT_O_CPUIRQSEL29 816 // 817 //***************************************************************************** 818 // Field: [6:0] EV 819 // 820 // Read only selection value 821 // ENUMs: 822 // AON_PROG0 AON programmable event 0. Event selected by 823 // AON_EVENT MCU event selector, 824 // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV 825 #define EVENT_CPUIRQSEL29_EV_W 7 826 #define EVENT_CPUIRQSEL29_EV_M 0x0000007F 827 #define EVENT_CPUIRQSEL29_EV_S 0 828 #define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 829 830 //***************************************************************************** 831 // 832 // Register: EVENT_O_CPUIRQSEL30 833 // 834 //***************************************************************************** 835 // Field: [6:0] EV 836 // 837 // Read/write selection value 838 // 839 // Writing any other value than values defined by a ENUM may result in 840 // undefined behavior. 841 // ENUMs: 842 // ALWAYS_ACTIVE Always asserted 843 // AON_RTC_UPD RTC periodic event controlled by 844 // AON_RTC:CTL.RTC_UPD_EN 845 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 846 // AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 847 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 848 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 849 // AUX_ADC_DONE AUX ADC done, corresponds to 850 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 851 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 852 // AUX_SMPH:AUTOTAKE 853 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 854 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 855 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 856 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 857 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 858 // flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and 859 // the AUX_TDC status AUX_TDC:STAT.DONE 860 // AUX_COMPB AUX Compare B event, corresponds to 861 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 862 // AUX_AON_WU_EV AON wakeup event, the corresponding flag is here 863 // AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 864 // CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg 865 // flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled 866 // by CRYPTO:IRQEN.DMA_IN_DONE 867 // AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag 868 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 869 // AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag 870 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 871 // AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag 872 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 873 // AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag 874 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 875 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 876 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 877 // DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, 878 // see UDMA0:SOFTREQ 879 // DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see 880 // UDMA0:SOFTREQ 881 // AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 882 // I2S_IRQ Interrupt event from I2S 883 // AON_PROG2 AON programmable event 2. Event selected by 884 // AON_EVENT MCU event selector, 885 // AON_EVENT:EVTOMCUSEL.AON_PROG2_EV 886 // AON_PROG1 AON programmable event 1. Event selected by 887 // AON_EVENT MCU event selector, 888 // AON_EVENT:EVTOMCUSEL.AON_PROG1_EV 889 // NONE Always inactive 890 #define EVENT_CPUIRQSEL30_EV_W 7 891 #define EVENT_CPUIRQSEL30_EV_M 0x0000007F 892 #define EVENT_CPUIRQSEL30_EV_S 0 893 #define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 894 #define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 895 #define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 896 #define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 897 #define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 898 #define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 899 #define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E 900 #define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D 901 #define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C 902 #define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B 903 #define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 904 #define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E 905 #define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_PULSE 0x0000003C 906 #define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV3 0x0000003B 907 #define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV2 0x0000003A 908 #define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV1 0x00000039 909 #define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV0 0x00000038 910 #define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 911 #define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 912 #define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A 913 #define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 914 #define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 915 #define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 916 #define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 917 918 //***************************************************************************** 919 // 920 // Register: EVENT_O_CPUIRQSEL31 921 // 922 //***************************************************************************** 923 // Field: [6:0] EV 924 // 925 // Read only selection value 926 // ENUMs: 927 // AUX_COMPA AUX Compare A event, corresponds to 928 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 929 #define EVENT_CPUIRQSEL31_EV_W 7 930 #define EVENT_CPUIRQSEL31_EV_M 0x0000007F 931 #define EVENT_CPUIRQSEL31_EV_S 0 932 #define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A 933 934 //***************************************************************************** 935 // 936 // Register: EVENT_O_CPUIRQSEL32 937 // 938 //***************************************************************************** 939 // Field: [6:0] EV 940 // 941 // Read only selection value 942 // ENUMs: 943 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 944 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status 945 // flags are found here AUX_EVCTL:EVTOMCUFLAGS 946 #define EVENT_CPUIRQSEL32_EV_W 7 947 #define EVENT_CPUIRQSEL32_EV_M 0x0000007F 948 #define EVENT_CPUIRQSEL32_EV_S 0 949 #define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 950 951 //***************************************************************************** 952 // 953 // Register: EVENT_O_CPUIRQSEL33 954 // 955 //***************************************************************************** 956 // Field: [6:0] EV 957 // 958 // Read only selection value 959 // ENUMs: 960 // TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN 961 #define EVENT_CPUIRQSEL33_EV_W 7 962 #define EVENT_CPUIRQSEL33_EV_M 0x0000007F 963 #define EVENT_CPUIRQSEL33_EV_S 0 964 #define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 965 966 //***************************************************************************** 967 // 968 // Register: EVENT_O_CPUIRQSEL34 969 // 970 //***************************************************************************** 971 // Field: [6:0] EV 972 // 973 // Read only selection value 974 // ENUMs: 975 // OSC_COMB Combined event from Oscillator control 976 #define EVENT_CPUIRQSEL34_EV_W 7 977 #define EVENT_CPUIRQSEL34_EV_M 0x0000007F 978 #define EVENT_CPUIRQSEL34_EV_S 0 979 #define EVENT_CPUIRQSEL34_EV_OSC_COMB 0x00000006 980 981 //***************************************************************************** 982 // 983 // Register: EVENT_O_CPUIRQSEL35 984 // 985 //***************************************************************************** 986 // Field: [6:0] EV 987 // 988 // Read only selection value 989 // ENUMs: 990 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 991 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 992 #define EVENT_CPUIRQSEL35_EV_W 7 993 #define EVENT_CPUIRQSEL35_EV_M 0x0000007F 994 #define EVENT_CPUIRQSEL35_EV_S 0 995 #define EVENT_CPUIRQSEL35_EV_AUX_TIMER2_EV0 0x00000038 996 997 //***************************************************************************** 998 // 999 // Register: EVENT_O_CPUIRQSEL36 1000 // 1001 //***************************************************************************** 1002 // Field: [6:0] EV 1003 // 1004 // Read only selection value 1005 // ENUMs: 1006 // UART1_COMB UART1 combined interrupt, interrupt flags are 1007 // found here UART1:MIS 1008 #define EVENT_CPUIRQSEL36_EV_W 7 1009 #define EVENT_CPUIRQSEL36_EV_M 0x0000007F 1010 #define EVENT_CPUIRQSEL36_EV_S 0 1011 #define EVENT_CPUIRQSEL36_EV_UART1_COMB 0x00000025 1012 1013 //***************************************************************************** 1014 // 1015 // Register: EVENT_O_CPUIRQSEL37 1016 // 1017 //***************************************************************************** 1018 // Field: [6:0] EV 1019 // 1020 // Read only selection value 1021 // ENUMs: 1022 // BATMON_COMB Combined event from battery monitor 1023 #define EVENT_CPUIRQSEL37_EV_W 7 1024 #define EVENT_CPUIRQSEL37_EV_M 0x0000007F 1025 #define EVENT_CPUIRQSEL37_EV_S 0 1026 #define EVENT_CPUIRQSEL37_EV_BATMON_COMB 0x00000005 1027 1028 //***************************************************************************** 1029 // 1030 // Register: EVENT_O_RFCSEL0 1031 // 1032 //***************************************************************************** 1033 // Field: [6:0] EV 1034 // 1035 // Read only selection value 1036 // ENUMs: 1037 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1038 #define EVENT_RFCSEL0_EV_W 7 1039 #define EVENT_RFCSEL0_EV_M 0x0000007F 1040 #define EVENT_RFCSEL0_EV_S 0 1041 #define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D 1042 1043 //***************************************************************************** 1044 // 1045 // Register: EVENT_O_RFCSEL1 1046 // 1047 //***************************************************************************** 1048 // Field: [6:0] EV 1049 // 1050 // Read only selection value 1051 // ENUMs: 1052 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1053 #define EVENT_RFCSEL1_EV_W 7 1054 #define EVENT_RFCSEL1_EV_M 0x0000007F 1055 #define EVENT_RFCSEL1_EV_S 0 1056 #define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E 1057 1058 //***************************************************************************** 1059 // 1060 // Register: EVENT_O_RFCSEL2 1061 // 1062 //***************************************************************************** 1063 // Field: [6:0] EV 1064 // 1065 // Read only selection value 1066 // ENUMs: 1067 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1068 #define EVENT_RFCSEL2_EV_W 7 1069 #define EVENT_RFCSEL2_EV_M 0x0000007F 1070 #define EVENT_RFCSEL2_EV_S 0 1071 #define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F 1072 1073 //***************************************************************************** 1074 // 1075 // Register: EVENT_O_RFCSEL3 1076 // 1077 //***************************************************************************** 1078 // Field: [6:0] EV 1079 // 1080 // Read only selection value 1081 // ENUMs: 1082 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1083 #define EVENT_RFCSEL3_EV_W 7 1084 #define EVENT_RFCSEL3_EV_M 0x0000007F 1085 #define EVENT_RFCSEL3_EV_S 0 1086 #define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 1087 1088 //***************************************************************************** 1089 // 1090 // Register: EVENT_O_RFCSEL4 1091 // 1092 //***************************************************************************** 1093 // Field: [6:0] EV 1094 // 1095 // Read only selection value 1096 // ENUMs: 1097 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1098 #define EVENT_RFCSEL4_EV_W 7 1099 #define EVENT_RFCSEL4_EV_M 0x0000007F 1100 #define EVENT_RFCSEL4_EV_S 0 1101 #define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 1102 1103 //***************************************************************************** 1104 // 1105 // Register: EVENT_O_RFCSEL5 1106 // 1107 //***************************************************************************** 1108 // Field: [6:0] EV 1109 // 1110 // Read only selection value 1111 // ENUMs: 1112 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1113 #define EVENT_RFCSEL5_EV_W 7 1114 #define EVENT_RFCSEL5_EV_M 0x0000007F 1115 #define EVENT_RFCSEL5_EV_S 0 1116 #define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 1117 1118 //***************************************************************************** 1119 // 1120 // Register: EVENT_O_RFCSEL6 1121 // 1122 //***************************************************************************** 1123 // Field: [6:0] EV 1124 // 1125 // Read only selection value 1126 // ENUMs: 1127 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1128 #define EVENT_RFCSEL6_EV_W 7 1129 #define EVENT_RFCSEL6_EV_M 0x0000007F 1130 #define EVENT_RFCSEL6_EV_S 0 1131 #define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 1132 1133 //***************************************************************************** 1134 // 1135 // Register: EVENT_O_RFCSEL7 1136 // 1137 //***************************************************************************** 1138 // Field: [6:0] EV 1139 // 1140 // Read only selection value 1141 // ENUMs: 1142 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1143 #define EVENT_RFCSEL7_EV_W 7 1144 #define EVENT_RFCSEL7_EV_M 0x0000007F 1145 #define EVENT_RFCSEL7_EV_S 0 1146 #define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 1147 1148 //***************************************************************************** 1149 // 1150 // Register: EVENT_O_RFCSEL8 1151 // 1152 //***************************************************************************** 1153 // Field: [6:0] EV 1154 // 1155 // Read only selection value 1156 // ENUMs: 1157 // AON_RTC_UPD RTC periodic event controlled by 1158 // AON_RTC:CTL.RTC_UPD_EN 1159 #define EVENT_RFCSEL8_EV_W 7 1160 #define EVENT_RFCSEL8_EV_M 0x0000007F 1161 #define EVENT_RFCSEL8_EV_S 0 1162 #define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 1163 1164 //***************************************************************************** 1165 // 1166 // Register: EVENT_O_RFCSEL9 1167 // 1168 //***************************************************************************** 1169 // Field: [6:0] EV 1170 // 1171 // Read/write selection value 1172 // 1173 // Writing any other value than values defined by a ENUM may result in 1174 // undefined behavior. 1175 // ENUMs: 1176 // ALWAYS_ACTIVE Always asserted 1177 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1178 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status 1179 // flags are found here AUX_EVCTL:EVTOMCUFLAGS 1180 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1181 // AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 1182 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1183 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 1184 // AUX_ADC_DONE AUX ADC done, corresponds to 1185 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 1186 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1187 // AUX_SMPH:AUTOTAKE 1188 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1189 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 1190 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1191 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 1192 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1193 // flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and 1194 // the AUX_TDC status AUX_TDC:STAT.DONE 1195 // AUX_COMPB AUX Compare B event, corresponds to 1196 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1197 // AUX_COMPA AUX Compare A event, corresponds to 1198 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1199 // AUX_AON_WU_EV AON wakeup event, the corresponding flag is here 1200 // AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 1201 // SWEV1 Software event 1, triggered by SWEV.SWEV1 1202 // SWEV0 Software event 0, triggered by SWEV.SWEV0 1203 // CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the 1204 // corresponding flag is found here 1205 // CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by 1206 // CRYPTO:IRQSTAT.RESULT_AVAIL 1207 // AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag 1208 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 1209 // AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag 1210 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 1211 // AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag 1212 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 1213 // AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag 1214 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 1215 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 1216 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 1217 // DMA_DONE_COMB Combined DMA done, corresponding flags are here 1218 // UDMA0:REQDONE 1219 // UART1_COMB UART1 combined interrupt, interrupt flags are 1220 // found here UART1:MIS 1221 // UART0_COMB UART0 combined interrupt, interrupt flags are 1222 // found here UART0:MIS 1223 // SSI1_COMB SSI1 combined interrupt, interrupt flags are found 1224 // here SSI1:MIS 1225 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1226 // here SSI0:MIS 1227 // WDT_IRQ Watchdog interrupt event, controlled by 1228 // WDT:CTL.INTEN 1229 // AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 1230 // I2S_IRQ Interrupt event from I2S 1231 // AON_PROG1 AON programmable event 1. Event selected by 1232 // AON_EVENT MCU event selector, 1233 // AON_EVENT:EVTOMCUSEL.AON_PROG1_EV 1234 // AON_PROG0 AON programmable event 0. Event selected by 1235 // AON_EVENT MCU event selector, 1236 // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV 1237 // NONE Always inactive 1238 #define EVENT_RFCSEL9_EV_W 7 1239 #define EVENT_RFCSEL9_EV_M 0x0000007F 1240 #define EVENT_RFCSEL9_EV_S 0 1241 #define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 1242 #define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 1243 #define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 1244 #define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1245 #define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 1246 #define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1247 #define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E 1248 #define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D 1249 #define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C 1250 #define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B 1251 #define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A 1252 #define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 1253 #define EVENT_RFCSEL9_EV_SWEV1 0x00000065 1254 #define EVENT_RFCSEL9_EV_SWEV0 0x00000064 1255 #define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D 1256 #define EVENT_RFCSEL9_EV_AUX_TIMER2_PULSE 0x0000003C 1257 #define EVENT_RFCSEL9_EV_AUX_TIMER2_EV3 0x0000003B 1258 #define EVENT_RFCSEL9_EV_AUX_TIMER2_EV2 0x0000003A 1259 #define EVENT_RFCSEL9_EV_AUX_TIMER2_EV1 0x00000039 1260 #define EVENT_RFCSEL9_EV_AUX_TIMER2_EV0 0x00000038 1261 #define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 1262 #define EVENT_RFCSEL9_EV_UART1_COMB 0x00000025 1263 #define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 1264 #define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 1265 #define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 1266 #define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 1267 #define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A 1268 #define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 1269 #define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 1270 #define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 1271 #define EVENT_RFCSEL9_EV_NONE 0x00000000 1272 1273 //***************************************************************************** 1274 // 1275 // Register: EVENT_O_GPT0ACAPTSEL 1276 // 1277 //***************************************************************************** 1278 // Field: [6:0] EV 1279 // 1280 // Read/write selection value 1281 // 1282 // Writing any other value than values defined by a ENUM may result in 1283 // undefined behavior. 1284 // ENUMs: 1285 // ALWAYS_ACTIVE Always asserted 1286 // AON_RTC_UPD RTC periodic event controlled by 1287 // AON_RTC:CTL.RTC_UPD_EN 1288 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1289 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status 1290 // flags are found here AUX_EVCTL:EVTOMCUFLAGS 1291 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1292 // AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 1293 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1294 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 1295 // AUX_ADC_DONE AUX ADC done, corresponds to 1296 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 1297 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1298 // AUX_SMPH:AUTOTAKE 1299 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1300 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 1301 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1302 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 1303 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1304 // flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and 1305 // the AUX_TDC status AUX_TDC:STAT.DONE 1306 // AUX_COMPB AUX Compare B event, corresponds to 1307 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1308 // AUX_COMPA AUX Compare A event, corresponds to 1309 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1310 // AUX_AON_WU_EV AON wakeup event, the corresponding flag is here 1311 // AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 1312 // PORT_EVENT1 Port capture event from IOC, configured by 1313 // IOC:IOCFGn.PORT_ID. Events on ports configured 1314 // with ENUM PORT_EVENT1 wil be routed here. 1315 // PORT_EVENT0 Port capture event from IOC, configured by 1316 // IOC:IOCFGn.PORT_ID. Events on ports configured 1317 // with ENUM PORT_EVENT0 wil be routed here. 1318 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1319 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1320 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1321 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1322 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1323 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1324 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1325 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1326 // AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag 1327 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 1328 // AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag 1329 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 1330 // AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag 1331 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 1332 // AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag 1333 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 1334 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 1335 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 1336 // UART1_COMB UART1 combined interrupt, interrupt flags are 1337 // found here UART1:MIS 1338 // UART0_COMB UART0 combined interrupt, interrupt flags are 1339 // found here UART0:MIS 1340 // SSI1_COMB SSI1 combined interrupt, interrupt flags are found 1341 // here SSI1:MIS 1342 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1343 // here SSI0:MIS 1344 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 1345 // Corresponding flags are here 1346 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1347 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 1348 // RFC_CPE_1 event 1349 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 1350 // Corresponding flags are here 1351 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1352 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 1353 // RFC_CPE_0 event 1354 // RFC_HW_COMB Combined RFC hardware interrupt, corresponding 1355 // flag is here RFC_DBELL:RFHWIFG 1356 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 1357 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1358 // FLASH FLASH controller error event, the status flags 1359 // are FLASH:FEDACSTAT.FSM_DONE and 1360 // FLASH:FEDACSTAT.RVF_INT 1361 // AUX_COMB AUX combined event, the corresponding flag 1362 // register is here AUX_EVCTL:EVTOMCUFLAGS 1363 // I2C_IRQ Interrupt event from I2C 1364 // AON_RTC_COMB Event from AON_RTC, controlled by the 1365 // AON_RTC:CTL.COMB_EV_MASK setting 1366 // OSC_COMB Combined event from Oscillator control 1367 // BATMON_COMB Combined event from battery monitor 1368 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 1369 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 1370 // settings 1371 // NONE Always inactive 1372 #define EVENT_GPT0ACAPTSEL_EV_W 7 1373 #define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F 1374 #define EVENT_GPT0ACAPTSEL_EV_S 0 1375 #define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 1376 #define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 1377 #define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 1378 #define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 1379 #define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1380 #define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 1381 #define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1382 #define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 1383 #define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 1384 #define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C 1385 #define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B 1386 #define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A 1387 #define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 1388 #define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 1389 #define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 1390 #define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 1391 #define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 1392 #define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 1393 #define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 1394 #define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 1395 #define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F 1396 #define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E 1397 #define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D 1398 #define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C 1399 #define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B 1400 #define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A 1401 #define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 1402 #define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 1403 #define EVENT_GPT0ACAPTSEL_EV_UART1_COMB 0x00000025 1404 #define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 1405 #define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 1406 #define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 1407 #define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E 1408 #define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B 1409 #define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A 1410 #define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 1411 #define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 1412 #define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B 1413 #define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 1414 #define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 1415 #define EVENT_GPT0ACAPTSEL_EV_OSC_COMB 0x00000006 1416 #define EVENT_GPT0ACAPTSEL_EV_BATMON_COMB 0x00000005 1417 #define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 1418 #define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 1419 1420 //***************************************************************************** 1421 // 1422 // Register: EVENT_O_GPT0BCAPTSEL 1423 // 1424 //***************************************************************************** 1425 // Field: [6:0] EV 1426 // 1427 // Read/write selection value 1428 // 1429 // Writing any other value than values defined by a ENUM may result in 1430 // undefined behavior. 1431 // ENUMs: 1432 // ALWAYS_ACTIVE Always asserted 1433 // AON_RTC_UPD RTC periodic event controlled by 1434 // AON_RTC:CTL.RTC_UPD_EN 1435 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1436 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status 1437 // flags are found here AUX_EVCTL:EVTOMCUFLAGS 1438 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1439 // AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 1440 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1441 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 1442 // AUX_ADC_DONE AUX ADC done, corresponds to 1443 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 1444 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1445 // AUX_SMPH:AUTOTAKE 1446 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1447 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 1448 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1449 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 1450 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1451 // flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and 1452 // the AUX_TDC status AUX_TDC:STAT.DONE 1453 // AUX_COMPB AUX Compare B event, corresponds to 1454 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1455 // AUX_COMPA AUX Compare A event, corresponds to 1456 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1457 // AUX_AON_WU_EV AON wakeup event, the corresponding flag is here 1458 // AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 1459 // PORT_EVENT1 Port capture event from IOC, configured by 1460 // IOC:IOCFGn.PORT_ID. Events on ports configured 1461 // with ENUM PORT_EVENT1 wil be routed here. 1462 // PORT_EVENT0 Port capture event from IOC, configured by 1463 // IOC:IOCFGn.PORT_ID. Events on ports configured 1464 // with ENUM PORT_EVENT0 wil be routed here. 1465 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1466 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1467 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1468 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1469 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1470 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1471 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1472 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1473 // AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag 1474 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 1475 // AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag 1476 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 1477 // AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag 1478 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 1479 // AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag 1480 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 1481 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 1482 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 1483 // UART1_COMB UART1 combined interrupt, interrupt flags are 1484 // found here UART1:MIS 1485 // UART0_COMB UART0 combined interrupt, interrupt flags are 1486 // found here UART0:MIS 1487 // SSI1_COMB SSI1 combined interrupt, interrupt flags are found 1488 // here SSI1:MIS 1489 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1490 // here SSI0:MIS 1491 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 1492 // Corresponding flags are here 1493 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1494 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 1495 // RFC_CPE_1 event 1496 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 1497 // Corresponding flags are here 1498 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1499 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 1500 // RFC_CPE_0 event 1501 // RFC_HW_COMB Combined RFC hardware interrupt, corresponding 1502 // flag is here RFC_DBELL:RFHWIFG 1503 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 1504 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1505 // FLASH FLASH controller error event, the status flags 1506 // are FLASH:FEDACSTAT.FSM_DONE and 1507 // FLASH:FEDACSTAT.RVF_INT 1508 // AUX_COMB AUX combined event, the corresponding flag 1509 // register is here AUX_EVCTL:EVTOMCUFLAGS 1510 // I2C_IRQ Interrupt event from I2C 1511 // AON_RTC_COMB Event from AON_RTC, controlled by the 1512 // AON_RTC:CTL.COMB_EV_MASK setting 1513 // OSC_COMB Combined event from Oscillator control 1514 // BATMON_COMB Combined event from battery monitor 1515 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 1516 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 1517 // settings 1518 // NONE Always inactive 1519 #define EVENT_GPT0BCAPTSEL_EV_W 7 1520 #define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F 1521 #define EVENT_GPT0BCAPTSEL_EV_S 0 1522 #define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 1523 #define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 1524 #define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 1525 #define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 1526 #define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1527 #define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 1528 #define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1529 #define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 1530 #define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 1531 #define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C 1532 #define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B 1533 #define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A 1534 #define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 1535 #define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 1536 #define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 1537 #define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 1538 #define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 1539 #define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 1540 #define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 1541 #define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 1542 #define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F 1543 #define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E 1544 #define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D 1545 #define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C 1546 #define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B 1547 #define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A 1548 #define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 1549 #define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 1550 #define EVENT_GPT0BCAPTSEL_EV_UART1_COMB 0x00000025 1551 #define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 1552 #define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 1553 #define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 1554 #define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E 1555 #define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B 1556 #define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A 1557 #define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 1558 #define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 1559 #define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B 1560 #define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 1561 #define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 1562 #define EVENT_GPT0BCAPTSEL_EV_OSC_COMB 0x00000006 1563 #define EVENT_GPT0BCAPTSEL_EV_BATMON_COMB 0x00000005 1564 #define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 1565 #define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 1566 1567 //***************************************************************************** 1568 // 1569 // Register: EVENT_O_GPT1ACAPTSEL 1570 // 1571 //***************************************************************************** 1572 // Field: [6:0] EV 1573 // 1574 // Read/write selection value 1575 // 1576 // Writing any other value than values defined by a ENUM may result in 1577 // undefined behavior. 1578 // ENUMs: 1579 // ALWAYS_ACTIVE Always asserted 1580 // AON_RTC_UPD RTC periodic event controlled by 1581 // AON_RTC:CTL.RTC_UPD_EN 1582 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1583 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status 1584 // flags are found here AUX_EVCTL:EVTOMCUFLAGS 1585 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1586 // AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 1587 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1588 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 1589 // AUX_ADC_DONE AUX ADC done, corresponds to 1590 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 1591 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1592 // AUX_SMPH:AUTOTAKE 1593 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1594 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 1595 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1596 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 1597 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1598 // flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and 1599 // the AUX_TDC status AUX_TDC:STAT.DONE 1600 // AUX_COMPB AUX Compare B event, corresponds to 1601 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1602 // AUX_COMPA AUX Compare A event, corresponds to 1603 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1604 // AUX_AON_WU_EV AON wakeup event, the corresponding flag is here 1605 // AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 1606 // PORT_EVENT3 Port capture event from IOC, configured by 1607 // IOC:IOCFGn.PORT_ID. Events on ports configured 1608 // with ENUM PORT_EVENT3 wil be routed here. 1609 // PORT_EVENT2 Port capture event from IOC, configured by 1610 // IOC:IOCFGn.PORT_ID. Events on ports configured 1611 // with ENUM PORT_EVENT2 wil be routed here. 1612 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1613 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1614 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1615 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1616 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1617 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1618 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1619 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1620 // AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag 1621 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 1622 // AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag 1623 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 1624 // AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag 1625 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 1626 // AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag 1627 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 1628 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 1629 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 1630 // UART1_COMB UART1 combined interrupt, interrupt flags are 1631 // found here UART1:MIS 1632 // UART0_COMB UART0 combined interrupt, interrupt flags are 1633 // found here UART0:MIS 1634 // SSI1_COMB SSI1 combined interrupt, interrupt flags are found 1635 // here SSI1:MIS 1636 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1637 // here SSI0:MIS 1638 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 1639 // Corresponding flags are here 1640 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1641 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 1642 // RFC_CPE_1 event 1643 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 1644 // Corresponding flags are here 1645 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1646 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 1647 // RFC_CPE_0 event 1648 // RFC_HW_COMB Combined RFC hardware interrupt, corresponding 1649 // flag is here RFC_DBELL:RFHWIFG 1650 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 1651 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1652 // FLASH FLASH controller error event, the status flags 1653 // are FLASH:FEDACSTAT.FSM_DONE and 1654 // FLASH:FEDACSTAT.RVF_INT 1655 // AUX_COMB AUX combined event, the corresponding flag 1656 // register is here AUX_EVCTL:EVTOMCUFLAGS 1657 // I2C_IRQ Interrupt event from I2C 1658 // AON_RTC_COMB Event from AON_RTC, controlled by the 1659 // AON_RTC:CTL.COMB_EV_MASK setting 1660 // OSC_COMB Combined event from Oscillator control 1661 // BATMON_COMB Combined event from battery monitor 1662 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 1663 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 1664 // settings 1665 // NONE Always inactive 1666 #define EVENT_GPT1ACAPTSEL_EV_W 7 1667 #define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F 1668 #define EVENT_GPT1ACAPTSEL_EV_S 0 1669 #define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 1670 #define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 1671 #define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 1672 #define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 1673 #define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1674 #define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 1675 #define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1676 #define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 1677 #define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 1678 #define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C 1679 #define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B 1680 #define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A 1681 #define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 1682 #define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 1683 #define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 1684 #define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 1685 #define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 1686 #define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 1687 #define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 1688 #define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 1689 #define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F 1690 #define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E 1691 #define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D 1692 #define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C 1693 #define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B 1694 #define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A 1695 #define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 1696 #define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 1697 #define EVENT_GPT1ACAPTSEL_EV_UART1_COMB 0x00000025 1698 #define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 1699 #define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 1700 #define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 1701 #define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E 1702 #define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B 1703 #define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A 1704 #define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 1705 #define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 1706 #define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B 1707 #define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 1708 #define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 1709 #define EVENT_GPT1ACAPTSEL_EV_OSC_COMB 0x00000006 1710 #define EVENT_GPT1ACAPTSEL_EV_BATMON_COMB 0x00000005 1711 #define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 1712 #define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 1713 1714 //***************************************************************************** 1715 // 1716 // Register: EVENT_O_GPT1BCAPTSEL 1717 // 1718 //***************************************************************************** 1719 // Field: [6:0] EV 1720 // 1721 // Read/write selection value 1722 // 1723 // Writing any other value than values defined by a ENUM may result in 1724 // undefined behavior. 1725 // ENUMs: 1726 // ALWAYS_ACTIVE Always asserted 1727 // AON_RTC_UPD RTC periodic event controlled by 1728 // AON_RTC:CTL.RTC_UPD_EN 1729 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1730 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status 1731 // flags are found here AUX_EVCTL:EVTOMCUFLAGS 1732 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1733 // AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 1734 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1735 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 1736 // AUX_ADC_DONE AUX ADC done, corresponds to 1737 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 1738 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1739 // AUX_SMPH:AUTOTAKE 1740 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1741 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 1742 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1743 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 1744 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1745 // flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and 1746 // the AUX_TDC status AUX_TDC:STAT.DONE 1747 // AUX_COMPB AUX Compare B event, corresponds to 1748 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1749 // AUX_COMPA AUX Compare A event, corresponds to 1750 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1751 // AUX_AON_WU_EV AON wakeup event, the corresponding flag is here 1752 // AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 1753 // PORT_EVENT3 Port capture event from IOC, configured by 1754 // IOC:IOCFGn.PORT_ID. Events on ports configured 1755 // with ENUM PORT_EVENT3 wil be routed here. 1756 // PORT_EVENT2 Port capture event from IOC, configured by 1757 // IOC:IOCFGn.PORT_ID. Events on ports configured 1758 // with ENUM PORT_EVENT2 wil be routed here. 1759 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1760 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1761 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1762 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1763 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1764 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1765 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1766 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1767 // AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag 1768 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 1769 // AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag 1770 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 1771 // AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag 1772 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 1773 // AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag 1774 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 1775 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 1776 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 1777 // UART1_COMB UART1 combined interrupt, interrupt flags are 1778 // found here UART1:MIS 1779 // UART0_COMB UART0 combined interrupt, interrupt flags are 1780 // found here UART0:MIS 1781 // SSI1_COMB SSI1 combined interrupt, interrupt flags are found 1782 // here SSI1:MIS 1783 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1784 // here SSI0:MIS 1785 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 1786 // Corresponding flags are here 1787 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1788 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 1789 // RFC_CPE_1 event 1790 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 1791 // Corresponding flags are here 1792 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1793 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 1794 // RFC_CPE_0 event 1795 // RFC_HW_COMB Combined RFC hardware interrupt, corresponding 1796 // flag is here RFC_DBELL:RFHWIFG 1797 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 1798 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1799 // FLASH FLASH controller error event, the status flags 1800 // are FLASH:FEDACSTAT.FSM_DONE and 1801 // FLASH:FEDACSTAT.RVF_INT 1802 // AUX_COMB AUX combined event, the corresponding flag 1803 // register is here AUX_EVCTL:EVTOMCUFLAGS 1804 // I2C_IRQ Interrupt event from I2C 1805 // AON_RTC_COMB Event from AON_RTC, controlled by the 1806 // AON_RTC:CTL.COMB_EV_MASK setting 1807 // OSC_COMB Combined event from Oscillator control 1808 // BATMON_COMB Combined event from battery monitor 1809 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 1810 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 1811 // settings 1812 // NONE Always inactive 1813 #define EVENT_GPT1BCAPTSEL_EV_W 7 1814 #define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F 1815 #define EVENT_GPT1BCAPTSEL_EV_S 0 1816 #define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 1817 #define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 1818 #define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 1819 #define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 1820 #define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1821 #define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 1822 #define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1823 #define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 1824 #define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 1825 #define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C 1826 #define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B 1827 #define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A 1828 #define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 1829 #define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 1830 #define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 1831 #define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 1832 #define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 1833 #define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 1834 #define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 1835 #define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 1836 #define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F 1837 #define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E 1838 #define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D 1839 #define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C 1840 #define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B 1841 #define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A 1842 #define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 1843 #define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 1844 #define EVENT_GPT1BCAPTSEL_EV_UART1_COMB 0x00000025 1845 #define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 1846 #define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 1847 #define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 1848 #define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E 1849 #define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B 1850 #define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A 1851 #define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 1852 #define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 1853 #define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B 1854 #define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 1855 #define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 1856 #define EVENT_GPT1BCAPTSEL_EV_OSC_COMB 0x00000006 1857 #define EVENT_GPT1BCAPTSEL_EV_BATMON_COMB 0x00000005 1858 #define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 1859 #define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 1860 1861 //***************************************************************************** 1862 // 1863 // Register: EVENT_O_GPT2ACAPTSEL 1864 // 1865 //***************************************************************************** 1866 // Field: [6:0] EV 1867 // 1868 // Read/write selection value 1869 // 1870 // Writing any other value than values defined by a ENUM may result in 1871 // undefined behavior. 1872 // ENUMs: 1873 // ALWAYS_ACTIVE Always asserted 1874 // AON_RTC_UPD RTC periodic event controlled by 1875 // AON_RTC:CTL.RTC_UPD_EN 1876 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 1877 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status 1878 // flags are found here AUX_EVCTL:EVTOMCUFLAGS 1879 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 1880 // AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 1881 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 1882 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 1883 // AUX_ADC_DONE AUX ADC done, corresponds to 1884 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 1885 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 1886 // AUX_SMPH:AUTOTAKE 1887 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 1888 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 1889 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 1890 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 1891 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 1892 // flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and 1893 // the AUX_TDC status AUX_TDC:STAT.DONE 1894 // AUX_COMPB AUX Compare B event, corresponds to 1895 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 1896 // AUX_COMPA AUX Compare A event, corresponds to 1897 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 1898 // AUX_AON_WU_EV AON wakeup event, the corresponding flag is here 1899 // AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 1900 // PORT_EVENT5 Port capture event from IOC, configured by 1901 // IOC:IOCFGn.PORT_ID. Events on ports configured 1902 // with ENUM PORT_EVENT4 wil be routed here. 1903 // PORT_EVENT4 Port capture event from IOC, configured by 1904 // IOC:IOCFGn.PORT_ID. Events on ports configured 1905 // with ENUM PORT_EVENT4 wil be routed here. 1906 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 1907 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 1908 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 1909 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 1910 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 1911 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 1912 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 1913 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 1914 // AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag 1915 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 1916 // AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag 1917 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 1918 // AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag 1919 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 1920 // AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag 1921 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 1922 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 1923 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 1924 // UART1_COMB UART1 combined interrupt, interrupt flags are 1925 // found here UART1:MIS 1926 // UART0_COMB UART0 combined interrupt, interrupt flags are 1927 // found here UART0:MIS 1928 // SSI1_COMB SSI1 combined interrupt, interrupt flags are found 1929 // here SSI1:MIS 1930 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 1931 // here SSI0:MIS 1932 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 1933 // Corresponding flags are here 1934 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1935 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 1936 // RFC_CPE_1 event 1937 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 1938 // Corresponding flags are here 1939 // RFC_DBELL:RFCPEIFG. Only interrupts selected 1940 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 1941 // RFC_CPE_0 event 1942 // RFC_HW_COMB Combined RFC hardware interrupt, corresponding 1943 // flag is here RFC_DBELL:RFHWIFG 1944 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 1945 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1946 // FLASH FLASH controller error event, the status flags 1947 // are FLASH:FEDACSTAT.FSM_DONE and 1948 // FLASH:FEDACSTAT.RVF_INT 1949 // AUX_COMB AUX combined event, the corresponding flag 1950 // register is here AUX_EVCTL:EVTOMCUFLAGS 1951 // I2C_IRQ Interrupt event from I2C 1952 // AON_RTC_COMB Event from AON_RTC, controlled by the 1953 // AON_RTC:CTL.COMB_EV_MASK setting 1954 // OSC_COMB Combined event from Oscillator control 1955 // BATMON_COMB Combined event from battery monitor 1956 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 1957 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 1958 // settings 1959 // NONE Always inactive 1960 #define EVENT_GPT2ACAPTSEL_EV_W 7 1961 #define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F 1962 #define EVENT_GPT2ACAPTSEL_EV_S 0 1963 #define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 1964 #define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 1965 #define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 1966 #define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 1967 #define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 1968 #define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 1969 #define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 1970 #define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 1971 #define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 1972 #define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C 1973 #define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B 1974 #define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A 1975 #define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 1976 #define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A 1977 #define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 1978 #define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 1979 #define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 1980 #define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 1981 #define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 1982 #define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 1983 #define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F 1984 #define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E 1985 #define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D 1986 #define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C 1987 #define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B 1988 #define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A 1989 #define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 1990 #define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 1991 #define EVENT_GPT2ACAPTSEL_EV_UART1_COMB 0x00000025 1992 #define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 1993 #define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 1994 #define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 1995 #define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E 1996 #define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B 1997 #define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A 1998 #define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 1999 #define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 2000 #define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B 2001 #define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 2002 #define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 2003 #define EVENT_GPT2ACAPTSEL_EV_OSC_COMB 0x00000006 2004 #define EVENT_GPT2ACAPTSEL_EV_BATMON_COMB 0x00000005 2005 #define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 2006 #define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 2007 2008 //***************************************************************************** 2009 // 2010 // Register: EVENT_O_GPT2BCAPTSEL 2011 // 2012 //***************************************************************************** 2013 // Field: [6:0] EV 2014 // 2015 // Read/write selection value 2016 // 2017 // Writing any other value than values defined by a ENUM may result in 2018 // undefined behavior. 2019 // ENUMs: 2020 // ALWAYS_ACTIVE Always asserted 2021 // AON_RTC_UPD RTC periodic event controlled by 2022 // AON_RTC:CTL.RTC_UPD_EN 2023 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 2024 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status 2025 // flags are found here AUX_EVCTL:EVTOMCUFLAGS 2026 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 2027 // AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 2028 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 2029 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 2030 // AUX_ADC_DONE AUX ADC done, corresponds to 2031 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 2032 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 2033 // AUX_SMPH:AUTOTAKE 2034 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 2035 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 2036 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 2037 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 2038 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 2039 // flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and 2040 // the AUX_TDC status AUX_TDC:STAT.DONE 2041 // AUX_COMPB AUX Compare B event, corresponds to 2042 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 2043 // AUX_COMPA AUX Compare A event, corresponds to 2044 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 2045 // AUX_AON_WU_EV AON wakeup event, the corresponding flag is here 2046 // AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 2047 // PORT_EVENT5 Port capture event from IOC, configured by 2048 // IOC:IOCFGn.PORT_ID. Events on ports configured 2049 // with ENUM PORT_EVENT4 wil be routed here. 2050 // PORT_EVENT4 Port capture event from IOC, configured by 2051 // IOC:IOCFGn.PORT_ID. Events on ports configured 2052 // with ENUM PORT_EVENT4 wil be routed here. 2053 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 2054 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 2055 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 2056 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 2057 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 2058 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 2059 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 2060 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 2061 // AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag 2062 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 2063 // AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag 2064 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 2065 // AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag 2066 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 2067 // AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag 2068 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 2069 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 2070 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 2071 // UART1_COMB UART1 combined interrupt, interrupt flags are 2072 // found here UART1:MIS 2073 // UART0_COMB UART0 combined interrupt, interrupt flags are 2074 // found here UART0:MIS 2075 // SSI1_COMB SSI1 combined interrupt, interrupt flags are found 2076 // here SSI1:MIS 2077 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 2078 // here SSI0:MIS 2079 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 2080 // Corresponding flags are here 2081 // RFC_DBELL:RFCPEIFG. Only interrupts selected 2082 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 2083 // RFC_CPE_1 event 2084 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 2085 // Corresponding flags are here 2086 // RFC_DBELL:RFCPEIFG. Only interrupts selected 2087 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 2088 // RFC_CPE_0 event 2089 // RFC_HW_COMB Combined RFC hardware interrupt, corresponding 2090 // flag is here RFC_DBELL:RFHWIFG 2091 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 2092 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 2093 // FLASH FLASH controller error event, the status flags 2094 // are FLASH:FEDACSTAT.FSM_DONE and 2095 // FLASH:FEDACSTAT.RVF_INT 2096 // AUX_COMB AUX combined event, the corresponding flag 2097 // register is here AUX_EVCTL:EVTOMCUFLAGS 2098 // I2C_IRQ Interrupt event from I2C 2099 // AON_RTC_COMB Event from AON_RTC, controlled by the 2100 // AON_RTC:CTL.COMB_EV_MASK setting 2101 // OSC_COMB Combined event from Oscillator control 2102 // BATMON_COMB Combined event from battery monitor 2103 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 2104 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 2105 // settings 2106 // NONE Always inactive 2107 #define EVENT_GPT2BCAPTSEL_EV_W 7 2108 #define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F 2109 #define EVENT_GPT2BCAPTSEL_EV_S 0 2110 #define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 2111 #define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 2112 #define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 2113 #define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 2114 #define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 2115 #define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 2116 #define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 2117 #define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 2118 #define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 2119 #define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C 2120 #define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B 2121 #define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A 2122 #define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 2123 #define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A 2124 #define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 2125 #define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 2126 #define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 2127 #define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 2128 #define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 2129 #define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 2130 #define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F 2131 #define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E 2132 #define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D 2133 #define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C 2134 #define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B 2135 #define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A 2136 #define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 2137 #define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 2138 #define EVENT_GPT2BCAPTSEL_EV_UART1_COMB 0x00000025 2139 #define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 2140 #define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 2141 #define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 2142 #define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E 2143 #define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B 2144 #define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A 2145 #define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 2146 #define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 2147 #define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B 2148 #define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 2149 #define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 2150 #define EVENT_GPT2BCAPTSEL_EV_OSC_COMB 0x00000006 2151 #define EVENT_GPT2BCAPTSEL_EV_BATMON_COMB 0x00000005 2152 #define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 2153 #define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 2154 2155 //***************************************************************************** 2156 // 2157 // Register: EVENT_O_UDMACH1SSEL 2158 // 2159 //***************************************************************************** 2160 // Field: [6:0] EV 2161 // 2162 // Read only selection value 2163 // ENUMs: 2164 // UART0_RX_DMASREQ UART0 RX DMA single request, controlled by 2165 // UART0:DMACTL.RXDMAE 2166 #define EVENT_UDMACH1SSEL_EV_W 7 2167 #define EVENT_UDMACH1SSEL_EV_M 0x0000007F 2168 #define EVENT_UDMACH1SSEL_EV_S 0 2169 #define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 2170 2171 //***************************************************************************** 2172 // 2173 // Register: EVENT_O_UDMACH1BSEL 2174 // 2175 //***************************************************************************** 2176 // Field: [6:0] EV 2177 // 2178 // Read only selection value 2179 // ENUMs: 2180 // UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by 2181 // UART0:DMACTL.RXDMAE 2182 #define EVENT_UDMACH1BSEL_EV_W 7 2183 #define EVENT_UDMACH1BSEL_EV_M 0x0000007F 2184 #define EVENT_UDMACH1BSEL_EV_S 0 2185 #define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 2186 2187 //***************************************************************************** 2188 // 2189 // Register: EVENT_O_UDMACH2SSEL 2190 // 2191 //***************************************************************************** 2192 // Field: [6:0] EV 2193 // 2194 // Read only selection value 2195 // ENUMs: 2196 // UART0_TX_DMASREQ UART0 TX DMA single request, controlled by 2197 // UART0:DMACTL.TXDMAE 2198 #define EVENT_UDMACH2SSEL_EV_W 7 2199 #define EVENT_UDMACH2SSEL_EV_M 0x0000007F 2200 #define EVENT_UDMACH2SSEL_EV_S 0 2201 #define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 2202 2203 //***************************************************************************** 2204 // 2205 // Register: EVENT_O_UDMACH2BSEL 2206 // 2207 //***************************************************************************** 2208 // Field: [6:0] EV 2209 // 2210 // Read only selection value 2211 // ENUMs: 2212 // UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by 2213 // UART0:DMACTL.TXDMAE 2214 #define EVENT_UDMACH2BSEL_EV_W 7 2215 #define EVENT_UDMACH2BSEL_EV_M 0x0000007F 2216 #define EVENT_UDMACH2BSEL_EV_S 0 2217 #define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 2218 2219 //***************************************************************************** 2220 // 2221 // Register: EVENT_O_UDMACH3SSEL 2222 // 2223 //***************************************************************************** 2224 // Field: [6:0] EV 2225 // 2226 // Read only selection value 2227 // ENUMs: 2228 // SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by 2229 // SSI0:DMACR.RXDMAE 2230 #define EVENT_UDMACH3SSEL_EV_W 7 2231 #define EVENT_UDMACH3SSEL_EV_M 0x0000007F 2232 #define EVENT_UDMACH3SSEL_EV_S 0 2233 #define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 2234 2235 //***************************************************************************** 2236 // 2237 // Register: EVENT_O_UDMACH3BSEL 2238 // 2239 //***************************************************************************** 2240 // Field: [6:0] EV 2241 // 2242 // Read only selection value 2243 // ENUMs: 2244 // SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by 2245 // SSI0:DMACR.RXDMAE 2246 #define EVENT_UDMACH3BSEL_EV_W 7 2247 #define EVENT_UDMACH3BSEL_EV_M 0x0000007F 2248 #define EVENT_UDMACH3BSEL_EV_S 0 2249 #define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 2250 2251 //***************************************************************************** 2252 // 2253 // Register: EVENT_O_UDMACH4SSEL 2254 // 2255 //***************************************************************************** 2256 // Field: [6:0] EV 2257 // 2258 // Read only selection value 2259 // ENUMs: 2260 // SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by 2261 // SSI0:DMACR.TXDMAE 2262 #define EVENT_UDMACH4SSEL_EV_W 7 2263 #define EVENT_UDMACH4SSEL_EV_M 0x0000007F 2264 #define EVENT_UDMACH4SSEL_EV_S 0 2265 #define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B 2266 2267 //***************************************************************************** 2268 // 2269 // Register: EVENT_O_UDMACH4BSEL 2270 // 2271 //***************************************************************************** 2272 // Field: [6:0] EV 2273 // 2274 // Read only selection value 2275 // ENUMs: 2276 // SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by 2277 // SSI0:DMACR.TXDMAE 2278 #define EVENT_UDMACH4BSEL_EV_W 7 2279 #define EVENT_UDMACH4BSEL_EV_M 0x0000007F 2280 #define EVENT_UDMACH4BSEL_EV_S 0 2281 #define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A 2282 2283 //***************************************************************************** 2284 // 2285 // Register: EVENT_O_UDMACH5SSEL 2286 // 2287 //***************************************************************************** 2288 // Field: [6:0] EV 2289 // 2290 // Read only selection value 2291 // ENUMs: 2292 // UART1_RX_DMASREQ UART1 RX DMA single request, controlled by 2293 // UART1:DMACTL.RXDMAE 2294 #define EVENT_UDMACH5SSEL_EV_W 7 2295 #define EVENT_UDMACH5SSEL_EV_M 0x0000007F 2296 #define EVENT_UDMACH5SSEL_EV_S 0 2297 #define EVENT_UDMACH5SSEL_EV_UART1_RX_DMASREQ 0x00000035 2298 2299 //***************************************************************************** 2300 // 2301 // Register: EVENT_O_UDMACH5BSEL 2302 // 2303 //***************************************************************************** 2304 // Field: [6:0] EV 2305 // 2306 // Read only selection value 2307 // ENUMs: 2308 // UART1_RX_DMABREQ UART1 RX DMA burst request, controlled by 2309 // UART1:DMACTL.RXDMAE 2310 #define EVENT_UDMACH5BSEL_EV_W 7 2311 #define EVENT_UDMACH5BSEL_EV_M 0x0000007F 2312 #define EVENT_UDMACH5BSEL_EV_S 0 2313 #define EVENT_UDMACH5BSEL_EV_UART1_RX_DMABREQ 0x00000034 2314 2315 //***************************************************************************** 2316 // 2317 // Register: EVENT_O_UDMACH6SSEL 2318 // 2319 //***************************************************************************** 2320 // Field: [6:0] EV 2321 // 2322 // Read only selection value 2323 // ENUMs: 2324 // UART1_TX_DMASREQ UART1 TX DMA single request, controlled by 2325 // UART1:DMACTL.TXDMAE 2326 #define EVENT_UDMACH6SSEL_EV_W 7 2327 #define EVENT_UDMACH6SSEL_EV_M 0x0000007F 2328 #define EVENT_UDMACH6SSEL_EV_S 0 2329 #define EVENT_UDMACH6SSEL_EV_UART1_TX_DMASREQ 0x00000037 2330 2331 //***************************************************************************** 2332 // 2333 // Register: EVENT_O_UDMACH6BSEL 2334 // 2335 //***************************************************************************** 2336 // Field: [6:0] EV 2337 // 2338 // Read only selection value 2339 // ENUMs: 2340 // UART1_TX_DMABREQ UART1 TX DMA burst request, controlled by 2341 // UART1:DMACTL.TXDMAE 2342 #define EVENT_UDMACH6BSEL_EV_W 7 2343 #define EVENT_UDMACH6BSEL_EV_M 0x0000007F 2344 #define EVENT_UDMACH6BSEL_EV_S 0 2345 #define EVENT_UDMACH6BSEL_EV_UART1_TX_DMABREQ 0x00000036 2346 2347 //***************************************************************************** 2348 // 2349 // Register: EVENT_O_UDMACH7SSEL 2350 // 2351 //***************************************************************************** 2352 // Field: [6:0] EV 2353 // 2354 // Read only selection value 2355 // ENUMs: 2356 // AUX_DMASREQ DMA single request event from AUX, configured by 2357 // AUX_EVCTL:DMACTL 2358 #define EVENT_UDMACH7SSEL_EV_W 7 2359 #define EVENT_UDMACH7SSEL_EV_M 0x0000007F 2360 #define EVENT_UDMACH7SSEL_EV_S 0 2361 #define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 2362 2363 //***************************************************************************** 2364 // 2365 // Register: EVENT_O_UDMACH7BSEL 2366 // 2367 //***************************************************************************** 2368 // Field: [6:0] EV 2369 // 2370 // Read only selection value 2371 // ENUMs: 2372 // AUX_DMABREQ DMA burst request event from AUX, configured by 2373 // AUX_EVCTL:DMACTL 2374 #define EVENT_UDMACH7BSEL_EV_W 7 2375 #define EVENT_UDMACH7BSEL_EV_M 0x0000007F 2376 #define EVENT_UDMACH7BSEL_EV_S 0 2377 #define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 2378 2379 //***************************************************************************** 2380 // 2381 // Register: EVENT_O_UDMACH8SSEL 2382 // 2383 //***************************************************************************** 2384 // Field: [6:0] EV 2385 // 2386 // Read only selection value 2387 // ENUMs: 2388 // AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by 2389 // AUX_EVCTL:DMASWREQ.START 2390 #define EVENT_UDMACH8SSEL_EV_W 7 2391 #define EVENT_UDMACH8SSEL_EV_M 0x0000007F 2392 #define EVENT_UDMACH8SSEL_EV_S 0 2393 #define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 2394 2395 //***************************************************************************** 2396 // 2397 // Register: EVENT_O_UDMACH8BSEL 2398 // 2399 //***************************************************************************** 2400 // Field: [6:0] EV 2401 // 2402 // Read only selection value 2403 // ENUMs: 2404 // AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by 2405 // AUX_EVCTL:DMASWREQ.START 2406 #define EVENT_UDMACH8BSEL_EV_W 7 2407 #define EVENT_UDMACH8BSEL_EV_M 0x0000007F 2408 #define EVENT_UDMACH8BSEL_EV_S 0 2409 #define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 2410 2411 //***************************************************************************** 2412 // 2413 // Register: EVENT_O_UDMACH9SSEL 2414 // 2415 //***************************************************************************** 2416 // Field: [6:0] EV 2417 // 2418 // Read/write selection value 2419 // 2420 // Writing any other value than values defined by a ENUM may result in 2421 // undefined behavior. 2422 // ENUMs: 2423 // ALWAYS_ACTIVE Always asserted 2424 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2425 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2426 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2427 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2428 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2429 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2430 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2431 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2432 // TIE_LOW Not used tied to 0 2433 // NONE Always inactive 2434 #define EVENT_UDMACH9SSEL_EV_W 7 2435 #define EVENT_UDMACH9SSEL_EV_M 0x0000007F 2436 #define EVENT_UDMACH9SSEL_EV_S 0 2437 #define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 2438 #define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 2439 #define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 2440 #define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 2441 #define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 2442 #define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 2443 #define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F 2444 #define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E 2445 #define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D 2446 #define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 2447 #define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 2448 2449 //***************************************************************************** 2450 // 2451 // Register: EVENT_O_UDMACH9BSEL 2452 // 2453 //***************************************************************************** 2454 // Field: [6:0] EV 2455 // 2456 // Read/write selection value 2457 // 2458 // Writing any other value than values defined by a ENUM may result in 2459 // undefined behavior. 2460 // ENUMs: 2461 // ALWAYS_ACTIVE Always asserted 2462 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2463 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2464 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2465 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2466 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2467 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2468 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2469 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2470 // NONE Always inactive 2471 #define EVENT_UDMACH9BSEL_EV_W 7 2472 #define EVENT_UDMACH9BSEL_EV_M 0x0000007F 2473 #define EVENT_UDMACH9BSEL_EV_S 0 2474 #define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 2475 #define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 2476 #define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 2477 #define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 2478 #define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 2479 #define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 2480 #define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F 2481 #define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E 2482 #define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D 2483 #define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 2484 2485 //***************************************************************************** 2486 // 2487 // Register: EVENT_O_UDMACH10SSEL 2488 // 2489 //***************************************************************************** 2490 // Field: [6:0] EV 2491 // 2492 // Read/write selection value 2493 // 2494 // Writing any other value than values defined by a ENUM may result in 2495 // undefined behavior. 2496 // ENUMs: 2497 // ALWAYS_ACTIVE Always asserted 2498 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2499 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2500 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2501 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2502 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2503 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2504 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2505 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2506 // TIE_LOW Not used tied to 0 2507 // NONE Always inactive 2508 #define EVENT_UDMACH10SSEL_EV_W 7 2509 #define EVENT_UDMACH10SSEL_EV_M 0x0000007F 2510 #define EVENT_UDMACH10SSEL_EV_S 0 2511 #define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 2512 #define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 2513 #define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 2514 #define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 2515 #define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 2516 #define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 2517 #define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F 2518 #define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E 2519 #define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D 2520 #define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 2521 #define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 2522 2523 //***************************************************************************** 2524 // 2525 // Register: EVENT_O_UDMACH10BSEL 2526 // 2527 //***************************************************************************** 2528 // Field: [6:0] EV 2529 // 2530 // Read/write selection value 2531 // 2532 // Writing any other value than values defined by a ENUM may result in 2533 // undefined behavior. 2534 // ENUMs: 2535 // ALWAYS_ACTIVE Always asserted 2536 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2537 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2538 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2539 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2540 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2541 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2542 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2543 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2544 // NONE Always inactive 2545 #define EVENT_UDMACH10BSEL_EV_W 7 2546 #define EVENT_UDMACH10BSEL_EV_M 0x0000007F 2547 #define EVENT_UDMACH10BSEL_EV_S 0 2548 #define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 2549 #define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 2550 #define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 2551 #define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 2552 #define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 2553 #define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 2554 #define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F 2555 #define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E 2556 #define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D 2557 #define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 2558 2559 //***************************************************************************** 2560 // 2561 // Register: EVENT_O_UDMACH11SSEL 2562 // 2563 //***************************************************************************** 2564 // Field: [6:0] EV 2565 // 2566 // Read/write selection value 2567 // 2568 // Writing any other value than values defined by a ENUM may result in 2569 // undefined behavior. 2570 // ENUMs: 2571 // ALWAYS_ACTIVE Always asserted 2572 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2573 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2574 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2575 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2576 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2577 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2578 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2579 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2580 // TIE_LOW Not used tied to 0 2581 // NONE Always inactive 2582 #define EVENT_UDMACH11SSEL_EV_W 7 2583 #define EVENT_UDMACH11SSEL_EV_M 0x0000007F 2584 #define EVENT_UDMACH11SSEL_EV_S 0 2585 #define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 2586 #define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 2587 #define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 2588 #define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 2589 #define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 2590 #define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 2591 #define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F 2592 #define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E 2593 #define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D 2594 #define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 2595 #define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 2596 2597 //***************************************************************************** 2598 // 2599 // Register: EVENT_O_UDMACH11BSEL 2600 // 2601 //***************************************************************************** 2602 // Field: [6:0] EV 2603 // 2604 // Read/write selection value 2605 // 2606 // Writing any other value than values defined by a ENUM may result in 2607 // undefined behavior. 2608 // ENUMs: 2609 // ALWAYS_ACTIVE Always asserted 2610 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2611 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2612 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2613 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2614 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2615 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2616 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2617 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2618 // NONE Always inactive 2619 #define EVENT_UDMACH11BSEL_EV_W 7 2620 #define EVENT_UDMACH11BSEL_EV_M 0x0000007F 2621 #define EVENT_UDMACH11BSEL_EV_S 0 2622 #define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 2623 #define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 2624 #define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 2625 #define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 2626 #define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 2627 #define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 2628 #define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F 2629 #define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E 2630 #define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D 2631 #define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 2632 2633 //***************************************************************************** 2634 // 2635 // Register: EVENT_O_UDMACH12SSEL 2636 // 2637 //***************************************************************************** 2638 // Field: [6:0] EV 2639 // 2640 // Read/write selection value 2641 // 2642 // Writing any other value than values defined by a ENUM may result in 2643 // undefined behavior. 2644 // ENUMs: 2645 // ALWAYS_ACTIVE Always asserted 2646 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2647 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2648 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2649 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2650 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2651 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2652 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2653 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2654 // TIE_LOW Not used tied to 0 2655 // NONE Always inactive 2656 #define EVENT_UDMACH12SSEL_EV_W 7 2657 #define EVENT_UDMACH12SSEL_EV_M 0x0000007F 2658 #define EVENT_UDMACH12SSEL_EV_S 0 2659 #define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 2660 #define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 2661 #define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 2662 #define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 2663 #define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 2664 #define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 2665 #define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F 2666 #define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E 2667 #define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D 2668 #define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 2669 #define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 2670 2671 //***************************************************************************** 2672 // 2673 // Register: EVENT_O_UDMACH12BSEL 2674 // 2675 //***************************************************************************** 2676 // Field: [6:0] EV 2677 // 2678 // Read/write selection value 2679 // 2680 // Writing any other value than values defined by a ENUM may result in 2681 // undefined behavior. 2682 // ENUMs: 2683 // ALWAYS_ACTIVE Always asserted 2684 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2685 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2686 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2687 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2688 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2689 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2690 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2691 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2692 // NONE Always inactive 2693 #define EVENT_UDMACH12BSEL_EV_W 7 2694 #define EVENT_UDMACH12BSEL_EV_M 0x0000007F 2695 #define EVENT_UDMACH12BSEL_EV_S 0 2696 #define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 2697 #define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 2698 #define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 2699 #define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 2700 #define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 2701 #define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 2702 #define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F 2703 #define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E 2704 #define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D 2705 #define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 2706 2707 //***************************************************************************** 2708 // 2709 // Register: EVENT_O_UDMACH13BSEL 2710 // 2711 //***************************************************************************** 2712 // Field: [6:0] EV 2713 // 2714 // Read only selection value 2715 // ENUMs: 2716 // AON_PROG2 AON programmable event 2. Event selected by 2717 // AON_EVENT MCU event selector, 2718 // AON_EVENT:EVTOMCUSEL.AON_PROG2_EV 2719 #define EVENT_UDMACH13BSEL_EV_W 7 2720 #define EVENT_UDMACH13BSEL_EV_M 0x0000007F 2721 #define EVENT_UDMACH13BSEL_EV_S 0 2722 #define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 2723 2724 //***************************************************************************** 2725 // 2726 // Register: EVENT_O_UDMACH14BSEL 2727 // 2728 //***************************************************************************** 2729 // Field: [6:0] EV 2730 // 2731 // Read/write selection value 2732 // 2733 // Writing any other value than values defined by a ENUM may result in 2734 // undefined behavior. 2735 // ENUMs: 2736 // ALWAYS_ACTIVE Always asserted 2737 // CPU_HALTED CPU halted 2738 // AON_RTC_UPD RTC periodic event controlled by 2739 // AON_RTC:CTL.RTC_UPD_EN 2740 // AUX_DMABREQ DMA burst request event from AUX, configured by 2741 // AUX_EVCTL:DMACTL 2742 // AUX_DMASREQ DMA single request event from AUX, configured by 2743 // AUX_EVCTL:DMACTL 2744 // AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by 2745 // AUX_EVCTL:DMASWREQ.START 2746 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 2747 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status 2748 // flags are found here AUX_EVCTL:EVTOMCUFLAGS 2749 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 2750 // AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 2751 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 2752 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 2753 // AUX_ADC_DONE AUX ADC done, corresponds to 2754 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 2755 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 2756 // AUX_SMPH:AUTOTAKE 2757 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 2758 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 2759 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 2760 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 2761 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 2762 // flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and 2763 // the AUX_TDC status AUX_TDC:STAT.DONE 2764 // AUX_COMPB AUX Compare B event, corresponds to 2765 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 2766 // AUX_COMPA AUX Compare A event, corresponds to 2767 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 2768 // AUX_AON_WU_EV AON wakeup event, the corresponding flag is here 2769 // AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 2770 // TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN 2771 // SWEV3 Software event 3, triggered by SWEV.SWEV3 2772 // SWEV2 Software event 2, triggered by SWEV.SWEV2 2773 // SWEV1 Software event 1, triggered by SWEV.SWEV1 2774 // SWEV0 Software event 0, triggered by SWEV.SWEV0 2775 // WDT_NMI Watchdog non maskable interrupt event, controlled 2776 // by WDT:CTL.INTTYPE 2777 // CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg 2778 // flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled 2779 // by CRYPTO:IRQEN.DMA_IN_DONE 2780 // CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the 2781 // corresponding flag is found here 2782 // CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by 2783 // CRYPTO:IRQSTAT.RESULT_AVAIL 2784 // PORT_EVENT7 Port capture event from IOC, configured by 2785 // IOC:IOCFGn.PORT_ID. Events on ports configured 2786 // with ENUM PORT_EVENT7 wil be routed here. 2787 // PORT_EVENT6 Port capture event from IOC, configured by 2788 // IOC:IOCFGn.PORT_ID. Events on ports configured 2789 // with ENUM PORT_EVENT6 wil be routed here. 2790 // PORT_EVENT5 Port capture event from IOC, configured by 2791 // IOC:IOCFGn.PORT_ID. Events on ports configured 2792 // with ENUM PORT_EVENT4 wil be routed here. 2793 // PORT_EVENT4 Port capture event from IOC, configured by 2794 // IOC:IOCFGn.PORT_ID. Events on ports configured 2795 // with ENUM PORT_EVENT4 wil be routed here. 2796 // PORT_EVENT3 Port capture event from IOC, configured by 2797 // IOC:IOCFGn.PORT_ID. Events on ports configured 2798 // with ENUM PORT_EVENT3 wil be routed here. 2799 // PORT_EVENT2 Port capture event from IOC, configured by 2800 // IOC:IOCFGn.PORT_ID. Events on ports configured 2801 // with ENUM PORT_EVENT2 wil be routed here. 2802 // PORT_EVENT1 Port capture event from IOC, configured by 2803 // IOC:IOCFGn.PORT_ID. Events on ports configured 2804 // with ENUM PORT_EVENT1 wil be routed here. 2805 // PORT_EVENT0 Port capture event from IOC, configured by 2806 // IOC:IOCFGn.PORT_ID. Events on ports configured 2807 // with ENUM PORT_EVENT0 wil be routed here. 2808 // GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV 2809 // GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV 2810 // GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV 2811 // GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV 2812 // GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV 2813 // GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV 2814 // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV 2815 // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV 2816 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 2817 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 2818 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 2819 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 2820 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 2821 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 2822 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 2823 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 2824 // AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag 2825 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 2826 // AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag 2827 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 2828 // AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag 2829 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 2830 // AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag 2831 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 2832 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 2833 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 2834 // UART1_TX_DMASREQ UART1 TX DMA single request, controlled by 2835 // UART1:DMACTL.TXDMAE 2836 // UART1_TX_DMABREQ UART1 TX DMA burst request, controlled by 2837 // UART1:DMACTL.TXDMAE 2838 // UART1_RX_DMASREQ UART1 RX DMA single request, controlled by 2839 // UART1:DMACTL.RXDMAE 2840 // UART1_RX_DMABREQ UART1 RX DMA burst request, controlled by 2841 // UART1:DMACTL.RXDMAE 2842 // UART0_TX_DMASREQ UART0 TX DMA single request, controlled by 2843 // UART0:DMACTL.TXDMAE 2844 // UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by 2845 // UART0:DMACTL.TXDMAE 2846 // UART0_RX_DMASREQ UART0 RX DMA single request, controlled by 2847 // UART0:DMACTL.RXDMAE 2848 // UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by 2849 // UART0:DMACTL.RXDMAE 2850 // SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by 2851 // SSI0:DMACR.TXDMAE 2852 // SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by 2853 // SSI0:DMACR.TXDMAE 2854 // SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by 2855 // SSI0:DMACR.RXDMAE 2856 // SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by 2857 // SSI0:DMACR.RXDMAE 2858 // SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by 2859 // SSI0:DMACR.TXDMAE 2860 // SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by 2861 // SSI0:DMACR.TXDMAE 2862 // SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by 2863 // SSI0:DMACR.RXDMAE 2864 // SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by 2865 // SSI0:DMACR.RXDMAE 2866 // DMA_DONE_COMB Combined DMA done, corresponding flags are here 2867 // UDMA0:REQDONE 2868 // DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS 2869 // UART1_COMB UART1 combined interrupt, interrupt flags are 2870 // found here UART1:MIS 2871 // UART0_COMB UART0 combined interrupt, interrupt flags are 2872 // found here UART0:MIS 2873 // SSI1_COMB SSI1 combined interrupt, interrupt flags are found 2874 // here SSI1:MIS 2875 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 2876 // here SSI0:MIS 2877 // PKA_IRQ PKA Interrupt event 2878 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 2879 // Corresponding flags are here 2880 // RFC_DBELL:RFCPEIFG. Only interrupts selected 2881 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 2882 // RFC_CPE_1 event 2883 // AUX_SWEV1 AUX software event 1, triggered by 2884 // AUX_EVCTL:SWEVSET.SWEV1, also available as 2885 // AUX_EVENT2 AON wake up event. 2886 // MCU domain wakeup control 2887 // AON_EVENT:MCUWUSEL 2888 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 2889 // Corresponding flags are here 2890 // RFC_DBELL:RFCPEIFG. Only interrupts selected 2891 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 2892 // RFC_CPE_0 event 2893 // RFC_HW_COMB Combined RFC hardware interrupt, corresponding 2894 // flag is here RFC_DBELL:RFHWIFG 2895 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 2896 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 2897 // WDT_IRQ Watchdog interrupt event, controlled by 2898 // WDT:CTL.INTEN 2899 // DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, 2900 // see UDMA0:SOFTREQ 2901 // FLASH FLASH controller error event, the status flags 2902 // are FLASH:FEDACSTAT.FSM_DONE and 2903 // FLASH:FEDACSTAT.RVF_INT 2904 // DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see 2905 // UDMA0:SOFTREQ 2906 // GPT1B GPT1B interrupt event, controlled by GPT1:TBMR 2907 // GPT1A GPT1A interrupt event, controlled by GPT1:TAMR 2908 // GPT0B GPT0B interrupt event, controlled by GPT0:TBMR 2909 // GPT0A GPT0A interrupt event, controlled by GPT0:TAMR 2910 // GPT3B GPT3B interrupt event, controlled by GPT3:TBMR 2911 // GPT3A GPT3A interrupt event, controlled by GPT3:TAMR 2912 // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR 2913 // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR 2914 // AUX_COMB AUX combined event, the corresponding flag 2915 // register is here AUX_EVCTL:EVTOMCUFLAGS 2916 // AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 2917 // I2C_IRQ Interrupt event from I2C 2918 // I2S_IRQ Interrupt event from I2S 2919 // AON_RTC_COMB Event from AON_RTC, controlled by the 2920 // AON_RTC:CTL.COMB_EV_MASK setting 2921 // OSC_COMB Combined event from Oscillator control 2922 // BATMON_COMB Combined event from battery monitor 2923 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 2924 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 2925 // settings 2926 // AON_PROG2 AON programmable event 2. Event selected by 2927 // AON_EVENT MCU event selector, 2928 // AON_EVENT:EVTOMCUSEL.AON_PROG2_EV 2929 // AON_PROG1 AON programmable event 1. Event selected by 2930 // AON_EVENT MCU event selector, 2931 // AON_EVENT:EVTOMCUSEL.AON_PROG1_EV 2932 // AON_PROG0 AON programmable event 0. Event selected by 2933 // AON_EVENT MCU event selector, 2934 // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV 2935 // NONE Always inactive 2936 #define EVENT_UDMACH14BSEL_EV_W 7 2937 #define EVENT_UDMACH14BSEL_EV_M 0x0000007F 2938 #define EVENT_UDMACH14BSEL_EV_S 0 2939 #define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 2940 #define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 2941 #define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 2942 #define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 2943 #define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 2944 #define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 2945 #define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 2946 #define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 2947 #define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 2948 #define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 2949 #define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 2950 #define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E 2951 #define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D 2952 #define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C 2953 #define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B 2954 #define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A 2955 #define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 2956 #define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 2957 #define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 2958 #define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 2959 #define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 2960 #define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 2961 #define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 2962 #define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E 2963 #define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D 2964 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C 2965 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B 2966 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A 2967 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 2968 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 2969 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 2970 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 2971 #define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 2972 #define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 2973 #define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 2974 #define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 2975 #define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 2976 #define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 2977 #define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F 2978 #define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E 2979 #define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D 2980 #define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 2981 #define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 2982 #define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 2983 #define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 2984 #define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 2985 #define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F 2986 #define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E 2987 #define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D 2988 #define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_PULSE 0x0000003C 2989 #define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV3 0x0000003B 2990 #define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV2 0x0000003A 2991 #define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV1 0x00000039 2992 #define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV0 0x00000038 2993 #define EVENT_UDMACH14BSEL_EV_UART1_TX_DMASREQ 0x00000037 2994 #define EVENT_UDMACH14BSEL_EV_UART1_TX_DMABREQ 0x00000036 2995 #define EVENT_UDMACH14BSEL_EV_UART1_RX_DMASREQ 0x00000035 2996 #define EVENT_UDMACH14BSEL_EV_UART1_RX_DMABREQ 0x00000034 2997 #define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 2998 #define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 2999 #define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 3000 #define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 3001 #define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F 3002 #define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E 3003 #define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D 3004 #define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C 3005 #define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B 3006 #define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A 3007 #define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 3008 #define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 3009 #define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 3010 #define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 3011 #define EVENT_UDMACH14BSEL_EV_UART1_COMB 0x00000025 3012 #define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 3013 #define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 3014 #define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 3015 #define EVENT_UDMACH14BSEL_EV_PKA_IRQ 0x0000001F 3016 #define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E 3017 #define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D 3018 #define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B 3019 #define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A 3020 #define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 3021 #define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 3022 #define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 3023 #define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 3024 #define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 3025 #define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 3026 #define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 3027 #define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 3028 #define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 3029 #define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F 3030 #define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E 3031 #define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D 3032 #define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C 3033 #define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B 3034 #define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A 3035 #define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 3036 #define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 3037 #define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 3038 #define EVENT_UDMACH14BSEL_EV_OSC_COMB 0x00000006 3039 #define EVENT_UDMACH14BSEL_EV_BATMON_COMB 0x00000005 3040 #define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 3041 #define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 3042 #define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 3043 #define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 3044 #define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 3045 3046 //***************************************************************************** 3047 // 3048 // Register: EVENT_O_UDMACH15BSEL 3049 // 3050 //***************************************************************************** 3051 // Field: [6:0] EV 3052 // 3053 // Read only selection value 3054 // ENUMs: 3055 // AON_RTC_COMB Event from AON_RTC, controlled by the 3056 // AON_RTC:CTL.COMB_EV_MASK setting 3057 #define EVENT_UDMACH15BSEL_EV_W 7 3058 #define EVENT_UDMACH15BSEL_EV_M 0x0000007F 3059 #define EVENT_UDMACH15BSEL_EV_S 0 3060 #define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 3061 3062 //***************************************************************************** 3063 // 3064 // Register: EVENT_O_UDMACH16SSEL 3065 // 3066 //***************************************************************************** 3067 // Field: [6:0] EV 3068 // 3069 // Read only selection value 3070 // ENUMs: 3071 // SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by 3072 // SSI0:DMACR.RXDMAE 3073 #define EVENT_UDMACH16SSEL_EV_W 7 3074 #define EVENT_UDMACH16SSEL_EV_M 0x0000007F 3075 #define EVENT_UDMACH16SSEL_EV_S 0 3076 #define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D 3077 3078 //***************************************************************************** 3079 // 3080 // Register: EVENT_O_UDMACH16BSEL 3081 // 3082 //***************************************************************************** 3083 // Field: [6:0] EV 3084 // 3085 // Read only selection value 3086 // ENUMs: 3087 // SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by 3088 // SSI0:DMACR.RXDMAE 3089 #define EVENT_UDMACH16BSEL_EV_W 7 3090 #define EVENT_UDMACH16BSEL_EV_M 0x0000007F 3091 #define EVENT_UDMACH16BSEL_EV_S 0 3092 #define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C 3093 3094 //***************************************************************************** 3095 // 3096 // Register: EVENT_O_UDMACH17SSEL 3097 // 3098 //***************************************************************************** 3099 // Field: [6:0] EV 3100 // 3101 // Read only selection value 3102 // ENUMs: 3103 // SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by 3104 // SSI0:DMACR.TXDMAE 3105 #define EVENT_UDMACH17SSEL_EV_W 7 3106 #define EVENT_UDMACH17SSEL_EV_M 0x0000007F 3107 #define EVENT_UDMACH17SSEL_EV_S 0 3108 #define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F 3109 3110 //***************************************************************************** 3111 // 3112 // Register: EVENT_O_UDMACH17BSEL 3113 // 3114 //***************************************************************************** 3115 // Field: [6:0] EV 3116 // 3117 // Read only selection value 3118 // ENUMs: 3119 // SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by 3120 // SSI0:DMACR.TXDMAE 3121 #define EVENT_UDMACH17BSEL_EV_W 7 3122 #define EVENT_UDMACH17BSEL_EV_M 0x0000007F 3123 #define EVENT_UDMACH17BSEL_EV_S 0 3124 #define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E 3125 3126 //***************************************************************************** 3127 // 3128 // Register: EVENT_O_UDMACH21SSEL 3129 // 3130 //***************************************************************************** 3131 // Field: [6:0] EV 3132 // 3133 // Read only selection value 3134 // ENUMs: 3135 // SWEV0 Software event 0, triggered by SWEV.SWEV0 3136 #define EVENT_UDMACH21SSEL_EV_W 7 3137 #define EVENT_UDMACH21SSEL_EV_M 0x0000007F 3138 #define EVENT_UDMACH21SSEL_EV_S 0 3139 #define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 3140 3141 //***************************************************************************** 3142 // 3143 // Register: EVENT_O_UDMACH21BSEL 3144 // 3145 //***************************************************************************** 3146 // Field: [6:0] EV 3147 // 3148 // Read only selection value 3149 // ENUMs: 3150 // SWEV0 Software event 0, triggered by SWEV.SWEV0 3151 #define EVENT_UDMACH21BSEL_EV_W 7 3152 #define EVENT_UDMACH21BSEL_EV_M 0x0000007F 3153 #define EVENT_UDMACH21BSEL_EV_S 0 3154 #define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 3155 3156 //***************************************************************************** 3157 // 3158 // Register: EVENT_O_UDMACH22SSEL 3159 // 3160 //***************************************************************************** 3161 // Field: [6:0] EV 3162 // 3163 // Read only selection value 3164 // ENUMs: 3165 // SWEV1 Software event 1, triggered by SWEV.SWEV1 3166 #define EVENT_UDMACH22SSEL_EV_W 7 3167 #define EVENT_UDMACH22SSEL_EV_M 0x0000007F 3168 #define EVENT_UDMACH22SSEL_EV_S 0 3169 #define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 3170 3171 //***************************************************************************** 3172 // 3173 // Register: EVENT_O_UDMACH22BSEL 3174 // 3175 //***************************************************************************** 3176 // Field: [6:0] EV 3177 // 3178 // Read only selection value 3179 // ENUMs: 3180 // SWEV1 Software event 1, triggered by SWEV.SWEV1 3181 #define EVENT_UDMACH22BSEL_EV_W 7 3182 #define EVENT_UDMACH22BSEL_EV_M 0x0000007F 3183 #define EVENT_UDMACH22BSEL_EV_S 0 3184 #define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 3185 3186 //***************************************************************************** 3187 // 3188 // Register: EVENT_O_UDMACH23SSEL 3189 // 3190 //***************************************************************************** 3191 // Field: [6:0] EV 3192 // 3193 // Read only selection value 3194 // ENUMs: 3195 // SWEV2 Software event 2, triggered by SWEV.SWEV2 3196 #define EVENT_UDMACH23SSEL_EV_W 7 3197 #define EVENT_UDMACH23SSEL_EV_M 0x0000007F 3198 #define EVENT_UDMACH23SSEL_EV_S 0 3199 #define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 3200 3201 //***************************************************************************** 3202 // 3203 // Register: EVENT_O_UDMACH23BSEL 3204 // 3205 //***************************************************************************** 3206 // Field: [6:0] EV 3207 // 3208 // Read only selection value 3209 // ENUMs: 3210 // SWEV2 Software event 2, triggered by SWEV.SWEV2 3211 #define EVENT_UDMACH23BSEL_EV_W 7 3212 #define EVENT_UDMACH23BSEL_EV_M 0x0000007F 3213 #define EVENT_UDMACH23BSEL_EV_S 0 3214 #define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 3215 3216 //***************************************************************************** 3217 // 3218 // Register: EVENT_O_UDMACH24SSEL 3219 // 3220 //***************************************************************************** 3221 // Field: [6:0] EV 3222 // 3223 // Read only selection value 3224 // ENUMs: 3225 // SWEV3 Software event 3, triggered by SWEV.SWEV3 3226 #define EVENT_UDMACH24SSEL_EV_W 7 3227 #define EVENT_UDMACH24SSEL_EV_M 0x0000007F 3228 #define EVENT_UDMACH24SSEL_EV_S 0 3229 #define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 3230 3231 //***************************************************************************** 3232 // 3233 // Register: EVENT_O_UDMACH24BSEL 3234 // 3235 //***************************************************************************** 3236 // Field: [6:0] EV 3237 // 3238 // Read only selection value 3239 // ENUMs: 3240 // SWEV3 Software event 3, triggered by SWEV.SWEV3 3241 #define EVENT_UDMACH24BSEL_EV_W 7 3242 #define EVENT_UDMACH24BSEL_EV_M 0x0000007F 3243 #define EVENT_UDMACH24BSEL_EV_S 0 3244 #define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 3245 3246 //***************************************************************************** 3247 // 3248 // Register: EVENT_O_GPT3ACAPTSEL 3249 // 3250 //***************************************************************************** 3251 // Field: [6:0] EV 3252 // 3253 // Read/write selection value 3254 // 3255 // Writing any other value than values defined by a ENUM may result in 3256 // undefined behavior. 3257 // ENUMs: 3258 // ALWAYS_ACTIVE Always asserted 3259 // AON_RTC_UPD RTC periodic event controlled by 3260 // AON_RTC:CTL.RTC_UPD_EN 3261 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 3262 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status 3263 // flags are found here AUX_EVCTL:EVTOMCUFLAGS 3264 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 3265 // AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 3266 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 3267 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 3268 // AUX_ADC_DONE AUX ADC done, corresponds to 3269 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 3270 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 3271 // AUX_SMPH:AUTOTAKE 3272 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 3273 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 3274 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 3275 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 3276 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 3277 // flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and 3278 // the AUX_TDC status AUX_TDC:STAT.DONE 3279 // AUX_COMPB AUX Compare B event, corresponds to 3280 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 3281 // AUX_COMPA AUX Compare A event, corresponds to 3282 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 3283 // AUX_AON_WU_EV AON wakeup event, the corresponding flag is here 3284 // AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 3285 // PORT_EVENT7 Port capture event from IOC, configured by 3286 // IOC:IOCFGn.PORT_ID. Events on ports configured 3287 // with ENUM PORT_EVENT7 wil be routed here. 3288 // PORT_EVENT6 Port capture event from IOC, configured by 3289 // IOC:IOCFGn.PORT_ID. Events on ports configured 3290 // with ENUM PORT_EVENT6 wil be routed here. 3291 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 3292 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 3293 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 3294 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 3295 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 3296 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 3297 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 3298 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 3299 // AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag 3300 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 3301 // AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag 3302 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3303 // AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag 3304 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3305 // AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag 3306 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3307 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 3308 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 3309 // UART1_COMB UART1 combined interrupt, interrupt flags are 3310 // found here UART1:MIS 3311 // UART0_COMB UART0 combined interrupt, interrupt flags are 3312 // found here UART0:MIS 3313 // SSI1_COMB SSI1 combined interrupt, interrupt flags are found 3314 // here SSI1:MIS 3315 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 3316 // here SSI0:MIS 3317 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 3318 // Corresponding flags are here 3319 // RFC_DBELL:RFCPEIFG. Only interrupts selected 3320 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 3321 // RFC_CPE_1 event 3322 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 3323 // Corresponding flags are here 3324 // RFC_DBELL:RFCPEIFG. Only interrupts selected 3325 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 3326 // RFC_CPE_0 event 3327 // RFC_HW_COMB Combined RFC hardware interrupt, corresponding 3328 // flag is here RFC_DBELL:RFHWIFG 3329 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 3330 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 3331 // FLASH FLASH controller error event, the status flags 3332 // are FLASH:FEDACSTAT.FSM_DONE and 3333 // FLASH:FEDACSTAT.RVF_INT 3334 // AUX_COMB AUX combined event, the corresponding flag 3335 // register is here AUX_EVCTL:EVTOMCUFLAGS 3336 // I2C_IRQ Interrupt event from I2C 3337 // AON_RTC_COMB Event from AON_RTC, controlled by the 3338 // AON_RTC:CTL.COMB_EV_MASK setting 3339 // OSC_COMB Combined event from Oscillator control 3340 // BATMON_COMB Combined event from battery monitor 3341 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 3342 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 3343 // settings 3344 // NONE Always inactive 3345 #define EVENT_GPT3ACAPTSEL_EV_W 7 3346 #define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F 3347 #define EVENT_GPT3ACAPTSEL_EV_S 0 3348 #define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 3349 #define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 3350 #define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 3351 #define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 3352 #define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 3353 #define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 3354 #define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 3355 #define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 3356 #define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 3357 #define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C 3358 #define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B 3359 #define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A 3360 #define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 3361 #define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C 3362 #define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B 3363 #define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 3364 #define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 3365 #define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 3366 #define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 3367 #define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 3368 #define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F 3369 #define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E 3370 #define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D 3371 #define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C 3372 #define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B 3373 #define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A 3374 #define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 3375 #define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 3376 #define EVENT_GPT3ACAPTSEL_EV_UART1_COMB 0x00000025 3377 #define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 3378 #define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 3379 #define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 3380 #define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E 3381 #define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B 3382 #define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A 3383 #define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 3384 #define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 3385 #define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B 3386 #define EVENT_GPT3ACAPTSEL_EV_I2C_IRQ 0x00000009 3387 #define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 3388 #define EVENT_GPT3ACAPTSEL_EV_OSC_COMB 0x00000006 3389 #define EVENT_GPT3ACAPTSEL_EV_BATMON_COMB 0x00000005 3390 #define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 3391 #define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 3392 3393 //***************************************************************************** 3394 // 3395 // Register: EVENT_O_GPT3BCAPTSEL 3396 // 3397 //***************************************************************************** 3398 // Field: [6:0] EV 3399 // 3400 // Read/write selection value 3401 // 3402 // Writing any other value than values defined by a ENUM may result in 3403 // undefined behavior. 3404 // ENUMs: 3405 // ALWAYS_ACTIVE Always asserted 3406 // AON_RTC_UPD RTC periodic event controlled by 3407 // AON_RTC:CTL.RTC_UPD_EN 3408 // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to 3409 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status 3410 // flags are found here AUX_EVCTL:EVTOMCUFLAGS 3411 // AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to 3412 // AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 3413 // AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to 3414 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 3415 // AUX_ADC_DONE AUX ADC done, corresponds to 3416 // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 3417 // AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by 3418 // AUX_SMPH:AUTOTAKE 3419 // AUX_TIMER1_EV AUX timer 1 event, corresponds to 3420 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 3421 // AUX_TIMER0_EV AUX timer 0 event, corresponds to 3422 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 3423 // AUX_TDC_DONE AUX TDC measurement done event, corresponds to the 3424 // flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and 3425 // the AUX_TDC status AUX_TDC:STAT.DONE 3426 // AUX_COMPB AUX Compare B event, corresponds to 3427 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 3428 // AUX_COMPA AUX Compare A event, corresponds to 3429 // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 3430 // AUX_AON_WU_EV AON wakeup event, the corresponding flag is here 3431 // AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 3432 // PORT_EVENT7 Port capture event from IOC, configured by 3433 // IOC:IOCFGn.PORT_ID. Events on ports configured 3434 // with ENUM PORT_EVENT7 wil be routed here. 3435 // PORT_EVENT6 Port capture event from IOC, configured by 3436 // IOC:IOCFGn.PORT_ID. Events on ports configured 3437 // with ENUM PORT_EVENT6 wil be routed here. 3438 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 3439 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 3440 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 3441 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 3442 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 3443 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 3444 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 3445 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 3446 // AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag 3447 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 3448 // AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag 3449 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3450 // AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag 3451 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3452 // AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag 3453 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3454 // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag 3455 // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 3456 // UART1_COMB UART1 combined interrupt, interrupt flags are 3457 // found here UART1:MIS 3458 // UART0_COMB UART0 combined interrupt, interrupt flags are 3459 // found here UART0:MIS 3460 // SSI1_COMB SSI1 combined interrupt, interrupt flags are found 3461 // here SSI1:MIS 3462 // SSI0_COMB SSI0 combined interrupt, interrupt flags are found 3463 // here SSI0:MIS 3464 // RFC_CPE_1 Combined Interrupt for CPE Generated events. 3465 // Corresponding flags are here 3466 // RFC_DBELL:RFCPEIFG. Only interrupts selected 3467 // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a 3468 // RFC_CPE_1 event 3469 // RFC_CPE_0 Combined Interrupt for CPE Generated events. 3470 // Corresponding flags are here 3471 // RFC_DBELL:RFCPEIFG. Only interrupts selected 3472 // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a 3473 // RFC_CPE_0 event 3474 // RFC_HW_COMB Combined RFC hardware interrupt, corresponding 3475 // flag is here RFC_DBELL:RFHWIFG 3476 // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, 3477 // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 3478 // FLASH FLASH controller error event, the status flags 3479 // are FLASH:FEDACSTAT.FSM_DONE and 3480 // FLASH:FEDACSTAT.RVF_INT 3481 // AUX_COMB AUX combined event, the corresponding flag 3482 // register is here AUX_EVCTL:EVTOMCUFLAGS 3483 // I2C_IRQ Interrupt event from I2C 3484 // AON_RTC_COMB Event from AON_RTC, controlled by the 3485 // AON_RTC:CTL.COMB_EV_MASK setting 3486 // OSC_COMB Combined event from Oscillator control 3487 // BATMON_COMB Combined event from battery monitor 3488 // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the 3489 // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET 3490 // settings 3491 // NONE Always inactive 3492 #define EVENT_GPT3BCAPTSEL_EV_W 7 3493 #define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F 3494 #define EVENT_GPT3BCAPTSEL_EV_S 0 3495 #define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 3496 #define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 3497 #define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 3498 #define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 3499 #define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 3500 #define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 3501 #define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F 3502 #define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E 3503 #define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D 3504 #define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C 3505 #define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B 3506 #define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A 3507 #define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 3508 #define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C 3509 #define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B 3510 #define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 3511 #define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 3512 #define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 3513 #define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 3514 #define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 3515 #define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F 3516 #define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E 3517 #define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D 3518 #define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C 3519 #define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B 3520 #define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A 3521 #define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 3522 #define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 3523 #define EVENT_GPT3BCAPTSEL_EV_UART1_COMB 0x00000025 3524 #define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 3525 #define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 3526 #define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 3527 #define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E 3528 #define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B 3529 #define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A 3530 #define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 3531 #define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 3532 #define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B 3533 #define EVENT_GPT3BCAPTSEL_EV_I2C_IRQ 0x00000009 3534 #define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 3535 #define EVENT_GPT3BCAPTSEL_EV_OSC_COMB 0x00000006 3536 #define EVENT_GPT3BCAPTSEL_EV_BATMON_COMB 0x00000005 3537 #define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 3538 #define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 3539 3540 //***************************************************************************** 3541 // 3542 // Register: EVENT_O_AUXSEL0 3543 // 3544 //***************************************************************************** 3545 // Field: [6:0] EV 3546 // 3547 // Read/write selection value 3548 // 3549 // Writing any other value than values defined by a ENUM may result in 3550 // undefined behavior. 3551 // ENUMs: 3552 // ALWAYS_ACTIVE Always asserted 3553 // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT 3554 // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT 3555 // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT 3556 // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT 3557 // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT 3558 // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT 3559 // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT 3560 // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT 3561 // GPT1B GPT1B interrupt event, controlled by GPT1:TBMR 3562 // GPT1A GPT1A interrupt event, controlled by GPT1:TAMR 3563 // GPT0B GPT0B interrupt event, controlled by GPT0:TBMR 3564 // GPT0A GPT0A interrupt event, controlled by GPT0:TAMR 3565 // GPT3B GPT3B interrupt event, controlled by GPT3:TBMR 3566 // GPT3A GPT3A interrupt event, controlled by GPT3:TAMR 3567 // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR 3568 // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR 3569 // NONE Always inactive 3570 #define EVENT_AUXSEL0_EV_W 7 3571 #define EVENT_AUXSEL0_EV_M 0x0000007F 3572 #define EVENT_AUXSEL0_EV_S 0 3573 #define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 3574 #define EVENT_AUXSEL0_EV_GPT3B_CMP 0x00000044 3575 #define EVENT_AUXSEL0_EV_GPT3A_CMP 0x00000043 3576 #define EVENT_AUXSEL0_EV_GPT2B_CMP 0x00000042 3577 #define EVENT_AUXSEL0_EV_GPT2A_CMP 0x00000041 3578 #define EVENT_AUXSEL0_EV_GPT1B_CMP 0x00000040 3579 #define EVENT_AUXSEL0_EV_GPT1A_CMP 0x0000003F 3580 #define EVENT_AUXSEL0_EV_GPT0B_CMP 0x0000003E 3581 #define EVENT_AUXSEL0_EV_GPT0A_CMP 0x0000003D 3582 #define EVENT_AUXSEL0_EV_GPT1B 0x00000013 3583 #define EVENT_AUXSEL0_EV_GPT1A 0x00000012 3584 #define EVENT_AUXSEL0_EV_GPT0B 0x00000011 3585 #define EVENT_AUXSEL0_EV_GPT0A 0x00000010 3586 #define EVENT_AUXSEL0_EV_GPT3B 0x0000000F 3587 #define EVENT_AUXSEL0_EV_GPT3A 0x0000000E 3588 #define EVENT_AUXSEL0_EV_GPT2B 0x0000000D 3589 #define EVENT_AUXSEL0_EV_GPT2A 0x0000000C 3590 #define EVENT_AUXSEL0_EV_NONE 0x00000000 3591 3592 //***************************************************************************** 3593 // 3594 // Register: EVENT_O_CM3NMISEL0 3595 // 3596 //***************************************************************************** 3597 // Field: [6:0] EV 3598 // 3599 // Read only selection value 3600 // ENUMs: 3601 // WDT_NMI Watchdog non maskable interrupt event, controlled 3602 // by WDT:CTL.INTTYPE 3603 #define EVENT_CM3NMISEL0_EV_W 7 3604 #define EVENT_CM3NMISEL0_EV_M 0x0000007F 3605 #define EVENT_CM3NMISEL0_EV_S 0 3606 #define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 3607 3608 //***************************************************************************** 3609 // 3610 // Register: EVENT_O_I2SSTMPSEL0 3611 // 3612 //***************************************************************************** 3613 // Field: [6:0] EV 3614 // 3615 // Read/write selection value 3616 // 3617 // Writing any other value than values defined by a ENUM may result in 3618 // undefined behavior. 3619 // ENUMs: 3620 // ALWAYS_ACTIVE Always asserted 3621 // NONE Always inactive 3622 #define EVENT_I2SSTMPSEL0_EV_W 7 3623 #define EVENT_I2SSTMPSEL0_EV_M 0x0000007F 3624 #define EVENT_I2SSTMPSEL0_EV_S 0 3625 #define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 3626 #define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 3627 3628 //***************************************************************************** 3629 // 3630 // Register: EVENT_O_FRZSEL0 3631 // 3632 //***************************************************************************** 3633 // Field: [6:0] EV 3634 // 3635 // Read/write selection value 3636 // 3637 // Writing any other value than values defined by a ENUM may result in 3638 // undefined behavior. 3639 // ENUMs: 3640 // ALWAYS_ACTIVE Always asserted 3641 // CPU_HALTED CPU halted 3642 // NONE Always inactive 3643 #define EVENT_FRZSEL0_EV_W 7 3644 #define EVENT_FRZSEL0_EV_M 0x0000007F 3645 #define EVENT_FRZSEL0_EV_S 0 3646 #define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 3647 #define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 3648 #define EVENT_FRZSEL0_EV_NONE 0x00000000 3649 3650 //***************************************************************************** 3651 // 3652 // Register: EVENT_O_SWEV 3653 // 3654 //***************************************************************************** 3655 // Field: [24] SWEV3 3656 // 3657 // Writing "1" to this bit when the value is "0" triggers the Software 3 event. 3658 #define EVENT_SWEV_SWEV3 0x01000000 3659 #define EVENT_SWEV_SWEV3_BITN 24 3660 #define EVENT_SWEV_SWEV3_M 0x01000000 3661 #define EVENT_SWEV_SWEV3_S 24 3662 3663 // Field: [16] SWEV2 3664 // 3665 // Writing "1" to this bit when the value is "0" triggers the Software 2 event. 3666 #define EVENT_SWEV_SWEV2 0x00010000 3667 #define EVENT_SWEV_SWEV2_BITN 16 3668 #define EVENT_SWEV_SWEV2_M 0x00010000 3669 #define EVENT_SWEV_SWEV2_S 16 3670 3671 // Field: [8] SWEV1 3672 // 3673 // Writing "1" to this bit when the value is "0" triggers the Software 1 event. 3674 #define EVENT_SWEV_SWEV1 0x00000100 3675 #define EVENT_SWEV_SWEV1_BITN 8 3676 #define EVENT_SWEV_SWEV1_M 0x00000100 3677 #define EVENT_SWEV_SWEV1_S 8 3678 3679 // Field: [0] SWEV0 3680 // 3681 // Writing "1" to this bit when the value is "0" triggers the Software 0 event. 3682 #define EVENT_SWEV_SWEV0 0x00000001 3683 #define EVENT_SWEV_SWEV0_BITN 0 3684 #define EVENT_SWEV_SWEV0_M 0x00000001 3685 #define EVENT_SWEV_SWEV0_S 0 3686 3687 3688 #endif // __EVENT__ 3689
