1 /****************************************************************************** 2 * Filename: hw_cpu_scs_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_CPU_SCS_H__ 38 #define __HW_CPU_SCS_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // CPU_SCS component 44 // 45 //***************************************************************************** 46 // Interrupt Control Type 47 #define CPU_SCS_O_ICTR 0x00000004 48 49 // Auxiliary Control 50 #define CPU_SCS_O_ACTLR 0x00000008 51 52 // SysTick Control and Status 53 #define CPU_SCS_O_STCSR 0x00000010 54 55 // SysTick Reload Value 56 #define CPU_SCS_O_STRVR 0x00000014 57 58 // SysTick Current Value 59 #define CPU_SCS_O_STCVR 0x00000018 60 61 // SysTick Calibration Value 62 #define CPU_SCS_O_STCR 0x0000001C 63 64 // Irq 0 to 31 Set Enable 65 #define CPU_SCS_O_NVIC_ISER0 0x00000100 66 67 // Irq 32 to 63 Set Enable 68 #define CPU_SCS_O_NVIC_ISER1 0x00000104 69 70 // Irq 0 to 31 Clear Enable 71 #define CPU_SCS_O_NVIC_ICER0 0x00000180 72 73 // Irq 32 to 63 Clear Enable 74 #define CPU_SCS_O_NVIC_ICER1 0x00000184 75 76 // Irq 0 to 31 Set Pending 77 #define CPU_SCS_O_NVIC_ISPR0 0x00000200 78 79 // Irq 32 to 63 Set Pending 80 #define CPU_SCS_O_NVIC_ISPR1 0x00000204 81 82 // Irq 0 to 31 Clear Pending 83 #define CPU_SCS_O_NVIC_ICPR0 0x00000280 84 85 // Irq 32 to 63 Clear Pending 86 #define CPU_SCS_O_NVIC_ICPR1 0x00000284 87 88 // Irq 0 to 31 Active Bit 89 #define CPU_SCS_O_NVIC_IABR0 0x00000300 90 91 // Irq 32 to 63 Active Bit 92 #define CPU_SCS_O_NVIC_IABR1 0x00000304 93 94 // Irq 0 to 3 Priority 95 #define CPU_SCS_O_NVIC_IPR0 0x00000400 96 97 // Irq 4 to 7 Priority 98 #define CPU_SCS_O_NVIC_IPR1 0x00000404 99 100 // Irq 8 to 11 Priority 101 #define CPU_SCS_O_NVIC_IPR2 0x00000408 102 103 // Irq 12 to 15 Priority 104 #define CPU_SCS_O_NVIC_IPR3 0x0000040C 105 106 // Irq 16 to 19 Priority 107 #define CPU_SCS_O_NVIC_IPR4 0x00000410 108 109 // Irq 20 to 23 Priority 110 #define CPU_SCS_O_NVIC_IPR5 0x00000414 111 112 // Irq 24 to 27 Priority 113 #define CPU_SCS_O_NVIC_IPR6 0x00000418 114 115 // Irq 28 to 31 Priority 116 #define CPU_SCS_O_NVIC_IPR7 0x0000041C 117 118 // Irq 32 to 35 Priority 119 #define CPU_SCS_O_NVIC_IPR8 0x00000420 120 121 // Irq 32 to 35 Priority 122 #define CPU_SCS_O_NVIC_IPR9 0x00000424 123 124 // CPUID Base 125 #define CPU_SCS_O_CPUID 0x00000D00 126 127 // Interrupt Control State 128 #define CPU_SCS_O_ICSR 0x00000D04 129 130 // Vector Table Offset 131 #define CPU_SCS_O_VTOR 0x00000D08 132 133 // Application Interrupt/Reset Control 134 #define CPU_SCS_O_AIRCR 0x00000D0C 135 136 // System Control 137 #define CPU_SCS_O_SCR 0x00000D10 138 139 // Configuration Control 140 #define CPU_SCS_O_CCR 0x00000D14 141 142 // System Handlers 4-7 Priority 143 #define CPU_SCS_O_SHPR1 0x00000D18 144 145 // System Handlers 8-11 Priority 146 #define CPU_SCS_O_SHPR2 0x00000D1C 147 148 // System Handlers 12-15 Priority 149 #define CPU_SCS_O_SHPR3 0x00000D20 150 151 // System Handler Control and State 152 #define CPU_SCS_O_SHCSR 0x00000D24 153 154 // Configurable Fault Status 155 #define CPU_SCS_O_CFSR 0x00000D28 156 157 // Hard Fault Status 158 #define CPU_SCS_O_HFSR 0x00000D2C 159 160 // Debug Fault Status 161 #define CPU_SCS_O_DFSR 0x00000D30 162 163 // Mem Manage Fault Address 164 #define CPU_SCS_O_MMFAR 0x00000D34 165 166 // Bus Fault Address 167 #define CPU_SCS_O_BFAR 0x00000D38 168 169 // Auxiliary Fault Status 170 #define CPU_SCS_O_AFSR 0x00000D3C 171 172 // Processor Feature 0 173 #define CPU_SCS_O_ID_PFR0 0x00000D40 174 175 // Processor Feature 1 176 #define CPU_SCS_O_ID_PFR1 0x00000D44 177 178 // Debug Feature 0 179 #define CPU_SCS_O_ID_DFR0 0x00000D48 180 181 // Auxiliary Feature 0 182 #define CPU_SCS_O_ID_AFR0 0x00000D4C 183 184 // Memory Model Feature 0 185 #define CPU_SCS_O_ID_MMFR0 0x00000D50 186 187 // Memory Model Feature 1 188 #define CPU_SCS_O_ID_MMFR1 0x00000D54 189 190 // Memory Model Feature 2 191 #define CPU_SCS_O_ID_MMFR2 0x00000D58 192 193 // Memory Model Feature 3 194 #define CPU_SCS_O_ID_MMFR3 0x00000D5C 195 196 // ISA Feature 0 197 #define CPU_SCS_O_ID_ISAR0 0x00000D60 198 199 // ISA Feature 1 200 #define CPU_SCS_O_ID_ISAR1 0x00000D64 201 202 // ISA Feature 2 203 #define CPU_SCS_O_ID_ISAR2 0x00000D68 204 205 // ISA Feature 3 206 #define CPU_SCS_O_ID_ISAR3 0x00000D6C 207 208 // ISA Feature 4 209 #define CPU_SCS_O_ID_ISAR4 0x00000D70 210 211 // Coprocessor Access Control 212 #define CPU_SCS_O_CPACR 0x00000D88 213 214 // MPU Type 215 #define CPU_SCS_O_MPU_TYPE 0x00000D90 216 217 // MPU Control 218 #define CPU_SCS_O_MPU_CTRL 0x00000D94 219 220 // MPU Region Number 221 #define CPU_SCS_O_MPU_RNR 0x00000D98 222 223 // MPU Region Base Address 224 #define CPU_SCS_O_MPU_RBAR 0x00000D9C 225 226 // MPU Region Attribute and Size 227 #define CPU_SCS_O_MPU_RASR 0x00000DA0 228 229 // MPU Alias 1 Region Base Address 230 #define CPU_SCS_O_MPU_RBAR_A1 0x00000DA4 231 232 // MPU Alias 1 Region Attribute and Size 233 #define CPU_SCS_O_MPU_RASR_A1 0x00000DA8 234 235 // MPU Alias 2 Region Base Address 236 #define CPU_SCS_O_MPU_RBAR_A2 0x00000DAC 237 238 // MPU Alias 2 Region Attribute and Size 239 #define CPU_SCS_O_MPU_RASR_A2 0x00000DB0 240 241 // MPU Alias 3 Region Base Address 242 #define CPU_SCS_O_MPU_RBAR_A3 0x00000DB4 243 244 // MPU Alias 3 Region Attribute and Size 245 #define CPU_SCS_O_MPU_RASR_A3 0x00000DB8 246 247 // Debug Halting Control and Status 248 #define CPU_SCS_O_DHCSR 0x00000DF0 249 250 // Deubg Core Register Selector 251 #define CPU_SCS_O_DCRSR 0x00000DF4 252 253 // Debug Core Register Data 254 #define CPU_SCS_O_DCRDR 0x00000DF8 255 256 // Debug Exception and Monitor Control 257 #define CPU_SCS_O_DEMCR 0x00000DFC 258 259 // Software Trigger Interrupt 260 #define CPU_SCS_O_STIR 0x00000F00 261 262 // Floating Point Context Control 263 #define CPU_SCS_O_FPCCR 0x00000F34 264 265 // Floating-Point Context Address 266 #define CPU_SCS_O_FPCAR 0x00000F38 267 268 // Floating Point Default Status Control 269 #define CPU_SCS_O_FPDSCR 0x00000F3C 270 271 // Media and FP Feature 0 272 #define CPU_SCS_O_MVFR0 0x00000F40 273 274 // Media and FP Feature 1 275 #define CPU_SCS_O_MVFR1 0x00000F44 276 277 //***************************************************************************** 278 // 279 // Register: CPU_SCS_O_ICTR 280 // 281 //***************************************************************************** 282 // Field: [2:0] INTLINESNUM 283 // 284 // Total number of interrupt lines in groups of 32. 285 // 286 // 0: 0...32 287 // 1: 33...64 288 // 2: 65...96 289 // 3: 97...128 290 // 4: 129...160 291 // 5: 161...192 292 // 6: 193...224 293 // 7: 225...256 294 #define CPU_SCS_ICTR_INTLINESNUM_W 3 295 #define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 296 #define CPU_SCS_ICTR_INTLINESNUM_S 0 297 298 //***************************************************************************** 299 // 300 // Register: CPU_SCS_O_ACTLR 301 // 302 //***************************************************************************** 303 // Field: [9] DISOOFP 304 // 305 // Disables floating point instructions completing out of order with respect to 306 // integer instructions. 307 #define CPU_SCS_ACTLR_DISOOFP 0x00000200 308 #define CPU_SCS_ACTLR_DISOOFP_BITN 9 309 #define CPU_SCS_ACTLR_DISOOFP_M 0x00000200 310 #define CPU_SCS_ACTLR_DISOOFP_S 9 311 312 // Field: [8] DISFPCA 313 // 314 // Disable automatic update of CONTROL.FPCA 315 #define CPU_SCS_ACTLR_DISFPCA 0x00000100 316 #define CPU_SCS_ACTLR_DISFPCA_BITN 8 317 #define CPU_SCS_ACTLR_DISFPCA_M 0x00000100 318 #define CPU_SCS_ACTLR_DISFPCA_S 8 319 320 // Field: [2] DISFOLD 321 // 322 // Disables folding of IT instruction. 323 #define CPU_SCS_ACTLR_DISFOLD 0x00000004 324 #define CPU_SCS_ACTLR_DISFOLD_BITN 2 325 #define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 326 #define CPU_SCS_ACTLR_DISFOLD_S 2 327 328 // Field: [1] DISDEFWBUF 329 // 330 // Disables write buffer use during default memory map accesses. This causes 331 // all bus faults to be precise bus faults but decreases the performance of the 332 // processor because the stores to memory have to complete before the next 333 // instruction can be executed. 334 #define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 335 #define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 336 #define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 337 #define CPU_SCS_ACTLR_DISDEFWBUF_S 1 338 339 // Field: [0] DISMCYCINT 340 // 341 // Disables interruption of multi-cycle instructions. This increases the 342 // interrupt latency of the processor becuase LDM/STM completes before 343 // interrupt stacking occurs. 344 #define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 345 #define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 346 #define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 347 #define CPU_SCS_ACTLR_DISMCYCINT_S 0 348 349 //***************************************************************************** 350 // 351 // Register: CPU_SCS_O_STCSR 352 // 353 //***************************************************************************** 354 // Field: [16] COUNTFLAG 355 // 356 // Returns 1 if timer counted to 0 since last time this was read. Clears on 357 // read by application of any part of the SysTick Control and Status Register. 358 // If read by the debugger using the DAP, this bit is cleared on read-only if 359 // the MasterType bit in the **AHB-AP** Control Register is set to 0. 360 // Otherwise, COUNTFLAG is not changed by the debugger read. 361 #define CPU_SCS_STCSR_COUNTFLAG 0x00010000 362 #define CPU_SCS_STCSR_COUNTFLAG_BITN 16 363 #define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 364 #define CPU_SCS_STCSR_COUNTFLAG_S 16 365 366 // Field: [2] CLKSOURCE 367 // 368 // Clock source: 369 // 370 // 0: External reference clock. 371 // 1: Core clock 372 // 373 // External clock is not available in this device. Writes to this field will be 374 // ignored. 375 #define CPU_SCS_STCSR_CLKSOURCE 0x00000004 376 #define CPU_SCS_STCSR_CLKSOURCE_BITN 2 377 #define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 378 #define CPU_SCS_STCSR_CLKSOURCE_S 2 379 380 // Field: [1] TICKINT 381 // 382 // 0: Counting down to zero does not pend the SysTick handler. Software can use 383 // COUNTFLAG to determine if the SysTick handler has ever counted to zero. 384 // 1: Counting down to zero pends the SysTick handler. 385 #define CPU_SCS_STCSR_TICKINT 0x00000002 386 #define CPU_SCS_STCSR_TICKINT_BITN 1 387 #define CPU_SCS_STCSR_TICKINT_M 0x00000002 388 #define CPU_SCS_STCSR_TICKINT_S 1 389 390 // Field: [0] ENABLE 391 // 392 // Enable SysTick counter 393 // 394 // 0: Counter disabled 395 // 1: Counter operates in a multi-shot way. That is, counter loads with the 396 // Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it 397 // sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on 398 // TICKINT. It then loads STRVR.RELOAD again, and begins counting. 399 #define CPU_SCS_STCSR_ENABLE 0x00000001 400 #define CPU_SCS_STCSR_ENABLE_BITN 0 401 #define CPU_SCS_STCSR_ENABLE_M 0x00000001 402 #define CPU_SCS_STCSR_ENABLE_S 0 403 404 //***************************************************************************** 405 // 406 // Register: CPU_SCS_O_STRVR 407 // 408 //***************************************************************************** 409 // Field: [23:0] RELOAD 410 // 411 // Value to load into the SysTick Current Value Register STCVR.CURRENT when the 412 // counter reaches 0. 413 #define CPU_SCS_STRVR_RELOAD_W 24 414 #define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF 415 #define CPU_SCS_STRVR_RELOAD_S 0 416 417 //***************************************************************************** 418 // 419 // Register: CPU_SCS_O_STCVR 420 // 421 //***************************************************************************** 422 // Field: [23:0] CURRENT 423 // 424 // Current value at the time the register is accessed. No read-modify-write 425 // protection is provided, so change with care. Writing to it with any value 426 // clears the register to 0. Clearing this register also clears 427 // STCSR.COUNTFLAG. 428 #define CPU_SCS_STCVR_CURRENT_W 24 429 #define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF 430 #define CPU_SCS_STCVR_CURRENT_S 0 431 432 //***************************************************************************** 433 // 434 // Register: CPU_SCS_O_STCR 435 // 436 //***************************************************************************** 437 // Field: [31] NOREF 438 // 439 // Reads as one. Indicates that no separate reference clock is provided. 440 #define CPU_SCS_STCR_NOREF 0x80000000 441 #define CPU_SCS_STCR_NOREF_BITN 31 442 #define CPU_SCS_STCR_NOREF_M 0x80000000 443 #define CPU_SCS_STCR_NOREF_S 31 444 445 // Field: [30] SKEW 446 // 447 // Reads as one. The calibration value is not exactly 10ms because of clock 448 // frequency. This could affect its suitability as a software real time clock. 449 #define CPU_SCS_STCR_SKEW 0x40000000 450 #define CPU_SCS_STCR_SKEW_BITN 30 451 #define CPU_SCS_STCR_SKEW_M 0x40000000 452 #define CPU_SCS_STCR_SKEW_S 30 453 454 // Field: [23:0] TENMS 455 // 456 // An optional Reload value to be used for 10ms (100Hz) timing, subject to 457 // system clock skew errors. The value read is valid only when core clock is at 458 // 48MHz. 459 #define CPU_SCS_STCR_TENMS_W 24 460 #define CPU_SCS_STCR_TENMS_M 0x00FFFFFF 461 #define CPU_SCS_STCR_TENMS_S 0 462 463 //***************************************************************************** 464 // 465 // Register: CPU_SCS_O_NVIC_ISER0 466 // 467 //***************************************************************************** 468 // Field: [31] SETENA31 469 // 470 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 471 // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit 472 // returns its current enable state. 473 #define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 474 #define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 475 #define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 476 #define CPU_SCS_NVIC_ISER0_SETENA31_S 31 477 478 // Field: [30] SETENA30 479 // 480 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 481 // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit 482 // returns its current enable state. 483 #define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 484 #define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 485 #define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 486 #define CPU_SCS_NVIC_ISER0_SETENA30_S 30 487 488 // Field: [29] SETENA29 489 // 490 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 491 // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit 492 // returns its current enable state. 493 #define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 494 #define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 495 #define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 496 #define CPU_SCS_NVIC_ISER0_SETENA29_S 29 497 498 // Field: [28] SETENA28 499 // 500 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 501 // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit 502 // returns its current enable state. 503 #define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 504 #define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 505 #define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 506 #define CPU_SCS_NVIC_ISER0_SETENA28_S 28 507 508 // Field: [27] SETENA27 509 // 510 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 511 // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit 512 // returns its current enable state. 513 #define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 514 #define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 515 #define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 516 #define CPU_SCS_NVIC_ISER0_SETENA27_S 27 517 518 // Field: [26] SETENA26 519 // 520 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 521 // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit 522 // returns its current enable state. 523 #define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 524 #define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 525 #define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 526 #define CPU_SCS_NVIC_ISER0_SETENA26_S 26 527 528 // Field: [25] SETENA25 529 // 530 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 531 // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit 532 // returns its current enable state. 533 #define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 534 #define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 535 #define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 536 #define CPU_SCS_NVIC_ISER0_SETENA25_S 25 537 538 // Field: [24] SETENA24 539 // 540 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 541 // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit 542 // returns its current enable state. 543 #define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 544 #define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 545 #define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 546 #define CPU_SCS_NVIC_ISER0_SETENA24_S 24 547 548 // Field: [23] SETENA23 549 // 550 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 551 // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit 552 // returns its current enable state. 553 #define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 554 #define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 555 #define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 556 #define CPU_SCS_NVIC_ISER0_SETENA23_S 23 557 558 // Field: [22] SETENA22 559 // 560 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 561 // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit 562 // returns its current enable state. 563 #define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 564 #define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 565 #define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 566 #define CPU_SCS_NVIC_ISER0_SETENA22_S 22 567 568 // Field: [21] SETENA21 569 // 570 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 571 // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit 572 // returns its current enable state. 573 #define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 574 #define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 575 #define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 576 #define CPU_SCS_NVIC_ISER0_SETENA21_S 21 577 578 // Field: [20] SETENA20 579 // 580 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 581 // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit 582 // returns its current enable state. 583 #define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 584 #define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 585 #define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 586 #define CPU_SCS_NVIC_ISER0_SETENA20_S 20 587 588 // Field: [19] SETENA19 589 // 590 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 591 // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit 592 // returns its current enable state. 593 #define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 594 #define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 595 #define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 596 #define CPU_SCS_NVIC_ISER0_SETENA19_S 19 597 598 // Field: [18] SETENA18 599 // 600 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 601 // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit 602 // returns its current enable state. 603 #define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 604 #define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 605 #define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 606 #define CPU_SCS_NVIC_ISER0_SETENA18_S 18 607 608 // Field: [17] SETENA17 609 // 610 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 611 // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit 612 // returns its current enable state. 613 #define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 614 #define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 615 #define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 616 #define CPU_SCS_NVIC_ISER0_SETENA17_S 17 617 618 // Field: [16] SETENA16 619 // 620 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 621 // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit 622 // returns its current enable state. 623 #define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 624 #define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 625 #define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 626 #define CPU_SCS_NVIC_ISER0_SETENA16_S 16 627 628 // Field: [15] SETENA15 629 // 630 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 631 // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit 632 // returns its current enable state. 633 #define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 634 #define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 635 #define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 636 #define CPU_SCS_NVIC_ISER0_SETENA15_S 15 637 638 // Field: [14] SETENA14 639 // 640 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 641 // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit 642 // returns its current enable state. 643 #define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 644 #define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 645 #define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 646 #define CPU_SCS_NVIC_ISER0_SETENA14_S 14 647 648 // Field: [13] SETENA13 649 // 650 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 651 // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit 652 // returns its current enable state. 653 #define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 654 #define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 655 #define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 656 #define CPU_SCS_NVIC_ISER0_SETENA13_S 13 657 658 // Field: [12] SETENA12 659 // 660 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 661 // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit 662 // returns its current enable state. 663 #define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 664 #define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 665 #define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 666 #define CPU_SCS_NVIC_ISER0_SETENA12_S 12 667 668 // Field: [11] SETENA11 669 // 670 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 671 // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit 672 // returns its current enable state. 673 #define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 674 #define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 675 #define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 676 #define CPU_SCS_NVIC_ISER0_SETENA11_S 11 677 678 // Field: [10] SETENA10 679 // 680 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 681 // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit 682 // returns its current enable state. 683 #define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 684 #define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 685 #define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 686 #define CPU_SCS_NVIC_ISER0_SETENA10_S 10 687 688 // Field: [9] SETENA9 689 // 690 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 691 // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit 692 // returns its current enable state. 693 #define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 694 #define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 695 #define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 696 #define CPU_SCS_NVIC_ISER0_SETENA9_S 9 697 698 // Field: [8] SETENA8 699 // 700 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 701 // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit 702 // returns its current enable state. 703 #define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 704 #define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 705 #define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 706 #define CPU_SCS_NVIC_ISER0_SETENA8_S 8 707 708 // Field: [7] SETENA7 709 // 710 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 711 // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit 712 // returns its current enable state. 713 #define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 714 #define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 715 #define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 716 #define CPU_SCS_NVIC_ISER0_SETENA7_S 7 717 718 // Field: [6] SETENA6 719 // 720 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 721 // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit 722 // returns its current enable state. 723 #define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 724 #define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 725 #define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 726 #define CPU_SCS_NVIC_ISER0_SETENA6_S 6 727 728 // Field: [5] SETENA5 729 // 730 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 731 // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit 732 // returns its current enable state. 733 #define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 734 #define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 735 #define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 736 #define CPU_SCS_NVIC_ISER0_SETENA5_S 5 737 738 // Field: [4] SETENA4 739 // 740 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 741 // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit 742 // returns its current enable state. 743 #define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 744 #define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 745 #define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 746 #define CPU_SCS_NVIC_ISER0_SETENA4_S 4 747 748 // Field: [3] SETENA3 749 // 750 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 751 // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit 752 // returns its current enable state. 753 #define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 754 #define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 755 #define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 756 #define CPU_SCS_NVIC_ISER0_SETENA3_S 3 757 758 // Field: [2] SETENA2 759 // 760 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 761 // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit 762 // returns its current enable state. 763 #define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 764 #define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 765 #define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 766 #define CPU_SCS_NVIC_ISER0_SETENA2_S 2 767 768 // Field: [1] SETENA1 769 // 770 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 771 // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit 772 // returns its current enable state. 773 #define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 774 #define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 775 #define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 776 #define CPU_SCS_NVIC_ISER0_SETENA1_S 1 777 778 // Field: [0] SETENA0 779 // 780 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 781 // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit 782 // returns its current enable state. 783 #define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 784 #define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 785 #define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 786 #define CPU_SCS_NVIC_ISER0_SETENA0_S 0 787 788 //***************************************************************************** 789 // 790 // Register: CPU_SCS_O_NVIC_ISER1 791 // 792 //***************************************************************************** 793 // Field: [5] SETENA37 794 // 795 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 796 // interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit 797 // returns its current enable state. 798 #define CPU_SCS_NVIC_ISER1_SETENA37 0x00000020 799 #define CPU_SCS_NVIC_ISER1_SETENA37_BITN 5 800 #define CPU_SCS_NVIC_ISER1_SETENA37_M 0x00000020 801 #define CPU_SCS_NVIC_ISER1_SETENA37_S 5 802 803 // Field: [4] SETENA36 804 // 805 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 806 // interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit 807 // returns its current enable state. 808 #define CPU_SCS_NVIC_ISER1_SETENA36 0x00000010 809 #define CPU_SCS_NVIC_ISER1_SETENA36_BITN 4 810 #define CPU_SCS_NVIC_ISER1_SETENA36_M 0x00000010 811 #define CPU_SCS_NVIC_ISER1_SETENA36_S 4 812 813 // Field: [3] SETENA35 814 // 815 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 816 // interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit 817 // returns its current enable state. 818 #define CPU_SCS_NVIC_ISER1_SETENA35 0x00000008 819 #define CPU_SCS_NVIC_ISER1_SETENA35_BITN 3 820 #define CPU_SCS_NVIC_ISER1_SETENA35_M 0x00000008 821 #define CPU_SCS_NVIC_ISER1_SETENA35_S 3 822 823 // Field: [2] SETENA34 824 // 825 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 826 // interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit 827 // returns its current enable state. 828 #define CPU_SCS_NVIC_ISER1_SETENA34 0x00000004 829 #define CPU_SCS_NVIC_ISER1_SETENA34_BITN 2 830 #define CPU_SCS_NVIC_ISER1_SETENA34_M 0x00000004 831 #define CPU_SCS_NVIC_ISER1_SETENA34_S 2 832 833 // Field: [1] SETENA33 834 // 835 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 836 // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit 837 // returns its current enable state. 838 #define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 839 #define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 840 #define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 841 #define CPU_SCS_NVIC_ISER1_SETENA33_S 1 842 843 // Field: [0] SETENA32 844 // 845 // Writing 0 to this bit has no effect, writing 1 to this bit enables the 846 // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit 847 // returns its current enable state. 848 #define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 849 #define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 850 #define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 851 #define CPU_SCS_NVIC_ISER1_SETENA32_S 0 852 853 //***************************************************************************** 854 // 855 // Register: CPU_SCS_O_NVIC_ICER0 856 // 857 //***************************************************************************** 858 // Field: [31] CLRENA31 859 // 860 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 861 // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit 862 // returns its current enable state. 863 #define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 864 #define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 865 #define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 866 #define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 867 868 // Field: [30] CLRENA30 869 // 870 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 871 // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit 872 // returns its current enable state. 873 #define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 874 #define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 875 #define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 876 #define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 877 878 // Field: [29] CLRENA29 879 // 880 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 881 // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit 882 // returns its current enable state. 883 #define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 884 #define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 885 #define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 886 #define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 887 888 // Field: [28] CLRENA28 889 // 890 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 891 // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit 892 // returns its current enable state. 893 #define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 894 #define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 895 #define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 896 #define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 897 898 // Field: [27] CLRENA27 899 // 900 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 901 // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit 902 // returns its current enable state. 903 #define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 904 #define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 905 #define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 906 #define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 907 908 // Field: [26] CLRENA26 909 // 910 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 911 // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit 912 // returns its current enable state. 913 #define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 914 #define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 915 #define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 916 #define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 917 918 // Field: [25] CLRENA25 919 // 920 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 921 // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit 922 // returns its current enable state. 923 #define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 924 #define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 925 #define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 926 #define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 927 928 // Field: [24] CLRENA24 929 // 930 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 931 // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit 932 // returns its current enable state. 933 #define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 934 #define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 935 #define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 936 #define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 937 938 // Field: [23] CLRENA23 939 // 940 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 941 // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit 942 // returns its current enable state. 943 #define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 944 #define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 945 #define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 946 #define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 947 948 // Field: [22] CLRENA22 949 // 950 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 951 // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit 952 // returns its current enable state. 953 #define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 954 #define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 955 #define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 956 #define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 957 958 // Field: [21] CLRENA21 959 // 960 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 961 // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit 962 // returns its current enable state. 963 #define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 964 #define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 965 #define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 966 #define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 967 968 // Field: [20] CLRENA20 969 // 970 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 971 // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit 972 // returns its current enable state. 973 #define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 974 #define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 975 #define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 976 #define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 977 978 // Field: [19] CLRENA19 979 // 980 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 981 // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit 982 // returns its current enable state. 983 #define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 984 #define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 985 #define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 986 #define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 987 988 // Field: [18] CLRENA18 989 // 990 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 991 // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit 992 // returns its current enable state. 993 #define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 994 #define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 995 #define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 996 #define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 997 998 // Field: [17] CLRENA17 999 // 1000 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1001 // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit 1002 // returns its current enable state. 1003 #define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 1004 #define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 1005 #define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 1006 #define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 1007 1008 // Field: [16] CLRENA16 1009 // 1010 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1011 // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit 1012 // returns its current enable state. 1013 #define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 1014 #define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 1015 #define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 1016 #define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 1017 1018 // Field: [15] CLRENA15 1019 // 1020 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1021 // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit 1022 // returns its current enable state. 1023 #define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 1024 #define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 1025 #define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 1026 #define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 1027 1028 // Field: [14] CLRENA14 1029 // 1030 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1031 // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit 1032 // returns its current enable state. 1033 #define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 1034 #define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 1035 #define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 1036 #define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 1037 1038 // Field: [13] CLRENA13 1039 // 1040 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1041 // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit 1042 // returns its current enable state. 1043 #define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 1044 #define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 1045 #define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 1046 #define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 1047 1048 // Field: [12] CLRENA12 1049 // 1050 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1051 // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit 1052 // returns its current enable state. 1053 #define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 1054 #define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 1055 #define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 1056 #define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 1057 1058 // Field: [11] CLRENA11 1059 // 1060 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1061 // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit 1062 // returns its current enable state. 1063 #define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 1064 #define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 1065 #define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 1066 #define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 1067 1068 // Field: [10] CLRENA10 1069 // 1070 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1071 // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit 1072 // returns its current enable state. 1073 #define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 1074 #define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 1075 #define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 1076 #define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 1077 1078 // Field: [9] CLRENA9 1079 // 1080 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1081 // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit 1082 // returns its current enable state. 1083 #define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 1084 #define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 1085 #define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 1086 #define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 1087 1088 // Field: [8] CLRENA8 1089 // 1090 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1091 // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit 1092 // returns its current enable state. 1093 #define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 1094 #define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 1095 #define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 1096 #define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 1097 1098 // Field: [7] CLRENA7 1099 // 1100 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1101 // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit 1102 // returns its current enable state. 1103 #define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 1104 #define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 1105 #define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 1106 #define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 1107 1108 // Field: [6] CLRENA6 1109 // 1110 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1111 // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit 1112 // returns its current enable state. 1113 #define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 1114 #define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 1115 #define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 1116 #define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 1117 1118 // Field: [5] CLRENA5 1119 // 1120 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1121 // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit 1122 // returns its current enable state. 1123 #define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 1124 #define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 1125 #define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 1126 #define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 1127 1128 // Field: [4] CLRENA4 1129 // 1130 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1131 // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit 1132 // returns its current enable state. 1133 #define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 1134 #define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 1135 #define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 1136 #define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 1137 1138 // Field: [3] CLRENA3 1139 // 1140 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1141 // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit 1142 // returns its current enable state. 1143 #define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 1144 #define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 1145 #define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 1146 #define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 1147 1148 // Field: [2] CLRENA2 1149 // 1150 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1151 // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit 1152 // returns its current enable state. 1153 #define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 1154 #define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 1155 #define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 1156 #define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 1157 1158 // Field: [1] CLRENA1 1159 // 1160 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1161 // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit 1162 // returns its current enable state. 1163 #define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 1164 #define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 1165 #define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 1166 #define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 1167 1168 // Field: [0] CLRENA0 1169 // 1170 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1171 // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit 1172 // returns its current enable state. 1173 #define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 1174 #define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 1175 #define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 1176 #define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 1177 1178 //***************************************************************************** 1179 // 1180 // Register: CPU_SCS_O_NVIC_ICER1 1181 // 1182 //***************************************************************************** 1183 // Field: [5] CLRENA37 1184 // 1185 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1186 // interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit 1187 // returns its current enable state. 1188 #define CPU_SCS_NVIC_ICER1_CLRENA37 0x00000020 1189 #define CPU_SCS_NVIC_ICER1_CLRENA37_BITN 5 1190 #define CPU_SCS_NVIC_ICER1_CLRENA37_M 0x00000020 1191 #define CPU_SCS_NVIC_ICER1_CLRENA37_S 5 1192 1193 // Field: [4] CLRENA36 1194 // 1195 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1196 // interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit 1197 // returns its current enable state. 1198 #define CPU_SCS_NVIC_ICER1_CLRENA36 0x00000010 1199 #define CPU_SCS_NVIC_ICER1_CLRENA36_BITN 4 1200 #define CPU_SCS_NVIC_ICER1_CLRENA36_M 0x00000010 1201 #define CPU_SCS_NVIC_ICER1_CLRENA36_S 4 1202 1203 // Field: [3] CLRENA35 1204 // 1205 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1206 // interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit 1207 // returns its current enable state. 1208 #define CPU_SCS_NVIC_ICER1_CLRENA35 0x00000008 1209 #define CPU_SCS_NVIC_ICER1_CLRENA35_BITN 3 1210 #define CPU_SCS_NVIC_ICER1_CLRENA35_M 0x00000008 1211 #define CPU_SCS_NVIC_ICER1_CLRENA35_S 3 1212 1213 // Field: [2] CLRENA34 1214 // 1215 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1216 // interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit 1217 // returns its current enable state. 1218 #define CPU_SCS_NVIC_ICER1_CLRENA34 0x00000004 1219 #define CPU_SCS_NVIC_ICER1_CLRENA34_BITN 2 1220 #define CPU_SCS_NVIC_ICER1_CLRENA34_M 0x00000004 1221 #define CPU_SCS_NVIC_ICER1_CLRENA34_S 2 1222 1223 // Field: [1] CLRENA33 1224 // 1225 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1226 // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit 1227 // returns its current enable state. 1228 #define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 1229 #define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 1230 #define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 1231 #define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 1232 1233 // Field: [0] CLRENA32 1234 // 1235 // Writing 0 to this bit has no effect, writing 1 to this bit disables the 1236 // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit 1237 // returns its current enable state. 1238 #define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 1239 #define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 1240 #define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 1241 #define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 1242 1243 //***************************************************************************** 1244 // 1245 // Register: CPU_SCS_O_NVIC_ISPR0 1246 // 1247 //***************************************************************************** 1248 // Field: [31] SETPEND31 1249 // 1250 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1251 // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit 1252 // returns its current state. 1253 #define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 1254 #define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 1255 #define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 1256 #define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 1257 1258 // Field: [30] SETPEND30 1259 // 1260 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1261 // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit 1262 // returns its current state. 1263 #define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 1264 #define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 1265 #define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 1266 #define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 1267 1268 // Field: [29] SETPEND29 1269 // 1270 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1271 // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit 1272 // returns its current state. 1273 #define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 1274 #define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 1275 #define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 1276 #define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 1277 1278 // Field: [28] SETPEND28 1279 // 1280 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1281 // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit 1282 // returns its current state. 1283 #define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 1284 #define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 1285 #define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 1286 #define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 1287 1288 // Field: [27] SETPEND27 1289 // 1290 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1291 // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit 1292 // returns its current state. 1293 #define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 1294 #define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 1295 #define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 1296 #define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 1297 1298 // Field: [26] SETPEND26 1299 // 1300 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1301 // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit 1302 // returns its current state. 1303 #define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 1304 #define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 1305 #define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 1306 #define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 1307 1308 // Field: [25] SETPEND25 1309 // 1310 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1311 // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit 1312 // returns its current state. 1313 #define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 1314 #define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 1315 #define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 1316 #define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 1317 1318 // Field: [24] SETPEND24 1319 // 1320 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1321 // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit 1322 // returns its current state. 1323 #define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 1324 #define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 1325 #define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 1326 #define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 1327 1328 // Field: [23] SETPEND23 1329 // 1330 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1331 // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit 1332 // returns its current state. 1333 #define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 1334 #define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 1335 #define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 1336 #define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 1337 1338 // Field: [22] SETPEND22 1339 // 1340 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1341 // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit 1342 // returns its current state. 1343 #define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 1344 #define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 1345 #define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 1346 #define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 1347 1348 // Field: [21] SETPEND21 1349 // 1350 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1351 // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit 1352 // returns its current state. 1353 #define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 1354 #define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 1355 #define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 1356 #define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 1357 1358 // Field: [20] SETPEND20 1359 // 1360 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1361 // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit 1362 // returns its current state. 1363 #define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 1364 #define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 1365 #define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 1366 #define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 1367 1368 // Field: [19] SETPEND19 1369 // 1370 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1371 // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit 1372 // returns its current state. 1373 #define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 1374 #define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 1375 #define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 1376 #define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 1377 1378 // Field: [18] SETPEND18 1379 // 1380 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1381 // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit 1382 // returns its current state. 1383 #define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 1384 #define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 1385 #define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 1386 #define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 1387 1388 // Field: [17] SETPEND17 1389 // 1390 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1391 // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit 1392 // returns its current state. 1393 #define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 1394 #define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 1395 #define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 1396 #define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 1397 1398 // Field: [16] SETPEND16 1399 // 1400 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1401 // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit 1402 // returns its current state. 1403 #define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 1404 #define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 1405 #define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 1406 #define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 1407 1408 // Field: [15] SETPEND15 1409 // 1410 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1411 // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit 1412 // returns its current state. 1413 #define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 1414 #define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 1415 #define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 1416 #define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 1417 1418 // Field: [14] SETPEND14 1419 // 1420 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1421 // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit 1422 // returns its current state. 1423 #define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 1424 #define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 1425 #define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 1426 #define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 1427 1428 // Field: [13] SETPEND13 1429 // 1430 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1431 // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit 1432 // returns its current state. 1433 #define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 1434 #define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 1435 #define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 1436 #define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 1437 1438 // Field: [12] SETPEND12 1439 // 1440 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1441 // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit 1442 // returns its current state. 1443 #define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 1444 #define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 1445 #define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 1446 #define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 1447 1448 // Field: [11] SETPEND11 1449 // 1450 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1451 // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit 1452 // returns its current state. 1453 #define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 1454 #define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 1455 #define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 1456 #define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 1457 1458 // Field: [10] SETPEND10 1459 // 1460 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1461 // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit 1462 // returns its current state. 1463 #define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 1464 #define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 1465 #define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 1466 #define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 1467 1468 // Field: [9] SETPEND9 1469 // 1470 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1471 // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit 1472 // returns its current state. 1473 #define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 1474 #define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 1475 #define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 1476 #define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 1477 1478 // Field: [8] SETPEND8 1479 // 1480 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1481 // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit 1482 // returns its current state. 1483 #define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 1484 #define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 1485 #define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 1486 #define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 1487 1488 // Field: [7] SETPEND7 1489 // 1490 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1491 // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit 1492 // returns its current state. 1493 #define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 1494 #define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 1495 #define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 1496 #define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 1497 1498 // Field: [6] SETPEND6 1499 // 1500 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1501 // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit 1502 // returns its current state. 1503 #define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 1504 #define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 1505 #define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 1506 #define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 1507 1508 // Field: [5] SETPEND5 1509 // 1510 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1511 // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit 1512 // returns its current state. 1513 #define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 1514 #define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 1515 #define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 1516 #define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 1517 1518 // Field: [4] SETPEND4 1519 // 1520 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1521 // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit 1522 // returns its current state. 1523 #define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 1524 #define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 1525 #define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 1526 #define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 1527 1528 // Field: [3] SETPEND3 1529 // 1530 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1531 // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit 1532 // returns its current state. 1533 #define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 1534 #define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 1535 #define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 1536 #define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 1537 1538 // Field: [2] SETPEND2 1539 // 1540 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1541 // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit 1542 // returns its current state. 1543 #define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 1544 #define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 1545 #define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 1546 #define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 1547 1548 // Field: [1] SETPEND1 1549 // 1550 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1551 // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit 1552 // returns its current state. 1553 #define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 1554 #define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 1555 #define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 1556 #define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 1557 1558 // Field: [0] SETPEND0 1559 // 1560 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1561 // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit 1562 // returns its current state. 1563 #define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 1564 #define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 1565 #define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 1566 #define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 1567 1568 //***************************************************************************** 1569 // 1570 // Register: CPU_SCS_O_NVIC_ISPR1 1571 // 1572 //***************************************************************************** 1573 // Field: [5] SETPEND37 1574 // 1575 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1576 // interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit 1577 // returns its current state. 1578 #define CPU_SCS_NVIC_ISPR1_SETPEND37 0x00000020 1579 #define CPU_SCS_NVIC_ISPR1_SETPEND37_BITN 5 1580 #define CPU_SCS_NVIC_ISPR1_SETPEND37_M 0x00000020 1581 #define CPU_SCS_NVIC_ISPR1_SETPEND37_S 5 1582 1583 // Field: [4] SETPEND36 1584 // 1585 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1586 // interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit 1587 // returns its current state. 1588 #define CPU_SCS_NVIC_ISPR1_SETPEND36 0x00000010 1589 #define CPU_SCS_NVIC_ISPR1_SETPEND36_BITN 4 1590 #define CPU_SCS_NVIC_ISPR1_SETPEND36_M 0x00000010 1591 #define CPU_SCS_NVIC_ISPR1_SETPEND36_S 4 1592 1593 // Field: [3] SETPEND35 1594 // 1595 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1596 // interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit 1597 // returns its current state. 1598 #define CPU_SCS_NVIC_ISPR1_SETPEND35 0x00000008 1599 #define CPU_SCS_NVIC_ISPR1_SETPEND35_BITN 3 1600 #define CPU_SCS_NVIC_ISPR1_SETPEND35_M 0x00000008 1601 #define CPU_SCS_NVIC_ISPR1_SETPEND35_S 3 1602 1603 // Field: [2] SETPEND34 1604 // 1605 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1606 // interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit 1607 // returns its current state. 1608 #define CPU_SCS_NVIC_ISPR1_SETPEND34 0x00000004 1609 #define CPU_SCS_NVIC_ISPR1_SETPEND34_BITN 2 1610 #define CPU_SCS_NVIC_ISPR1_SETPEND34_M 0x00000004 1611 #define CPU_SCS_NVIC_ISPR1_SETPEND34_S 2 1612 1613 // Field: [1] SETPEND33 1614 // 1615 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1616 // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit 1617 // returns its current state. 1618 #define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 1619 #define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 1620 #define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 1621 #define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 1622 1623 // Field: [0] SETPEND32 1624 // 1625 // Writing 0 to this bit has no effect, writing 1 to this bit pends the 1626 // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit 1627 // returns its current state. 1628 #define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 1629 #define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 1630 #define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 1631 #define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 1632 1633 //***************************************************************************** 1634 // 1635 // Register: CPU_SCS_O_NVIC_ICPR0 1636 // 1637 //***************************************************************************** 1638 // Field: [31] CLRPEND31 1639 // 1640 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1641 // corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). 1642 // Reading the bit returns its current state. 1643 #define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 1644 #define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 1645 #define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 1646 #define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 1647 1648 // Field: [30] CLRPEND30 1649 // 1650 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1651 // corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). 1652 // Reading the bit returns its current state. 1653 #define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 1654 #define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 1655 #define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 1656 #define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 1657 1658 // Field: [29] CLRPEND29 1659 // 1660 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1661 // corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). 1662 // Reading the bit returns its current state. 1663 #define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 1664 #define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 1665 #define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 1666 #define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 1667 1668 // Field: [28] CLRPEND28 1669 // 1670 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1671 // corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). 1672 // Reading the bit returns its current state. 1673 #define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 1674 #define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 1675 #define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 1676 #define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 1677 1678 // Field: [27] CLRPEND27 1679 // 1680 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1681 // corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). 1682 // Reading the bit returns its current state. 1683 #define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 1684 #define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 1685 #define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 1686 #define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 1687 1688 // Field: [26] CLRPEND26 1689 // 1690 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1691 // corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). 1692 // Reading the bit returns its current state. 1693 #define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 1694 #define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 1695 #define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 1696 #define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 1697 1698 // Field: [25] CLRPEND25 1699 // 1700 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1701 // corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). 1702 // Reading the bit returns its current state. 1703 #define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 1704 #define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 1705 #define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 1706 #define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 1707 1708 // Field: [24] CLRPEND24 1709 // 1710 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1711 // corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). 1712 // Reading the bit returns its current state. 1713 #define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 1714 #define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 1715 #define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 1716 #define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 1717 1718 // Field: [23] CLRPEND23 1719 // 1720 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1721 // corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). 1722 // Reading the bit returns its current state. 1723 #define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 1724 #define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 1725 #define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 1726 #define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 1727 1728 // Field: [22] CLRPEND22 1729 // 1730 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1731 // corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). 1732 // Reading the bit returns its current state. 1733 #define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 1734 #define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 1735 #define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 1736 #define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 1737 1738 // Field: [21] CLRPEND21 1739 // 1740 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1741 // corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). 1742 // Reading the bit returns its current state. 1743 #define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 1744 #define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 1745 #define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 1746 #define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 1747 1748 // Field: [20] CLRPEND20 1749 // 1750 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1751 // corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). 1752 // Reading the bit returns its current state. 1753 #define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 1754 #define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 1755 #define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 1756 #define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 1757 1758 // Field: [19] CLRPEND19 1759 // 1760 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1761 // corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). 1762 // Reading the bit returns its current state. 1763 #define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 1764 #define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 1765 #define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 1766 #define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 1767 1768 // Field: [18] CLRPEND18 1769 // 1770 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1771 // corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). 1772 // Reading the bit returns its current state. 1773 #define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 1774 #define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 1775 #define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 1776 #define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 1777 1778 // Field: [17] CLRPEND17 1779 // 1780 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1781 // corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). 1782 // Reading the bit returns its current state. 1783 #define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 1784 #define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 1785 #define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 1786 #define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 1787 1788 // Field: [16] CLRPEND16 1789 // 1790 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1791 // corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). 1792 // Reading the bit returns its current state. 1793 #define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 1794 #define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 1795 #define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 1796 #define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 1797 1798 // Field: [15] CLRPEND15 1799 // 1800 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1801 // corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). 1802 // Reading the bit returns its current state. 1803 #define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 1804 #define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 1805 #define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 1806 #define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 1807 1808 // Field: [14] CLRPEND14 1809 // 1810 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1811 // corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). 1812 // Reading the bit returns its current state. 1813 #define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 1814 #define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 1815 #define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 1816 #define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 1817 1818 // Field: [13] CLRPEND13 1819 // 1820 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1821 // corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). 1822 // Reading the bit returns its current state. 1823 #define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 1824 #define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 1825 #define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 1826 #define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 1827 1828 // Field: [12] CLRPEND12 1829 // 1830 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1831 // corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). 1832 // Reading the bit returns its current state. 1833 #define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 1834 #define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 1835 #define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 1836 #define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 1837 1838 // Field: [11] CLRPEND11 1839 // 1840 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1841 // corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). 1842 // Reading the bit returns its current state. 1843 #define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 1844 #define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 1845 #define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 1846 #define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 1847 1848 // Field: [10] CLRPEND10 1849 // 1850 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1851 // corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). 1852 // Reading the bit returns its current state. 1853 #define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 1854 #define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 1855 #define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 1856 #define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 1857 1858 // Field: [9] CLRPEND9 1859 // 1860 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1861 // corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). 1862 // Reading the bit returns its current state. 1863 #define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 1864 #define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 1865 #define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 1866 #define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 1867 1868 // Field: [8] CLRPEND8 1869 // 1870 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1871 // corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). 1872 // Reading the bit returns its current state. 1873 #define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 1874 #define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 1875 #define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 1876 #define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 1877 1878 // Field: [7] CLRPEND7 1879 // 1880 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1881 // corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). 1882 // Reading the bit returns its current state. 1883 #define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 1884 #define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 1885 #define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 1886 #define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 1887 1888 // Field: [6] CLRPEND6 1889 // 1890 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1891 // corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). 1892 // Reading the bit returns its current state. 1893 #define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 1894 #define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 1895 #define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 1896 #define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 1897 1898 // Field: [5] CLRPEND5 1899 // 1900 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1901 // corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). 1902 // Reading the bit returns its current state. 1903 #define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 1904 #define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 1905 #define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 1906 #define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 1907 1908 // Field: [4] CLRPEND4 1909 // 1910 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1911 // corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). 1912 // Reading the bit returns its current state. 1913 #define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 1914 #define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 1915 #define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 1916 #define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 1917 1918 // Field: [3] CLRPEND3 1919 // 1920 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1921 // corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). 1922 // Reading the bit returns its current state. 1923 #define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 1924 #define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 1925 #define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 1926 #define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 1927 1928 // Field: [2] CLRPEND2 1929 // 1930 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1931 // corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). 1932 // Reading the bit returns its current state. 1933 #define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 1934 #define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 1935 #define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 1936 #define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 1937 1938 // Field: [1] CLRPEND1 1939 // 1940 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1941 // corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). 1942 // Reading the bit returns its current state. 1943 #define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 1944 #define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 1945 #define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 1946 #define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 1947 1948 // Field: [0] CLRPEND0 1949 // 1950 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1951 // corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). 1952 // Reading the bit returns its current state. 1953 #define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 1954 #define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 1955 #define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 1956 #define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 1957 1958 //***************************************************************************** 1959 // 1960 // Register: CPU_SCS_O_NVIC_ICPR1 1961 // 1962 //***************************************************************************** 1963 // Field: [5] CLRPEND37 1964 // 1965 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1966 // corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). 1967 // Reading the bit returns its current state. 1968 #define CPU_SCS_NVIC_ICPR1_CLRPEND37 0x00000020 1969 #define CPU_SCS_NVIC_ICPR1_CLRPEND37_BITN 5 1970 #define CPU_SCS_NVIC_ICPR1_CLRPEND37_M 0x00000020 1971 #define CPU_SCS_NVIC_ICPR1_CLRPEND37_S 5 1972 1973 // Field: [4] CLRPEND36 1974 // 1975 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1976 // corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). 1977 // Reading the bit returns its current state. 1978 #define CPU_SCS_NVIC_ICPR1_CLRPEND36 0x00000010 1979 #define CPU_SCS_NVIC_ICPR1_CLRPEND36_BITN 4 1980 #define CPU_SCS_NVIC_ICPR1_CLRPEND36_M 0x00000010 1981 #define CPU_SCS_NVIC_ICPR1_CLRPEND36_S 4 1982 1983 // Field: [3] CLRPEND35 1984 // 1985 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1986 // corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). 1987 // Reading the bit returns its current state. 1988 #define CPU_SCS_NVIC_ICPR1_CLRPEND35 0x00000008 1989 #define CPU_SCS_NVIC_ICPR1_CLRPEND35_BITN 3 1990 #define CPU_SCS_NVIC_ICPR1_CLRPEND35_M 0x00000008 1991 #define CPU_SCS_NVIC_ICPR1_CLRPEND35_S 3 1992 1993 // Field: [2] CLRPEND34 1994 // 1995 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 1996 // corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). 1997 // Reading the bit returns its current state. 1998 #define CPU_SCS_NVIC_ICPR1_CLRPEND34 0x00000004 1999 #define CPU_SCS_NVIC_ICPR1_CLRPEND34_BITN 2 2000 #define CPU_SCS_NVIC_ICPR1_CLRPEND34_M 0x00000004 2001 #define CPU_SCS_NVIC_ICPR1_CLRPEND34_S 2 2002 2003 // Field: [1] CLRPEND33 2004 // 2005 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 2006 // corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). 2007 // Reading the bit returns its current state. 2008 #define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 2009 #define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 2010 #define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 2011 #define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 2012 2013 // Field: [0] CLRPEND32 2014 // 2015 // Writing 0 to this bit has no effect, writing 1 to this bit clears the 2016 // corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). 2017 // Reading the bit returns its current state. 2018 #define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 2019 #define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 2020 #define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 2021 #define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 2022 2023 //***************************************************************************** 2024 // 2025 // Register: CPU_SCS_O_NVIC_IABR0 2026 // 2027 //***************************************************************************** 2028 // Field: [31] ACTIVE31 2029 // 2030 // Reading 0 from this bit implies that interrupt line 31 is not active. 2031 // Reading 1 from this bit implies that the interrupt line 31 is active (See 2032 // EVENT:CPUIRQSEL31.EV for details). 2033 #define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 2034 #define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 2035 #define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 2036 #define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 2037 2038 // Field: [30] ACTIVE30 2039 // 2040 // Reading 0 from this bit implies that interrupt line 30 is not active. 2041 // Reading 1 from this bit implies that the interrupt line 30 is active (See 2042 // EVENT:CPUIRQSEL30.EV for details). 2043 #define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 2044 #define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 2045 #define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 2046 #define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 2047 2048 // Field: [29] ACTIVE29 2049 // 2050 // Reading 0 from this bit implies that interrupt line 29 is not active. 2051 // Reading 1 from this bit implies that the interrupt line 29 is active (See 2052 // EVENT:CPUIRQSEL29.EV for details). 2053 #define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 2054 #define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 2055 #define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 2056 #define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 2057 2058 // Field: [28] ACTIVE28 2059 // 2060 // Reading 0 from this bit implies that interrupt line 28 is not active. 2061 // Reading 1 from this bit implies that the interrupt line 28 is active (See 2062 // EVENT:CPUIRQSEL28.EV for details). 2063 #define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 2064 #define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 2065 #define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 2066 #define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 2067 2068 // Field: [27] ACTIVE27 2069 // 2070 // Reading 0 from this bit implies that interrupt line 27 is not active. 2071 // Reading 1 from this bit implies that the interrupt line 27 is active (See 2072 // EVENT:CPUIRQSEL27.EV for details). 2073 #define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 2074 #define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 2075 #define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 2076 #define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 2077 2078 // Field: [26] ACTIVE26 2079 // 2080 // Reading 0 from this bit implies that interrupt line 26 is not active. 2081 // Reading 1 from this bit implies that the interrupt line 26 is active (See 2082 // EVENT:CPUIRQSEL26.EV for details). 2083 #define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 2084 #define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 2085 #define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 2086 #define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 2087 2088 // Field: [25] ACTIVE25 2089 // 2090 // Reading 0 from this bit implies that interrupt line 25 is not active. 2091 // Reading 1 from this bit implies that the interrupt line 25 is active (See 2092 // EVENT:CPUIRQSEL25.EV for details). 2093 #define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 2094 #define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 2095 #define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 2096 #define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 2097 2098 // Field: [24] ACTIVE24 2099 // 2100 // Reading 0 from this bit implies that interrupt line 24 is not active. 2101 // Reading 1 from this bit implies that the interrupt line 24 is active (See 2102 // EVENT:CPUIRQSEL24.EV for details). 2103 #define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 2104 #define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 2105 #define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 2106 #define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 2107 2108 // Field: [23] ACTIVE23 2109 // 2110 // Reading 0 from this bit implies that interrupt line 23 is not active. 2111 // Reading 1 from this bit implies that the interrupt line 23 is active (See 2112 // EVENT:CPUIRQSEL23.EV for details). 2113 #define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 2114 #define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 2115 #define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 2116 #define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 2117 2118 // Field: [22] ACTIVE22 2119 // 2120 // Reading 0 from this bit implies that interrupt line 22 is not active. 2121 // Reading 1 from this bit implies that the interrupt line 22 is active (See 2122 // EVENT:CPUIRQSEL22.EV for details). 2123 #define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 2124 #define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 2125 #define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 2126 #define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 2127 2128 // Field: [21] ACTIVE21 2129 // 2130 // Reading 0 from this bit implies that interrupt line 21 is not active. 2131 // Reading 1 from this bit implies that the interrupt line 21 is active (See 2132 // EVENT:CPUIRQSEL21.EV for details). 2133 #define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 2134 #define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 2135 #define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 2136 #define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 2137 2138 // Field: [20] ACTIVE20 2139 // 2140 // Reading 0 from this bit implies that interrupt line 20 is not active. 2141 // Reading 1 from this bit implies that the interrupt line 20 is active (See 2142 // EVENT:CPUIRQSEL20.EV for details). 2143 #define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 2144 #define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 2145 #define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 2146 #define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 2147 2148 // Field: [19] ACTIVE19 2149 // 2150 // Reading 0 from this bit implies that interrupt line 19 is not active. 2151 // Reading 1 from this bit implies that the interrupt line 19 is active (See 2152 // EVENT:CPUIRQSEL19.EV for details). 2153 #define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 2154 #define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 2155 #define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 2156 #define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 2157 2158 // Field: [18] ACTIVE18 2159 // 2160 // Reading 0 from this bit implies that interrupt line 18 is not active. 2161 // Reading 1 from this bit implies that the interrupt line 18 is active (See 2162 // EVENT:CPUIRQSEL18.EV for details). 2163 #define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 2164 #define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 2165 #define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 2166 #define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 2167 2168 // Field: [17] ACTIVE17 2169 // 2170 // Reading 0 from this bit implies that interrupt line 17 is not active. 2171 // Reading 1 from this bit implies that the interrupt line 17 is active (See 2172 // EVENT:CPUIRQSEL17.EV for details). 2173 #define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 2174 #define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 2175 #define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 2176 #define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 2177 2178 // Field: [16] ACTIVE16 2179 // 2180 // Reading 0 from this bit implies that interrupt line 16 is not active. 2181 // Reading 1 from this bit implies that the interrupt line 16 is active (See 2182 // EVENT:CPUIRQSEL16.EV for details). 2183 #define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 2184 #define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 2185 #define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 2186 #define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 2187 2188 // Field: [15] ACTIVE15 2189 // 2190 // Reading 0 from this bit implies that interrupt line 15 is not active. 2191 // Reading 1 from this bit implies that the interrupt line 15 is active (See 2192 // EVENT:CPUIRQSEL15.EV for details). 2193 #define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 2194 #define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 2195 #define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 2196 #define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 2197 2198 // Field: [14] ACTIVE14 2199 // 2200 // Reading 0 from this bit implies that interrupt line 14 is not active. 2201 // Reading 1 from this bit implies that the interrupt line 14 is active (See 2202 // EVENT:CPUIRQSEL14.EV for details). 2203 #define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 2204 #define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 2205 #define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 2206 #define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 2207 2208 // Field: [13] ACTIVE13 2209 // 2210 // Reading 0 from this bit implies that interrupt line 13 is not active. 2211 // Reading 1 from this bit implies that the interrupt line 13 is active (See 2212 // EVENT:CPUIRQSEL13.EV for details). 2213 #define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 2214 #define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 2215 #define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 2216 #define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 2217 2218 // Field: [12] ACTIVE12 2219 // 2220 // Reading 0 from this bit implies that interrupt line 12 is not active. 2221 // Reading 1 from this bit implies that the interrupt line 12 is active (See 2222 // EVENT:CPUIRQSEL12.EV for details). 2223 #define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 2224 #define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 2225 #define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 2226 #define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 2227 2228 // Field: [11] ACTIVE11 2229 // 2230 // Reading 0 from this bit implies that interrupt line 11 is not active. 2231 // Reading 1 from this bit implies that the interrupt line 11 is active (See 2232 // EVENT:CPUIRQSEL11.EV for details). 2233 #define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 2234 #define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 2235 #define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 2236 #define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 2237 2238 // Field: [10] ACTIVE10 2239 // 2240 // Reading 0 from this bit implies that interrupt line 10 is not active. 2241 // Reading 1 from this bit implies that the interrupt line 10 is active (See 2242 // EVENT:CPUIRQSEL10.EV for details). 2243 #define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 2244 #define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 2245 #define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 2246 #define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 2247 2248 // Field: [9] ACTIVE9 2249 // 2250 // Reading 0 from this bit implies that interrupt line 9 is not active. Reading 2251 // 1 from this bit implies that the interrupt line 9 is active (See 2252 // EVENT:CPUIRQSEL9.EV for details). 2253 #define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 2254 #define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 2255 #define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 2256 #define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 2257 2258 // Field: [8] ACTIVE8 2259 // 2260 // Reading 0 from this bit implies that interrupt line 8 is not active. Reading 2261 // 1 from this bit implies that the interrupt line 8 is active (See 2262 // EVENT:CPUIRQSEL8.EV for details). 2263 #define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 2264 #define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 2265 #define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 2266 #define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 2267 2268 // Field: [7] ACTIVE7 2269 // 2270 // Reading 0 from this bit implies that interrupt line 7 is not active. Reading 2271 // 1 from this bit implies that the interrupt line 7 is active (See 2272 // EVENT:CPUIRQSEL7.EV for details). 2273 #define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 2274 #define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 2275 #define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 2276 #define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 2277 2278 // Field: [6] ACTIVE6 2279 // 2280 // Reading 0 from this bit implies that interrupt line 6 is not active. Reading 2281 // 1 from this bit implies that the interrupt line 6 is active (See 2282 // EVENT:CPUIRQSEL6.EV for details). 2283 #define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 2284 #define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 2285 #define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 2286 #define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 2287 2288 // Field: [5] ACTIVE5 2289 // 2290 // Reading 0 from this bit implies that interrupt line 5 is not active. Reading 2291 // 1 from this bit implies that the interrupt line 5 is active (See 2292 // EVENT:CPUIRQSEL5.EV for details). 2293 #define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 2294 #define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 2295 #define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 2296 #define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 2297 2298 // Field: [4] ACTIVE4 2299 // 2300 // Reading 0 from this bit implies that interrupt line 4 is not active. Reading 2301 // 1 from this bit implies that the interrupt line 4 is active (See 2302 // EVENT:CPUIRQSEL4.EV for details). 2303 #define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 2304 #define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 2305 #define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 2306 #define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 2307 2308 // Field: [3] ACTIVE3 2309 // 2310 // Reading 0 from this bit implies that interrupt line 3 is not active. Reading 2311 // 1 from this bit implies that the interrupt line 3 is active (See 2312 // EVENT:CPUIRQSEL3.EV for details). 2313 #define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 2314 #define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 2315 #define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 2316 #define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 2317 2318 // Field: [2] ACTIVE2 2319 // 2320 // Reading 0 from this bit implies that interrupt line 2 is not active. Reading 2321 // 1 from this bit implies that the interrupt line 2 is active (See 2322 // EVENT:CPUIRQSEL2.EV for details). 2323 #define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 2324 #define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 2325 #define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 2326 #define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 2327 2328 // Field: [1] ACTIVE1 2329 // 2330 // Reading 0 from this bit implies that interrupt line 1 is not active. Reading 2331 // 1 from this bit implies that the interrupt line 1 is active (See 2332 // EVENT:CPUIRQSEL1.EV for details). 2333 #define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 2334 #define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 2335 #define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 2336 #define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 2337 2338 // Field: [0] ACTIVE0 2339 // 2340 // Reading 0 from this bit implies that interrupt line 0 is not active. Reading 2341 // 1 from this bit implies that the interrupt line 0 is active (See 2342 // EVENT:CPUIRQSEL0.EV for details). 2343 #define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 2344 #define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 2345 #define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 2346 #define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 2347 2348 //***************************************************************************** 2349 // 2350 // Register: CPU_SCS_O_NVIC_IABR1 2351 // 2352 //***************************************************************************** 2353 // Field: [5] ACTIVE37 2354 // 2355 // Reading 0 from this bit implies that interrupt line 37 is not active. 2356 // Reading 1 from this bit implies that the interrupt line 37 is active (See 2357 // EVENT:CPUIRQSEL37.EV for details). 2358 #define CPU_SCS_NVIC_IABR1_ACTIVE37 0x00000020 2359 #define CPU_SCS_NVIC_IABR1_ACTIVE37_BITN 5 2360 #define CPU_SCS_NVIC_IABR1_ACTIVE37_M 0x00000020 2361 #define CPU_SCS_NVIC_IABR1_ACTIVE37_S 5 2362 2363 // Field: [4] ACTIVE36 2364 // 2365 // Reading 0 from this bit implies that interrupt line 36 is not active. 2366 // Reading 1 from this bit implies that the interrupt line 36 is active (See 2367 // EVENT:CPUIRQSEL36.EV for details). 2368 #define CPU_SCS_NVIC_IABR1_ACTIVE36 0x00000010 2369 #define CPU_SCS_NVIC_IABR1_ACTIVE36_BITN 4 2370 #define CPU_SCS_NVIC_IABR1_ACTIVE36_M 0x00000010 2371 #define CPU_SCS_NVIC_IABR1_ACTIVE36_S 4 2372 2373 // Field: [3] ACTIVE35 2374 // 2375 // Reading 0 from this bit implies that interrupt line 35 is not active. 2376 // Reading 1 from this bit implies that the interrupt line 35 is active (See 2377 // EVENT:CPUIRQSEL35.EV for details). 2378 #define CPU_SCS_NVIC_IABR1_ACTIVE35 0x00000008 2379 #define CPU_SCS_NVIC_IABR1_ACTIVE35_BITN 3 2380 #define CPU_SCS_NVIC_IABR1_ACTIVE35_M 0x00000008 2381 #define CPU_SCS_NVIC_IABR1_ACTIVE35_S 3 2382 2383 // Field: [2] ACTIVE34 2384 // 2385 // Reading 0 from this bit implies that interrupt line 34 is not active. 2386 // Reading 1 from this bit implies that the interrupt line 34 is active (See 2387 // EVENT:CPUIRQSEL34.EV for details). 2388 #define CPU_SCS_NVIC_IABR1_ACTIVE34 0x00000004 2389 #define CPU_SCS_NVIC_IABR1_ACTIVE34_BITN 2 2390 #define CPU_SCS_NVIC_IABR1_ACTIVE34_M 0x00000004 2391 #define CPU_SCS_NVIC_IABR1_ACTIVE34_S 2 2392 2393 // Field: [1] ACTIVE33 2394 // 2395 // Reading 0 from this bit implies that interrupt line 33 is not active. 2396 // Reading 1 from this bit implies that the interrupt line 33 is active (See 2397 // EVENT:CPUIRQSEL33.EV for details). 2398 #define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 2399 #define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 2400 #define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 2401 #define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 2402 2403 // Field: [0] ACTIVE32 2404 // 2405 // Reading 0 from this bit implies that interrupt line 32 is not active. 2406 // Reading 1 from this bit implies that the interrupt line 32 is active (See 2407 // EVENT:CPUIRQSEL32.EV for details). 2408 #define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 2409 #define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 2410 #define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 2411 #define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 2412 2413 //***************************************************************************** 2414 // 2415 // Register: CPU_SCS_O_NVIC_IPR0 2416 // 2417 //***************************************************************************** 2418 // Field: [31:24] PRI_3 2419 // 2420 // Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). 2421 #define CPU_SCS_NVIC_IPR0_PRI_3_W 8 2422 #define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 2423 #define CPU_SCS_NVIC_IPR0_PRI_3_S 24 2424 2425 // Field: [23:16] PRI_2 2426 // 2427 // Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). 2428 #define CPU_SCS_NVIC_IPR0_PRI_2_W 8 2429 #define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 2430 #define CPU_SCS_NVIC_IPR0_PRI_2_S 16 2431 2432 // Field: [15:8] PRI_1 2433 // 2434 // Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). 2435 #define CPU_SCS_NVIC_IPR0_PRI_1_W 8 2436 #define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 2437 #define CPU_SCS_NVIC_IPR0_PRI_1_S 8 2438 2439 // Field: [7:0] PRI_0 2440 // 2441 // Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). 2442 #define CPU_SCS_NVIC_IPR0_PRI_0_W 8 2443 #define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF 2444 #define CPU_SCS_NVIC_IPR0_PRI_0_S 0 2445 2446 //***************************************************************************** 2447 // 2448 // Register: CPU_SCS_O_NVIC_IPR1 2449 // 2450 //***************************************************************************** 2451 // Field: [31:24] PRI_7 2452 // 2453 // Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). 2454 #define CPU_SCS_NVIC_IPR1_PRI_7_W 8 2455 #define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 2456 #define CPU_SCS_NVIC_IPR1_PRI_7_S 24 2457 2458 // Field: [23:16] PRI_6 2459 // 2460 // Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). 2461 #define CPU_SCS_NVIC_IPR1_PRI_6_W 8 2462 #define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 2463 #define CPU_SCS_NVIC_IPR1_PRI_6_S 16 2464 2465 // Field: [15:8] PRI_5 2466 // 2467 // Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). 2468 #define CPU_SCS_NVIC_IPR1_PRI_5_W 8 2469 #define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 2470 #define CPU_SCS_NVIC_IPR1_PRI_5_S 8 2471 2472 // Field: [7:0] PRI_4 2473 // 2474 // Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). 2475 #define CPU_SCS_NVIC_IPR1_PRI_4_W 8 2476 #define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF 2477 #define CPU_SCS_NVIC_IPR1_PRI_4_S 0 2478 2479 //***************************************************************************** 2480 // 2481 // Register: CPU_SCS_O_NVIC_IPR2 2482 // 2483 //***************************************************************************** 2484 // Field: [31:24] PRI_11 2485 // 2486 // Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). 2487 #define CPU_SCS_NVIC_IPR2_PRI_11_W 8 2488 #define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 2489 #define CPU_SCS_NVIC_IPR2_PRI_11_S 24 2490 2491 // Field: [23:16] PRI_10 2492 // 2493 // Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). 2494 #define CPU_SCS_NVIC_IPR2_PRI_10_W 8 2495 #define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 2496 #define CPU_SCS_NVIC_IPR2_PRI_10_S 16 2497 2498 // Field: [15:8] PRI_9 2499 // 2500 // Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). 2501 #define CPU_SCS_NVIC_IPR2_PRI_9_W 8 2502 #define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 2503 #define CPU_SCS_NVIC_IPR2_PRI_9_S 8 2504 2505 // Field: [7:0] PRI_8 2506 // 2507 // Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). 2508 #define CPU_SCS_NVIC_IPR2_PRI_8_W 8 2509 #define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF 2510 #define CPU_SCS_NVIC_IPR2_PRI_8_S 0 2511 2512 //***************************************************************************** 2513 // 2514 // Register: CPU_SCS_O_NVIC_IPR3 2515 // 2516 //***************************************************************************** 2517 // Field: [31:24] PRI_15 2518 // 2519 // Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). 2520 #define CPU_SCS_NVIC_IPR3_PRI_15_W 8 2521 #define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 2522 #define CPU_SCS_NVIC_IPR3_PRI_15_S 24 2523 2524 // Field: [23:16] PRI_14 2525 // 2526 // Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). 2527 #define CPU_SCS_NVIC_IPR3_PRI_14_W 8 2528 #define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 2529 #define CPU_SCS_NVIC_IPR3_PRI_14_S 16 2530 2531 // Field: [15:8] PRI_13 2532 // 2533 // Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). 2534 #define CPU_SCS_NVIC_IPR3_PRI_13_W 8 2535 #define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 2536 #define CPU_SCS_NVIC_IPR3_PRI_13_S 8 2537 2538 // Field: [7:0] PRI_12 2539 // 2540 // Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). 2541 #define CPU_SCS_NVIC_IPR3_PRI_12_W 8 2542 #define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF 2543 #define CPU_SCS_NVIC_IPR3_PRI_12_S 0 2544 2545 //***************************************************************************** 2546 // 2547 // Register: CPU_SCS_O_NVIC_IPR4 2548 // 2549 //***************************************************************************** 2550 // Field: [31:24] PRI_19 2551 // 2552 // Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). 2553 #define CPU_SCS_NVIC_IPR4_PRI_19_W 8 2554 #define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 2555 #define CPU_SCS_NVIC_IPR4_PRI_19_S 24 2556 2557 // Field: [23:16] PRI_18 2558 // 2559 // Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). 2560 #define CPU_SCS_NVIC_IPR4_PRI_18_W 8 2561 #define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 2562 #define CPU_SCS_NVIC_IPR4_PRI_18_S 16 2563 2564 // Field: [15:8] PRI_17 2565 // 2566 // Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). 2567 #define CPU_SCS_NVIC_IPR4_PRI_17_W 8 2568 #define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 2569 #define CPU_SCS_NVIC_IPR4_PRI_17_S 8 2570 2571 // Field: [7:0] PRI_16 2572 // 2573 // Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). 2574 #define CPU_SCS_NVIC_IPR4_PRI_16_W 8 2575 #define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF 2576 #define CPU_SCS_NVIC_IPR4_PRI_16_S 0 2577 2578 //***************************************************************************** 2579 // 2580 // Register: CPU_SCS_O_NVIC_IPR5 2581 // 2582 //***************************************************************************** 2583 // Field: [31:24] PRI_23 2584 // 2585 // Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). 2586 #define CPU_SCS_NVIC_IPR5_PRI_23_W 8 2587 #define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 2588 #define CPU_SCS_NVIC_IPR5_PRI_23_S 24 2589 2590 // Field: [23:16] PRI_22 2591 // 2592 // Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). 2593 #define CPU_SCS_NVIC_IPR5_PRI_22_W 8 2594 #define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 2595 #define CPU_SCS_NVIC_IPR5_PRI_22_S 16 2596 2597 // Field: [15:8] PRI_21 2598 // 2599 // Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). 2600 #define CPU_SCS_NVIC_IPR5_PRI_21_W 8 2601 #define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 2602 #define CPU_SCS_NVIC_IPR5_PRI_21_S 8 2603 2604 // Field: [7:0] PRI_20 2605 // 2606 // Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). 2607 #define CPU_SCS_NVIC_IPR5_PRI_20_W 8 2608 #define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF 2609 #define CPU_SCS_NVIC_IPR5_PRI_20_S 0 2610 2611 //***************************************************************************** 2612 // 2613 // Register: CPU_SCS_O_NVIC_IPR6 2614 // 2615 //***************************************************************************** 2616 // Field: [31:24] PRI_27 2617 // 2618 // Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). 2619 #define CPU_SCS_NVIC_IPR6_PRI_27_W 8 2620 #define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 2621 #define CPU_SCS_NVIC_IPR6_PRI_27_S 24 2622 2623 // Field: [23:16] PRI_26 2624 // 2625 // Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). 2626 #define CPU_SCS_NVIC_IPR6_PRI_26_W 8 2627 #define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 2628 #define CPU_SCS_NVIC_IPR6_PRI_26_S 16 2629 2630 // Field: [15:8] PRI_25 2631 // 2632 // Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). 2633 #define CPU_SCS_NVIC_IPR6_PRI_25_W 8 2634 #define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 2635 #define CPU_SCS_NVIC_IPR6_PRI_25_S 8 2636 2637 // Field: [7:0] PRI_24 2638 // 2639 // Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). 2640 #define CPU_SCS_NVIC_IPR6_PRI_24_W 8 2641 #define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF 2642 #define CPU_SCS_NVIC_IPR6_PRI_24_S 0 2643 2644 //***************************************************************************** 2645 // 2646 // Register: CPU_SCS_O_NVIC_IPR7 2647 // 2648 //***************************************************************************** 2649 // Field: [31:24] PRI_31 2650 // 2651 // Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). 2652 #define CPU_SCS_NVIC_IPR7_PRI_31_W 8 2653 #define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 2654 #define CPU_SCS_NVIC_IPR7_PRI_31_S 24 2655 2656 // Field: [23:16] PRI_30 2657 // 2658 // Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). 2659 #define CPU_SCS_NVIC_IPR7_PRI_30_W 8 2660 #define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 2661 #define CPU_SCS_NVIC_IPR7_PRI_30_S 16 2662 2663 // Field: [15:8] PRI_29 2664 // 2665 // Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). 2666 #define CPU_SCS_NVIC_IPR7_PRI_29_W 8 2667 #define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 2668 #define CPU_SCS_NVIC_IPR7_PRI_29_S 8 2669 2670 // Field: [7:0] PRI_28 2671 // 2672 // Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). 2673 #define CPU_SCS_NVIC_IPR7_PRI_28_W 8 2674 #define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF 2675 #define CPU_SCS_NVIC_IPR7_PRI_28_S 0 2676 2677 //***************************************************************************** 2678 // 2679 // Register: CPU_SCS_O_NVIC_IPR8 2680 // 2681 //***************************************************************************** 2682 // Field: [31:24] PRI_35 2683 // 2684 // Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). 2685 #define CPU_SCS_NVIC_IPR8_PRI_35_W 8 2686 #define CPU_SCS_NVIC_IPR8_PRI_35_M 0xFF000000 2687 #define CPU_SCS_NVIC_IPR8_PRI_35_S 24 2688 2689 // Field: [23:16] PRI_34 2690 // 2691 // Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). 2692 #define CPU_SCS_NVIC_IPR8_PRI_34_W 8 2693 #define CPU_SCS_NVIC_IPR8_PRI_34_M 0x00FF0000 2694 #define CPU_SCS_NVIC_IPR8_PRI_34_S 16 2695 2696 // Field: [15:8] PRI_33 2697 // 2698 // Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). 2699 #define CPU_SCS_NVIC_IPR8_PRI_33_W 8 2700 #define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 2701 #define CPU_SCS_NVIC_IPR8_PRI_33_S 8 2702 2703 // Field: [7:0] PRI_32 2704 // 2705 // Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). 2706 #define CPU_SCS_NVIC_IPR8_PRI_32_W 8 2707 #define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF 2708 #define CPU_SCS_NVIC_IPR8_PRI_32_S 0 2709 2710 //***************************************************************************** 2711 // 2712 // Register: CPU_SCS_O_NVIC_IPR9 2713 // 2714 //***************************************************************************** 2715 // Field: [15:8] PRI_37 2716 // 2717 // Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). 2718 #define CPU_SCS_NVIC_IPR9_PRI_37_W 8 2719 #define CPU_SCS_NVIC_IPR9_PRI_37_M 0x0000FF00 2720 #define CPU_SCS_NVIC_IPR9_PRI_37_S 8 2721 2722 // Field: [7:0] PRI_36 2723 // 2724 // Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). 2725 #define CPU_SCS_NVIC_IPR9_PRI_36_W 8 2726 #define CPU_SCS_NVIC_IPR9_PRI_36_M 0x000000FF 2727 #define CPU_SCS_NVIC_IPR9_PRI_36_S 0 2728 2729 //***************************************************************************** 2730 // 2731 // Register: CPU_SCS_O_CPUID 2732 // 2733 //***************************************************************************** 2734 // Field: [31:24] IMPLEMENTER 2735 // 2736 // Implementor code. 2737 #define CPU_SCS_CPUID_IMPLEMENTER_W 8 2738 #define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 2739 #define CPU_SCS_CPUID_IMPLEMENTER_S 24 2740 2741 // Field: [23:20] VARIANT 2742 // 2743 // Implementation defined variant number. 2744 #define CPU_SCS_CPUID_VARIANT_W 4 2745 #define CPU_SCS_CPUID_VARIANT_M 0x00F00000 2746 #define CPU_SCS_CPUID_VARIANT_S 20 2747 2748 // Field: [19:16] CONSTANT 2749 // 2750 // Reads as 0xF 2751 #define CPU_SCS_CPUID_CONSTANT_W 4 2752 #define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 2753 #define CPU_SCS_CPUID_CONSTANT_S 16 2754 2755 // Field: [15:4] PARTNO 2756 // 2757 // Number of processor within family. 2758 #define CPU_SCS_CPUID_PARTNO_W 12 2759 #define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 2760 #define CPU_SCS_CPUID_PARTNO_S 4 2761 2762 // Field: [3:0] REVISION 2763 // 2764 // Implementation defined revision number. 2765 #define CPU_SCS_CPUID_REVISION_W 4 2766 #define CPU_SCS_CPUID_REVISION_M 0x0000000F 2767 #define CPU_SCS_CPUID_REVISION_S 0 2768 2769 //***************************************************************************** 2770 // 2771 // Register: CPU_SCS_O_ICSR 2772 // 2773 //***************************************************************************** 2774 // Field: [31] NMIPENDSET 2775 // 2776 // Set pending NMI bit. Setting this bit pends and activates an NMI. Because 2777 // NMI is the highest-priority interrupt, it takes effect as soon as it 2778 // registers. 2779 // 2780 // 0: No action 2781 // 1: Set pending NMI 2782 #define CPU_SCS_ICSR_NMIPENDSET 0x80000000 2783 #define CPU_SCS_ICSR_NMIPENDSET_BITN 31 2784 #define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 2785 #define CPU_SCS_ICSR_NMIPENDSET_S 31 2786 2787 // Field: [28] PENDSVSET 2788 // 2789 // Set pending pendSV bit. 2790 // 2791 // 0: No action 2792 // 1: Set pending PendSV 2793 #define CPU_SCS_ICSR_PENDSVSET 0x10000000 2794 #define CPU_SCS_ICSR_PENDSVSET_BITN 28 2795 #define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 2796 #define CPU_SCS_ICSR_PENDSVSET_S 28 2797 2798 // Field: [27] PENDSVCLR 2799 // 2800 // Clear pending pendSV bit 2801 // 2802 // 0: No action 2803 // 1: Clear pending pendSV 2804 #define CPU_SCS_ICSR_PENDSVCLR 0x08000000 2805 #define CPU_SCS_ICSR_PENDSVCLR_BITN 27 2806 #define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 2807 #define CPU_SCS_ICSR_PENDSVCLR_S 27 2808 2809 // Field: [26] PENDSTSET 2810 // 2811 // Set a pending SysTick bit. 2812 // 2813 // 0: No action 2814 // 1: Set pending SysTick 2815 #define CPU_SCS_ICSR_PENDSTSET 0x04000000 2816 #define CPU_SCS_ICSR_PENDSTSET_BITN 26 2817 #define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 2818 #define CPU_SCS_ICSR_PENDSTSET_S 26 2819 2820 // Field: [25] PENDSTCLR 2821 // 2822 // Clear pending SysTick bit 2823 // 2824 // 0: No action 2825 // 1: Clear pending SysTick 2826 #define CPU_SCS_ICSR_PENDSTCLR 0x02000000 2827 #define CPU_SCS_ICSR_PENDSTCLR_BITN 25 2828 #define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 2829 #define CPU_SCS_ICSR_PENDSTCLR_S 25 2830 2831 // Field: [23] ISRPREEMPT 2832 // 2833 // This field can only be used at debug time. It indicates that a pending 2834 // interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, 2835 // the interrupt is serviced. 2836 // 2837 // 0: A pending exception is not serviced. 2838 // 1: A pending exception is serviced on exit from the debug halt state 2839 #define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 2840 #define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 2841 #define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 2842 #define CPU_SCS_ICSR_ISRPREEMPT_S 23 2843 2844 // Field: [22] ISRPENDING 2845 // 2846 // Interrupt pending flag. Excludes NMI and faults. 2847 // 2848 // 0x0: Interrupt not pending 2849 // 0x1: Interrupt pending 2850 #define CPU_SCS_ICSR_ISRPENDING 0x00400000 2851 #define CPU_SCS_ICSR_ISRPENDING_BITN 22 2852 #define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 2853 #define CPU_SCS_ICSR_ISRPENDING_S 22 2854 2855 // Field: [17:12] VECTPENDING 2856 // 2857 // Pending ISR number field. This field contains the interrupt number of the 2858 // highest priority pending ISR. 2859 #define CPU_SCS_ICSR_VECTPENDING_W 6 2860 #define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 2861 #define CPU_SCS_ICSR_VECTPENDING_S 12 2862 2863 // Field: [11] RETTOBASE 2864 // 2865 // Indicates whether there are preempted active exceptions: 2866 // 2867 // 0: There are preempted active exceptions to execute 2868 // 1: There are no active exceptions, or the currently-executing exception is 2869 // the only active exception. 2870 #define CPU_SCS_ICSR_RETTOBASE 0x00000800 2871 #define CPU_SCS_ICSR_RETTOBASE_BITN 11 2872 #define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 2873 #define CPU_SCS_ICSR_RETTOBASE_S 11 2874 2875 // Field: [8:0] VECTACTIVE 2876 // 2877 // Active ISR number field. Reset clears this field. 2878 #define CPU_SCS_ICSR_VECTACTIVE_W 9 2879 #define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF 2880 #define CPU_SCS_ICSR_VECTACTIVE_S 0 2881 2882 //***************************************************************************** 2883 // 2884 // Register: CPU_SCS_O_VTOR 2885 // 2886 //***************************************************************************** 2887 // Field: [29:7] TBLOFF 2888 // 2889 // Bits 29 down to 7 of the vector table base offset. 2890 #define CPU_SCS_VTOR_TBLOFF_W 23 2891 #define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 2892 #define CPU_SCS_VTOR_TBLOFF_S 7 2893 2894 //***************************************************************************** 2895 // 2896 // Register: CPU_SCS_O_AIRCR 2897 // 2898 //***************************************************************************** 2899 // Field: [31:16] VECTKEY 2900 // 2901 // Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. 2902 // Otherwise the write value is ignored. Read always returns 0xFA05. 2903 #define CPU_SCS_AIRCR_VECTKEY_W 16 2904 #define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 2905 #define CPU_SCS_AIRCR_VECTKEY_S 16 2906 2907 // Field: [15] ENDIANESS 2908 // 2909 // Data endianness bit 2910 // ENUMs: 2911 // BIG Big endian 2912 // LITTLE Little endian 2913 #define CPU_SCS_AIRCR_ENDIANESS 0x00008000 2914 #define CPU_SCS_AIRCR_ENDIANESS_BITN 15 2915 #define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 2916 #define CPU_SCS_AIRCR_ENDIANESS_S 15 2917 #define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 2918 #define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 2919 2920 // Field: [10:8] PRIGROUP 2921 // 2922 // Interrupt priority grouping field. This field is a binary point position 2923 // indicator for creating subpriorities for exceptions that share the same 2924 // pre-emption level. It divides the PRI_n field in the Interrupt Priority 2925 // Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption 2926 // level and a subpriority level. The binary point is a left-of value. This 2927 // means that the PRIGROUP value represents a point starting at the left of the 2928 // Least Significant Bit (LSB). The lowest value might not be 0 depending on 2929 // the number of bits allocated for priorities, and implementation choices. 2930 #define CPU_SCS_AIRCR_PRIGROUP_W 3 2931 #define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 2932 #define CPU_SCS_AIRCR_PRIGROUP_S 8 2933 2934 // Field: [2] SYSRESETREQ 2935 // 2936 // Requests a warm reset. Setting this bit does not prevent Halting Debug from 2937 // running. 2938 #define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 2939 #define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 2940 #define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 2941 #define CPU_SCS_AIRCR_SYSRESETREQ_S 2 2942 2943 // Field: [1] VECTCLRACTIVE 2944 // 2945 // Clears all active state information for active NMI, fault, and interrupts. 2946 // It is the responsibility of the application to reinitialize the stack. This 2947 // bit is for returning to a known state during debug. The bit self-clears. 2948 // IPSR is not cleared by this operation. So, if used by an application, it 2949 // must only be used at the base level of activation, or within a system 2950 // handler whose active bit can be set. 2951 #define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 2952 #define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 2953 #define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 2954 #define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 2955 2956 // Field: [0] VECTRESET 2957 // 2958 // System Reset bit. Resets the system, with the exception of debug components. 2959 // This bit is reserved for debug use and can be written to 1 only when the 2960 // core is halted. The bit self-clears. Writing this bit to 1 while core is not 2961 // halted may result in unpredictable behavior. 2962 #define CPU_SCS_AIRCR_VECTRESET 0x00000001 2963 #define CPU_SCS_AIRCR_VECTRESET_BITN 0 2964 #define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 2965 #define CPU_SCS_AIRCR_VECTRESET_S 0 2966 2967 //***************************************************************************** 2968 // 2969 // Register: CPU_SCS_O_SCR 2970 // 2971 //***************************************************************************** 2972 // Field: [4] SEVONPEND 2973 // 2974 // Send Event on Pending bit: 2975 // 2976 // 0: Only enabled interrupts or events can wakeup the processor, disabled 2977 // interrupts are excluded 2978 // 1: Enabled events and all interrupts, including disabled interrupts, can 2979 // wakeup the processor. 2980 // 2981 // When an event or interrupt enters pending state, the event signal wakes up 2982 // the processor from WFE. If 2983 // the processor is not waiting for an event, the event is registered and 2984 // affects the next WFE. 2985 // The processor also wakes up on execution of an SEV instruction. 2986 #define CPU_SCS_SCR_SEVONPEND 0x00000010 2987 #define CPU_SCS_SCR_SEVONPEND_BITN 4 2988 #define CPU_SCS_SCR_SEVONPEND_M 0x00000010 2989 #define CPU_SCS_SCR_SEVONPEND_S 4 2990 2991 // Field: [2] SLEEPDEEP 2992 // 2993 // Controls whether the processor uses sleep or deep sleep as its low power 2994 // mode 2995 // ENUMs: 2996 // DEEPSLEEP Deep sleep 2997 // SLEEP Sleep 2998 #define CPU_SCS_SCR_SLEEPDEEP 0x00000004 2999 #define CPU_SCS_SCR_SLEEPDEEP_BITN 2 3000 #define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 3001 #define CPU_SCS_SCR_SLEEPDEEP_S 2 3002 #define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 3003 #define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 3004 3005 // Field: [1] SLEEPONEXIT 3006 // 3007 // Sleep on exit when returning from Handler mode to Thread mode. Enables 3008 // interrupt driven applications to avoid returning to empty main application. 3009 // 3010 // 0: Do not sleep when returning to thread mode 3011 // 1: Sleep on ISR exit 3012 #define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 3013 #define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 3014 #define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 3015 #define CPU_SCS_SCR_SLEEPONEXIT_S 1 3016 3017 //***************************************************************************** 3018 // 3019 // Register: CPU_SCS_O_CCR 3020 // 3021 //***************************************************************************** 3022 // Field: [9] STKALIGN 3023 // 3024 // Stack alignment bit. 3025 // 3026 // 0: Only 4-byte alignment is guaranteed for the SP used prior to the 3027 // exception on exception entry. 3028 // 1: On exception entry, the SP used prior to the exception is adjusted to be 3029 // 8-byte aligned and the context to restore it is saved. The SP is restored on 3030 // the associated exception return. 3031 #define CPU_SCS_CCR_STKALIGN 0x00000200 3032 #define CPU_SCS_CCR_STKALIGN_BITN 9 3033 #define CPU_SCS_CCR_STKALIGN_M 0x00000200 3034 #define CPU_SCS_CCR_STKALIGN_S 9 3035 3036 // Field: [8] BFHFNMIGN 3037 // 3038 // Enables handlers with priority -1 or -2 to ignore data BusFaults caused by 3039 // load and store instructions. This applies to the HardFault, NMI, and 3040 // FAULTMASK escalated handlers: 3041 // 3042 // 0: Data BusFaults caused by load and store instructions cause a lock-up 3043 // 1: Data BusFaults caused by load and store instructions are ignored. 3044 // 3045 // Set this bit to 1 only when the handler and its data are in absolutely safe 3046 // memory. The normal use 3047 // of this bit is to probe system devices and bridges to detect problems. 3048 #define CPU_SCS_CCR_BFHFNMIGN 0x00000100 3049 #define CPU_SCS_CCR_BFHFNMIGN_BITN 8 3050 #define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 3051 #define CPU_SCS_CCR_BFHFNMIGN_S 8 3052 3053 // Field: [4] DIV_0_TRP 3054 // 3055 // Enables faulting or halting when the processor executes an SDIV or UDIV 3056 // instruction with a divisor of 0: 3057 // 3058 // 0: Do not trap divide by 0. In this mode, a divide by zero returns a 3059 // quotient of 0. 3060 // 1: Trap divide by 0. The relevant Usage Fault Status Register bit is 3061 // CFSR.DIVBYZERO. 3062 #define CPU_SCS_CCR_DIV_0_TRP 0x00000010 3063 #define CPU_SCS_CCR_DIV_0_TRP_BITN 4 3064 #define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 3065 #define CPU_SCS_CCR_DIV_0_TRP_S 4 3066 3067 // Field: [3] UNALIGN_TRP 3068 // 3069 // Enables unaligned access traps: 3070 // 3071 // 0: Do not trap unaligned halfword and word accesses 3072 // 1: Trap unaligned halfword and word accesses. The relevant Usage Fault 3073 // Status Register bit is CFSR.UNALIGNED. 3074 // 3075 // If this bit is set to 1, an unaligned access generates a UsageFault. 3076 // Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of 3077 // the value in UNALIGN_TRP. 3078 #define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 3079 #define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 3080 #define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 3081 #define CPU_SCS_CCR_UNALIGN_TRP_S 3 3082 3083 // Field: [1] USERSETMPEND 3084 // 3085 // Enables unprivileged software access to STIR: 3086 // 3087 // 0: User code is not allowed to write to the Software Trigger Interrupt 3088 // register (STIR). 3089 // 1: User code can write the Software Trigger Interrupt register (STIR) to 3090 // trigger (pend) a Main exception, which is associated with the Main stack 3091 // pointer. 3092 #define CPU_SCS_CCR_USERSETMPEND 0x00000002 3093 #define CPU_SCS_CCR_USERSETMPEND_BITN 1 3094 #define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 3095 #define CPU_SCS_CCR_USERSETMPEND_S 1 3096 3097 // Field: [0] NONBASETHREDENA 3098 // 3099 // Indicates how the processor enters Thread mode: 3100 // 3101 // 0: Processor can enter Thread mode only when no exception is active. 3102 // 1: Processor can enter Thread mode from any level using the appropriate 3103 // return value (EXC_RETURN). 3104 // 3105 // Exception returns occur when one of the following instructions loads a value 3106 // of 0xFXXXXXXX into the PC while in Handler mode: 3107 // - POP/LDM which includes loading the PC. 3108 // - LDR with PC as a destination. 3109 // - BX with any register. 3110 // The value written to the PC is intercepted and is referred to as the 3111 // EXC_RETURN value. 3112 #define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 3113 #define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 3114 #define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 3115 #define CPU_SCS_CCR_NONBASETHREDENA_S 0 3116 3117 //***************************************************************************** 3118 // 3119 // Register: CPU_SCS_O_SHPR1 3120 // 3121 //***************************************************************************** 3122 // Field: [23:16] PRI_6 3123 // 3124 // Priority of system handler 6. UsageFault 3125 #define CPU_SCS_SHPR1_PRI_6_W 8 3126 #define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 3127 #define CPU_SCS_SHPR1_PRI_6_S 16 3128 3129 // Field: [15:8] PRI_5 3130 // 3131 // Priority of system handler 5: BusFault 3132 #define CPU_SCS_SHPR1_PRI_5_W 8 3133 #define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 3134 #define CPU_SCS_SHPR1_PRI_5_S 8 3135 3136 // Field: [7:0] PRI_4 3137 // 3138 // Priority of system handler 4: MemManage 3139 #define CPU_SCS_SHPR1_PRI_4_W 8 3140 #define CPU_SCS_SHPR1_PRI_4_M 0x000000FF 3141 #define CPU_SCS_SHPR1_PRI_4_S 0 3142 3143 //***************************************************************************** 3144 // 3145 // Register: CPU_SCS_O_SHPR2 3146 // 3147 //***************************************************************************** 3148 // Field: [31:24] PRI_11 3149 // 3150 // Priority of system handler 11. SVCall 3151 #define CPU_SCS_SHPR2_PRI_11_W 8 3152 #define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 3153 #define CPU_SCS_SHPR2_PRI_11_S 24 3154 3155 //***************************************************************************** 3156 // 3157 // Register: CPU_SCS_O_SHPR3 3158 // 3159 //***************************************************************************** 3160 // Field: [31:24] PRI_15 3161 // 3162 // Priority of system handler 15. SysTick exception 3163 #define CPU_SCS_SHPR3_PRI_15_W 8 3164 #define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 3165 #define CPU_SCS_SHPR3_PRI_15_S 24 3166 3167 // Field: [23:16] PRI_14 3168 // 3169 // Priority of system handler 14. Pend SV 3170 #define CPU_SCS_SHPR3_PRI_14_W 8 3171 #define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 3172 #define CPU_SCS_SHPR3_PRI_14_S 16 3173 3174 // Field: [7:0] PRI_12 3175 // 3176 // Priority of system handler 12. Debug Monitor 3177 #define CPU_SCS_SHPR3_PRI_12_W 8 3178 #define CPU_SCS_SHPR3_PRI_12_M 0x000000FF 3179 #define CPU_SCS_SHPR3_PRI_12_S 0 3180 3181 //***************************************************************************** 3182 // 3183 // Register: CPU_SCS_O_SHCSR 3184 // 3185 //***************************************************************************** 3186 // Field: [18] USGFAULTENA 3187 // 3188 // Usage fault system handler enable 3189 // ENUMs: 3190 // EN Exception enabled 3191 // DIS Exception disabled 3192 #define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 3193 #define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 3194 #define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 3195 #define CPU_SCS_SHCSR_USGFAULTENA_S 18 3196 #define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 3197 #define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 3198 3199 // Field: [17] BUSFAULTENA 3200 // 3201 // Bus fault system handler enable 3202 // ENUMs: 3203 // EN Exception enabled 3204 // DIS Exception disabled 3205 #define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 3206 #define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 3207 #define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 3208 #define CPU_SCS_SHCSR_BUSFAULTENA_S 17 3209 #define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 3210 #define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 3211 3212 // Field: [16] MEMFAULTENA 3213 // 3214 // MemManage fault system handler enable 3215 // ENUMs: 3216 // EN Exception enabled 3217 // DIS Exception disabled 3218 #define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 3219 #define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 3220 #define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 3221 #define CPU_SCS_SHCSR_MEMFAULTENA_S 16 3222 #define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 3223 #define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 3224 3225 // Field: [15] SVCALLPENDED 3226 // 3227 // SVCall pending 3228 // ENUMs: 3229 // PENDING Exception is pending. 3230 // NOTPENDING Exception is not active 3231 #define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 3232 #define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 3233 #define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 3234 #define CPU_SCS_SHCSR_SVCALLPENDED_S 15 3235 #define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 3236 #define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 3237 3238 // Field: [14] BUSFAULTPENDED 3239 // 3240 // BusFault pending 3241 // ENUMs: 3242 // PENDING Exception is pending. 3243 // NOTPENDING Exception is not active 3244 #define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 3245 #define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 3246 #define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 3247 #define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 3248 #define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 3249 #define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 3250 3251 // Field: [13] MEMFAULTPENDED 3252 // 3253 // MemManage exception pending 3254 // ENUMs: 3255 // PENDING Exception is pending. 3256 // NOTPENDING Exception is not active 3257 #define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 3258 #define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 3259 #define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 3260 #define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 3261 #define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 3262 #define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 3263 3264 // Field: [12] USGFAULTPENDED 3265 // 3266 // Usage fault pending 3267 // ENUMs: 3268 // PENDING Exception is pending. 3269 // NOTPENDING Exception is not active 3270 #define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 3271 #define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 3272 #define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 3273 #define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 3274 #define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 3275 #define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 3276 3277 // Field: [11] SYSTICKACT 3278 // 3279 // SysTick active flag. 3280 // 3281 // 0x0: Not active 3282 // 0x1: Active 3283 // ENUMs: 3284 // ACTIVE Exception is active 3285 // NOTACTIVE Exception is not active 3286 #define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 3287 #define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 3288 #define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 3289 #define CPU_SCS_SHCSR_SYSTICKACT_S 11 3290 #define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 3291 #define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 3292 3293 // Field: [10] PENDSVACT 3294 // 3295 // PendSV active 3296 // 3297 // 0x0: Not active 3298 // 0x1: Active 3299 #define CPU_SCS_SHCSR_PENDSVACT 0x00000400 3300 #define CPU_SCS_SHCSR_PENDSVACT_BITN 10 3301 #define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 3302 #define CPU_SCS_SHCSR_PENDSVACT_S 10 3303 3304 // Field: [8] MONITORACT 3305 // 3306 // Debug monitor active 3307 // ENUMs: 3308 // ACTIVE Exception is active 3309 // NOTACTIVE Exception is not active 3310 #define CPU_SCS_SHCSR_MONITORACT 0x00000100 3311 #define CPU_SCS_SHCSR_MONITORACT_BITN 8 3312 #define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 3313 #define CPU_SCS_SHCSR_MONITORACT_S 8 3314 #define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 3315 #define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 3316 3317 // Field: [7] SVCALLACT 3318 // 3319 // SVCall active 3320 // ENUMs: 3321 // ACTIVE Exception is active 3322 // NOTACTIVE Exception is not active 3323 #define CPU_SCS_SHCSR_SVCALLACT 0x00000080 3324 #define CPU_SCS_SHCSR_SVCALLACT_BITN 7 3325 #define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 3326 #define CPU_SCS_SHCSR_SVCALLACT_S 7 3327 #define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 3328 #define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 3329 3330 // Field: [3] USGFAULTACT 3331 // 3332 // UsageFault exception active 3333 // ENUMs: 3334 // ACTIVE Exception is active 3335 // NOTACTIVE Exception is not active 3336 #define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 3337 #define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 3338 #define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 3339 #define CPU_SCS_SHCSR_USGFAULTACT_S 3 3340 #define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 3341 #define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 3342 3343 // Field: [1] BUSFAULTACT 3344 // 3345 // BusFault exception active 3346 // ENUMs: 3347 // ACTIVE Exception is active 3348 // NOTACTIVE Exception is not active 3349 #define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 3350 #define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 3351 #define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 3352 #define CPU_SCS_SHCSR_BUSFAULTACT_S 1 3353 #define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 3354 #define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 3355 3356 // Field: [0] MEMFAULTACT 3357 // 3358 // MemManage exception active 3359 // ENUMs: 3360 // ACTIVE Exception is active 3361 // NOTACTIVE Exception is not active 3362 #define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 3363 #define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 3364 #define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 3365 #define CPU_SCS_SHCSR_MEMFAULTACT_S 0 3366 #define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 3367 #define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 3368 3369 //***************************************************************************** 3370 // 3371 // Register: CPU_SCS_O_CFSR 3372 // 3373 //***************************************************************************** 3374 // Field: [25] DIVBYZERO 3375 // 3376 // When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is 3377 // enabled and an SDIV or UDIV instruction is used with a divisor of 0, this 3378 // fault occurs The instruction is executed and the return PC points to it. If 3379 // CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. 3380 #define CPU_SCS_CFSR_DIVBYZERO 0x02000000 3381 #define CPU_SCS_CFSR_DIVBYZERO_BITN 25 3382 #define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 3383 #define CPU_SCS_CFSR_DIVBYZERO_S 25 3384 3385 // Field: [24] UNALIGNED 3386 // 3387 // When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an 3388 // unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD 3389 // instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. 3390 #define CPU_SCS_CFSR_UNALIGNED 0x01000000 3391 #define CPU_SCS_CFSR_UNALIGNED_BITN 24 3392 #define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 3393 #define CPU_SCS_CFSR_UNALIGNED_S 24 3394 3395 // Field: [19] NOCP 3396 // 3397 // Attempt to use a coprocessor instruction. The processor does not support 3398 // coprocessor instructions. 3399 #define CPU_SCS_CFSR_NOCP 0x00080000 3400 #define CPU_SCS_CFSR_NOCP_BITN 19 3401 #define CPU_SCS_CFSR_NOCP_M 0x00080000 3402 #define CPU_SCS_CFSR_NOCP_S 19 3403 3404 // Field: [18] INVPC 3405 // 3406 // Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid 3407 // context, invalid value. The return PC points to the instruction that tried 3408 // to set the PC. 3409 #define CPU_SCS_CFSR_INVPC 0x00040000 3410 #define CPU_SCS_CFSR_INVPC_BITN 18 3411 #define CPU_SCS_CFSR_INVPC_M 0x00040000 3412 #define CPU_SCS_CFSR_INVPC_S 18 3413 3414 // Field: [17] INVSTATE 3415 // 3416 // Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX 3417 // type instruction has changed state). This includes state change after entry 3418 // to or return from exception, as well as from inter-working instructions. 3419 // Return PC points to faulting instruction, with the invalid state. 3420 #define CPU_SCS_CFSR_INVSTATE 0x00020000 3421 #define CPU_SCS_CFSR_INVSTATE_BITN 17 3422 #define CPU_SCS_CFSR_INVSTATE_M 0x00020000 3423 #define CPU_SCS_CFSR_INVSTATE_S 17 3424 3425 // Field: [16] UNDEFINSTR 3426 // 3427 // This bit is set when the processor attempts to execute an undefined 3428 // instruction. This is an instruction that the processor cannot decode. The 3429 // return PC points to the undefined instruction. 3430 #define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 3431 #define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 3432 #define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 3433 #define CPU_SCS_CFSR_UNDEFINSTR_S 16 3434 3435 // Field: [15] BFARVALID 3436 // 3437 // This bit is set if the Bus Fault Address Register (BFAR) contains a valid 3438 // address. This is true after a bus fault where the address is known. Other 3439 // faults can clear this bit, such as a Mem Manage fault occurring later. If a 3440 // Bus fault occurs that is escalated to a Hard Fault because of priority, the 3441 // Hard Fault handler must clear this bit. This prevents problems if returning 3442 // to a stacked active Bus fault handler whose BFAR value has been overwritten. 3443 #define CPU_SCS_CFSR_BFARVALID 0x00008000 3444 #define CPU_SCS_CFSR_BFARVALID_BITN 15 3445 #define CPU_SCS_CFSR_BFARVALID_M 0x00008000 3446 #define CPU_SCS_CFSR_BFARVALID_S 15 3447 3448 // Field: [12] STKERR 3449 // 3450 // Stacking from exception has caused one or more bus faults. The SP is still 3451 // adjusted and the values in the context area on the stack might be incorrect. 3452 // BFAR is not written. 3453 #define CPU_SCS_CFSR_STKERR 0x00001000 3454 #define CPU_SCS_CFSR_STKERR_BITN 12 3455 #define CPU_SCS_CFSR_STKERR_M 0x00001000 3456 #define CPU_SCS_CFSR_STKERR_S 12 3457 3458 // Field: [11] UNSTKERR 3459 // 3460 // Unstack from exception return has caused one or more bus faults. This is 3461 // chained to the handler, so that the original return stack is still present. 3462 // SP is not adjusted from failing return and new save is not performed. BFAR 3463 // is not written. 3464 #define CPU_SCS_CFSR_UNSTKERR 0x00000800 3465 #define CPU_SCS_CFSR_UNSTKERR_BITN 11 3466 #define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 3467 #define CPU_SCS_CFSR_UNSTKERR_S 11 3468 3469 // Field: [10] IMPRECISERR 3470 // 3471 // Imprecise data bus error. It is a BusFault, but the Return PC is not related 3472 // to the causing instruction. This is not a synchronous fault. So, if detected 3473 // when the priority of the current activation is higher than the Bus Fault, it 3474 // only pends. Bus fault activates when returning to a lower priority 3475 // activation. If a precise fault occurs before returning to a lower priority 3476 // exception, the handler detects both IMPRECISERR set and one of the precise 3477 // fault status bits set at the same time. BFAR is not written. 3478 #define CPU_SCS_CFSR_IMPRECISERR 0x00000400 3479 #define CPU_SCS_CFSR_IMPRECISERR_BITN 10 3480 #define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 3481 #define CPU_SCS_CFSR_IMPRECISERR_S 10 3482 3483 // Field: [9] PRECISERR 3484 // 3485 // Precise data bus error return. 3486 #define CPU_SCS_CFSR_PRECISERR 0x00000200 3487 #define CPU_SCS_CFSR_PRECISERR_BITN 9 3488 #define CPU_SCS_CFSR_PRECISERR_M 0x00000200 3489 #define CPU_SCS_CFSR_PRECISERR_S 9 3490 3491 // Field: [8] IBUSERR 3492 // 3493 // Instruction bus error flag. This flag is set by a prefetch error. The fault 3494 // stops on the instruction, so if the error occurs under a branch shadow, no 3495 // fault occurs. BFAR is not written. 3496 #define CPU_SCS_CFSR_IBUSERR 0x00000100 3497 #define CPU_SCS_CFSR_IBUSERR_BITN 8 3498 #define CPU_SCS_CFSR_IBUSERR_M 0x00000100 3499 #define CPU_SCS_CFSR_IBUSERR_S 8 3500 3501 // Field: [7] MMARVALID 3502 // 3503 // Memory Manage Address Register (MMFAR) address valid flag. A later-arriving 3504 // fault, such as a bus fault, can clear a memory manage fault.. If a MemManage 3505 // fault occurs that is escalated to a Hard Fault because of priority, the Hard 3506 // Fault handler must clear this bit. This prevents problems on return to a 3507 // stacked active MemManage handler whose MMFAR value has been overwritten. 3508 #define CPU_SCS_CFSR_MMARVALID 0x00000080 3509 #define CPU_SCS_CFSR_MMARVALID_BITN 7 3510 #define CPU_SCS_CFSR_MMARVALID_M 0x00000080 3511 #define CPU_SCS_CFSR_MMARVALID_S 7 3512 3513 // Field: [4] MSTKERR 3514 // 3515 // Stacking from exception has caused one or more access violations. The SP is 3516 // still adjusted and the values in the context area on the stack might be 3517 // incorrect. MMFAR is not written. 3518 #define CPU_SCS_CFSR_MSTKERR 0x00000010 3519 #define CPU_SCS_CFSR_MSTKERR_BITN 4 3520 #define CPU_SCS_CFSR_MSTKERR_M 0x00000010 3521 #define CPU_SCS_CFSR_MSTKERR_S 4 3522 3523 // Field: [3] MUNSTKERR 3524 // 3525 // Unstack from exception return has caused one or more access violations. This 3526 // is chained to the handler, so that the original return stack is still 3527 // present. SP is not adjusted from failing return and new save is not 3528 // performed. MMFAR is not written. 3529 #define CPU_SCS_CFSR_MUNSTKERR 0x00000008 3530 #define CPU_SCS_CFSR_MUNSTKERR_BITN 3 3531 #define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 3532 #define CPU_SCS_CFSR_MUNSTKERR_S 3 3533 3534 // Field: [1] DACCVIOL 3535 // 3536 // Data access violation flag. Attempting to load or store at a location that 3537 // does not permit the operation sets this flag. The return PC points to the 3538 // faulting instruction. This error loads MMFAR with the address of the 3539 // attempted access. 3540 #define CPU_SCS_CFSR_DACCVIOL 0x00000002 3541 #define CPU_SCS_CFSR_DACCVIOL_BITN 1 3542 #define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 3543 #define CPU_SCS_CFSR_DACCVIOL_S 1 3544 3545 // Field: [0] IACCVIOL 3546 // 3547 // Instruction access violation flag. Attempting to fetch an instruction from a 3548 // location that does not permit execution sets this flag. This occurs on any 3549 // access to an XN region, even when the MPU is disabled or not present. The 3550 // return PC points to the faulting instruction. MMFAR is not written. 3551 #define CPU_SCS_CFSR_IACCVIOL 0x00000001 3552 #define CPU_SCS_CFSR_IACCVIOL_BITN 0 3553 #define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 3554 #define CPU_SCS_CFSR_IACCVIOL_S 0 3555 3556 //***************************************************************************** 3557 // 3558 // Register: CPU_SCS_O_HFSR 3559 // 3560 //***************************************************************************** 3561 // Field: [31] DEBUGEVT 3562 // 3563 // This bit is set if there is a fault related to debug. This is only possible 3564 // when halting debug is not enabled. For monitor enabled debug, it only 3565 // happens for BKPT when the current priority is higher than the monitor. When 3566 // both halting and monitor debug are disabled, it only happens for debug 3567 // events that are not ignored (minimally, BKPT). The Debug Fault Status 3568 // Register is updated. 3569 #define CPU_SCS_HFSR_DEBUGEVT 0x80000000 3570 #define CPU_SCS_HFSR_DEBUGEVT_BITN 31 3571 #define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 3572 #define CPU_SCS_HFSR_DEBUGEVT_S 31 3573 3574 // Field: [30] FORCED 3575 // 3576 // Hard Fault activated because a Configurable Fault was received and cannot 3577 // activate because of priority or because the Configurable Fault is disabled. 3578 // The Hard Fault handler then has to read the other fault status registers to 3579 // determine cause. 3580 #define CPU_SCS_HFSR_FORCED 0x40000000 3581 #define CPU_SCS_HFSR_FORCED_BITN 30 3582 #define CPU_SCS_HFSR_FORCED_M 0x40000000 3583 #define CPU_SCS_HFSR_FORCED_S 30 3584 3585 // Field: [1] VECTTBL 3586 // 3587 // This bit is set if there is a fault because of vector table read on 3588 // exception processing (Bus Fault). This case is always a Hard Fault. The 3589 // return PC points to the pre-empted instruction. 3590 #define CPU_SCS_HFSR_VECTTBL 0x00000002 3591 #define CPU_SCS_HFSR_VECTTBL_BITN 1 3592 #define CPU_SCS_HFSR_VECTTBL_M 0x00000002 3593 #define CPU_SCS_HFSR_VECTTBL_S 1 3594 3595 //***************************************************************************** 3596 // 3597 // Register: CPU_SCS_O_DFSR 3598 // 3599 //***************************************************************************** 3600 // Field: [4] EXTERNAL 3601 // 3602 // External debug request flag. The processor stops on next instruction 3603 // boundary. 3604 // 3605 // 0x0: External debug request signal not asserted 3606 // 0x1: External debug request signal asserted 3607 #define CPU_SCS_DFSR_EXTERNAL 0x00000010 3608 #define CPU_SCS_DFSR_EXTERNAL_BITN 4 3609 #define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 3610 #define CPU_SCS_DFSR_EXTERNAL_S 4 3611 3612 // Field: [3] VCATCH 3613 // 3614 // Vector catch flag. When this flag is set, a flag in one of the local fault 3615 // status registers is also set to indicate the type of fault. 3616 // 3617 // 0x0: No vector catch occurred 3618 // 0x1: Vector catch occurred 3619 #define CPU_SCS_DFSR_VCATCH 0x00000008 3620 #define CPU_SCS_DFSR_VCATCH_BITN 3 3621 #define CPU_SCS_DFSR_VCATCH_M 0x00000008 3622 #define CPU_SCS_DFSR_VCATCH_S 3 3623 3624 // Field: [2] DWTTRAP 3625 // 3626 // Data Watchpoint and Trace (DWT) flag. The processor stops at the current 3627 // instruction or at the next instruction. 3628 // 3629 // 0x0: No DWT match 3630 // 0x1: DWT match 3631 #define CPU_SCS_DFSR_DWTTRAP 0x00000004 3632 #define CPU_SCS_DFSR_DWTTRAP_BITN 2 3633 #define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 3634 #define CPU_SCS_DFSR_DWTTRAP_S 2 3635 3636 // Field: [1] BKPT 3637 // 3638 // BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, 3639 // and also by normal code. Return PC points to breakpoint containing 3640 // instruction. 3641 // 3642 // 0x0: No BKPT instruction execution 3643 // 0x1: BKPT instruction execution 3644 #define CPU_SCS_DFSR_BKPT 0x00000002 3645 #define CPU_SCS_DFSR_BKPT_BITN 1 3646 #define CPU_SCS_DFSR_BKPT_M 0x00000002 3647 #define CPU_SCS_DFSR_BKPT_S 1 3648 3649 // Field: [0] HALTED 3650 // 3651 // Halt request flag. The processor is halted on the next instruction. 3652 // 3653 // 0x0: No halt request 3654 // 0x1: Halt requested by NVIC, including step 3655 #define CPU_SCS_DFSR_HALTED 0x00000001 3656 #define CPU_SCS_DFSR_HALTED_BITN 0 3657 #define CPU_SCS_DFSR_HALTED_M 0x00000001 3658 #define CPU_SCS_DFSR_HALTED_S 0 3659 3660 //***************************************************************************** 3661 // 3662 // Register: CPU_SCS_O_MMFAR 3663 // 3664 //***************************************************************************** 3665 // Field: [31:0] ADDRESS 3666 // 3667 // Mem Manage fault address field. 3668 // This field is the data address of a faulted load or store attempt. When an 3669 // unaligned access faults, the address is the actual address that faulted. 3670 // Because an access can be split into multiple parts, each aligned, this 3671 // address can be any offset in the range of the requested size. Flags 3672 // CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination 3673 // with CFSR.MMARVALIDindicate the cause of the fault. 3674 #define CPU_SCS_MMFAR_ADDRESS_W 32 3675 #define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF 3676 #define CPU_SCS_MMFAR_ADDRESS_S 0 3677 3678 //***************************************************************************** 3679 // 3680 // Register: CPU_SCS_O_BFAR 3681 // 3682 //***************************************************************************** 3683 // Field: [31:0] ADDRESS 3684 // 3685 // Bus fault address field. This field is the data address of a faulted load or 3686 // store attempt. When an unaligned access faults, the address is the address 3687 // requested by the instruction, even if that is not the address that faulted. 3688 // Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and 3689 // CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the 3690 // fault. 3691 #define CPU_SCS_BFAR_ADDRESS_W 32 3692 #define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF 3693 #define CPU_SCS_BFAR_ADDRESS_S 0 3694 3695 //***************************************************************************** 3696 // 3697 // Register: CPU_SCS_O_AFSR 3698 // 3699 //***************************************************************************** 3700 // Field: [31:0] IMPDEF 3701 // 3702 // Implementation defined. The bits map directly onto the signal assignment to 3703 // the auxiliary fault inputs. Tied to 0 3704 #define CPU_SCS_AFSR_IMPDEF_W 32 3705 #define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF 3706 #define CPU_SCS_AFSR_IMPDEF_S 0 3707 3708 //***************************************************************************** 3709 // 3710 // Register: CPU_SCS_O_ID_PFR0 3711 // 3712 //***************************************************************************** 3713 // Field: [7:4] STATE1 3714 // 3715 // State1 (T-bit == 1) 3716 // 3717 // 0x0: N/A 3718 // 0x1: N/A 3719 // 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit 3720 // Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit 3721 // instructions can be added using the appropriate instruction attribute, but 3722 // other 32-bit basic instructions cannot.) 3723 // 0x3: Thumb-2 encoding with all Thumb-2 basic instructions 3724 #define CPU_SCS_ID_PFR0_STATE1_W 4 3725 #define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 3726 #define CPU_SCS_ID_PFR0_STATE1_S 4 3727 3728 // Field: [3:0] STATE0 3729 // 3730 // State0 (T-bit == 0) 3731 // 3732 // 0x0: No ARM encoding 3733 // 0x1: N/A 3734 #define CPU_SCS_ID_PFR0_STATE0_W 4 3735 #define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F 3736 #define CPU_SCS_ID_PFR0_STATE0_S 0 3737 3738 //***************************************************************************** 3739 // 3740 // Register: CPU_SCS_O_ID_PFR1 3741 // 3742 //***************************************************************************** 3743 // Field: [11:8] MICROCONTROLLER_PROGRAMMERS_MODEL 3744 // 3745 // Microcontroller programmer's model 3746 // 3747 // 0x0: Not supported 3748 // 0x2: Two-stack support 3749 #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 3750 #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 3751 #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 3752 3753 //***************************************************************************** 3754 // 3755 // Register: CPU_SCS_O_ID_DFR0 3756 // 3757 //***************************************************************************** 3758 // Field: [23:20] MICROCONTROLLER_DEBUG_MODEL 3759 // 3760 // Microcontroller Debug Model - memory mapped 3761 // 3762 // 0x0: Not supported 3763 // 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) 3764 #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 3765 #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 3766 #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 3767 3768 //***************************************************************************** 3769 // 3770 // Register: CPU_SCS_O_ID_AFR0 3771 // 3772 //***************************************************************************** 3773 //***************************************************************************** 3774 // 3775 // Register: CPU_SCS_O_ID_MMFR0 3776 // 3777 //***************************************************************************** 3778 //***************************************************************************** 3779 // 3780 // Register: CPU_SCS_O_ID_MMFR1 3781 // 3782 //***************************************************************************** 3783 //***************************************************************************** 3784 // 3785 // Register: CPU_SCS_O_ID_MMFR2 3786 // 3787 //***************************************************************************** 3788 // Field: [24] WAIT_FOR_INTERRUPT_STALLING 3789 // 3790 // wait for interrupt stalling 3791 // 3792 // 0x0: Not supported 3793 // 0x1: Wait for interrupt supported 3794 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 3795 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 3796 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 3797 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 3798 3799 //***************************************************************************** 3800 // 3801 // Register: CPU_SCS_O_ID_MMFR3 3802 // 3803 //***************************************************************************** 3804 //***************************************************************************** 3805 // 3806 // Register: CPU_SCS_O_ID_ISAR0 3807 // 3808 //***************************************************************************** 3809 //***************************************************************************** 3810 // 3811 // Register: CPU_SCS_O_ID_ISAR1 3812 // 3813 //***************************************************************************** 3814 //***************************************************************************** 3815 // 3816 // Register: CPU_SCS_O_ID_ISAR2 3817 // 3818 //***************************************************************************** 3819 //***************************************************************************** 3820 // 3821 // Register: CPU_SCS_O_ID_ISAR3 3822 // 3823 //***************************************************************************** 3824 //***************************************************************************** 3825 // 3826 // Register: CPU_SCS_O_ID_ISAR4 3827 // 3828 //***************************************************************************** 3829 //***************************************************************************** 3830 // 3831 // Register: CPU_SCS_O_CPACR 3832 // 3833 //***************************************************************************** 3834 //***************************************************************************** 3835 // 3836 // Register: CPU_SCS_O_MPU_TYPE 3837 // 3838 //***************************************************************************** 3839 // Field: [23:16] IREGION 3840 // 3841 // The processor core uses only a unified MPU, this field always reads 0x0. 3842 #define CPU_SCS_MPU_TYPE_IREGION_W 8 3843 #define CPU_SCS_MPU_TYPE_IREGION_M 0x00FF0000 3844 #define CPU_SCS_MPU_TYPE_IREGION_S 16 3845 3846 // Field: [15:8] DREGION 3847 // 3848 // Number of supported MPU regions field. This field reads 0x08 indicating 3849 // eight MPU regions. 3850 #define CPU_SCS_MPU_TYPE_DREGION_W 8 3851 #define CPU_SCS_MPU_TYPE_DREGION_M 0x0000FF00 3852 #define CPU_SCS_MPU_TYPE_DREGION_S 8 3853 3854 // Field: [0] SEPARATE 3855 // 3856 // The processor core uses only a unified MPU, thus this field is always 0. 3857 #define CPU_SCS_MPU_TYPE_SEPARATE 0x00000001 3858 #define CPU_SCS_MPU_TYPE_SEPARATE_BITN 0 3859 #define CPU_SCS_MPU_TYPE_SEPARATE_M 0x00000001 3860 #define CPU_SCS_MPU_TYPE_SEPARATE_S 0 3861 3862 //***************************************************************************** 3863 // 3864 // Register: CPU_SCS_O_MPU_CTRL 3865 // 3866 //***************************************************************************** 3867 // Field: [2] PRIVDEFENA 3868 // 3869 // This bit enables the default memory map for privileged access, as a 3870 // background region, when the MPU is enabled. The background region acts as if 3871 // it was region number 1 before any settable regions. Any region that is set 3872 // up overlays this default map, and overrides it. If this bit is not set, the 3873 // default memory map is disabled, and memory not covered by a region faults. 3874 // This applies to memory type, Execute Never (XN), cache and shareable rules. 3875 // However, this only applies to privileged mode (fetch and data access). User 3876 // mode code faults unless a region has been set up for its code and data. When 3877 // the MPU is disabled, the default map acts on both privileged and user mode 3878 // code. XN and SO rules always apply to the system partition whether this 3879 // enable is set or not. If the MPU is disabled, this bit is ignored. 3880 #define CPU_SCS_MPU_CTRL_PRIVDEFENA 0x00000004 3881 #define CPU_SCS_MPU_CTRL_PRIVDEFENA_BITN 2 3882 #define CPU_SCS_MPU_CTRL_PRIVDEFENA_M 0x00000004 3883 #define CPU_SCS_MPU_CTRL_PRIVDEFENA_S 2 3884 3885 // Field: [1] HFNMIENA 3886 // 3887 // This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated 3888 // handlers. If this bit and ENABLE are set, the MPU is enabled when in these 3889 // handlers. If this bit is not set, the MPU is disabled when in these 3890 // handlers, regardless of the value of ENABLE bit. If this bit is set and 3891 // ENABLE is not set, behavior is unpredictable. 3892 #define CPU_SCS_MPU_CTRL_HFNMIENA 0x00000002 3893 #define CPU_SCS_MPU_CTRL_HFNMIENA_BITN 1 3894 #define CPU_SCS_MPU_CTRL_HFNMIENA_M 0x00000002 3895 #define CPU_SCS_MPU_CTRL_HFNMIENA_S 1 3896 3897 // Field: [0] ENABLE 3898 // 3899 // Enable MPU 3900 // 3901 // 0: MPU disabled 3902 // 1: MPU enabled 3903 #define CPU_SCS_MPU_CTRL_ENABLE 0x00000001 3904 #define CPU_SCS_MPU_CTRL_ENABLE_BITN 0 3905 #define CPU_SCS_MPU_CTRL_ENABLE_M 0x00000001 3906 #define CPU_SCS_MPU_CTRL_ENABLE_S 0 3907 3908 //***************************************************************************** 3909 // 3910 // Register: CPU_SCS_O_MPU_RNR 3911 // 3912 //***************************************************************************** 3913 // Field: [7:0] REGION 3914 // 3915 // Region select field. 3916 // This field selects the region to operate on when using the MPU_RASR and 3917 // MPU_RBAR. It must be written first except when the address MPU_RBAR.VALID 3918 // and MPU_RBAR.REGION fields are written, which overwrites this. 3919 #define CPU_SCS_MPU_RNR_REGION_W 8 3920 #define CPU_SCS_MPU_RNR_REGION_M 0x000000FF 3921 #define CPU_SCS_MPU_RNR_REGION_S 0 3922 3923 //***************************************************************************** 3924 // 3925 // Register: CPU_SCS_O_MPU_RBAR 3926 // 3927 //***************************************************************************** 3928 // Field: [31:5] ADDR 3929 // 3930 // Region base address field. 3931 // The position of the LSB depends on the region size, so that the base address 3932 // is aligned according to an even multiple of size. The power of 2 size 3933 // specified by the SZENABLE field of the MPU Region Attribute and Size 3934 // Register defines how many bits of base address are used. 3935 #define CPU_SCS_MPU_RBAR_ADDR_W 27 3936 #define CPU_SCS_MPU_RBAR_ADDR_M 0xFFFFFFE0 3937 #define CPU_SCS_MPU_RBAR_ADDR_S 5 3938 3939 // Field: [4] VALID 3940 // 3941 // MPU region number valid: 3942 // 0: MPU_RNR remains unchanged and is interpreted. 3943 // 1: MPU_RNR is overwritten by REGION. 3944 #define CPU_SCS_MPU_RBAR_VALID 0x00000010 3945 #define CPU_SCS_MPU_RBAR_VALID_BITN 4 3946 #define CPU_SCS_MPU_RBAR_VALID_M 0x00000010 3947 #define CPU_SCS_MPU_RBAR_VALID_S 4 3948 3949 // Field: [3:0] REGION 3950 // 3951 // MPU region override field 3952 #define CPU_SCS_MPU_RBAR_REGION_W 4 3953 #define CPU_SCS_MPU_RBAR_REGION_M 0x0000000F 3954 #define CPU_SCS_MPU_RBAR_REGION_S 0 3955 3956 //***************************************************************************** 3957 // 3958 // Register: CPU_SCS_O_MPU_RASR 3959 // 3960 //***************************************************************************** 3961 // Field: [28] XN 3962 // 3963 // Instruction access disable: 3964 // 0: Enable instruction fetches 3965 // 1: Disable instruction fetches 3966 #define CPU_SCS_MPU_RASR_XN 0x10000000 3967 #define CPU_SCS_MPU_RASR_XN_BITN 28 3968 #define CPU_SCS_MPU_RASR_XN_M 0x10000000 3969 #define CPU_SCS_MPU_RASR_XN_S 28 3970 3971 // Field: [26:24] AP 3972 // 3973 // Data access permission: 3974 // 0x0: Priviliged permissions: No access. User permissions: No access. 3975 // 0x1: Priviliged permissions: Read-write. User permissions: No access. 3976 // 0x2: Priviliged permissions: Read-write. User permissions: Read-only. 3977 // 0x3: Priviliged permissions: Read-write. User permissions: Read-write. 3978 // 0x4: Reserved 3979 // 0x5: Priviliged permissions: Read-only. User permissions: No access. 3980 // 0x6: Priviliged permissions: Read-only. User permissions: Read-only. 3981 // 0x7: Priviliged permissions: Read-only. User permissions: Read-only. 3982 #define CPU_SCS_MPU_RASR_AP_W 3 3983 #define CPU_SCS_MPU_RASR_AP_M 0x07000000 3984 #define CPU_SCS_MPU_RASR_AP_S 24 3985 3986 // Field: [21:19] TEX 3987 // 3988 // Type extension 3989 #define CPU_SCS_MPU_RASR_TEX_W 3 3990 #define CPU_SCS_MPU_RASR_TEX_M 0x00380000 3991 #define CPU_SCS_MPU_RASR_TEX_S 19 3992 3993 // Field: [18] S 3994 // 3995 // Shareable bit: 3996 // 0: Not shareable 3997 // 1: Shareable 3998 #define CPU_SCS_MPU_RASR_S 0x00040000 3999 #define CPU_SCS_MPU_RASR_S_BITN 18 4000 #define CPU_SCS_MPU_RASR_S_M 0x00040000 4001 #define CPU_SCS_MPU_RASR_S_S 18 4002 4003 // Field: [17] C 4004 // 4005 // Cacheable bit: 4006 // 0: Not cacheable 4007 // 1: Cacheable 4008 #define CPU_SCS_MPU_RASR_C 0x00020000 4009 #define CPU_SCS_MPU_RASR_C_BITN 17 4010 #define CPU_SCS_MPU_RASR_C_M 0x00020000 4011 #define CPU_SCS_MPU_RASR_C_S 17 4012 4013 // Field: [16] B 4014 // 4015 // Bufferable bit: 4016 // 0: Not bufferable 4017 // 1: Bufferable 4018 #define CPU_SCS_MPU_RASR_B 0x00010000 4019 #define CPU_SCS_MPU_RASR_B_BITN 16 4020 #define CPU_SCS_MPU_RASR_B_M 0x00010000 4021 #define CPU_SCS_MPU_RASR_B_S 16 4022 4023 // Field: [15:8] SRD 4024 // 4025 // Sub-Region Disable field: 4026 // Setting a bit in this field disables the corresponding sub-region. Regions 4027 // are split into eight equal-sized sub-regions. Sub-regions are not supported 4028 // for region sizes of 128 bytes and less. 4029 #define CPU_SCS_MPU_RASR_SRD_W 8 4030 #define CPU_SCS_MPU_RASR_SRD_M 0x0000FF00 4031 #define CPU_SCS_MPU_RASR_SRD_S 8 4032 4033 // Field: [5:1] SIZE 4034 // 4035 // MPU Protection Region Size Field: 4036 // 0x04: 32B 4037 // 0x05: 64B 4038 // 0x06: 128B 4039 // 0x07: 256B 4040 // 0x08: 512B 4041 // 0x09: 1KB 4042 // 0x0A: 2KB 4043 // 0x0B: 4KB 4044 // 0x0C: 8KB 4045 // 0x0D: 16KB 4046 // 0x0E: 32KB 4047 // 0x0F: 64KB 4048 // 0x10: 128KB 4049 // 0x11: 256KB 4050 // 0x12: 512KB 4051 // 0x13: 1MB 4052 // 0x14: 2MB 4053 // 0x15: 4MB 4054 // 0x16: 8MB 4055 // 0x17: 16MB 4056 // 0x18: 32MB 4057 // 0x19: 64MB 4058 // 0x1A: 128MB 4059 // 0x1B: 256MB 4060 // 0x1C: 512MB 4061 // 0x1D: 1GB 4062 // 0x1E: 2GB 4063 // 0x1F: 4GB 4064 #define CPU_SCS_MPU_RASR_SIZE_W 5 4065 #define CPU_SCS_MPU_RASR_SIZE_M 0x0000003E 4066 #define CPU_SCS_MPU_RASR_SIZE_S 1 4067 4068 // Field: [0] ENABLE 4069 // 4070 // Region enable bit: 4071 // 0: Disable region 4072 // 1: Enable region 4073 #define CPU_SCS_MPU_RASR_ENABLE 0x00000001 4074 #define CPU_SCS_MPU_RASR_ENABLE_BITN 0 4075 #define CPU_SCS_MPU_RASR_ENABLE_M 0x00000001 4076 #define CPU_SCS_MPU_RASR_ENABLE_S 0 4077 4078 //***************************************************************************** 4079 // 4080 // Register: CPU_SCS_O_MPU_RBAR_A1 4081 // 4082 //***************************************************************************** 4083 // Field: [31:0] MPU_RBAR_A1 4084 // 4085 // Alias for MPU_RBAR 4086 #define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_W 32 4087 #define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_M 0xFFFFFFFF 4088 #define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_S 0 4089 4090 //***************************************************************************** 4091 // 4092 // Register: CPU_SCS_O_MPU_RASR_A1 4093 // 4094 //***************************************************************************** 4095 // Field: [31:0] MPU_RASR_A1 4096 // 4097 // Alias for MPU_RASR 4098 #define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_W 32 4099 #define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_M 0xFFFFFFFF 4100 #define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_S 0 4101 4102 //***************************************************************************** 4103 // 4104 // Register: CPU_SCS_O_MPU_RBAR_A2 4105 // 4106 //***************************************************************************** 4107 // Field: [31:0] MPU_RBAR_A2 4108 // 4109 // Alias for MPU_RBAR 4110 #define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_W 32 4111 #define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_M 0xFFFFFFFF 4112 #define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_S 0 4113 4114 //***************************************************************************** 4115 // 4116 // Register: CPU_SCS_O_MPU_RASR_A2 4117 // 4118 //***************************************************************************** 4119 // Field: [31:0] MPU_RASR_A2 4120 // 4121 // Alias for MPU_RASR 4122 #define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_W 32 4123 #define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_M 0xFFFFFFFF 4124 #define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_S 0 4125 4126 //***************************************************************************** 4127 // 4128 // Register: CPU_SCS_O_MPU_RBAR_A3 4129 // 4130 //***************************************************************************** 4131 // Field: [31:0] MPU_RBAR_A3 4132 // 4133 // Alias for MPU_RBAR 4134 #define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_W 32 4135 #define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_M 0xFFFFFFFF 4136 #define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_S 0 4137 4138 //***************************************************************************** 4139 // 4140 // Register: CPU_SCS_O_MPU_RASR_A3 4141 // 4142 //***************************************************************************** 4143 // Field: [31:0] MPU_RASR_A3 4144 // 4145 // Alias for MPU_RASR 4146 #define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_W 32 4147 #define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_M 0xFFFFFFFF 4148 #define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_S 0 4149 4150 //***************************************************************************** 4151 // 4152 // Register: CPU_SCS_O_DHCSR 4153 // 4154 //***************************************************************************** 4155 // Field: [25] S_RESET_ST 4156 // 4157 // Indicates that the core has been reset, or is now being reset, since the 4158 // last time this bit was read. This a sticky bit that clears on read. So, 4159 // reading twice and getting 1 then 0 means it was reset in the past. Reading 4160 // twice and getting 1 both times means that it is being reset now (held in 4161 // reset still). 4162 // When writing to this register, 0 must be written this bit-field, otherwise 4163 // the write operation is ignored and no bits are written into the register. 4164 #define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 4165 #define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 4166 #define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 4167 #define CPU_SCS_DHCSR_S_RESET_ST_S 25 4168 4169 // Field: [24] S_RETIRE_ST 4170 // 4171 // Indicates that an instruction has completed since last read. This is a 4172 // sticky bit that clears on read. This determines if the core is stalled on a 4173 // load/store or fetch. 4174 // When writing to this register, 0 must be written this bit-field, otherwise 4175 // the write operation is ignored and no bits are written into the register. 4176 #define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 4177 #define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 4178 #define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 4179 #define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 4180 4181 // Field: [19] S_LOCKUP 4182 // 4183 // Reads as one if the core is running (not halted) and a lockup condition is 4184 // present. 4185 // When writing to this register, 1 must be written this bit-field, otherwise 4186 // the write operation is ignored and no bits are written into the register. 4187 #define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 4188 #define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 4189 #define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 4190 #define CPU_SCS_DHCSR_S_LOCKUP_S 19 4191 4192 // Field: [18] S_SLEEP 4193 // 4194 // Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must 4195 // use C_HALT to gain control or wait for interrupt to wake-up. 4196 // When writing to this register, 1 must be written this bit-field, otherwise 4197 // the write operation is ignored and no bits are written into the register. 4198 #define CPU_SCS_DHCSR_S_SLEEP 0x00040000 4199 #define CPU_SCS_DHCSR_S_SLEEP_BITN 18 4200 #define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 4201 #define CPU_SCS_DHCSR_S_SLEEP_S 18 4202 4203 // Field: [17] S_HALT 4204 // 4205 // The core is in debug state when this bit is set. 4206 // When writing to this register, 1 must be written this bit-field, otherwise 4207 // the write operation is ignored and no bits are written into the register. 4208 #define CPU_SCS_DHCSR_S_HALT 0x00020000 4209 #define CPU_SCS_DHCSR_S_HALT_BITN 17 4210 #define CPU_SCS_DHCSR_S_HALT_M 0x00020000 4211 #define CPU_SCS_DHCSR_S_HALT_S 17 4212 4213 // Field: [16] S_REGRDY 4214 // 4215 // Register Read/Write on the Debug Core Register Selector register is 4216 // available. Last transfer is complete. 4217 // When writing to this register, 1 must be written this bit-field, otherwise 4218 // the write operation is ignored and no bits are written into the register. 4219 #define CPU_SCS_DHCSR_S_REGRDY 0x00010000 4220 #define CPU_SCS_DHCSR_S_REGRDY_BITN 16 4221 #define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 4222 #define CPU_SCS_DHCSR_S_REGRDY_S 16 4223 4224 // Field: [5] C_SNAPSTALL 4225 // 4226 // If the core is stalled on a load/store operation the stall ceases and the 4227 // instruction is forced to complete. This enables Halting debug to gain 4228 // control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. 4229 // The core reads S_RETIRE_ST as 0. This indicates that no instruction has 4230 // advanced. This prevents misuse. The bus state is Unpredictable when this is 4231 // used. S_RETIRE_ST can detect core stalls on load/store operations. 4232 #define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 4233 #define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 4234 #define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 4235 #define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 4236 4237 // Field: [3] C_MASKINTS 4238 // 4239 // Mask interrupts when stepping or running in halted debug. This masking does 4240 // not affect NMI, fault exceptions and SVC caused by execution of the 4241 // instructions. This bit must only be modified when the processor is halted 4242 // (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released 4243 // (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must 4244 // be separate). Modifying C_MASKINTS while the system is running with halting 4245 // debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable 4246 // behavior. 4247 #define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 4248 #define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 4249 #define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 4250 #define CPU_SCS_DHCSR_C_MASKINTS_S 3 4251 4252 // Field: [2] C_STEP 4253 // 4254 // Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. 4255 // Must only be modified when the processor is halted (S_HALT == 1). 4256 // Modifying C_STEP while the system is running with halting debug support 4257 // enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. 4258 #define CPU_SCS_DHCSR_C_STEP 0x00000004 4259 #define CPU_SCS_DHCSR_C_STEP_BITN 2 4260 #define CPU_SCS_DHCSR_C_STEP_M 0x00000004 4261 #define CPU_SCS_DHCSR_C_STEP_S 2 4262 4263 // Field: [1] C_HALT 4264 // 4265 // Halts the core. This bit is set automatically when the core Halts. For 4266 // example Breakpoint. This bit clears on core reset. 4267 #define CPU_SCS_DHCSR_C_HALT 0x00000002 4268 #define CPU_SCS_DHCSR_C_HALT_BITN 1 4269 #define CPU_SCS_DHCSR_C_HALT_M 0x00000002 4270 #define CPU_SCS_DHCSR_C_HALT_S 1 4271 4272 // Field: [0] C_DEBUGEN 4273 // 4274 // Enables debug. This can only be written by AHB-AP and not by the core. It is 4275 // ignored when written by the core, which cannot set or clear it. The core 4276 // must write a 1 to it when writing C_HALT to halt itself. 4277 // The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when 4278 // C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will 4279 // be unknown to software when C_DEBUGEN = 0. 4280 #define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 4281 #define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 4282 #define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 4283 #define CPU_SCS_DHCSR_C_DEBUGEN_S 0 4284 4285 //***************************************************************************** 4286 // 4287 // Register: CPU_SCS_O_DCRSR 4288 // 4289 //***************************************************************************** 4290 // Field: [16] REGWNR 4291 // 4292 // 1: Write 4293 // 0: Read 4294 #define CPU_SCS_DCRSR_REGWNR 0x00010000 4295 #define CPU_SCS_DCRSR_REGWNR_BITN 16 4296 #define CPU_SCS_DCRSR_REGWNR_M 0x00010000 4297 #define CPU_SCS_DCRSR_REGWNR_S 16 4298 4299 // Field: [4:0] REGSEL 4300 // 4301 // Register select 4302 // 4303 // 0x00: R0 4304 // 0x01: R1 4305 // 0x02: R2 4306 // 0x03: R3 4307 // 0x04: R4 4308 // 0x05: R5 4309 // 0x06: R6 4310 // 0x07: R7 4311 // 0x08: R8 4312 // 0x09: R9 4313 // 0x0A: R10 4314 // 0x0B: R11 4315 // 0x0C: R12 4316 // 0x0D: Current SP 4317 // 0x0E: LR 4318 // 0x0F: DebugReturnAddress 4319 // 0x10: XPSR/flags, execution state information, and exception number 4320 // 0x11: MSP (Main SP) 4321 // 0x12: PSP (Process SP) 4322 // 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK 4323 #define CPU_SCS_DCRSR_REGSEL_W 5 4324 #define CPU_SCS_DCRSR_REGSEL_M 0x0000001F 4325 #define CPU_SCS_DCRSR_REGSEL_S 0 4326 4327 //***************************************************************************** 4328 // 4329 // Register: CPU_SCS_O_DCRDR 4330 // 4331 //***************************************************************************** 4332 // Field: [31:0] DCRDR 4333 // 4334 // This register holds data for reading and writing registers to and from the 4335 // processor. This is the data value written to the register selected by DCRSR. 4336 // When the processor receives a request from DCRSR, this register is read or 4337 // written by the processor using a normal load-store unit operation. If core 4338 // register transfers are not being performed, software-based debug monitors 4339 // can use this register for communication in non-halting debug. This enables 4340 // flags and bits to acknowledge state and indicate if commands have been 4341 // accepted to, replied to, or accepted and replied to. 4342 #define CPU_SCS_DCRDR_DCRDR_W 32 4343 #define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF 4344 #define CPU_SCS_DCRDR_DCRDR_S 0 4345 4346 //***************************************************************************** 4347 // 4348 // Register: CPU_SCS_O_DEMCR 4349 // 4350 //***************************************************************************** 4351 // Field: [24] TRCENA 4352 // 4353 // This bit must be set to 1 to enable use of the trace and debug blocks: DWT, 4354 // ITM, ETM and TPIU. This enables control of power usage unless tracing is 4355 // required. The application can enable this, for ITM use, or use by a 4356 // debugger. 4357 #define CPU_SCS_DEMCR_TRCENA 0x01000000 4358 #define CPU_SCS_DEMCR_TRCENA_BITN 24 4359 #define CPU_SCS_DEMCR_TRCENA_M 0x01000000 4360 #define CPU_SCS_DEMCR_TRCENA_S 24 4361 4362 // Field: [19] MON_REQ 4363 // 4364 // This enables the monitor to identify how it wakes up. This bit clears on a 4365 // Core Reset. 4366 // 4367 // 0x0: Woken up by debug exception. 4368 // 0x1: Woken up by MON_PEND 4369 #define CPU_SCS_DEMCR_MON_REQ 0x00080000 4370 #define CPU_SCS_DEMCR_MON_REQ_BITN 19 4371 #define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 4372 #define CPU_SCS_DEMCR_MON_REQ_S 19 4373 4374 // Field: [18] MON_STEP 4375 // 4376 // When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. 4377 // This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped 4378 // according to the priority of the monitor and settings of PRIMASK, FAULTMASK, 4379 // or BASEPRI. 4380 #define CPU_SCS_DEMCR_MON_STEP 0x00040000 4381 #define CPU_SCS_DEMCR_MON_STEP_BITN 18 4382 #define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 4383 #define CPU_SCS_DEMCR_MON_STEP_S 18 4384 4385 // Field: [17] MON_PEND 4386 // 4387 // Pend the monitor to activate when priority permits. This can wake up the 4388 // monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for 4389 // Monitor debug. This register does not reset on a system reset. It is only 4390 // reset by a power-on reset. Software in the reset handler or later, or by the 4391 // DAP must enable the debug monitor. 4392 #define CPU_SCS_DEMCR_MON_PEND 0x00020000 4393 #define CPU_SCS_DEMCR_MON_PEND_BITN 17 4394 #define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 4395 #define CPU_SCS_DEMCR_MON_PEND_S 17 4396 4397 // Field: [16] MON_EN 4398 // 4399 // Enable the debug monitor. 4400 // When enabled, the System handler priority register controls its priority 4401 // level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN 4402 // overrides this bit. Vector catching is semi-synchronous. When a matching 4403 // event is seen, a Halt is requested. Because the processor can only halt on 4404 // an instruction boundary, it must wait until the next instruction boundary. 4405 // As a result, it stops on the first instruction of the exception handler. 4406 // However, two special cases exist when a vector catch has triggered: 1. If a 4407 // fault is taken during vectoring, vector read or stack push error, the halt 4408 // occurs on the corresponding fault handler, for the vector error or stack 4409 // push. 2. If a late arriving interrupt comes in during vectoring, it is not 4410 // taken. That is, an implementation that supports the late arrival 4411 // optimization must suppress it in this case. 4412 #define CPU_SCS_DEMCR_MON_EN 0x00010000 4413 #define CPU_SCS_DEMCR_MON_EN_BITN 16 4414 #define CPU_SCS_DEMCR_MON_EN_M 0x00010000 4415 #define CPU_SCS_DEMCR_MON_EN_S 16 4416 4417 // Field: [10] VC_HARDERR 4418 // 4419 // Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. 4420 #define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 4421 #define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 4422 #define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 4423 #define CPU_SCS_DEMCR_VC_HARDERR_S 10 4424 4425 // Field: [9] VC_INTERR 4426 // 4427 // Debug trap on a fault occurring during an exception entry or return 4428 // sequence. Ignored when DHCSR.C_DEBUGEN is cleared. 4429 #define CPU_SCS_DEMCR_VC_INTERR 0x00000200 4430 #define CPU_SCS_DEMCR_VC_INTERR_BITN 9 4431 #define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 4432 #define CPU_SCS_DEMCR_VC_INTERR_S 9 4433 4434 // Field: [8] VC_BUSERR 4435 // 4436 // Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. 4437 #define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 4438 #define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 4439 #define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 4440 #define CPU_SCS_DEMCR_VC_BUSERR_S 8 4441 4442 // Field: [7] VC_STATERR 4443 // 4444 // Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is 4445 // cleared. 4446 #define CPU_SCS_DEMCR_VC_STATERR 0x00000080 4447 #define CPU_SCS_DEMCR_VC_STATERR_BITN 7 4448 #define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 4449 #define CPU_SCS_DEMCR_VC_STATERR_S 7 4450 4451 // Field: [6] VC_CHKERR 4452 // 4453 // Debug trap on Usage Fault enabled checking errors. Ignored when 4454 // DHCSR.C_DEBUGEN is cleared. 4455 #define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 4456 #define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 4457 #define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 4458 #define CPU_SCS_DEMCR_VC_CHKERR_S 6 4459 4460 // Field: [5] VC_NOCPERR 4461 // 4462 // Debug trap on a UsageFault access to a Coprocessor. Ignored when 4463 // DHCSR.C_DEBUGEN is cleared. 4464 #define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 4465 #define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 4466 #define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 4467 #define CPU_SCS_DEMCR_VC_NOCPERR_S 5 4468 4469 // Field: [4] VC_MMERR 4470 // 4471 // Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is 4472 // cleared. 4473 #define CPU_SCS_DEMCR_VC_MMERR 0x00000010 4474 #define CPU_SCS_DEMCR_VC_MMERR_BITN 4 4475 #define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 4476 #define CPU_SCS_DEMCR_VC_MMERR_S 4 4477 4478 // Field: [0] VC_CORERESET 4479 // 4480 // Reset Vector Catch. Halt running system if Core reset occurs. Ignored when 4481 // DHCSR.C_DEBUGEN is cleared. 4482 #define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 4483 #define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 4484 #define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 4485 #define CPU_SCS_DEMCR_VC_CORERESET_S 0 4486 4487 //***************************************************************************** 4488 // 4489 // Register: CPU_SCS_O_STIR 4490 // 4491 //***************************************************************************** 4492 // Field: [8:0] INTID 4493 // 4494 // Interrupt ID field. Writing a value to this bit-field is the same as 4495 // manually pending an interrupt by setting the corresponding interrupt bit in 4496 // an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. 4497 #define CPU_SCS_STIR_INTID_W 9 4498 #define CPU_SCS_STIR_INTID_M 0x000001FF 4499 #define CPU_SCS_STIR_INTID_S 0 4500 4501 //***************************************************************************** 4502 // 4503 // Register: CPU_SCS_O_FPCCR 4504 // 4505 //***************************************************************************** 4506 // Field: [31] ASPEN 4507 // 4508 // Automatic State Preservation enable. 4509 // When this bit is set is will cause bit [2] of the Special CONTROL register 4510 // to be set (FPCA) on execution of a floating point instruction which results 4511 // in the floating point state automatically being preserved on exception 4512 // entry. 4513 #define CPU_SCS_FPCCR_ASPEN 0x80000000 4514 #define CPU_SCS_FPCCR_ASPEN_BITN 31 4515 #define CPU_SCS_FPCCR_ASPEN_M 0x80000000 4516 #define CPU_SCS_FPCCR_ASPEN_S 31 4517 4518 // Field: [30] LSPEN 4519 // 4520 // Lazy State Preservation enable. 4521 // Lazy state preservation is when the processor performs a context save, space 4522 // on the stack is reserved for the floating point state but it is not stacked 4523 // until the new context performs a floating point operation. 4524 // 0: Disable automatic lazy state preservation for floating-point context. 4525 // 1: Enable automatic lazy state preservation for floating-point context. 4526 #define CPU_SCS_FPCCR_LSPEN 0x40000000 4527 #define CPU_SCS_FPCCR_LSPEN_BITN 30 4528 #define CPU_SCS_FPCCR_LSPEN_M 0x40000000 4529 #define CPU_SCS_FPCCR_LSPEN_S 30 4530 4531 // Field: [8] MONRDY 4532 // 4533 // Indicates whether the the software executing when the processor allocated 4534 // the FP stack frame was able to set the DebugMonitor exception to pending. 4535 // 0: DebugMonitor is disabled or priority did not permit setting 4536 // DEMCR.MON_PEND when the floating-point stack frame was allocated. 4537 // 1: DebugMonitor is enabled and priority permits setting DEMCR.MON_PEND when 4538 // the floating-point stack frame was allocated. 4539 #define CPU_SCS_FPCCR_MONRDY 0x00000100 4540 #define CPU_SCS_FPCCR_MONRDY_BITN 8 4541 #define CPU_SCS_FPCCR_MONRDY_M 0x00000100 4542 #define CPU_SCS_FPCCR_MONRDY_S 8 4543 4544 // Field: [6] BFRDY 4545 // 4546 // Indicates whether the software executing when the processor allocated the FP 4547 // stack frame was able to set the BusFault exception to pending. 4548 // 0: BusFault is disabled or priority did not permit setting the BusFault 4549 // handler to the pending state when the floating-point stack frame was 4550 // allocated. 4551 // 1: BusFault is enabled and priority permitted setting the BusFault handler 4552 // to the pending state when the floating-point stack frame was allocated. 4553 #define CPU_SCS_FPCCR_BFRDY 0x00000040 4554 #define CPU_SCS_FPCCR_BFRDY_BITN 6 4555 #define CPU_SCS_FPCCR_BFRDY_M 0x00000040 4556 #define CPU_SCS_FPCCR_BFRDY_S 6 4557 4558 // Field: [5] MMRDY 4559 // 4560 // Indicates whether the software executing when the processor allocated the FP 4561 // stack frame was able to set the MemManage exception to pending. 4562 // 0: MemManage is disabled or priority did not permit setting the MemManage 4563 // handler to the pending state when the floating-point stack frame was 4564 // allocated. 4565 // 1: MemManage is enabled and priority permitted setting the MemManage handler 4566 // to the pending state when the floating-point stack frame was allocated. 4567 #define CPU_SCS_FPCCR_MMRDY 0x00000020 4568 #define CPU_SCS_FPCCR_MMRDY_BITN 5 4569 #define CPU_SCS_FPCCR_MMRDY_M 0x00000020 4570 #define CPU_SCS_FPCCR_MMRDY_S 5 4571 4572 // Field: [4] HFRDY 4573 // 4574 // Indicates whether the software executing when the processor allocated the FP 4575 // stack frame was able to set the HardFault exception to pending. 4576 // 0: Priority did not permit setting the HardFault handler to the pending 4577 // state when the floating-point stack frame was allocated. 4578 // 1: Priority permitted setting the HardFault handler to the pending state 4579 // when the floating-point stack frame was allocated. 4580 #define CPU_SCS_FPCCR_HFRDY 0x00000010 4581 #define CPU_SCS_FPCCR_HFRDY_BITN 4 4582 #define CPU_SCS_FPCCR_HFRDY_M 0x00000010 4583 #define CPU_SCS_FPCCR_HFRDY_S 4 4584 4585 // Field: [3] THREAD 4586 // 4587 // Indicates the processor mode was Thread when it allocated the FP stack 4588 // frame. 4589 // 0: Mode was not Thread Mode when the floating-point stack frame was 4590 // allocated. 4591 // 1: Mode was Thread Mode when the floating-point stack frame was allocated. 4592 #define CPU_SCS_FPCCR_THREAD 0x00000008 4593 #define CPU_SCS_FPCCR_THREAD_BITN 3 4594 #define CPU_SCS_FPCCR_THREAD_M 0x00000008 4595 #define CPU_SCS_FPCCR_THREAD_S 3 4596 4597 // Field: [1] USER 4598 // 4599 // Indicates the privilege level of the software executing was User 4600 // (Unpriviledged) when the processor allocated the FP stack frame: 4601 // 0: Privilege level was not user when the floating-point stack frame was 4602 // allocated. 4603 // 1: Privilege level was user when the floating-point stack frame was 4604 // allocated. 4605 #define CPU_SCS_FPCCR_USER 0x00000002 4606 #define CPU_SCS_FPCCR_USER_BITN 1 4607 #define CPU_SCS_FPCCR_USER_M 0x00000002 4608 #define CPU_SCS_FPCCR_USER_S 1 4609 4610 // Field: [0] LSPACT 4611 // 4612 // Indicates whether Lazy preservation of the FP state is active: 4613 // 0: Lazy state preservation is not active. 4614 // 1: Lazy state preservation is active. floating-point stack frame has been 4615 // allocated but saving state to it has been deferred. 4616 #define CPU_SCS_FPCCR_LSPACT 0x00000001 4617 #define CPU_SCS_FPCCR_LSPACT_BITN 0 4618 #define CPU_SCS_FPCCR_LSPACT_M 0x00000001 4619 #define CPU_SCS_FPCCR_LSPACT_S 0 4620 4621 //***************************************************************************** 4622 // 4623 // Register: CPU_SCS_O_FPCAR 4624 // 4625 //***************************************************************************** 4626 // Field: [31:2] ADDRESS 4627 // 4628 // Holds the (double-word-aligned) location of the unpopulated floating-point 4629 // register space allocated on an exception stack frame. 4630 #define CPU_SCS_FPCAR_ADDRESS_W 30 4631 #define CPU_SCS_FPCAR_ADDRESS_M 0xFFFFFFFC 4632 #define CPU_SCS_FPCAR_ADDRESS_S 2 4633 4634 //***************************************************************************** 4635 // 4636 // Register: CPU_SCS_O_FPDSCR 4637 // 4638 //***************************************************************************** 4639 // Field: [26] AHP 4640 // 4641 // Default value for Alternative Half Precision bit. (If this bit is set to 1 4642 // then Alternative half-precision format is selected). 4643 #define CPU_SCS_FPDSCR_AHP 0x04000000 4644 #define CPU_SCS_FPDSCR_AHP_BITN 26 4645 #define CPU_SCS_FPDSCR_AHP_M 0x04000000 4646 #define CPU_SCS_FPDSCR_AHP_S 26 4647 4648 // Field: [25] DN 4649 // 4650 // Default value for Default NaN mode bit. (If this bit is set to 1 then any 4651 // operation involving one or more NaNs returns the Default NaN). 4652 #define CPU_SCS_FPDSCR_DN 0x02000000 4653 #define CPU_SCS_FPDSCR_DN_BITN 25 4654 #define CPU_SCS_FPDSCR_DN_M 0x02000000 4655 #define CPU_SCS_FPDSCR_DN_S 25 4656 4657 // Field: [24] FZ 4658 // 4659 // Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then 4660 // Flush-to-zero mode is enabled). 4661 #define CPU_SCS_FPDSCR_FZ 0x01000000 4662 #define CPU_SCS_FPDSCR_FZ_BITN 24 4663 #define CPU_SCS_FPDSCR_FZ_M 0x01000000 4664 #define CPU_SCS_FPDSCR_FZ_S 24 4665 4666 // Field: [23:22] RMODE 4667 // 4668 // Default value for Rounding Mode control field. (The encoding for this field 4669 // is: 4670 // 0b00 Round to Nearest (RN) mode 4671 // 0b01 Round towards Plus Infinity (RP) mode 4672 // 0b10 Round towards Minus Infinity (RM) mode 4673 // 0b11 Round towards Zero (RZ) mode. 4674 // The specified rounding mode is used by almost all floating-point 4675 // instructions). 4676 #define CPU_SCS_FPDSCR_RMODE_W 2 4677 #define CPU_SCS_FPDSCR_RMODE_M 0x00C00000 4678 #define CPU_SCS_FPDSCR_RMODE_S 22 4679 4680 //***************************************************************************** 4681 // 4682 // Register: CPU_SCS_O_MVFR0 4683 // 4684 //***************************************************************************** 4685 // Field: [31:28] FP_ROUNDING_MODES 4686 // 4687 // Indicates the rounding modes supported by the FP floating-point hardware. 4688 // The value of this field is: 0b0001 - all rounding modes supported. 4689 #define CPU_SCS_MVFR0_FP_ROUNDING_MODES_W 4 4690 #define CPU_SCS_MVFR0_FP_ROUNDING_MODES_M 0xF0000000 4691 #define CPU_SCS_MVFR0_FP_ROUNDING_MODES_S 28 4692 4693 // Field: [27:24] SHORT_VECTORS 4694 // 4695 // Indicates the hardware support for FP short vectors. The value of this field 4696 // is: 0b0000 - not supported. 4697 #define CPU_SCS_MVFR0_SHORT_VECTORS_W 4 4698 #define CPU_SCS_MVFR0_SHORT_VECTORS_M 0x0F000000 4699 #define CPU_SCS_MVFR0_SHORT_VECTORS_S 24 4700 4701 // Field: [23:20] SQUARE_ROOT 4702 // 4703 // Indicates the hardware support for FP square root operations. The value of 4704 // this field is: 0b0001 - supported. 4705 #define CPU_SCS_MVFR0_SQUARE_ROOT_W 4 4706 #define CPU_SCS_MVFR0_SQUARE_ROOT_M 0x00F00000 4707 #define CPU_SCS_MVFR0_SQUARE_ROOT_S 20 4708 4709 // Field: [19:16] DIVIDE 4710 // 4711 // Indicates the hardware support for FP divide operations. The value of this 4712 // field is: 0b0001 - supported. 4713 #define CPU_SCS_MVFR0_DIVIDE_W 4 4714 #define CPU_SCS_MVFR0_DIVIDE_M 0x000F0000 4715 #define CPU_SCS_MVFR0_DIVIDE_S 16 4716 4717 // Field: [15:12] FP_EXCEPTION_TRAPPING 4718 // 4719 // Indicates whether the FP hardware implementation supports exception 4720 // trapping. The value of this field is: 0b0000 - not supported. 4721 #define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_W 4 4722 #define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_M 0x0000F000 4723 #define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_S 12 4724 4725 // Field: [11:8] DOUBLE_PRECISION 4726 // 4727 // Indicates the hardware support for FP double-precision operations. The value 4728 // of this field is: 0b0000 - not supported. 4729 #define CPU_SCS_MVFR0_DOUBLE_PRECISION_W 4 4730 #define CPU_SCS_MVFR0_DOUBLE_PRECISION_M 0x00000F00 4731 #define CPU_SCS_MVFR0_DOUBLE_PRECISION_S 8 4732 4733 // Field: [7:4] SINGLE_PRECISION 4734 // 4735 // Indicates the hardware support for FP single-precision operations. The value 4736 // of this field is: 0b0010 - supported. 4737 #define CPU_SCS_MVFR0_SINGLE_PRECISION_W 4 4738 #define CPU_SCS_MVFR0_SINGLE_PRECISION_M 0x000000F0 4739 #define CPU_SCS_MVFR0_SINGLE_PRECISION_S 4 4740 4741 // Field: [3:0] A_SIMD 4742 // 4743 // Indicates the size of the FP register bank. The value of this field is: 4744 // 0b0001 - supported, 16 x 64-bit registers. 4745 #define CPU_SCS_MVFR0_A_SIMD_W 4 4746 #define CPU_SCS_MVFR0_A_SIMD_M 0x0000000F 4747 #define CPU_SCS_MVFR0_A_SIMD_S 0 4748 4749 //***************************************************************************** 4750 // 4751 // Register: CPU_SCS_O_MVFR1 4752 // 4753 //***************************************************************************** 4754 // Field: [31:28] FP_FUSED_MAC 4755 // 4756 // Indicates whether the FP supports fused multiply accumulate operations. The 4757 // value of this field is: 0b0001 - supported. 4758 #define CPU_SCS_MVFR1_FP_FUSED_MAC_W 4 4759 #define CPU_SCS_MVFR1_FP_FUSED_MAC_M 0xF0000000 4760 #define CPU_SCS_MVFR1_FP_FUSED_MAC_S 28 4761 4762 // Field: [27:24] FP_HPFP 4763 // 4764 // Indicates whether the FP supports half-precision floating-point conversion 4765 // operations. The value of this field is: 0b0001 - supported. 4766 #define CPU_SCS_MVFR1_FP_HPFP_W 4 4767 #define CPU_SCS_MVFR1_FP_HPFP_M 0x0F000000 4768 #define CPU_SCS_MVFR1_FP_HPFP_S 24 4769 4770 // Field: [7:4] D_NAN_MODE 4771 // 4772 // Indicates whether the FP hardware implementation supports only the Default 4773 // NaN mode. The value of this field is: 0b0001 - hardware supports propagation 4774 // of NaN values. 4775 #define CPU_SCS_MVFR1_D_NAN_MODE_W 4 4776 #define CPU_SCS_MVFR1_D_NAN_MODE_M 0x000000F0 4777 #define CPU_SCS_MVFR1_D_NAN_MODE_S 4 4778 4779 // Field: [3:0] FTZ_MODE 4780 // 4781 // Indicates whether the FP hardware implementation supports only the 4782 // Flush-to-Zero mode of operation. The value of this field is: 0b0001 - 4783 // hardware supports full denormalized number arithmetic. 4784 #define CPU_SCS_MVFR1_FTZ_MODE_W 4 4785 #define CPU_SCS_MVFR1_FTZ_MODE_M 0x0000000F 4786 #define CPU_SCS_MVFR1_FTZ_MODE_S 0 4787 4788 4789 #endif // __CPU_SCS__ 4790
