1 /****************************************************************************** 2 * Filename: hw_cpu_itm_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_CPU_ITM_H__ 38 #define __HW_CPU_ITM_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // CPU_ITM component 44 // 45 //***************************************************************************** 46 // Stimulus Port 0 47 #define CPU_ITM_O_STIM0 0x00000000 48 49 // Stimulus Port 1 50 #define CPU_ITM_O_STIM1 0x00000004 51 52 // Stimulus Port 2 53 #define CPU_ITM_O_STIM2 0x00000008 54 55 // Stimulus Port 3 56 #define CPU_ITM_O_STIM3 0x0000000C 57 58 // Stimulus Port 4 59 #define CPU_ITM_O_STIM4 0x00000010 60 61 // Stimulus Port 5 62 #define CPU_ITM_O_STIM5 0x00000014 63 64 // Stimulus Port 6 65 #define CPU_ITM_O_STIM6 0x00000018 66 67 // Stimulus Port 7 68 #define CPU_ITM_O_STIM7 0x0000001C 69 70 // Stimulus Port 8 71 #define CPU_ITM_O_STIM8 0x00000020 72 73 // Stimulus Port 9 74 #define CPU_ITM_O_STIM9 0x00000024 75 76 // Stimulus Port 10 77 #define CPU_ITM_O_STIM10 0x00000028 78 79 // Stimulus Port 11 80 #define CPU_ITM_O_STIM11 0x0000002C 81 82 // Stimulus Port 12 83 #define CPU_ITM_O_STIM12 0x00000030 84 85 // Stimulus Port 13 86 #define CPU_ITM_O_STIM13 0x00000034 87 88 // Stimulus Port 14 89 #define CPU_ITM_O_STIM14 0x00000038 90 91 // Stimulus Port 15 92 #define CPU_ITM_O_STIM15 0x0000003C 93 94 // Stimulus Port 16 95 #define CPU_ITM_O_STIM16 0x00000040 96 97 // Stimulus Port 17 98 #define CPU_ITM_O_STIM17 0x00000044 99 100 // Stimulus Port 18 101 #define CPU_ITM_O_STIM18 0x00000048 102 103 // Stimulus Port 19 104 #define CPU_ITM_O_STIM19 0x0000004C 105 106 // Stimulus Port 20 107 #define CPU_ITM_O_STIM20 0x00000050 108 109 // Stimulus Port 21 110 #define CPU_ITM_O_STIM21 0x00000054 111 112 // Stimulus Port 22 113 #define CPU_ITM_O_STIM22 0x00000058 114 115 // Stimulus Port 23 116 #define CPU_ITM_O_STIM23 0x0000005C 117 118 // Stimulus Port 24 119 #define CPU_ITM_O_STIM24 0x00000060 120 121 // Stimulus Port 25 122 #define CPU_ITM_O_STIM25 0x00000064 123 124 // Stimulus Port 26 125 #define CPU_ITM_O_STIM26 0x00000068 126 127 // Stimulus Port 27 128 #define CPU_ITM_O_STIM27 0x0000006C 129 130 // Stimulus Port 28 131 #define CPU_ITM_O_STIM28 0x00000070 132 133 // Stimulus Port 29 134 #define CPU_ITM_O_STIM29 0x00000074 135 136 // Stimulus Port 30 137 #define CPU_ITM_O_STIM30 0x00000078 138 139 // Stimulus Port 31 140 #define CPU_ITM_O_STIM31 0x0000007C 141 142 // Trace Enable 143 #define CPU_ITM_O_TER 0x00000E00 144 145 // Trace Privilege 146 #define CPU_ITM_O_TPR 0x00000E40 147 148 // Trace Control 149 #define CPU_ITM_O_TCR 0x00000E80 150 151 // Lock Access 152 #define CPU_ITM_O_LAR 0x00000FB0 153 154 // Lock Status 155 #define CPU_ITM_O_LSR 0x00000FB4 156 157 //***************************************************************************** 158 // 159 // Register: CPU_ITM_O_STIM0 160 // 161 //***************************************************************************** 162 // Field: [31:0] STIM0 163 // 164 // A write to this location causes data to be written into the FIFO if 165 // TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status 166 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 167 // provide an atomic read-modify-write, so it's users responsibility to ensure 168 // exclusive read-modify-write if this ITM port is used concurrently by 169 // interrupts or other threads. 170 #define CPU_ITM_STIM0_STIM0_W 32 171 #define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF 172 #define CPU_ITM_STIM0_STIM0_S 0 173 174 //***************************************************************************** 175 // 176 // Register: CPU_ITM_O_STIM1 177 // 178 //***************************************************************************** 179 // Field: [31:0] STIM1 180 // 181 // A write to this location causes data to be written into the FIFO if 182 // TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status 183 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 184 // provide an atomic read-modify-write, so it's users responsibility to ensure 185 // exclusive read-modify-write if this ITM port is used concurrently by 186 // interrupts or other threads. 187 #define CPU_ITM_STIM1_STIM1_W 32 188 #define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF 189 #define CPU_ITM_STIM1_STIM1_S 0 190 191 //***************************************************************************** 192 // 193 // Register: CPU_ITM_O_STIM2 194 // 195 //***************************************************************************** 196 // Field: [31:0] STIM2 197 // 198 // A write to this location causes data to be written into the FIFO if 199 // TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status 200 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 201 // provide an atomic read-modify-write, so it's users responsibility to ensure 202 // exclusive read-modify-write if this ITM port is used concurrently by 203 // interrupts or other threads. 204 #define CPU_ITM_STIM2_STIM2_W 32 205 #define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF 206 #define CPU_ITM_STIM2_STIM2_S 0 207 208 //***************************************************************************** 209 // 210 // Register: CPU_ITM_O_STIM3 211 // 212 //***************************************************************************** 213 // Field: [31:0] STIM3 214 // 215 // A write to this location causes data to be written into the FIFO if 216 // TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status 217 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 218 // provide an atomic read-modify-write, so it's users responsibility to ensure 219 // exclusive read-modify-write if this ITM port is used concurrently by 220 // interrupts or other threads. 221 #define CPU_ITM_STIM3_STIM3_W 32 222 #define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF 223 #define CPU_ITM_STIM3_STIM3_S 0 224 225 //***************************************************************************** 226 // 227 // Register: CPU_ITM_O_STIM4 228 // 229 //***************************************************************************** 230 // Field: [31:0] STIM4 231 // 232 // A write to this location causes data to be written into the FIFO if 233 // TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status 234 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 235 // provide an atomic read-modify-write, so it's users responsibility to ensure 236 // exclusive read-modify-write if this ITM port is used concurrently by 237 // interrupts or other threads. 238 #define CPU_ITM_STIM4_STIM4_W 32 239 #define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF 240 #define CPU_ITM_STIM4_STIM4_S 0 241 242 //***************************************************************************** 243 // 244 // Register: CPU_ITM_O_STIM5 245 // 246 //***************************************************************************** 247 // Field: [31:0] STIM5 248 // 249 // A write to this location causes data to be written into the FIFO if 250 // TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status 251 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 252 // provide an atomic read-modify-write, so it's users responsibility to ensure 253 // exclusive read-modify-write if this ITM port is used concurrently by 254 // interrupts or other threads. 255 #define CPU_ITM_STIM5_STIM5_W 32 256 #define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF 257 #define CPU_ITM_STIM5_STIM5_S 0 258 259 //***************************************************************************** 260 // 261 // Register: CPU_ITM_O_STIM6 262 // 263 //***************************************************************************** 264 // Field: [31:0] STIM6 265 // 266 // A write to this location causes data to be written into the FIFO if 267 // TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status 268 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 269 // provide an atomic read-modify-write, so it's users responsibility to ensure 270 // exclusive read-modify-write if this ITM port is used concurrently by 271 // interrupts or other threads. 272 #define CPU_ITM_STIM6_STIM6_W 32 273 #define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF 274 #define CPU_ITM_STIM6_STIM6_S 0 275 276 //***************************************************************************** 277 // 278 // Register: CPU_ITM_O_STIM7 279 // 280 //***************************************************************************** 281 // Field: [31:0] STIM7 282 // 283 // A write to this location causes data to be written into the FIFO if 284 // TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status 285 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 286 // provide an atomic read-modify-write, so it's users responsibility to ensure 287 // exclusive read-modify-write if this ITM port is used concurrently by 288 // interrupts or other threads. 289 #define CPU_ITM_STIM7_STIM7_W 32 290 #define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF 291 #define CPU_ITM_STIM7_STIM7_S 0 292 293 //***************************************************************************** 294 // 295 // Register: CPU_ITM_O_STIM8 296 // 297 //***************************************************************************** 298 // Field: [31:0] STIM8 299 // 300 // A write to this location causes data to be written into the FIFO if 301 // TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status 302 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 303 // provide an atomic read-modify-write, so it's users responsibility to ensure 304 // exclusive read-modify-write if this ITM port is used concurrently by 305 // interrupts or other threads. 306 #define CPU_ITM_STIM8_STIM8_W 32 307 #define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF 308 #define CPU_ITM_STIM8_STIM8_S 0 309 310 //***************************************************************************** 311 // 312 // Register: CPU_ITM_O_STIM9 313 // 314 //***************************************************************************** 315 // Field: [31:0] STIM9 316 // 317 // A write to this location causes data to be written into the FIFO if 318 // TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status 319 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 320 // provide an atomic read-modify-write, so it's users responsibility to ensure 321 // exclusive read-modify-write if this ITM port is used concurrently by 322 // interrupts or other threads. 323 #define CPU_ITM_STIM9_STIM9_W 32 324 #define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF 325 #define CPU_ITM_STIM9_STIM9_S 0 326 327 //***************************************************************************** 328 // 329 // Register: CPU_ITM_O_STIM10 330 // 331 //***************************************************************************** 332 // Field: [31:0] STIM10 333 // 334 // A write to this location causes data to be written into the FIFO if 335 // TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status 336 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 337 // provide an atomic read-modify-write, so it's users responsibility to ensure 338 // exclusive read-modify-write if this ITM port is used concurrently by 339 // interrupts or other threads. 340 #define CPU_ITM_STIM10_STIM10_W 32 341 #define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF 342 #define CPU_ITM_STIM10_STIM10_S 0 343 344 //***************************************************************************** 345 // 346 // Register: CPU_ITM_O_STIM11 347 // 348 //***************************************************************************** 349 // Field: [31:0] STIM11 350 // 351 // A write to this location causes data to be written into the FIFO if 352 // TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status 353 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 354 // provide an atomic read-modify-write, so it's users responsibility to ensure 355 // exclusive read-modify-write if this ITM port is used concurrently by 356 // interrupts or other threads. 357 #define CPU_ITM_STIM11_STIM11_W 32 358 #define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF 359 #define CPU_ITM_STIM11_STIM11_S 0 360 361 //***************************************************************************** 362 // 363 // Register: CPU_ITM_O_STIM12 364 // 365 //***************************************************************************** 366 // Field: [31:0] STIM12 367 // 368 // A write to this location causes data to be written into the FIFO if 369 // TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status 370 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 371 // provide an atomic read-modify-write, so it's users responsibility to ensure 372 // exclusive read-modify-write if this ITM port is used concurrently by 373 // interrupts or other threads. 374 #define CPU_ITM_STIM12_STIM12_W 32 375 #define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF 376 #define CPU_ITM_STIM12_STIM12_S 0 377 378 //***************************************************************************** 379 // 380 // Register: CPU_ITM_O_STIM13 381 // 382 //***************************************************************************** 383 // Field: [31:0] STIM13 384 // 385 // A write to this location causes data to be written into the FIFO if 386 // TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status 387 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 388 // provide an atomic read-modify-write, so it's users responsibility to ensure 389 // exclusive read-modify-write if this ITM port is used concurrently by 390 // interrupts or other threads. 391 #define CPU_ITM_STIM13_STIM13_W 32 392 #define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF 393 #define CPU_ITM_STIM13_STIM13_S 0 394 395 //***************************************************************************** 396 // 397 // Register: CPU_ITM_O_STIM14 398 // 399 //***************************************************************************** 400 // Field: [31:0] STIM14 401 // 402 // A write to this location causes data to be written into the FIFO if 403 // TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status 404 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 405 // provide an atomic read-modify-write, so it's users responsibility to ensure 406 // exclusive read-modify-write if this ITM port is used concurrently by 407 // interrupts or other threads. 408 #define CPU_ITM_STIM14_STIM14_W 32 409 #define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF 410 #define CPU_ITM_STIM14_STIM14_S 0 411 412 //***************************************************************************** 413 // 414 // Register: CPU_ITM_O_STIM15 415 // 416 //***************************************************************************** 417 // Field: [31:0] STIM15 418 // 419 // A write to this location causes data to be written into the FIFO if 420 // TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status 421 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 422 // provide an atomic read-modify-write, so it's users responsibility to ensure 423 // exclusive read-modify-write if this ITM port is used concurrently by 424 // interrupts or other threads. 425 #define CPU_ITM_STIM15_STIM15_W 32 426 #define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF 427 #define CPU_ITM_STIM15_STIM15_S 0 428 429 //***************************************************************************** 430 // 431 // Register: CPU_ITM_O_STIM16 432 // 433 //***************************************************************************** 434 // Field: [31:0] STIM16 435 // 436 // A write to this location causes data to be written into the FIFO if 437 // TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status 438 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 439 // provide an atomic read-modify-write, so it's users responsibility to ensure 440 // exclusive read-modify-write if this ITM port is used concurrently by 441 // interrupts or other threads. 442 #define CPU_ITM_STIM16_STIM16_W 32 443 #define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF 444 #define CPU_ITM_STIM16_STIM16_S 0 445 446 //***************************************************************************** 447 // 448 // Register: CPU_ITM_O_STIM17 449 // 450 //***************************************************************************** 451 // Field: [31:0] STIM17 452 // 453 // A write to this location causes data to be written into the FIFO if 454 // TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status 455 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 456 // provide an atomic read-modify-write, so it's users responsibility to ensure 457 // exclusive read-modify-write if this ITM port is used concurrently by 458 // interrupts or other threads. 459 #define CPU_ITM_STIM17_STIM17_W 32 460 #define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF 461 #define CPU_ITM_STIM17_STIM17_S 0 462 463 //***************************************************************************** 464 // 465 // Register: CPU_ITM_O_STIM18 466 // 467 //***************************************************************************** 468 // Field: [31:0] STIM18 469 // 470 // A write to this location causes data to be written into the FIFO if 471 // TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status 472 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 473 // provide an atomic read-modify-write, so it's users responsibility to ensure 474 // exclusive read-modify-write if this ITM port is used concurrently by 475 // interrupts or other threads. 476 #define CPU_ITM_STIM18_STIM18_W 32 477 #define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF 478 #define CPU_ITM_STIM18_STIM18_S 0 479 480 //***************************************************************************** 481 // 482 // Register: CPU_ITM_O_STIM19 483 // 484 //***************************************************************************** 485 // Field: [31:0] STIM19 486 // 487 // A write to this location causes data to be written into the FIFO if 488 // TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status 489 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 490 // provide an atomic read-modify-write, so it's users responsibility to ensure 491 // exclusive read-modify-write if this ITM port is used concurrently by 492 // interrupts or other threads. 493 #define CPU_ITM_STIM19_STIM19_W 32 494 #define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF 495 #define CPU_ITM_STIM19_STIM19_S 0 496 497 //***************************************************************************** 498 // 499 // Register: CPU_ITM_O_STIM20 500 // 501 //***************************************************************************** 502 // Field: [31:0] STIM20 503 // 504 // A write to this location causes data to be written into the FIFO if 505 // TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status 506 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 507 // provide an atomic read-modify-write, so it's users responsibility to ensure 508 // exclusive read-modify-write if this ITM port is used concurrently by 509 // interrupts or other threads. 510 #define CPU_ITM_STIM20_STIM20_W 32 511 #define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF 512 #define CPU_ITM_STIM20_STIM20_S 0 513 514 //***************************************************************************** 515 // 516 // Register: CPU_ITM_O_STIM21 517 // 518 //***************************************************************************** 519 // Field: [31:0] STIM21 520 // 521 // A write to this location causes data to be written into the FIFO if 522 // TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status 523 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 524 // provide an atomic read-modify-write, so it's users responsibility to ensure 525 // exclusive read-modify-write if this ITM port is used concurrently by 526 // interrupts or other threads. 527 #define CPU_ITM_STIM21_STIM21_W 32 528 #define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF 529 #define CPU_ITM_STIM21_STIM21_S 0 530 531 //***************************************************************************** 532 // 533 // Register: CPU_ITM_O_STIM22 534 // 535 //***************************************************************************** 536 // Field: [31:0] STIM22 537 // 538 // A write to this location causes data to be written into the FIFO if 539 // TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status 540 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 541 // provide an atomic read-modify-write, so it's users responsibility to ensure 542 // exclusive read-modify-write if this ITM port is used concurrently by 543 // interrupts or other threads. 544 #define CPU_ITM_STIM22_STIM22_W 32 545 #define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF 546 #define CPU_ITM_STIM22_STIM22_S 0 547 548 //***************************************************************************** 549 // 550 // Register: CPU_ITM_O_STIM23 551 // 552 //***************************************************************************** 553 // Field: [31:0] STIM23 554 // 555 // A write to this location causes data to be written into the FIFO if 556 // TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status 557 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 558 // provide an atomic read-modify-write, so it's users responsibility to ensure 559 // exclusive read-modify-write if this ITM port is used concurrently by 560 // interrupts or other threads. 561 #define CPU_ITM_STIM23_STIM23_W 32 562 #define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF 563 #define CPU_ITM_STIM23_STIM23_S 0 564 565 //***************************************************************************** 566 // 567 // Register: CPU_ITM_O_STIM24 568 // 569 //***************************************************************************** 570 // Field: [31:0] STIM24 571 // 572 // A write to this location causes data to be written into the FIFO if 573 // TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status 574 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 575 // provide an atomic read-modify-write, so it's users responsibility to ensure 576 // exclusive read-modify-write if this ITM port is used concurrently by 577 // interrupts or other threads. 578 #define CPU_ITM_STIM24_STIM24_W 32 579 #define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF 580 #define CPU_ITM_STIM24_STIM24_S 0 581 582 //***************************************************************************** 583 // 584 // Register: CPU_ITM_O_STIM25 585 // 586 //***************************************************************************** 587 // Field: [31:0] STIM25 588 // 589 // A write to this location causes data to be written into the FIFO if 590 // TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status 591 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 592 // provide an atomic read-modify-write, so it's users responsibility to ensure 593 // exclusive read-modify-write if this ITM port is used concurrently by 594 // interrupts or other threads. 595 #define CPU_ITM_STIM25_STIM25_W 32 596 #define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF 597 #define CPU_ITM_STIM25_STIM25_S 0 598 599 //***************************************************************************** 600 // 601 // Register: CPU_ITM_O_STIM26 602 // 603 //***************************************************************************** 604 // Field: [31:0] STIM26 605 // 606 // A write to this location causes data to be written into the FIFO if 607 // TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status 608 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 609 // provide an atomic read-modify-write, so it's users responsibility to ensure 610 // exclusive read-modify-write if this ITM port is used concurrently by 611 // interrupts or other threads. 612 #define CPU_ITM_STIM26_STIM26_W 32 613 #define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF 614 #define CPU_ITM_STIM26_STIM26_S 0 615 616 //***************************************************************************** 617 // 618 // Register: CPU_ITM_O_STIM27 619 // 620 //***************************************************************************** 621 // Field: [31:0] STIM27 622 // 623 // A write to this location causes data to be written into the FIFO if 624 // TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status 625 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 626 // provide an atomic read-modify-write, so it's users responsibility to ensure 627 // exclusive read-modify-write if this ITM port is used concurrently by 628 // interrupts or other threads. 629 #define CPU_ITM_STIM27_STIM27_W 32 630 #define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF 631 #define CPU_ITM_STIM27_STIM27_S 0 632 633 //***************************************************************************** 634 // 635 // Register: CPU_ITM_O_STIM28 636 // 637 //***************************************************************************** 638 // Field: [31:0] STIM28 639 // 640 // A write to this location causes data to be written into the FIFO if 641 // TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status 642 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 643 // provide an atomic read-modify-write, so it's users responsibility to ensure 644 // exclusive read-modify-write if this ITM port is used concurrently by 645 // interrupts or other threads. 646 #define CPU_ITM_STIM28_STIM28_W 32 647 #define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF 648 #define CPU_ITM_STIM28_STIM28_S 0 649 650 //***************************************************************************** 651 // 652 // Register: CPU_ITM_O_STIM29 653 // 654 //***************************************************************************** 655 // Field: [31:0] STIM29 656 // 657 // A write to this location causes data to be written into the FIFO if 658 // TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status 659 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 660 // provide an atomic read-modify-write, so it's users responsibility to ensure 661 // exclusive read-modify-write if this ITM port is used concurrently by 662 // interrupts or other threads. 663 #define CPU_ITM_STIM29_STIM29_W 32 664 #define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF 665 #define CPU_ITM_STIM29_STIM29_S 0 666 667 //***************************************************************************** 668 // 669 // Register: CPU_ITM_O_STIM30 670 // 671 //***************************************************************************** 672 // Field: [31:0] STIM30 673 // 674 // A write to this location causes data to be written into the FIFO if 675 // TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status 676 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 677 // provide an atomic read-modify-write, so it's users responsibility to ensure 678 // exclusive read-modify-write if this ITM port is used concurrently by 679 // interrupts or other threads. 680 #define CPU_ITM_STIM30_STIM30_W 32 681 #define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF 682 #define CPU_ITM_STIM30_STIM30_S 0 683 684 //***************************************************************************** 685 // 686 // Register: CPU_ITM_O_STIM31 687 // 688 //***************************************************************************** 689 // Field: [31:0] STIM31 690 // 691 // A write to this location causes data to be written into the FIFO if 692 // TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status 693 // in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not 694 // provide an atomic read-modify-write, so it's users responsibility to ensure 695 // exclusive read-modify-write if this ITM port is used concurrently by 696 // interrupts or other threads. 697 #define CPU_ITM_STIM31_STIM31_W 32 698 #define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF 699 #define CPU_ITM_STIM31_STIM31_S 0 700 701 //***************************************************************************** 702 // 703 // Register: CPU_ITM_O_TER 704 // 705 //***************************************************************************** 706 // Field: [31] STIMENA31 707 // 708 // Bit mask to enable tracing on ITM stimulus port 31. 709 #define CPU_ITM_TER_STIMENA31 0x80000000 710 #define CPU_ITM_TER_STIMENA31_BITN 31 711 #define CPU_ITM_TER_STIMENA31_M 0x80000000 712 #define CPU_ITM_TER_STIMENA31_S 31 713 714 // Field: [30] STIMENA30 715 // 716 // Bit mask to enable tracing on ITM stimulus port 30. 717 #define CPU_ITM_TER_STIMENA30 0x40000000 718 #define CPU_ITM_TER_STIMENA30_BITN 30 719 #define CPU_ITM_TER_STIMENA30_M 0x40000000 720 #define CPU_ITM_TER_STIMENA30_S 30 721 722 // Field: [29] STIMENA29 723 // 724 // Bit mask to enable tracing on ITM stimulus port 29. 725 #define CPU_ITM_TER_STIMENA29 0x20000000 726 #define CPU_ITM_TER_STIMENA29_BITN 29 727 #define CPU_ITM_TER_STIMENA29_M 0x20000000 728 #define CPU_ITM_TER_STIMENA29_S 29 729 730 // Field: [28] STIMENA28 731 // 732 // Bit mask to enable tracing on ITM stimulus port 28. 733 #define CPU_ITM_TER_STIMENA28 0x10000000 734 #define CPU_ITM_TER_STIMENA28_BITN 28 735 #define CPU_ITM_TER_STIMENA28_M 0x10000000 736 #define CPU_ITM_TER_STIMENA28_S 28 737 738 // Field: [27] STIMENA27 739 // 740 // Bit mask to enable tracing on ITM stimulus port 27. 741 #define CPU_ITM_TER_STIMENA27 0x08000000 742 #define CPU_ITM_TER_STIMENA27_BITN 27 743 #define CPU_ITM_TER_STIMENA27_M 0x08000000 744 #define CPU_ITM_TER_STIMENA27_S 27 745 746 // Field: [26] STIMENA26 747 // 748 // Bit mask to enable tracing on ITM stimulus port 26. 749 #define CPU_ITM_TER_STIMENA26 0x04000000 750 #define CPU_ITM_TER_STIMENA26_BITN 26 751 #define CPU_ITM_TER_STIMENA26_M 0x04000000 752 #define CPU_ITM_TER_STIMENA26_S 26 753 754 // Field: [25] STIMENA25 755 // 756 // Bit mask to enable tracing on ITM stimulus port 25. 757 #define CPU_ITM_TER_STIMENA25 0x02000000 758 #define CPU_ITM_TER_STIMENA25_BITN 25 759 #define CPU_ITM_TER_STIMENA25_M 0x02000000 760 #define CPU_ITM_TER_STIMENA25_S 25 761 762 // Field: [24] STIMENA24 763 // 764 // Bit mask to enable tracing on ITM stimulus port 24. 765 #define CPU_ITM_TER_STIMENA24 0x01000000 766 #define CPU_ITM_TER_STIMENA24_BITN 24 767 #define CPU_ITM_TER_STIMENA24_M 0x01000000 768 #define CPU_ITM_TER_STIMENA24_S 24 769 770 // Field: [23] STIMENA23 771 // 772 // Bit mask to enable tracing on ITM stimulus port 23. 773 #define CPU_ITM_TER_STIMENA23 0x00800000 774 #define CPU_ITM_TER_STIMENA23_BITN 23 775 #define CPU_ITM_TER_STIMENA23_M 0x00800000 776 #define CPU_ITM_TER_STIMENA23_S 23 777 778 // Field: [22] STIMENA22 779 // 780 // Bit mask to enable tracing on ITM stimulus port 22. 781 #define CPU_ITM_TER_STIMENA22 0x00400000 782 #define CPU_ITM_TER_STIMENA22_BITN 22 783 #define CPU_ITM_TER_STIMENA22_M 0x00400000 784 #define CPU_ITM_TER_STIMENA22_S 22 785 786 // Field: [21] STIMENA21 787 // 788 // Bit mask to enable tracing on ITM stimulus port 21. 789 #define CPU_ITM_TER_STIMENA21 0x00200000 790 #define CPU_ITM_TER_STIMENA21_BITN 21 791 #define CPU_ITM_TER_STIMENA21_M 0x00200000 792 #define CPU_ITM_TER_STIMENA21_S 21 793 794 // Field: [20] STIMENA20 795 // 796 // Bit mask to enable tracing on ITM stimulus port 20. 797 #define CPU_ITM_TER_STIMENA20 0x00100000 798 #define CPU_ITM_TER_STIMENA20_BITN 20 799 #define CPU_ITM_TER_STIMENA20_M 0x00100000 800 #define CPU_ITM_TER_STIMENA20_S 20 801 802 // Field: [19] STIMENA19 803 // 804 // Bit mask to enable tracing on ITM stimulus port 19. 805 #define CPU_ITM_TER_STIMENA19 0x00080000 806 #define CPU_ITM_TER_STIMENA19_BITN 19 807 #define CPU_ITM_TER_STIMENA19_M 0x00080000 808 #define CPU_ITM_TER_STIMENA19_S 19 809 810 // Field: [18] STIMENA18 811 // 812 // Bit mask to enable tracing on ITM stimulus port 18. 813 #define CPU_ITM_TER_STIMENA18 0x00040000 814 #define CPU_ITM_TER_STIMENA18_BITN 18 815 #define CPU_ITM_TER_STIMENA18_M 0x00040000 816 #define CPU_ITM_TER_STIMENA18_S 18 817 818 // Field: [17] STIMENA17 819 // 820 // Bit mask to enable tracing on ITM stimulus port 17. 821 #define CPU_ITM_TER_STIMENA17 0x00020000 822 #define CPU_ITM_TER_STIMENA17_BITN 17 823 #define CPU_ITM_TER_STIMENA17_M 0x00020000 824 #define CPU_ITM_TER_STIMENA17_S 17 825 826 // Field: [16] STIMENA16 827 // 828 // Bit mask to enable tracing on ITM stimulus port 16. 829 #define CPU_ITM_TER_STIMENA16 0x00010000 830 #define CPU_ITM_TER_STIMENA16_BITN 16 831 #define CPU_ITM_TER_STIMENA16_M 0x00010000 832 #define CPU_ITM_TER_STIMENA16_S 16 833 834 // Field: [15] STIMENA15 835 // 836 // Bit mask to enable tracing on ITM stimulus port 15. 837 #define CPU_ITM_TER_STIMENA15 0x00008000 838 #define CPU_ITM_TER_STIMENA15_BITN 15 839 #define CPU_ITM_TER_STIMENA15_M 0x00008000 840 #define CPU_ITM_TER_STIMENA15_S 15 841 842 // Field: [14] STIMENA14 843 // 844 // Bit mask to enable tracing on ITM stimulus port 14. 845 #define CPU_ITM_TER_STIMENA14 0x00004000 846 #define CPU_ITM_TER_STIMENA14_BITN 14 847 #define CPU_ITM_TER_STIMENA14_M 0x00004000 848 #define CPU_ITM_TER_STIMENA14_S 14 849 850 // Field: [13] STIMENA13 851 // 852 // Bit mask to enable tracing on ITM stimulus port 13. 853 #define CPU_ITM_TER_STIMENA13 0x00002000 854 #define CPU_ITM_TER_STIMENA13_BITN 13 855 #define CPU_ITM_TER_STIMENA13_M 0x00002000 856 #define CPU_ITM_TER_STIMENA13_S 13 857 858 // Field: [12] STIMENA12 859 // 860 // Bit mask to enable tracing on ITM stimulus port 12. 861 #define CPU_ITM_TER_STIMENA12 0x00001000 862 #define CPU_ITM_TER_STIMENA12_BITN 12 863 #define CPU_ITM_TER_STIMENA12_M 0x00001000 864 #define CPU_ITM_TER_STIMENA12_S 12 865 866 // Field: [11] STIMENA11 867 // 868 // Bit mask to enable tracing on ITM stimulus port 11. 869 #define CPU_ITM_TER_STIMENA11 0x00000800 870 #define CPU_ITM_TER_STIMENA11_BITN 11 871 #define CPU_ITM_TER_STIMENA11_M 0x00000800 872 #define CPU_ITM_TER_STIMENA11_S 11 873 874 // Field: [10] STIMENA10 875 // 876 // Bit mask to enable tracing on ITM stimulus port 10. 877 #define CPU_ITM_TER_STIMENA10 0x00000400 878 #define CPU_ITM_TER_STIMENA10_BITN 10 879 #define CPU_ITM_TER_STIMENA10_M 0x00000400 880 #define CPU_ITM_TER_STIMENA10_S 10 881 882 // Field: [9] STIMENA9 883 // 884 // Bit mask to enable tracing on ITM stimulus port 9. 885 #define CPU_ITM_TER_STIMENA9 0x00000200 886 #define CPU_ITM_TER_STIMENA9_BITN 9 887 #define CPU_ITM_TER_STIMENA9_M 0x00000200 888 #define CPU_ITM_TER_STIMENA9_S 9 889 890 // Field: [8] STIMENA8 891 // 892 // Bit mask to enable tracing on ITM stimulus port 8. 893 #define CPU_ITM_TER_STIMENA8 0x00000100 894 #define CPU_ITM_TER_STIMENA8_BITN 8 895 #define CPU_ITM_TER_STIMENA8_M 0x00000100 896 #define CPU_ITM_TER_STIMENA8_S 8 897 898 // Field: [7] STIMENA7 899 // 900 // Bit mask to enable tracing on ITM stimulus port 7. 901 #define CPU_ITM_TER_STIMENA7 0x00000080 902 #define CPU_ITM_TER_STIMENA7_BITN 7 903 #define CPU_ITM_TER_STIMENA7_M 0x00000080 904 #define CPU_ITM_TER_STIMENA7_S 7 905 906 // Field: [6] STIMENA6 907 // 908 // Bit mask to enable tracing on ITM stimulus port 6. 909 #define CPU_ITM_TER_STIMENA6 0x00000040 910 #define CPU_ITM_TER_STIMENA6_BITN 6 911 #define CPU_ITM_TER_STIMENA6_M 0x00000040 912 #define CPU_ITM_TER_STIMENA6_S 6 913 914 // Field: [5] STIMENA5 915 // 916 // Bit mask to enable tracing on ITM stimulus port 5. 917 #define CPU_ITM_TER_STIMENA5 0x00000020 918 #define CPU_ITM_TER_STIMENA5_BITN 5 919 #define CPU_ITM_TER_STIMENA5_M 0x00000020 920 #define CPU_ITM_TER_STIMENA5_S 5 921 922 // Field: [4] STIMENA4 923 // 924 // Bit mask to enable tracing on ITM stimulus port 4. 925 #define CPU_ITM_TER_STIMENA4 0x00000010 926 #define CPU_ITM_TER_STIMENA4_BITN 4 927 #define CPU_ITM_TER_STIMENA4_M 0x00000010 928 #define CPU_ITM_TER_STIMENA4_S 4 929 930 // Field: [3] STIMENA3 931 // 932 // Bit mask to enable tracing on ITM stimulus port 3. 933 #define CPU_ITM_TER_STIMENA3 0x00000008 934 #define CPU_ITM_TER_STIMENA3_BITN 3 935 #define CPU_ITM_TER_STIMENA3_M 0x00000008 936 #define CPU_ITM_TER_STIMENA3_S 3 937 938 // Field: [2] STIMENA2 939 // 940 // Bit mask to enable tracing on ITM stimulus port 2. 941 #define CPU_ITM_TER_STIMENA2 0x00000004 942 #define CPU_ITM_TER_STIMENA2_BITN 2 943 #define CPU_ITM_TER_STIMENA2_M 0x00000004 944 #define CPU_ITM_TER_STIMENA2_S 2 945 946 // Field: [1] STIMENA1 947 // 948 // Bit mask to enable tracing on ITM stimulus port 1. 949 #define CPU_ITM_TER_STIMENA1 0x00000002 950 #define CPU_ITM_TER_STIMENA1_BITN 1 951 #define CPU_ITM_TER_STIMENA1_M 0x00000002 952 #define CPU_ITM_TER_STIMENA1_S 1 953 954 // Field: [0] STIMENA0 955 // 956 // Bit mask to enable tracing on ITM stimulus port 0. 957 #define CPU_ITM_TER_STIMENA0 0x00000001 958 #define CPU_ITM_TER_STIMENA0_BITN 0 959 #define CPU_ITM_TER_STIMENA0_M 0x00000001 960 #define CPU_ITM_TER_STIMENA0_S 0 961 962 //***************************************************************************** 963 // 964 // Register: CPU_ITM_O_TPR 965 // 966 //***************************************************************************** 967 // Field: [3:0] PRIVMASK 968 // 969 // Bit mask to enable unprivileged (User) access to ITM stimulus ports: 970 // 971 // Bit [0] enables stimulus ports 0, 1, ..., and 7. 972 // Bit [1] enables stimulus ports 8, 9, ..., and 15. 973 // Bit [2] enables stimulus ports 16, 17, ..., and 23. 974 // Bit [3] enables stimulus ports 24, 25, ..., and 31. 975 // 976 // 0: User access allowed to stimulus ports 977 // 1: Privileged access only to stimulus ports 978 #define CPU_ITM_TPR_PRIVMASK_W 4 979 #define CPU_ITM_TPR_PRIVMASK_M 0x0000000F 980 #define CPU_ITM_TPR_PRIVMASK_S 0 981 982 //***************************************************************************** 983 // 984 // Register: CPU_ITM_O_TCR 985 // 986 //***************************************************************************** 987 // Field: [23] BUSY 988 // 989 // Set when ITM events present and being drained. 990 #define CPU_ITM_TCR_BUSY 0x00800000 991 #define CPU_ITM_TCR_BUSY_BITN 23 992 #define CPU_ITM_TCR_BUSY_M 0x00800000 993 #define CPU_ITM_TCR_BUSY_S 23 994 995 // Field: [22:16] ATBID 996 // 997 // Trace Bus ID for CoreSight system. Optional identifier for multi-source 998 // trace stream formatting. If multi-source trace is in use, this field must be 999 // written with a non-zero value. 1000 #define CPU_ITM_TCR_ATBID_W 7 1001 #define CPU_ITM_TCR_ATBID_M 0x007F0000 1002 #define CPU_ITM_TCR_ATBID_S 16 1003 1004 // Field: [9:8] TSPRESCALE 1005 // 1006 // Timestamp prescaler 1007 // ENUMs: 1008 // DIV64 Divide by 64 1009 // DIV16 Divide by 16 1010 // DIV4 Divide by 4 1011 // NOPRESCALING No prescaling 1012 #define CPU_ITM_TCR_TSPRESCALE_W 2 1013 #define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 1014 #define CPU_ITM_TCR_TSPRESCALE_S 8 1015 #define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 1016 #define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 1017 #define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 1018 #define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 1019 1020 // Field: [4] SWOENA 1021 // 1022 // Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If 1023 // TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of 1024 // the timestamp counter. 1025 // 1026 // 0x0: Mode disabled. Timestamp counter uses system clock from the core and 1027 // counts continuously. 1028 // 0x1: Timestamp counter uses lineout (data related) clock from TPIU 1029 // interface. The timestamp counter is held in reset while the output line is 1030 // idle. 1031 #define CPU_ITM_TCR_SWOENA 0x00000010 1032 #define CPU_ITM_TCR_SWOENA_BITN 4 1033 #define CPU_ITM_TCR_SWOENA_M 0x00000010 1034 #define CPU_ITM_TCR_SWOENA_S 4 1035 1036 // Field: [3] DWTENA 1037 // 1038 // Enables the DWT stimulus (hardware event packet emission to the TPIU from 1039 // the DWT) 1040 #define CPU_ITM_TCR_DWTENA 0x00000008 1041 #define CPU_ITM_TCR_DWTENA_BITN 3 1042 #define CPU_ITM_TCR_DWTENA_M 0x00000008 1043 #define CPU_ITM_TCR_DWTENA_S 3 1044 1045 // Field: [2] SYNCENA 1046 // 1047 // Enables synchronization packet transmission for a synchronous TPIU. 1048 // CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization 1049 // speed. 1050 #define CPU_ITM_TCR_SYNCENA 0x00000004 1051 #define CPU_ITM_TCR_SYNCENA_BITN 2 1052 #define CPU_ITM_TCR_SYNCENA_M 0x00000004 1053 #define CPU_ITM_TCR_SYNCENA_S 2 1054 1055 // Field: [1] TSENA 1056 // 1057 // Enables differential timestamps. Differential timestamps are emitted when a 1058 // packet is written to the FIFO with a non-zero timestamp counter, and when 1059 // the timestamp counter overflows. Timestamps are emitted during idle times 1060 // after a fixed number of two million cycles. This provides a time reference 1061 // for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps 1062 // are triggered by activity on the internal trace bus only. In this case there 1063 // is no regular timestamp output when the ITM is idle. 1064 #define CPU_ITM_TCR_TSENA 0x00000002 1065 #define CPU_ITM_TCR_TSENA_BITN 1 1066 #define CPU_ITM_TCR_TSENA_M 0x00000002 1067 #define CPU_ITM_TCR_TSENA_S 1 1068 1069 // Field: [0] ITMENA 1070 // 1071 // Enables ITM. This is the master enable, and must be set before ITM Stimulus 1072 // and Trace Enable registers can be written. 1073 #define CPU_ITM_TCR_ITMENA 0x00000001 1074 #define CPU_ITM_TCR_ITMENA_BITN 0 1075 #define CPU_ITM_TCR_ITMENA_M 0x00000001 1076 #define CPU_ITM_TCR_ITMENA_S 0 1077 1078 //***************************************************************************** 1079 // 1080 // Register: CPU_ITM_O_LAR 1081 // 1082 //***************************************************************************** 1083 // Field: [31:0] LOCK_ACCESS 1084 // 1085 // A privileged write of 0xC5ACCE55 enables more write access to Control 1086 // Registers TER, TPR and TCR. An invalid write removes write access. 1087 #define CPU_ITM_LAR_LOCK_ACCESS_W 32 1088 #define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF 1089 #define CPU_ITM_LAR_LOCK_ACCESS_S 0 1090 1091 //***************************************************************************** 1092 // 1093 // Register: CPU_ITM_O_LSR 1094 // 1095 //***************************************************************************** 1096 // Field: [2] BYTEACC 1097 // 1098 // Reads 0 which means 8-bit lock access is not be implemented. 1099 #define CPU_ITM_LSR_BYTEACC 0x00000004 1100 #define CPU_ITM_LSR_BYTEACC_BITN 2 1101 #define CPU_ITM_LSR_BYTEACC_M 0x00000004 1102 #define CPU_ITM_LSR_BYTEACC_S 2 1103 1104 // Field: [1] ACCESS 1105 // 1106 // Write access to component is blocked. All writes are ignored, reads are 1107 // permitted. 1108 #define CPU_ITM_LSR_ACCESS 0x00000002 1109 #define CPU_ITM_LSR_ACCESS_BITN 1 1110 #define CPU_ITM_LSR_ACCESS_M 0x00000002 1111 #define CPU_ITM_LSR_ACCESS_S 1 1112 1113 // Field: [0] PRESENT 1114 // 1115 // Indicates that a lock mechanism exists for this component. 1116 #define CPU_ITM_LSR_PRESENT 0x00000001 1117 #define CPU_ITM_LSR_PRESENT_BITN 0 1118 #define CPU_ITM_LSR_PRESENT_M 0x00000001 1119 #define CPU_ITM_LSR_PRESENT_S 0 1120 1121 1122 #endif // __CPU_ITM__ 1123
