1 /****************************************************************************** 2 * Filename: hw_cpu_dwt_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_CPU_DWT_H__ 38 #define __HW_CPU_DWT_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // CPU_DWT component 44 // 45 //***************************************************************************** 46 // Control 47 #define CPU_DWT_O_CTRL 0x00000000 48 49 // Current PC Sampler Cycle Count 50 #define CPU_DWT_O_CYCCNT 0x00000004 51 52 // CPI Count 53 #define CPU_DWT_O_CPICNT 0x00000008 54 55 // Exception Overhead Count 56 #define CPU_DWT_O_EXCCNT 0x0000000C 57 58 // Sleep Count 59 #define CPU_DWT_O_SLEEPCNT 0x00000010 60 61 // LSU Count 62 #define CPU_DWT_O_LSUCNT 0x00000014 63 64 // Fold Count 65 #define CPU_DWT_O_FOLDCNT 0x00000018 66 67 // Program Counter Sample 68 #define CPU_DWT_O_PCSR 0x0000001C 69 70 // Comparator 0 71 #define CPU_DWT_O_COMP0 0x00000020 72 73 // Mask 0 74 #define CPU_DWT_O_MASK0 0x00000024 75 76 // Function 0 77 #define CPU_DWT_O_FUNCTION0 0x00000028 78 79 // Comparator 1 80 #define CPU_DWT_O_COMP1 0x00000030 81 82 // Mask 1 83 #define CPU_DWT_O_MASK1 0x00000034 84 85 // Function 1 86 #define CPU_DWT_O_FUNCTION1 0x00000038 87 88 // Comparator 2 89 #define CPU_DWT_O_COMP2 0x00000040 90 91 // Mask 2 92 #define CPU_DWT_O_MASK2 0x00000044 93 94 // Function 2 95 #define CPU_DWT_O_FUNCTION2 0x00000048 96 97 // Comparator 3 98 #define CPU_DWT_O_COMP3 0x00000050 99 100 // Mask 3 101 #define CPU_DWT_O_MASK3 0x00000054 102 103 // Function 3 104 #define CPU_DWT_O_FUNCTION3 0x00000058 105 106 //***************************************************************************** 107 // 108 // Register: CPU_DWT_O_CTRL 109 // 110 //***************************************************************************** 111 // Field: [25] NOCYCCNT 112 // 113 // When set, CYCCNT is not supported. 114 #define CPU_DWT_CTRL_NOCYCCNT 0x02000000 115 #define CPU_DWT_CTRL_NOCYCCNT_BITN 25 116 #define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 117 #define CPU_DWT_CTRL_NOCYCCNT_S 25 118 119 // Field: [24] NOPRFCNT 120 // 121 // When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. 122 #define CPU_DWT_CTRL_NOPRFCNT 0x01000000 123 #define CPU_DWT_CTRL_NOPRFCNT_BITN 24 124 #define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 125 #define CPU_DWT_CTRL_NOPRFCNT_S 24 126 127 // Field: [22] CYCEVTENA 128 // 129 // Enables Cycle count event. Emits an event when the POSTCNT counter triggers 130 // it. See CYCTAP and POSTPRESET for details. This event is only emitted if 131 // PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. 132 // 133 // 0: Cycle count events disabled 134 // 1: Cycle count events enabled 135 #define CPU_DWT_CTRL_CYCEVTENA 0x00400000 136 #define CPU_DWT_CTRL_CYCEVTENA_BITN 22 137 #define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 138 #define CPU_DWT_CTRL_CYCEVTENA_S 22 139 140 // Field: [21] FOLDEVTENA 141 // 142 // Enables Folded instruction count event. Emits an event when FOLDCNT 143 // overflows (every 256 cycles of folded instructions). A folded instruction is 144 // one that does not incur even one cycle to execute. For example, an IT 145 // instruction is folded away and so does not use up one cycle. 146 // 147 // 0: Folded instruction count events disabled. 148 // 1: Folded instruction count events enabled. 149 #define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 150 #define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 151 #define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 152 #define CPU_DWT_CTRL_FOLDEVTENA_S 21 153 154 // Field: [20] LSUEVTENA 155 // 156 // Enables LSU count event. Emits an event when LSUCNT overflows (every 256 157 // cycles of LSU operation). LSU counts include all LSU costs after the initial 158 // cycle for the instruction. 159 // 160 // 0: LSU count events disabled. 161 // 1: LSU count events enabled. 162 #define CPU_DWT_CTRL_LSUEVTENA 0x00100000 163 #define CPU_DWT_CTRL_LSUEVTENA_BITN 20 164 #define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 165 #define CPU_DWT_CTRL_LSUEVTENA_S 20 166 167 // Field: [19] SLEEPEVTENA 168 // 169 // Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 170 // cycles that the processor is sleeping). 171 // 172 // 0: Sleep count events disabled. 173 // 1: Sleep count events enabled. 174 #define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 175 #define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 176 #define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 177 #define CPU_DWT_CTRL_SLEEPEVTENA_S 19 178 179 // Field: [18] EXCEVTENA 180 // 181 // Enables Interrupt overhead event. Emits an event when EXCCNT overflows 182 // (every 256 cycles of interrupt overhead). 183 // 184 // 0x0: Interrupt overhead event disabled. 185 // 0x1: Interrupt overhead event enabled. 186 #define CPU_DWT_CTRL_EXCEVTENA 0x00040000 187 #define CPU_DWT_CTRL_EXCEVTENA_BITN 18 188 #define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 189 #define CPU_DWT_CTRL_EXCEVTENA_S 18 190 191 // Field: [17] CPIEVTENA 192 // 193 // Enables CPI count event. Emits an event when CPICNT overflows (every 256 194 // cycles of multi-cycle instructions). 195 // 196 // 0: CPI counter events disabled. 197 // 1: CPI counter events enabled. 198 #define CPU_DWT_CTRL_CPIEVTENA 0x00020000 199 #define CPU_DWT_CTRL_CPIEVTENA_BITN 17 200 #define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 201 #define CPU_DWT_CTRL_CPIEVTENA_S 17 202 203 // Field: [16] EXCTRCENA 204 // 205 // Enables Interrupt event tracing. 206 // 207 // 0: Interrupt event trace disabled. 208 // 1: Interrupt event trace enabled. 209 #define CPU_DWT_CTRL_EXCTRCENA 0x00010000 210 #define CPU_DWT_CTRL_EXCTRCENA_BITN 16 211 #define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 212 #define CPU_DWT_CTRL_EXCTRCENA_S 16 213 214 // Field: [12] PCSAMPLEENA 215 // 216 // Enables PC Sampling event. A PC sample event is emitted when the POSTCNT 217 // counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this 218 // bit overrides CYCEVTENA. 219 // 220 // 0: PC Sampling event disabled. 221 // 1: Sampling event enabled. 222 #define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 223 #define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 224 #define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 225 #define CPU_DWT_CTRL_PCSAMPLEENA_S 12 226 227 // Field: [11:10] SYNCTAP 228 // 229 // Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA 230 // must also be enabled for this feature. 231 // Synchronization packets (if enabled) are generated on tap transitions (0 to1 232 // or 1 to 0). 233 // ENUMs: 234 // BIT28 Tap at bit 28 of CYCCNT 235 // BIT26 Tap at bit 26 of CYCCNT 236 // BIT24 Tap at bit 24 of CYCCNT 237 // DIS Disabled. No synchronization packets 238 #define CPU_DWT_CTRL_SYNCTAP_W 2 239 #define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 240 #define CPU_DWT_CTRL_SYNCTAP_S 10 241 #define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 242 #define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 243 #define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 244 #define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 245 246 // Field: [9] CYCTAP 247 // 248 // Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the 249 // selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the 250 // POSTCNT, post-scalar counter. That counter then counts down. On a bit change 251 // when post-scalar is 0, it triggers an event for PC sampling or cycle count 252 // event (see details in CYCEVTENA). 253 // ENUMs: 254 // BIT10 Selects bit [10] to tap 255 // BIT6 Selects bit [6] to tap 256 #define CPU_DWT_CTRL_CYCTAP 0x00000200 257 #define CPU_DWT_CTRL_CYCTAP_BITN 9 258 #define CPU_DWT_CTRL_CYCTAP_M 0x00000200 259 #define CPU_DWT_CTRL_CYCTAP_S 9 260 #define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 261 #define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 262 263 // Field: [8:5] POSTCNT 264 // 265 // Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 266 // to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it 267 // triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the 268 // value from POSTPRESET. 269 #define CPU_DWT_CTRL_POSTCNT_W 4 270 #define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 271 #define CPU_DWT_CTRL_POSTCNT_S 5 272 273 // Field: [4:1] POSTPRESET 274 // 275 // Reload value for post-scalar counter POSTCNT. When 0, events are triggered 276 // on each tap change (a power of 2). If this field has a non-0 value, it forms 277 // a count-down value, to be reloaded into POSTCNT each time it reaches 0. For 278 // example, a value 1 in this register means an event is formed every other tap 279 // change. 280 #define CPU_DWT_CTRL_POSTPRESET_W 4 281 #define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E 282 #define CPU_DWT_CTRL_POSTPRESET_S 1 283 284 // Field: [0] CYCCNTENA 285 // 286 // Enable CYCCNT, allowing it to increment and generate synchronization and 287 // count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. 288 #define CPU_DWT_CTRL_CYCCNTENA 0x00000001 289 #define CPU_DWT_CTRL_CYCCNTENA_BITN 0 290 #define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 291 #define CPU_DWT_CTRL_CYCCNTENA_S 0 292 293 //***************************************************************************** 294 // 295 // Register: CPU_DWT_O_CYCCNT 296 // 297 //***************************************************************************** 298 // Field: [31:0] CYCCNT 299 // 300 // Current PC Sampler Cycle Counter count value. When enabled, this counter 301 // counts the number of core cycles, except when the core is halted. The cycle 302 // counter is a free running counter, counting upwards (this counter will not 303 // advance in power modes where free-running clock to CPU stops). It wraps 304 // around to 0 on overflow. The debugger must initialize this to 0 when first 305 // enabling. 306 #define CPU_DWT_CYCCNT_CYCCNT_W 32 307 #define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF 308 #define CPU_DWT_CYCCNT_CYCCNT_S 0 309 310 //***************************************************************************** 311 // 312 // Register: CPU_DWT_O_CPICNT 313 // 314 //***************************************************************************** 315 // Field: [7:0] CPICNT 316 // 317 // Current CPI counter value. Increments on the additional cycles (the first 318 // cycle is not counted) required to execute all instructions except those 319 // recorded by LSUCNT. This counter also increments on all instruction fetch 320 // stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter 321 // overflows. This counter initializes to 0 when it is enabled using 322 // CTRL.CPIEVTENA. 323 #define CPU_DWT_CPICNT_CPICNT_W 8 324 #define CPU_DWT_CPICNT_CPICNT_M 0x000000FF 325 #define CPU_DWT_CPICNT_CPICNT_S 0 326 327 //***************************************************************************** 328 // 329 // Register: CPU_DWT_O_EXCCNT 330 // 331 //***************************************************************************** 332 // Field: [7:0] EXCCNT 333 // 334 // Current interrupt overhead counter value. Counts the total cycles spent in 335 // interrupt processing (for example entry stacking, return unstacking, 336 // pre-emption). An event is emitted on counter overflow (every 256 cycles). 337 // This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. 338 #define CPU_DWT_EXCCNT_EXCCNT_W 8 339 #define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF 340 #define CPU_DWT_EXCCNT_EXCCNT_S 0 341 342 //***************************************************************************** 343 // 344 // Register: CPU_DWT_O_SLEEPCNT 345 // 346 //***************************************************************************** 347 // Field: [7:0] SLEEPCNT 348 // 349 // Sleep counter. Counts the number of cycles during which the processor is 350 // sleeping. An event is emitted on counter overflow (every 256 cycles). This 351 // counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note 352 // that the sleep counter is clocked using CPU's free-running clock. In some 353 // power modes the free-running clock to CPU is gated to minimize power 354 // consumption. This means that the sleep counter will be invalid in these 355 // power modes. 356 #define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 357 #define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF 358 #define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 359 360 //***************************************************************************** 361 // 362 // Register: CPU_DWT_O_LSUCNT 363 // 364 //***************************************************************************** 365 // Field: [7:0] LSUCNT 366 // 367 // LSU counter. This counts the total number of cycles that the processor is 368 // processing an LSU operation. The initial execution cost of the instruction 369 // is not counted. For example, an LDR that takes two cycles to complete 370 // increments this counter one cycle. Equivalently, an LDR that stalls for two 371 // cycles (i.e. takes four cycles to execute), increments this counter three 372 // times. An event is emitted on counter overflow (every 256 cycles). This 373 // counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. 374 #define CPU_DWT_LSUCNT_LSUCNT_W 8 375 #define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF 376 #define CPU_DWT_LSUCNT_LSUCNT_S 0 377 378 //***************************************************************************** 379 // 380 // Register: CPU_DWT_O_FOLDCNT 381 // 382 //***************************************************************************** 383 // Field: [7:0] FOLDCNT 384 // 385 // This counts the total number folded instructions. This counter initializes 386 // to 0 when it is enabled using CTRL.FOLDEVTENA. 387 #define CPU_DWT_FOLDCNT_FOLDCNT_W 8 388 #define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF 389 #define CPU_DWT_FOLDCNT_FOLDCNT_S 0 390 391 //***************************************************************************** 392 // 393 // Register: CPU_DWT_O_PCSR 394 // 395 //***************************************************************************** 396 // Field: [31:0] EIASAMPLE 397 // 398 // Execution instruction address sample, or 0xFFFFFFFF if the core is halted. 399 #define CPU_DWT_PCSR_EIASAMPLE_W 32 400 #define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF 401 #define CPU_DWT_PCSR_EIASAMPLE_S 0 402 403 //***************************************************************************** 404 // 405 // Register: CPU_DWT_O_COMP0 406 // 407 //***************************************************************************** 408 // Field: [31:0] COMP 409 // 410 // Reference value to compare against PC or the data address as given by 411 // FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler 412 // Counter (CYCCNT). 413 #define CPU_DWT_COMP0_COMP_W 32 414 #define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF 415 #define CPU_DWT_COMP0_COMP_S 0 416 417 //***************************************************************************** 418 // 419 // Register: CPU_DWT_O_MASK0 420 // 421 //***************************************************************************** 422 // Field: [3:0] MASK 423 // 424 // Mask on data address when matching against COMP0. This is the size of the 425 // ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF 426 // left bit-shifted by MASK)) == COMP0. However, the actual comparison is 427 // slightly more complex to enable matching an address wherever it appears on a 428 // bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be 429 // within the word. 430 #define CPU_DWT_MASK0_MASK_W 4 431 #define CPU_DWT_MASK0_MASK_M 0x0000000F 432 #define CPU_DWT_MASK0_MASK_S 0 433 434 //***************************************************************************** 435 // 436 // Register: CPU_DWT_O_FUNCTION0 437 // 438 //***************************************************************************** 439 // Field: [24] MATCHED 440 // 441 // This bit is set when the comparator matches, and indicates that the 442 // operation defined by FUNCTION has occurred since this bit was last read. 443 // This bit is cleared on read. 444 #define CPU_DWT_FUNCTION0_MATCHED 0x01000000 445 #define CPU_DWT_FUNCTION0_MATCHED_BITN 24 446 #define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 447 #define CPU_DWT_FUNCTION0_MATCHED_S 24 448 449 // Field: [7] CYCMATCH 450 // 451 // This bit is only available in comparator 0. When set, COMP0 will compare 452 // against the cycle counter (CYCCNT). 453 #define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 454 #define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 455 #define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 456 #define CPU_DWT_FUNCTION0_CYCMATCH_S 7 457 458 // Field: [5] EMITRANGE 459 // 460 // Emit range field. This bit permits emitting offset when range match occurs. 461 // PC sampling is not supported when emit range is enabled. 462 // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. 463 #define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 464 #define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 465 #define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 466 #define CPU_DWT_FUNCTION0_EMITRANGE_S 5 467 468 // Field: [3:0] FUNCTION 469 // 470 // Function settings. 471 // 472 // 0x0: Disabled 473 // 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit 474 // address offset through ITM 475 // 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, 476 // emit data and address offset through ITM on read or write. 477 // 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. 478 // EMITRANGE = 1, emit address offset and data value through ITM on read or 479 // write. 480 // 0x4: Watchpoint on PC match. 481 // 0x5: Watchpoint on read. 482 // 0x6: Watchpoint on write. 483 // 0x7: Watchpoint on read or write. 484 // 0x8: ETM trigger on PC match 485 // 0x9: ETM trigger on read 486 // 0xA: ETM trigger on write 487 // 0xB: ETM trigger on read or write 488 // 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample 489 // Daddr (lower 16 bits) for read transfers 490 // 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample 491 // Daddr (lower 16 bits) for write transfers 492 // 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, 493 // sample Daddr (lower 16 bits) + data for read transfers 494 // 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, 495 // sample Daddr (lower 16 bits) + data for write transfers 496 // 497 // Note 1: If the ETM is not fitted, then ETM trigger is not possible. 498 // Note 2: Data value is only sampled for accesses that do not fault (MPU or 499 // bus fault). The PC is sampled irrespective of any faults. The PC is only 500 // sampled for the first address of a burst. 501 // Note 3: PC match is not recommended for watchpoints because it stops after 502 // the instruction. It mainly guards and triggers the ETM. 503 #define CPU_DWT_FUNCTION0_FUNCTION_W 4 504 #define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F 505 #define CPU_DWT_FUNCTION0_FUNCTION_S 0 506 507 //***************************************************************************** 508 // 509 // Register: CPU_DWT_O_COMP1 510 // 511 //***************************************************************************** 512 // Field: [31:0] COMP 513 // 514 // Reference value to compare against PC or the data address as given by 515 // FUNCTION1. 516 // Comparator 1 can also compare data values. So this register can contain 517 // reference values for data matching. 518 #define CPU_DWT_COMP1_COMP_W 32 519 #define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF 520 #define CPU_DWT_COMP1_COMP_S 0 521 522 //***************************************************************************** 523 // 524 // Register: CPU_DWT_O_MASK1 525 // 526 //***************************************************************************** 527 // Field: [3:0] MASK 528 // 529 // Mask on data address when matching against COMP1. This is the size of the 530 // ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF 531 // left bit-shifted by MASK)) == COMP1. However, the actual comparison is 532 // slightly more complex to enable matching an address wherever it appears on a 533 // bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be 534 // within the word. 535 #define CPU_DWT_MASK1_MASK_W 4 536 #define CPU_DWT_MASK1_MASK_M 0x0000000F 537 #define CPU_DWT_MASK1_MASK_S 0 538 539 //***************************************************************************** 540 // 541 // Register: CPU_DWT_O_FUNCTION1 542 // 543 //***************************************************************************** 544 // Field: [24] MATCHED 545 // 546 // This bit is set when the comparator matches, and indicates that the 547 // operation defined by FUNCTION has occurred since this bit was last read. 548 // This bit is cleared on read. 549 #define CPU_DWT_FUNCTION1_MATCHED 0x01000000 550 #define CPU_DWT_FUNCTION1_MATCHED_BITN 24 551 #define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 552 #define CPU_DWT_FUNCTION1_MATCHED_S 24 553 554 // Field: [19:16] DATAVADDR1 555 // 556 // Identity of a second linked address comparator for data value matching when 557 // DATAVMATCH == 1 and LNK1ENA == 1. 558 #define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 559 #define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 560 #define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 561 562 // Field: [15:12] DATAVADDR0 563 // 564 // Identity of a linked address comparator for data value matching when 565 // DATAVMATCH == 1. 566 #define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 567 #define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 568 #define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 569 570 // Field: [11:10] DATAVSIZE 571 // 572 // Defines the size of the data in the COMP1 register that is to be matched: 573 // 574 // 0x0: Byte 575 // 0x1: Halfword 576 // 0x2: Word 577 // 0x3: Unpredictable. 578 #define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 579 #define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 580 #define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 581 582 // Field: [9] LNK1ENA 583 // 584 // Read only bit-field only supported in comparator 1. 585 // 586 // 0: DATAVADDR1 not supported 587 // 1: DATAVADDR1 supported (enabled) 588 #define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 589 #define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 590 #define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 591 #define CPU_DWT_FUNCTION1_LNK1ENA_S 9 592 593 // Field: [8] DATAVMATCH 594 // 595 // Data match feature: 596 // 597 // 0: Perform address comparison 598 // 1: Perform data value compare. The comparators given by DATAVADDR0 and 599 // DATAVADDR1 provide the address for the data comparison. The FUNCTION setting 600 // for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and 601 // those comparators only provide the address match for the data comparison. 602 // 603 // This bit is only available in comparator 1. 604 #define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 605 #define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 606 #define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 607 #define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 608 609 // Field: [5] EMITRANGE 610 // 611 // Emit range field. This bit permits emitting offset when range match occurs. 612 // PC sampling is not supported when emit range is enabled. 613 // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. 614 #define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 615 #define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 616 #define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 617 #define CPU_DWT_FUNCTION1_EMITRANGE_S 5 618 619 // Field: [3:0] FUNCTION 620 // 621 // Function settings: 622 // 623 // 0x0: Disabled 624 // 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit 625 // address offset through ITM 626 // 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, 627 // emit data and address offset through ITM on read or write. 628 // 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. 629 // EMITRANGE = 1, emit address offset and data value through ITM on read or 630 // write. 631 // 0x4: Watchpoint on PC match. 632 // 0x5: Watchpoint on read. 633 // 0x6: Watchpoint on write. 634 // 0x7: Watchpoint on read or write. 635 // 0x8: ETM trigger on PC match 636 // 0x9: ETM trigger on read 637 // 0xA: ETM trigger on write 638 // 0xB: ETM trigger on read or write 639 // 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample 640 // Daddr (lower 16 bits) for read transfers 641 // 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample 642 // Daddr (lower 16 bits) for write transfers 643 // 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, 644 // sample Daddr (lower 16 bits) + data for read transfers 645 // 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, 646 // sample Daddr (lower 16 bits) + data for write transfers 647 // 648 // Note 1: If the ETM is not fitted, then ETM trigger is not possible. 649 // Note 2: Data value is only sampled for accesses that do not fault (MPU or 650 // bus fault). The PC is sampled irrespective of any faults. The PC is only 651 // sampled for the first address of a burst. 652 // Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and 653 // DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 654 // and DATAVADDR1 can then only perform address comparator matches for 655 // comparator 1 data matches. 656 // Note 4: If the data matching functionality is not included during 657 // implementation it is not possible to set DATAVADDR0, DATAVADDR1, or 658 // DATAVMATCH. This means that the data matching functionality is not available 659 // in the implementation. Test the availability of data matching by writing and 660 // reading DATAVMATCH. If it is not settable then data matching is unavailable. 661 // Note 5: PC match is not recommended for watchpoints because it stops after 662 // the instruction. It mainly guards and triggers the ETM. 663 #define CPU_DWT_FUNCTION1_FUNCTION_W 4 664 #define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F 665 #define CPU_DWT_FUNCTION1_FUNCTION_S 0 666 667 //***************************************************************************** 668 // 669 // Register: CPU_DWT_O_COMP2 670 // 671 //***************************************************************************** 672 // Field: [31:0] COMP 673 // 674 // Reference value to compare against PC or the data address as given by 675 // FUNCTION2. 676 #define CPU_DWT_COMP2_COMP_W 32 677 #define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF 678 #define CPU_DWT_COMP2_COMP_S 0 679 680 //***************************************************************************** 681 // 682 // Register: CPU_DWT_O_MASK2 683 // 684 //***************************************************************************** 685 // Field: [3:0] MASK 686 // 687 // Mask on data address when matching against COMP2. This is the size of the 688 // ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF 689 // left bit-shifted by MASK)) == COMP2. However, the actual comparison is 690 // slightly more complex to enable matching an address wherever it appears on a 691 // bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be 692 // within the word. 693 #define CPU_DWT_MASK2_MASK_W 4 694 #define CPU_DWT_MASK2_MASK_M 0x0000000F 695 #define CPU_DWT_MASK2_MASK_S 0 696 697 //***************************************************************************** 698 // 699 // Register: CPU_DWT_O_FUNCTION2 700 // 701 //***************************************************************************** 702 // Field: [24] MATCHED 703 // 704 // This bit is set when the comparator matches, and indicates that the 705 // operation defined by FUNCTION has occurred since this bit was last read. 706 // This bit is cleared on read. 707 #define CPU_DWT_FUNCTION2_MATCHED 0x01000000 708 #define CPU_DWT_FUNCTION2_MATCHED_BITN 24 709 #define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 710 #define CPU_DWT_FUNCTION2_MATCHED_S 24 711 712 // Field: [5] EMITRANGE 713 // 714 // Emit range field. This bit permits emitting offset when range match occurs. 715 // PC sampling is not supported when emit range is enabled. 716 // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. 717 #define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 718 #define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 719 #define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 720 #define CPU_DWT_FUNCTION2_EMITRANGE_S 5 721 722 // Field: [3:0] FUNCTION 723 // 724 // Function settings. 725 // 726 // 0x0: Disabled 727 // 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit 728 // address offset through ITM 729 // 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, 730 // emit data and address offset through ITM on read or write. 731 // 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. 732 // EMITRANGE = 1, emit address offset and data value through ITM on read or 733 // write. 734 // 0x4: Watchpoint on PC match. 735 // 0x5: Watchpoint on read. 736 // 0x6: Watchpoint on write. 737 // 0x7: Watchpoint on read or write. 738 // 0x8: ETM trigger on PC match 739 // 0x9: ETM trigger on read 740 // 0xA: ETM trigger on write 741 // 0xB: ETM trigger on read or write 742 // 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample 743 // Daddr (lower 16 bits) for read transfers 744 // 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample 745 // Daddr (lower 16 bits) for write transfers 746 // 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, 747 // sample Daddr (lower 16 bits) + data for read transfers 748 // 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, 749 // sample Daddr (lower 16 bits) + data for write transfers 750 // 751 // Note 1: If the ETM is not fitted, then ETM trigger is not possible. 752 // Note 2: Data value is only sampled for accesses that do not fault (MPU or 753 // bus fault). The PC is sampled irrespective of any faults. The PC is only 754 // sampled for the first address of a burst. 755 // Note 3: PC match is not recommended for watchpoints because it stops after 756 // the instruction. It mainly guards and triggers the ETM. 757 #define CPU_DWT_FUNCTION2_FUNCTION_W 4 758 #define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F 759 #define CPU_DWT_FUNCTION2_FUNCTION_S 0 760 761 //***************************************************************************** 762 // 763 // Register: CPU_DWT_O_COMP3 764 // 765 //***************************************************************************** 766 // Field: [31:0] COMP 767 // 768 // Reference value to compare against PC or the data address as given by 769 // FUNCTION3. 770 #define CPU_DWT_COMP3_COMP_W 32 771 #define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF 772 #define CPU_DWT_COMP3_COMP_S 0 773 774 //***************************************************************************** 775 // 776 // Register: CPU_DWT_O_MASK3 777 // 778 //***************************************************************************** 779 // Field: [3:0] MASK 780 // 781 // Mask on data address when matching against COMP3. This is the size of the 782 // ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF 783 // left bit-shifted by MASK)) == COMP3. However, the actual comparison is 784 // slightly more complex to enable matching an address wherever it appears on a 785 // bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be 786 // within the word. 787 #define CPU_DWT_MASK3_MASK_W 4 788 #define CPU_DWT_MASK3_MASK_M 0x0000000F 789 #define CPU_DWT_MASK3_MASK_S 0 790 791 //***************************************************************************** 792 // 793 // Register: CPU_DWT_O_FUNCTION3 794 // 795 //***************************************************************************** 796 // Field: [24] MATCHED 797 // 798 // This bit is set when the comparator matches, and indicates that the 799 // operation defined by FUNCTION has occurred since this bit was last read. 800 // This bit is cleared on read. 801 #define CPU_DWT_FUNCTION3_MATCHED 0x01000000 802 #define CPU_DWT_FUNCTION3_MATCHED_BITN 24 803 #define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 804 #define CPU_DWT_FUNCTION3_MATCHED_S 24 805 806 // Field: [5] EMITRANGE 807 // 808 // Emit range field. This bit permits emitting offset when range match occurs. 809 // PC sampling is not supported when emit range is enabled. 810 // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. 811 #define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 812 #define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 813 #define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 814 #define CPU_DWT_FUNCTION3_EMITRANGE_S 5 815 816 // Field: [3:0] FUNCTION 817 // 818 // Function settings. 819 // 820 // 0x0: Disabled 821 // 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit 822 // address offset through ITM 823 // 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, 824 // emit data and address offset through ITM on read or write. 825 // 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. 826 // EMITRANGE = 1, emit address offset and data value through ITM on read or 827 // write. 828 // 0x4: Watchpoint on PC match. 829 // 0x5: Watchpoint on read. 830 // 0x6: Watchpoint on write. 831 // 0x7: Watchpoint on read or write. 832 // 0x8: ETM trigger on PC match 833 // 0x9: ETM trigger on read 834 // 0xA: ETM trigger on write 835 // 0xB: ETM trigger on read or write 836 // 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample 837 // Daddr (lower 16 bits) for read transfers 838 // 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample 839 // Daddr (lower 16 bits) for write transfers 840 // 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, 841 // sample Daddr (lower 16 bits) + data for read transfers 842 // 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, 843 // sample Daddr (lower 16 bits) + data for write transfers 844 // 845 // Note 1: If the ETM is not fitted, then ETM trigger is not possible. 846 // Note 2: Data value is only sampled for accesses that do not fault (MPU or 847 // bus fault). The PC is sampled irrespective of any faults. The PC is only 848 // sampled for the first address of a burst. 849 // Note 3: PC match is not recommended for watchpoints because it stops after 850 // the instruction. It mainly guards and triggers the ETM. 851 #define CPU_DWT_FUNCTION3_FUNCTION_W 4 852 #define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F 853 #define CPU_DWT_FUNCTION3_FUNCTION_S 0 854 855 856 #endif // __CPU_DWT__ 857
