1 /****************************************************************************** 2 * Filename: hw_aux_timer2_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AUX_TIMER2_H__ 38 #define __HW_AUX_TIMER2_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AUX_TIMER2 component 44 // 45 //***************************************************************************** 46 // Timer Control 47 #define AUX_TIMER2_O_CTL 0x00000000 48 49 // Target 50 #define AUX_TIMER2_O_TARGET 0x00000004 51 52 // Shadow Target 53 #define AUX_TIMER2_O_SHDWTARGET 0x00000008 54 55 // Counter 56 #define AUX_TIMER2_O_CNTR 0x0000000C 57 58 // Clock Prescaler Configuration 59 #define AUX_TIMER2_O_PRECFG 0x00000010 60 61 // Event Control 62 #define AUX_TIMER2_O_EVCTL 0x00000014 63 64 // Pulse Trigger 65 #define AUX_TIMER2_O_PULSETRIG 0x00000018 66 67 // Channel 0 Event Configuration 68 #define AUX_TIMER2_O_CH0EVCFG 0x00000080 69 70 // Channel 0 Capture Configuration 71 #define AUX_TIMER2_O_CH0CCFG 0x00000084 72 73 // Channel 0 Pipeline Capture Compare 74 #define AUX_TIMER2_O_CH0PCC 0x00000088 75 76 // Channel 0 Capture Compare 77 #define AUX_TIMER2_O_CH0CC 0x0000008C 78 79 // Channel 1 Event Configuration 80 #define AUX_TIMER2_O_CH1EVCFG 0x00000090 81 82 // Channel 1 Capture Configuration 83 #define AUX_TIMER2_O_CH1CCFG 0x00000094 84 85 // Channel 1 Pipeline Capture Compare 86 #define AUX_TIMER2_O_CH1PCC 0x00000098 87 88 // Channel 1 Capture Compare 89 #define AUX_TIMER2_O_CH1CC 0x0000009C 90 91 // Channel 2 Event Configuration 92 #define AUX_TIMER2_O_CH2EVCFG 0x000000A0 93 94 // Channel 2 Capture Configuration 95 #define AUX_TIMER2_O_CH2CCFG 0x000000A4 96 97 // Channel 2 Pipeline Capture Compare 98 #define AUX_TIMER2_O_CH2PCC 0x000000A8 99 100 // Channel 2 Capture Compare 101 #define AUX_TIMER2_O_CH2CC 0x000000AC 102 103 // Channel 3 Event Configuration 104 #define AUX_TIMER2_O_CH3EVCFG 0x000000B0 105 106 // Channel 3 Capture Configuration 107 #define AUX_TIMER2_O_CH3CCFG 0x000000B4 108 109 // Channel 3 Pipeline Capture Compare 110 #define AUX_TIMER2_O_CH3PCC 0x000000B8 111 112 // Channel 3 Capture Compare 113 #define AUX_TIMER2_O_CH3CC 0x000000BC 114 115 //***************************************************************************** 116 // 117 // Register: AUX_TIMER2_O_CTL 118 // 119 //***************************************************************************** 120 // Field: [6] CH3_RESET 121 // 122 // Channel 3 reset. 123 // 124 // 0: No effect. 125 // 1: Reset CH3CC, CH3PCC, CH3EVCFG, and CH3CCFG. 126 // 127 // Read returns 0. 128 #define AUX_TIMER2_CTL_CH3_RESET 0x00000040 129 #define AUX_TIMER2_CTL_CH3_RESET_BITN 6 130 #define AUX_TIMER2_CTL_CH3_RESET_M 0x00000040 131 #define AUX_TIMER2_CTL_CH3_RESET_S 6 132 133 // Field: [5] CH2_RESET 134 // 135 // Channel 2 reset. 136 // 137 // 0: No effect. 138 // 1: Reset CH2CC, CH2PCC, CH2EVCFG, and CH2CCFG. 139 // 140 // Read returns 0. 141 #define AUX_TIMER2_CTL_CH2_RESET 0x00000020 142 #define AUX_TIMER2_CTL_CH2_RESET_BITN 5 143 #define AUX_TIMER2_CTL_CH2_RESET_M 0x00000020 144 #define AUX_TIMER2_CTL_CH2_RESET_S 5 145 146 // Field: [4] CH1_RESET 147 // 148 // Channel 1 reset. 149 // 150 // 0: No effect. 151 // 1: Reset CH1CC, CH1PCC, CH1EVCFG, and CH1CCFG. 152 // 153 // Read returns 0. 154 #define AUX_TIMER2_CTL_CH1_RESET 0x00000010 155 #define AUX_TIMER2_CTL_CH1_RESET_BITN 4 156 #define AUX_TIMER2_CTL_CH1_RESET_M 0x00000010 157 #define AUX_TIMER2_CTL_CH1_RESET_S 4 158 159 // Field: [3] CH0_RESET 160 // 161 // Channel 0 reset. 162 // 163 // 0: No effect. 164 // 1: Reset CH0CC, CH0PCC, CH0EVCFG, and CH0CCFG. 165 // 166 // Read returns 0. 167 #define AUX_TIMER2_CTL_CH0_RESET 0x00000008 168 #define AUX_TIMER2_CTL_CH0_RESET_BITN 3 169 #define AUX_TIMER2_CTL_CH0_RESET_M 0x00000008 170 #define AUX_TIMER2_CTL_CH0_RESET_S 3 171 172 // Field: [2] TARGET_EN 173 // 174 // Select counter target value. 175 // 176 // You must select TARGET to use shadow target functionality. 177 // ENUMs: 178 // TARGET TARGET.VALUE 179 // CNTR_MAX 65535 180 #define AUX_TIMER2_CTL_TARGET_EN 0x00000004 181 #define AUX_TIMER2_CTL_TARGET_EN_BITN 2 182 #define AUX_TIMER2_CTL_TARGET_EN_M 0x00000004 183 #define AUX_TIMER2_CTL_TARGET_EN_S 2 184 #define AUX_TIMER2_CTL_TARGET_EN_TARGET 0x00000004 185 #define AUX_TIMER2_CTL_TARGET_EN_CNTR_MAX 0x00000000 186 187 // Field: [1:0] MODE 188 // 189 // Timer mode control. 190 // 191 // The timer restarts from 0 when you set MODE to UP_ONCE, UP_PER, or 192 // UPDWN_PER. 193 // 194 // When you write MODE all internally queued updates to [CHnCC.*] and TARGET 195 // clear. 196 // ENUMs: 197 // UPDWN_PER Count up and down periodically. The timer counts 198 // from 0 to target value and back to 0, 199 // repeatedly. 200 // 201 // Period = (target value * 202 // 2) * timer clock period 203 // UP_PER Count up periodically. The timer increments from 0 204 // to target value, repeatedly. 205 // 206 // Period = (target value + 207 // 1) * timer clock period 208 // UP_ONCE Count up once. The timer increments from 0 to 209 // target value, then stops and sets MODE to DIS. 210 // DIS Disable timer. Updates to counter, channels, and 211 // events stop. 212 #define AUX_TIMER2_CTL_MODE_W 2 213 #define AUX_TIMER2_CTL_MODE_M 0x00000003 214 #define AUX_TIMER2_CTL_MODE_S 0 215 #define AUX_TIMER2_CTL_MODE_UPDWN_PER 0x00000003 216 #define AUX_TIMER2_CTL_MODE_UP_PER 0x00000002 217 #define AUX_TIMER2_CTL_MODE_UP_ONCE 0x00000001 218 #define AUX_TIMER2_CTL_MODE_DIS 0x00000000 219 220 //***************************************************************************** 221 // 222 // Register: AUX_TIMER2_O_TARGET 223 // 224 //***************************************************************************** 225 // Field: [15:0] VALUE 226 // 227 // 16 bit user defined counter target value, which is used when selected by 228 // CTL.TARGET_EN. 229 #define AUX_TIMER2_TARGET_VALUE_W 16 230 #define AUX_TIMER2_TARGET_VALUE_M 0x0000FFFF 231 #define AUX_TIMER2_TARGET_VALUE_S 0 232 233 //***************************************************************************** 234 // 235 // Register: AUX_TIMER2_O_SHDWTARGET 236 // 237 //***************************************************************************** 238 // Field: [15:0] VALUE 239 // 240 // Target value for next counter period. 241 // 242 // The timer copies VALUE to TARGET.VALUE when CNTR.VALUE becomes 0. The copy 243 // does not happen when you restart the timer. 244 // 245 // This is useful to avoid period jitter in PWM applications with time-varying 246 // period, sometimes referenced as phase corrected PWM. 247 #define AUX_TIMER2_SHDWTARGET_VALUE_W 16 248 #define AUX_TIMER2_SHDWTARGET_VALUE_M 0x0000FFFF 249 #define AUX_TIMER2_SHDWTARGET_VALUE_S 0 250 251 //***************************************************************************** 252 // 253 // Register: AUX_TIMER2_O_CNTR 254 // 255 //***************************************************************************** 256 // Field: [15:0] VALUE 257 // 258 // 16 bit current counter value. 259 #define AUX_TIMER2_CNTR_VALUE_W 16 260 #define AUX_TIMER2_CNTR_VALUE_M 0x0000FFFF 261 #define AUX_TIMER2_CNTR_VALUE_S 0 262 263 //***************************************************************************** 264 // 265 // Register: AUX_TIMER2_O_PRECFG 266 // 267 //***************************************************************************** 268 // Field: [7:0] CLKDIV 269 // 270 // Clock division. 271 // 272 // CLKDIV determines the timer clock frequency for counter, synchronization, 273 // and timer event updates. The timer clock frequency is the clock selected by 274 // AUX_SYSIF:TIMER2CLKCTL.SRC divided by (CLKDIV + 1). This inverse is the 275 // timer clock period. 276 // 277 // 0x00: Divide by 1. 278 // 0x01: Divide by 2. 279 // ... 280 // 0xFF: Divide by 256. 281 #define AUX_TIMER2_PRECFG_CLKDIV_W 8 282 #define AUX_TIMER2_PRECFG_CLKDIV_M 0x000000FF 283 #define AUX_TIMER2_PRECFG_CLKDIV_S 0 284 285 //***************************************************************************** 286 // 287 // Register: AUX_TIMER2_O_EVCTL 288 // 289 //***************************************************************************** 290 // Field: [7] EV3_SET 291 // 292 // Set event 3. 293 // 294 // Write 1 to set event 3. 295 #define AUX_TIMER2_EVCTL_EV3_SET 0x00000080 296 #define AUX_TIMER2_EVCTL_EV3_SET_BITN 7 297 #define AUX_TIMER2_EVCTL_EV3_SET_M 0x00000080 298 #define AUX_TIMER2_EVCTL_EV3_SET_S 7 299 300 // Field: [6] EV3_CLR 301 // 302 // Clear event 3. 303 // 304 // Write 1 to clear event 3. 305 #define AUX_TIMER2_EVCTL_EV3_CLR 0x00000040 306 #define AUX_TIMER2_EVCTL_EV3_CLR_BITN 6 307 #define AUX_TIMER2_EVCTL_EV3_CLR_M 0x00000040 308 #define AUX_TIMER2_EVCTL_EV3_CLR_S 6 309 310 // Field: [5] EV2_SET 311 // 312 // Set event 2. 313 // 314 // Write 1 to set event 2. 315 #define AUX_TIMER2_EVCTL_EV2_SET 0x00000020 316 #define AUX_TIMER2_EVCTL_EV2_SET_BITN 5 317 #define AUX_TIMER2_EVCTL_EV2_SET_M 0x00000020 318 #define AUX_TIMER2_EVCTL_EV2_SET_S 5 319 320 // Field: [4] EV2_CLR 321 // 322 // Clear event 2. 323 // 324 // Write 1 to clear event 2. 325 #define AUX_TIMER2_EVCTL_EV2_CLR 0x00000010 326 #define AUX_TIMER2_EVCTL_EV2_CLR_BITN 4 327 #define AUX_TIMER2_EVCTL_EV2_CLR_M 0x00000010 328 #define AUX_TIMER2_EVCTL_EV2_CLR_S 4 329 330 // Field: [3] EV1_SET 331 // 332 // Set event 1. 333 // 334 // Write 1 to set event 1. 335 #define AUX_TIMER2_EVCTL_EV1_SET 0x00000008 336 #define AUX_TIMER2_EVCTL_EV1_SET_BITN 3 337 #define AUX_TIMER2_EVCTL_EV1_SET_M 0x00000008 338 #define AUX_TIMER2_EVCTL_EV1_SET_S 3 339 340 // Field: [2] EV1_CLR 341 // 342 // Clear event 1. 343 // 344 // Write 1 to clear event 1. 345 #define AUX_TIMER2_EVCTL_EV1_CLR 0x00000004 346 #define AUX_TIMER2_EVCTL_EV1_CLR_BITN 2 347 #define AUX_TIMER2_EVCTL_EV1_CLR_M 0x00000004 348 #define AUX_TIMER2_EVCTL_EV1_CLR_S 2 349 350 // Field: [1] EV0_SET 351 // 352 // Set event 0. 353 // 354 // Write 1 to set event 0. 355 #define AUX_TIMER2_EVCTL_EV0_SET 0x00000002 356 #define AUX_TIMER2_EVCTL_EV0_SET_BITN 1 357 #define AUX_TIMER2_EVCTL_EV0_SET_M 0x00000002 358 #define AUX_TIMER2_EVCTL_EV0_SET_S 1 359 360 // Field: [0] EV0_CLR 361 // 362 // Clear event 0. 363 // 364 // Write 1 to clear event 0. 365 #define AUX_TIMER2_EVCTL_EV0_CLR 0x00000001 366 #define AUX_TIMER2_EVCTL_EV0_CLR_BITN 0 367 #define AUX_TIMER2_EVCTL_EV0_CLR_M 0x00000001 368 #define AUX_TIMER2_EVCTL_EV0_CLR_S 0 369 370 //***************************************************************************** 371 // 372 // Register: AUX_TIMER2_O_PULSETRIG 373 // 374 //***************************************************************************** 375 // Field: [0] TRIG 376 // 377 // Pulse trigger. 378 // 379 // Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. Pulse 380 // width equals the duty cycle of AUX_SYSIF:TIMER2CLKCTL.SRC. 381 #define AUX_TIMER2_PULSETRIG_TRIG 0x00000001 382 #define AUX_TIMER2_PULSETRIG_TRIG_BITN 0 383 #define AUX_TIMER2_PULSETRIG_TRIG_M 0x00000001 384 #define AUX_TIMER2_PULSETRIG_TRIG_S 0 385 386 //***************************************************************************** 387 // 388 // Register: AUX_TIMER2_O_CH0EVCFG 389 // 390 //***************************************************************************** 391 // Field: [7] EV3_GEN 392 // 393 // Event 3 enable. 394 // 395 // 0: Channel 0 does not control event 3. 396 // 1: Channel 0 controls event 3. 397 // 398 // When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. 399 #define AUX_TIMER2_CH0EVCFG_EV3_GEN 0x00000080 400 #define AUX_TIMER2_CH0EVCFG_EV3_GEN_BITN 7 401 #define AUX_TIMER2_CH0EVCFG_EV3_GEN_M 0x00000080 402 #define AUX_TIMER2_CH0EVCFG_EV3_GEN_S 7 403 404 // Field: [6] EV2_GEN 405 // 406 // Event 2 enable. 407 // 408 // 0: Channel 0 does not control event 2. 409 // 1: Channel 0 controls event 2. 410 // 411 // When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. 412 #define AUX_TIMER2_CH0EVCFG_EV2_GEN 0x00000040 413 #define AUX_TIMER2_CH0EVCFG_EV2_GEN_BITN 6 414 #define AUX_TIMER2_CH0EVCFG_EV2_GEN_M 0x00000040 415 #define AUX_TIMER2_CH0EVCFG_EV2_GEN_S 6 416 417 // Field: [5] EV1_GEN 418 // 419 // Event 1 enable. 420 // 421 // 0: Channel 0 does not control event 1. 422 // 1: Channel 0 controls event 1. 423 // 424 // When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. 425 #define AUX_TIMER2_CH0EVCFG_EV1_GEN 0x00000020 426 #define AUX_TIMER2_CH0EVCFG_EV1_GEN_BITN 5 427 #define AUX_TIMER2_CH0EVCFG_EV1_GEN_M 0x00000020 428 #define AUX_TIMER2_CH0EVCFG_EV1_GEN_S 5 429 430 // Field: [4] EV0_GEN 431 // 432 // Event 0 enable. 433 // 434 // 0: Channel 0 does not control event 0. 435 // 1: Channel 0 controls event 0. 436 // 437 // When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. 438 #define AUX_TIMER2_CH0EVCFG_EV0_GEN 0x00000010 439 #define AUX_TIMER2_CH0EVCFG_EV0_GEN_BITN 4 440 #define AUX_TIMER2_CH0EVCFG_EV0_GEN_M 0x00000010 441 #define AUX_TIMER2_CH0EVCFG_EV0_GEN_S 4 442 443 // Field: [3:0] CCACT 444 // 445 // Capture-Compare action. 446 // 447 // Capture-Compare action defines 15 different channel functions that utilize 448 // capture, compare, and zero events. 449 // ENUMs: 450 // PULSE_ON_CMP Pulse on compare repeatedly. 451 // 452 // Channel function 453 // sequence: 454 // - Pulse enabled events 455 // when CH0CC.VALUE = CNTR.VALUE. 456 // 457 // The event is high for 458 // two timer clock periods. 459 // TGL_ON_CMP Toggle on compare repeatedly. 460 // 461 // Channel function 462 // sequence: 463 // - Toggle enabled events 464 // when CH0CC.VALUE = CNTR.VALUE. 465 // SET_ON_CMP Set on compare repeatedly. 466 // 467 // Channel function 468 // sequence: 469 // - Set enabled events 470 // when CH0CC.VALUE = CNTR.VALUE. 471 // CLR_ON_CMP Clear on compare repeatedly. 472 // 473 // Channel function 474 // sequence: 475 // - Clear enabled events 476 // when CH0CC.VALUE = CNTR.VALUE. 477 // SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. 478 // 479 // Channel function 480 // sequence: 481 // - Set enabled events when 482 // CNTR.VALUE = 0. 483 // - Toggle enabled events 484 // when CH0CC.VALUE = CNTR.VALUE. 485 // 486 // Set CTL.MODE to UP_PER 487 // for edge-aligned PWM generation. Duty cycle is 488 // given by: 489 // 490 // When CH0CC.VALUE <= 491 // TARGET.VALUE: 492 // Duty cycle = 493 // CH0CC.VALUE / ( TARGET.VALUE + 1 ). 494 // 495 // When CH0CC.VALUE > 496 // TARGET.VALUE: 497 // Duty cycle = 1. 498 // 499 // Enabled events are 500 // cleared when CH0CC.VALUE = 0 and CNTR.VALUE = 501 // 0. 502 // CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. 503 // 504 // Channel function 505 // sequence: 506 // - Clear enabled events 507 // when CNTR.VALUE = 0. 508 // - Toggle enabled events 509 // when CH0CC.VALUE = CNTR.VALUE. 510 // 511 // Set CTL.MODE to UPDWN_PER 512 // for center-aligned PWM generation. Duty cycle 513 // is given by: 514 // 515 // When CH0CC.VALUE <= 516 // TARGET.VALUE: 517 // Duty cycle = 1 - ( 518 // CH0CC.VALUE / TARGET.VALUE ). 519 // 520 // When CH0CC.VALUE > 521 // TARGET.VALUE: 522 // Duty cycle = 0. 523 // 524 // Enabled events are set 525 // when CH0CC.VALUE = 0 and CNTR.VALUE = 0. 526 // SET_ON_CAPT Set on capture repeatedly. 527 // 528 // Channel function 529 // sequence: 530 // - Set enabled events on 531 // capture event and copy CNTR.VALUE to 532 // CH0CC.VALUE. 533 // 534 // Primary use scenario is 535 // to select this function before you start the 536 // timer. 537 // Follow these steps if you 538 // need to select this function while CTL.MODE is 539 // different from DIS: 540 // - Select this function 541 // with no event enable. 542 // - Configure CH0CCFG 543 // (optional). 544 // - Wait for three timer 545 // clock periods as defined in PRECFG before you 546 // enable events. 547 // 548 // These steps prevent 549 // capture events caused by expired signal values 550 // in edge-detection circuit. 551 // PER_PULSE_WIDTH_MEAS Period and pulse width measurement. 552 // 553 // Continuously capture 554 // period and pulse width of the signal selected 555 // by CH0CCFG.CAPT_SRC relative to the signal edge 556 // given by CH0CCFG.EDGE. 557 // 558 // Set enabled events when 559 // CH0CC.VALUE contains signal period and 560 // CH0PCC.VALUE contains signal pulse width. 561 // 562 // Notes: 563 // - Make sure that you 564 // configure CH0CCFG.CAPT_SRC and CCACT when 565 // CTL.MODE equals DIS, then set CTL.MODE to 566 // UP_ONCE or UP_PER. 567 // - The counter restarts in 568 // the selected timer mode when CH0CC.VALUE 569 // contains the signal period. 570 // - If more than one 571 // channel uses this function, the channels will 572 // perform this function one at a time. The 573 // channel with lowest number has priority and 574 // performs the function first. Next measurement 575 // starts when current measurement completes 576 // successfully or times out. A timeout occurs 577 // when counter equals target. 578 // - If you want to observe 579 // a timeout event configure another channel to 580 // SET_ON_CAPT. 581 // 582 // Signal property 583 // requirements: 584 // - Signal Period >= 2 * ( 585 // 1 + PRECFG.CLKDIV ) * timer clock period. 586 // - Signal Period <= 65535 587 // * (1 + PRECFG.CLKDIV ) * timer clock period. 588 // - Signal low and high 589 // phase >= (1 + PRECFG.CLKDIV ) * timer clock 590 // period. 591 // PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. 592 // 593 // Channel function 594 // sequence: 595 // - Pulse enabled events 596 // when CH0CC.VALUE = CNTR.VALUE. 597 // - Disable channel. 598 // 599 // The event is high for 600 // two timer clock periods. 601 // TGL_ON_CMP_DIS Toggle on compare, and then disable channel. 602 // 603 // Channel function 604 // sequence: 605 // - Toggle enabled events 606 // when CH0CC.VALUE = CNTR.VALUE. 607 // - Disable channel. 608 // SET_ON_CMP_DIS Set on compare, and then disable channel. 609 // 610 // Channel function 611 // sequence: 612 // - Set enabled events when 613 // CH0CC.VALUE = CNTR.VALUE. 614 // - Disable channel. 615 // CLR_ON_CMP_DIS Clear on compare, and then disable channel. 616 // 617 // Channel function 618 // sequence: 619 // - Clear enabled events 620 // when CH0CC.VALUE = CNTR.VALUE. 621 // - Disable channel. 622 // SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable 623 // channel. 624 // 625 // Channel function 626 // sequence: 627 // - Set enabled events when 628 // CNTR.VALUE = 0. 629 // - Toggle enabled events 630 // when CH0CC.VALUE = CNTR.VALUE. 631 // - Disable channel. 632 // 633 // Enabled events are 634 // cleared when CH0CC.VALUE = 0 and CNTR.VALUE = 635 // 0. 636 // CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable 637 // channel. 638 // 639 // Channel function 640 // sequence: 641 // - Clear enabled events 642 // when CNTR.VALUE = 0. 643 // - Toggle enabled events 644 // when CH0CC.VALUE = CNTR.VALUE. 645 // - Disable channel. 646 // 647 // Enabled events are set 648 // when CH0CC.VALUE = 0 and CNTR.VALUE = 0. 649 // SET_ON_CAPT_DIS Set on capture, and then disable channel. 650 // 651 // Channel function 652 // sequence: 653 // - Set enabled events on 654 // capture event and copy CNTR.VALUE to 655 // CH0CC.VALUE. 656 // - Disable channel. 657 // 658 // Primary use scenario is 659 // to select this function before you start the 660 // timer. 661 // Follow these steps if you 662 // need to select this function while CTL.MODE is 663 // different from DIS: 664 // - Set CCACT to 665 // SET_ON_CAPT with no event enable. 666 // - Configure CH0CCFG 667 // (optional). 668 // - Wait for three timer 669 // clock periods as defined in PRECFG before you 670 // set CCACT to SET_ON_CAPT_DIS. Event enable is 671 // optional. 672 // 673 // These steps prevent 674 // capture events caused by expired signal values 675 // in edge-detection circuit. 676 // DIS Disable channel. 677 #define AUX_TIMER2_CH0EVCFG_CCACT_W 4 678 #define AUX_TIMER2_CH0EVCFG_CCACT_M 0x0000000F 679 #define AUX_TIMER2_CH0EVCFG_CCACT_S 0 680 #define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP 0x0000000F 681 #define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP 0x0000000E 682 #define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP 0x0000000D 683 #define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP 0x0000000C 684 #define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B 685 #define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A 686 #define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT 0x00000009 687 #define AUX_TIMER2_CH0EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 688 #define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 689 #define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 690 #define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 691 #define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 692 #define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 693 #define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 694 #define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 695 #define AUX_TIMER2_CH0EVCFG_CCACT_DIS 0x00000000 696 697 //***************************************************************************** 698 // 699 // Register: AUX_TIMER2_O_CH0CCFG 700 // 701 //***************************************************************************** 702 // Field: [6:1] CAPT_SRC 703 // 704 // Select capture signal source from the asynchronous AUX event bus. 705 // 706 // The selected signal enters the edge-detection circuit. False capture events 707 // can occur when: 708 // - the edge-detection circuit contains expired signal samples and the circuit 709 // is enabled without flush as described in CH0EVCFG 710 // - this register is reconfigured while CTL.MODE is different from DIS. 711 // 712 // You can avoid false capture events. When wanted channel function is: 713 // - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH0EVCFG.CCACT. 714 // - SET_ON_CAPT, see description for SET_ON_CAPT in CH0EVCFG.CCACT. 715 // - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in 716 // CH0EVCFG.CCACT. 717 // 718 // If you write a non-enumerated value the behavior is identical to NO_EVENT. 719 // The written value is returned when read. 720 // ENUMs: 721 // NO_EVENT No event. 722 // AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 723 // AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 724 // AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 725 // AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 726 // AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 727 // AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 728 // AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 729 // AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 730 // AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 731 // AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 732 // AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 733 // AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 734 // AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 735 // AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB 736 // AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA 737 // MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 738 // MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 739 // MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV 740 // ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF 741 // VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 742 // MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE 743 // PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN 744 // SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF 745 // AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 746 // AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 747 // AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 748 // AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 749 // AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 750 // MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV 751 // AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 752 // AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 753 // AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 754 // AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 755 // AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 756 // AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 757 // AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 758 // AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 759 // AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 760 // AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 761 // AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 762 // AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 763 // AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 764 // AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 765 // AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 766 // AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 767 // AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 768 // AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 769 // AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 770 // AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 771 // AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 772 // AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 773 // AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 774 // AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 775 // AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 776 // AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 777 // AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 778 // AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 779 // AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 780 // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 781 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 782 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 783 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_W 6 784 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_M 0x0000007E 785 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_S 1 786 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_NO_EVENT 0x0000007E 787 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A 788 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 789 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 790 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 791 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 792 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 793 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E 794 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C 795 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A 796 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 797 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 798 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 799 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 800 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPB 0x0000005E 801 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPA 0x0000005C 802 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A 803 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 804 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_EV 0x00000056 805 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_ACLK_REF 0x00000054 806 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 807 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 808 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_PWR_DWN 0x0000004E 809 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_SCLK_LF 0x0000004C 810 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A 811 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 812 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 813 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 814 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 815 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_MANUAL_EV 0x00000040 816 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO31 0x0000003E 817 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO30 0x0000003C 818 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO29 0x0000003A 819 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO28 0x00000038 820 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO27 0x00000036 821 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO26 0x00000034 822 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO25 0x00000032 823 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO24 0x00000030 824 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO23 0x0000002E 825 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO22 0x0000002C 826 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO21 0x0000002A 827 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO20 0x00000028 828 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO19 0x00000026 829 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO18 0x00000024 830 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO17 0x00000022 831 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO16 0x00000020 832 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO15 0x0000001E 833 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO14 0x0000001C 834 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO13 0x0000001A 835 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO12 0x00000018 836 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO11 0x00000016 837 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO10 0x00000014 838 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO9 0x00000012 839 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO8 0x00000010 840 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO7 0x0000000E 841 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO6 0x0000000C 842 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO5 0x0000000A 843 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO4 0x00000008 844 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO3 0x00000006 845 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO2 0x00000004 846 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO1 0x00000002 847 #define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO0 0x00000000 848 849 // Field: [0] EDGE 850 // 851 // Edge configuration. 852 // 853 // Channel captures counter value at selected edge on signal source selected by 854 // CAPT_SRC. See CH0EVCFG.CCACT. 855 // ENUMs: 856 // RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. 857 // FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. 858 #define AUX_TIMER2_CH0CCFG_EDGE 0x00000001 859 #define AUX_TIMER2_CH0CCFG_EDGE_BITN 0 860 #define AUX_TIMER2_CH0CCFG_EDGE_M 0x00000001 861 #define AUX_TIMER2_CH0CCFG_EDGE_S 0 862 #define AUX_TIMER2_CH0CCFG_EDGE_RISING 0x00000001 863 #define AUX_TIMER2_CH0CCFG_EDGE_FALLING 0x00000000 864 865 //***************************************************************************** 866 // 867 // Register: AUX_TIMER2_O_CH0PCC 868 // 869 //***************************************************************************** 870 // Field: [15:0] VALUE 871 // 872 // Pipeline Capture Compare value. 873 // 874 // 16-bit user defined pipeline compare value or channel-updated capture value. 875 // 876 // Compare mode: 877 // An update of VALUE will be transferred to CH0CC.VALUE when the next 878 // CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for 879 // PWM generation and prevents jitter on the edges of the generated signal. 880 // 881 // Capture mode: 882 // When CH0EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the 883 // width of the low or high phase of the selected signal. This is specified by 884 // CH0CCFG.EDGE and CH0CCFG.CAPT_SRC. 885 #define AUX_TIMER2_CH0PCC_VALUE_W 16 886 #define AUX_TIMER2_CH0PCC_VALUE_M 0x0000FFFF 887 #define AUX_TIMER2_CH0PCC_VALUE_S 0 888 889 //***************************************************************************** 890 // 891 // Register: AUX_TIMER2_O_CH0CC 892 // 893 //***************************************************************************** 894 // Field: [15:0] VALUE 895 // 896 // Capture Compare value. 897 // 898 // 16-bit user defined compare value or channel-updated capture value. 899 // 900 // Compare mode: 901 // VALUE is compared against CNTR.VALUE and an event is generated as specified 902 // by CH0EVCFG.CCACT when these are equal. 903 // 904 // Capture mode: 905 // The current counter value is stored in VALUE when a capture event occurs. 906 // CH0EVCFG.CCACT determines if VALUE is a signal period or a regular capture 907 // value. 908 #define AUX_TIMER2_CH0CC_VALUE_W 16 909 #define AUX_TIMER2_CH0CC_VALUE_M 0x0000FFFF 910 #define AUX_TIMER2_CH0CC_VALUE_S 0 911 912 //***************************************************************************** 913 // 914 // Register: AUX_TIMER2_O_CH1EVCFG 915 // 916 //***************************************************************************** 917 // Field: [7] EV3_GEN 918 // 919 // Event 3 enable. 920 // 921 // 0: Channel 1 does not control event 3. 922 // 1: Channel 1 controls event 3. 923 // 924 // When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. 925 #define AUX_TIMER2_CH1EVCFG_EV3_GEN 0x00000080 926 #define AUX_TIMER2_CH1EVCFG_EV3_GEN_BITN 7 927 #define AUX_TIMER2_CH1EVCFG_EV3_GEN_M 0x00000080 928 #define AUX_TIMER2_CH1EVCFG_EV3_GEN_S 7 929 930 // Field: [6] EV2_GEN 931 // 932 // Event 2 enable. 933 // 934 // 0: Channel 1 does not control event 2. 935 // 1: Channel 1 controls event 2. 936 // 937 // When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. 938 #define AUX_TIMER2_CH1EVCFG_EV2_GEN 0x00000040 939 #define AUX_TIMER2_CH1EVCFG_EV2_GEN_BITN 6 940 #define AUX_TIMER2_CH1EVCFG_EV2_GEN_M 0x00000040 941 #define AUX_TIMER2_CH1EVCFG_EV2_GEN_S 6 942 943 // Field: [5] EV1_GEN 944 // 945 // Event 1 enable. 946 // 947 // 0: Channel 1 does not control event 1. 948 // 1: Channel 1 controls event 1. 949 // 950 // When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. 951 #define AUX_TIMER2_CH1EVCFG_EV1_GEN 0x00000020 952 #define AUX_TIMER2_CH1EVCFG_EV1_GEN_BITN 5 953 #define AUX_TIMER2_CH1EVCFG_EV1_GEN_M 0x00000020 954 #define AUX_TIMER2_CH1EVCFG_EV1_GEN_S 5 955 956 // Field: [4] EV0_GEN 957 // 958 // Event 0 enable. 959 // 960 // 0: Channel 1 does not control event 0. 961 // 1: Channel 1 controls event 0. 962 // 963 // When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. 964 #define AUX_TIMER2_CH1EVCFG_EV0_GEN 0x00000010 965 #define AUX_TIMER2_CH1EVCFG_EV0_GEN_BITN 4 966 #define AUX_TIMER2_CH1EVCFG_EV0_GEN_M 0x00000010 967 #define AUX_TIMER2_CH1EVCFG_EV0_GEN_S 4 968 969 // Field: [3:0] CCACT 970 // 971 // Capture-Compare action. 972 // 973 // Capture-Compare action defines 15 different channel functions that utilize 974 // capture, compare, and zero events. 975 // ENUMs: 976 // PULSE_ON_CMP Pulse on compare repeatedly. 977 // 978 // Channel function 979 // sequence: 980 // - Pulse enabled events 981 // when CH1CC.VALUE = CNTR.VALUE. 982 // 983 // The event is high for 984 // two timer clock periods. 985 // TGL_ON_CMP Toggle on compare repeatedly. 986 // 987 // Channel function 988 // sequence: 989 // - Toggle enabled events 990 // when CH1CC.VALUE = CNTR.VALUE. 991 // SET_ON_CMP Set on compare repeatedly. 992 // 993 // Channel function 994 // sequence: 995 // - Set enabled events 996 // when CH1CC.VALUE = CNTR.VALUE. 997 // CLR_ON_CMP Clear on compare repeatedly. 998 // 999 // Channel function 1000 // sequence: 1001 // - Clear enabled events 1002 // when CH1CC.VALUE = CNTR.VALUE. 1003 // SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. 1004 // 1005 // Channel function 1006 // sequence: 1007 // - Set enabled events when 1008 // CNTR.VALUE = 0. 1009 // - Toggle enabled events 1010 // when CH1CC.VALUE = CNTR.VALUE. 1011 // 1012 // Set CTL.MODE to UP_PER 1013 // for edge-aligned PWM generation. Duty cycle is 1014 // given by: 1015 // 1016 // When CH1CC.VALUE <= 1017 // TARGET.VALUE: 1018 // Duty cycle = 1019 // CH1CC.VALUE / ( TARGET.VALUE + 1 ). 1020 // 1021 // When CH1CC.VALUE > 1022 // TARGET.VALUE: 1023 // Duty cycle = 1. 1024 // 1025 // Enabled events are 1026 // cleared when CH1CC.VALUE = 0 and CNTR.VALUE = 1027 // 0. 1028 // CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. 1029 // 1030 // Channel function 1031 // sequence: 1032 // - Clear enabled events 1033 // when CNTR.VALUE = 0. 1034 // - Toggle enabled events 1035 // when CH1CC.VALUE = CNTR.VALUE. 1036 // 1037 // Set CTL.MODE to UPDWN_PER 1038 // for center-aligned PWM generation. Duty cycle 1039 // is given by: 1040 // 1041 // When CH1CC.VALUE <= 1042 // TARGET.VALUE: 1043 // Duty cycle = 1 - ( 1044 // CH1CC.VALUE / TARGET.VALUE ). 1045 // 1046 // When CH1CC.VALUE > 1047 // TARGET.VALUE: 1048 // Duty cycle = 0. 1049 // 1050 // Enabled events are set 1051 // when CH1CC.VALUE = 0 and CNTR.VALUE = 0. 1052 // SET_ON_CAPT Set on capture repeatedly. 1053 // 1054 // Channel function 1055 // sequence: 1056 // - Set enabled events on 1057 // capture event and copy CNTR.VALUE to 1058 // CH1CC.VALUE. 1059 // 1060 // Primary use scenario is 1061 // to select this function before you start the 1062 // timer. 1063 // Follow these steps if you 1064 // need to select this function while CTL.MODE is 1065 // different from DIS: 1066 // - Select this function 1067 // with no event enable. 1068 // - Configure CH1CCFG 1069 // (optional). 1070 // - Wait for three timer 1071 // clock periods as defined in PRECFG before you 1072 // enable events. 1073 // 1074 // These steps prevent 1075 // capture events caused by expired signal values 1076 // in edge-detection circuit. 1077 // PER_PULSE_WIDTH_MEAS Period and pulse width measurement. 1078 // 1079 // Continuously capture 1080 // period and pulse width of the signal selected 1081 // by CH1CCFG.CAPT_SRC relative to the signal edge 1082 // given by CH1CCFG.EDGE. 1083 // 1084 // Set enabled events when 1085 // CH1CC.VALUE contains signal period and 1086 // CH1PCC.VALUE contains signal pulse width. 1087 // 1088 // Notes: 1089 // - Make sure that you 1090 // configure CH1CCFG.CAPT_SRC and CCACT when 1091 // CTL.MODE equals DIS, then set CTL.MODE to 1092 // UP_ONCE or UP_PER. 1093 // - The counter restarts in 1094 // the selected timer mode when CH1CC.VALUE 1095 // contains the signal period. 1096 // - If more than one 1097 // channel uses this function, the channels will 1098 // perform this function one at a time. The 1099 // channel with lowest number has priority and 1100 // performs the function first. Next measurement 1101 // starts when current measurement completes 1102 // successfully or times out. A timeout occurs 1103 // when counter equals target. 1104 // - If you want to observe 1105 // a timeout event configure another channel to 1106 // SET_ON_CAPT. 1107 // 1108 // Signal property 1109 // requirements: 1110 // - Signal Period >= 2 * ( 1111 // 1 + PRECFG.CLKDIV ) * timer clock period. 1112 // - Signal Period <= 65535 1113 // * (1 + PRECFG.CLKDIV ) * timer clock period. 1114 // - Signal low and high 1115 // phase >= (1 + PRECFG.CLKDIV ) * timer clock 1116 // period. 1117 // PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. 1118 // 1119 // Channel function 1120 // sequence: 1121 // - Pulse enabled events 1122 // when CH1CC.VALUE = CNTR.VALUE. 1123 // - Disable channel. 1124 // 1125 // The event is high for 1126 // two timer clock periods. 1127 // TGL_ON_CMP_DIS Toggle on compare, and then disable channel. 1128 // 1129 // Channel function 1130 // sequence: 1131 // - Toggle enabled events 1132 // when CH1CC.VALUE = CNTR.VALUE. 1133 // - Disable channel. 1134 // SET_ON_CMP_DIS Set on compare, and then disable channel. 1135 // 1136 // Channel function 1137 // sequence: 1138 // - Set enabled events when 1139 // CH1CC.VALUE = CNTR.VALUE. 1140 // - Disable channel. 1141 // CLR_ON_CMP_DIS Clear on compare, and then disable channel. 1142 // 1143 // Channel function 1144 // sequence: 1145 // - Clear enabled events 1146 // when CH1CC.VALUE = CNTR.VALUE. 1147 // - Disable channel. 1148 // SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable 1149 // channel. 1150 // 1151 // Channel function 1152 // sequence: 1153 // - Set enabled events when 1154 // CNTR.VALUE = 0. 1155 // - Toggle enabled events 1156 // when CH1CC.VALUE = CNTR.VALUE. 1157 // - Disable channel. 1158 // 1159 // Enabled events are 1160 // cleared when CH1CC.VALUE = 0 and CNTR.VALUE = 1161 // 0. 1162 // CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable 1163 // channel. 1164 // 1165 // Channel function 1166 // sequence: 1167 // - Clear enabled events 1168 // when CNTR.VALUE = 0. 1169 // - Toggle enabled events 1170 // when CH1CC.VALUE = CNTR.VALUE. 1171 // - Disable channel. 1172 // 1173 // Enabled events are set 1174 // when CH1CC.VALUE = 0 and CNTR.VALUE = 0. 1175 // SET_ON_CAPT_DIS Set on capture, and then disable channel. 1176 // 1177 // Channel function 1178 // sequence: 1179 // - Set enabled events on 1180 // capture event and copy CNTR.VALUE to 1181 // CH1CC.VALUE. 1182 // - Disable channel. 1183 // 1184 // Primary use scenario is 1185 // to select this function before you start the 1186 // timer. 1187 // Follow these steps if you 1188 // need to select this function while CTL.MODE is 1189 // different from DIS: 1190 // - Set CCACT to 1191 // SET_ON_CAPT with no event enable. 1192 // - Configure CH1CCFG 1193 // (optional). 1194 // - Wait for three timer 1195 // clock periods as defined in PRECFG before you 1196 // set CCACT to SET_ON_CAPT_DIS. Event enable is 1197 // optional. 1198 // 1199 // These steps prevent 1200 // capture events caused by expired signal values 1201 // in edge-detection circuit. 1202 // DIS Disable channel. 1203 #define AUX_TIMER2_CH1EVCFG_CCACT_W 4 1204 #define AUX_TIMER2_CH1EVCFG_CCACT_M 0x0000000F 1205 #define AUX_TIMER2_CH1EVCFG_CCACT_S 0 1206 #define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP 0x0000000F 1207 #define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP 0x0000000E 1208 #define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP 0x0000000D 1209 #define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP 0x0000000C 1210 #define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B 1211 #define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A 1212 #define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT 0x00000009 1213 #define AUX_TIMER2_CH1EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 1214 #define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 1215 #define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 1216 #define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 1217 #define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 1218 #define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 1219 #define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 1220 #define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 1221 #define AUX_TIMER2_CH1EVCFG_CCACT_DIS 0x00000000 1222 1223 //***************************************************************************** 1224 // 1225 // Register: AUX_TIMER2_O_CH1CCFG 1226 // 1227 //***************************************************************************** 1228 // Field: [6:1] CAPT_SRC 1229 // 1230 // Select capture signal source from the asynchronous AUX event bus. 1231 // 1232 // The selected signal enters the edge-detection circuit. False capture events 1233 // can occur when: 1234 // - the edge-detection circuit contains expired signal samples and the circuit 1235 // is enabled without flush as described in CH1EVCFG 1236 // - this register is reconfigured while CTL.MODE is different from DIS. 1237 // 1238 // You can avoid false capture events. When wanted channel function is: 1239 // - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH1EVCFG.CCACT. 1240 // - SET_ON_CAPT, see description for SET_ON_CAPT in CH1EVCFG.CCACT. 1241 // - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in 1242 // CH1EVCFG.CCACT. 1243 // 1244 // If you write a non-enumerated value the behavior is identical to NO_EVENT. 1245 // The written value is returned when read. 1246 // ENUMs: 1247 // NO_EVENT No event. 1248 // AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 1249 // AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 1250 // AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 1251 // AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 1252 // AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 1253 // AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 1254 // AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 1255 // AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 1256 // AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 1257 // AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 1258 // AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 1259 // AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 1260 // AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 1261 // AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB 1262 // AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA 1263 // MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 1264 // MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 1265 // MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV 1266 // ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF 1267 // VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 1268 // MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE 1269 // PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN 1270 // SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF 1271 // AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 1272 // AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 1273 // AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 1274 // AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 1275 // AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 1276 // MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV 1277 // AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 1278 // AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 1279 // AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 1280 // AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 1281 // AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 1282 // AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 1283 // AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 1284 // AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 1285 // AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 1286 // AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 1287 // AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 1288 // AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 1289 // AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 1290 // AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 1291 // AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 1292 // AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 1293 // AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 1294 // AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 1295 // AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 1296 // AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 1297 // AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 1298 // AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 1299 // AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 1300 // AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 1301 // AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 1302 // AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 1303 // AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 1304 // AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 1305 // AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 1306 // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 1307 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 1308 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 1309 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_W 6 1310 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_M 0x0000007E 1311 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_S 1 1312 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_NO_EVENT 0x0000007E 1313 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A 1314 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 1315 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 1316 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 1317 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 1318 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 1319 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E 1320 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C 1321 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A 1322 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 1323 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 1324 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 1325 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 1326 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPB 0x0000005E 1327 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPA 0x0000005C 1328 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A 1329 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 1330 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_EV 0x00000056 1331 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_ACLK_REF 0x00000054 1332 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 1333 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 1334 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_PWR_DWN 0x0000004E 1335 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_SCLK_LF 0x0000004C 1336 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A 1337 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 1338 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 1339 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 1340 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 1341 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_MANUAL_EV 0x00000040 1342 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO31 0x0000003E 1343 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO30 0x0000003C 1344 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO29 0x0000003A 1345 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO28 0x00000038 1346 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO27 0x00000036 1347 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO26 0x00000034 1348 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO25 0x00000032 1349 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO24 0x00000030 1350 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO23 0x0000002E 1351 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO22 0x0000002C 1352 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO21 0x0000002A 1353 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO20 0x00000028 1354 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO19 0x00000026 1355 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO18 0x00000024 1356 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO17 0x00000022 1357 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO16 0x00000020 1358 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO15 0x0000001E 1359 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO14 0x0000001C 1360 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO13 0x0000001A 1361 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO12 0x00000018 1362 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO11 0x00000016 1363 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO10 0x00000014 1364 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO9 0x00000012 1365 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO8 0x00000010 1366 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO7 0x0000000E 1367 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO6 0x0000000C 1368 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO5 0x0000000A 1369 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO4 0x00000008 1370 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO3 0x00000006 1371 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO2 0x00000004 1372 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO1 0x00000002 1373 #define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO0 0x00000000 1374 1375 // Field: [0] EDGE 1376 // 1377 // Edge configuration. 1378 // 1379 // Channel captures counter value at selected edge on signal source selected by 1380 // CAPT_SRC. See CH1EVCFG.CCACT. 1381 // ENUMs: 1382 // RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. 1383 // FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. 1384 #define AUX_TIMER2_CH1CCFG_EDGE 0x00000001 1385 #define AUX_TIMER2_CH1CCFG_EDGE_BITN 0 1386 #define AUX_TIMER2_CH1CCFG_EDGE_M 0x00000001 1387 #define AUX_TIMER2_CH1CCFG_EDGE_S 0 1388 #define AUX_TIMER2_CH1CCFG_EDGE_RISING 0x00000001 1389 #define AUX_TIMER2_CH1CCFG_EDGE_FALLING 0x00000000 1390 1391 //***************************************************************************** 1392 // 1393 // Register: AUX_TIMER2_O_CH1PCC 1394 // 1395 //***************************************************************************** 1396 // Field: [15:0] VALUE 1397 // 1398 // Pipeline Capture Compare value. 1399 // 1400 // 16-bit user defined pipeline compare value or channel-updated capture value. 1401 // 1402 // Compare mode: 1403 // An update of VALUE will be transferred to CH1CC.VALUE when the next 1404 // CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for 1405 // PWM generation and prevents jitter on the edges of the generated signal. 1406 // 1407 // Capture mode: 1408 // When CH1EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the 1409 // width of the low or high phase of the selected signal. This is specified by 1410 // CH1CCFG.EDGE and CH1CCFG.CAPT_SRC. 1411 #define AUX_TIMER2_CH1PCC_VALUE_W 16 1412 #define AUX_TIMER2_CH1PCC_VALUE_M 0x0000FFFF 1413 #define AUX_TIMER2_CH1PCC_VALUE_S 0 1414 1415 //***************************************************************************** 1416 // 1417 // Register: AUX_TIMER2_O_CH1CC 1418 // 1419 //***************************************************************************** 1420 // Field: [15:0] VALUE 1421 // 1422 // Capture Compare value. 1423 // 1424 // 16-bit user defined compare value or channel-updated capture value. 1425 // 1426 // Compare mode: 1427 // VALUE is compared against CNTR.VALUE and an event is generated as specified 1428 // by CH1EVCFG.CCACT when these are equal. 1429 // 1430 // Capture mode: 1431 // The current counter value is stored in VALUE when a capture event occurs. 1432 // CH1EVCFG.CCACT determines if VALUE is a signal period or a regular capture 1433 // value. 1434 #define AUX_TIMER2_CH1CC_VALUE_W 16 1435 #define AUX_TIMER2_CH1CC_VALUE_M 0x0000FFFF 1436 #define AUX_TIMER2_CH1CC_VALUE_S 0 1437 1438 //***************************************************************************** 1439 // 1440 // Register: AUX_TIMER2_O_CH2EVCFG 1441 // 1442 //***************************************************************************** 1443 // Field: [7] EV3_GEN 1444 // 1445 // Event 3 enable. 1446 // 1447 // 0: Channel 2 does not control event 3. 1448 // 1: Channel 2 controls event 3. 1449 // 1450 // When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. 1451 #define AUX_TIMER2_CH2EVCFG_EV3_GEN 0x00000080 1452 #define AUX_TIMER2_CH2EVCFG_EV3_GEN_BITN 7 1453 #define AUX_TIMER2_CH2EVCFG_EV3_GEN_M 0x00000080 1454 #define AUX_TIMER2_CH2EVCFG_EV3_GEN_S 7 1455 1456 // Field: [6] EV2_GEN 1457 // 1458 // Event 2 enable. 1459 // 1460 // 0: Channel 2 does not control event 2. 1461 // 1: Channel 2 controls event 2. 1462 // 1463 // When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. 1464 #define AUX_TIMER2_CH2EVCFG_EV2_GEN 0x00000040 1465 #define AUX_TIMER2_CH2EVCFG_EV2_GEN_BITN 6 1466 #define AUX_TIMER2_CH2EVCFG_EV2_GEN_M 0x00000040 1467 #define AUX_TIMER2_CH2EVCFG_EV2_GEN_S 6 1468 1469 // Field: [5] EV1_GEN 1470 // 1471 // Event 1 enable. 1472 // 1473 // 0: Channel 2 does not control event 1. 1474 // 1: Channel 2 controls event 1. 1475 // 1476 // When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. 1477 #define AUX_TIMER2_CH2EVCFG_EV1_GEN 0x00000020 1478 #define AUX_TIMER2_CH2EVCFG_EV1_GEN_BITN 5 1479 #define AUX_TIMER2_CH2EVCFG_EV1_GEN_M 0x00000020 1480 #define AUX_TIMER2_CH2EVCFG_EV1_GEN_S 5 1481 1482 // Field: [4] EV0_GEN 1483 // 1484 // Event 0 enable. 1485 // 1486 // 0: Channel 2 does not control event 0. 1487 // 1: Channel 2 controls event 0. 1488 // 1489 // When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. 1490 #define AUX_TIMER2_CH2EVCFG_EV0_GEN 0x00000010 1491 #define AUX_TIMER2_CH2EVCFG_EV0_GEN_BITN 4 1492 #define AUX_TIMER2_CH2EVCFG_EV0_GEN_M 0x00000010 1493 #define AUX_TIMER2_CH2EVCFG_EV0_GEN_S 4 1494 1495 // Field: [3:0] CCACT 1496 // 1497 // Capture-Compare action. 1498 // 1499 // Capture-Compare action defines 15 different channel functions that utilize 1500 // capture, compare, and zero events. 1501 // ENUMs: 1502 // PULSE_ON_CMP Pulse on compare repeatedly. 1503 // 1504 // Channel function 1505 // sequence: 1506 // - Pulse enabled events 1507 // when CH2CC.VALUE = CNTR.VALUE. 1508 // 1509 // The event is high for 1510 // two timer clock periods. 1511 // TGL_ON_CMP Toggle on compare repeatedly. 1512 // 1513 // Channel function 1514 // sequence: 1515 // - Toggle enabled events 1516 // when CH2CC.VALUE = CNTR.VALUE. 1517 // SET_ON_CMP Set on compare repeatedly. 1518 // 1519 // Channel function 1520 // sequence: 1521 // - Set enabled events 1522 // when CH2CC.VALUE = CNTR.VALUE. 1523 // CLR_ON_CMP Clear on compare repeatedly. 1524 // 1525 // Channel function 1526 // sequence: 1527 // - Clear enabled events 1528 // when CH2CC.VALUE = CNTR.VALUE. 1529 // SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. 1530 // 1531 // Channel function 1532 // sequence: 1533 // - Set enabled events when 1534 // CNTR.VALUE = 0. 1535 // - Toggle enabled events 1536 // when CH2CC.VALUE = CNTR.VALUE. 1537 // 1538 // Set CTL.MODE to UP_PER 1539 // for edge-aligned PWM generation. Duty cycle is 1540 // given by: 1541 // 1542 // When CH2CC.VALUE <= 1543 // TARGET.VALUE: 1544 // Duty cycle = 1545 // CH2CC.VALUE / ( TARGET.VALUE + 1 ). 1546 // 1547 // When CH2CC.VALUE > 1548 // TARGET.VALUE: 1549 // Duty cycle = 1. 1550 // 1551 // Enabled events are 1552 // cleared when CH2CC.VALUE = 0 and CNTR.VALUE = 1553 // 0. 1554 // CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. 1555 // 1556 // Channel function 1557 // sequence: 1558 // - Clear enabled events 1559 // when CNTR.VALUE = 0. 1560 // - Toggle enabled events 1561 // when CH2CC.VALUE = CNTR.VALUE. 1562 // 1563 // Set CTL.MODE to UPDWN_PER 1564 // for center-aligned PWM generation. Duty cycle 1565 // is given by: 1566 // 1567 // When CH2CC.VALUE <= 1568 // TARGET.VALUE: 1569 // Duty cycle = 1 - ( 1570 // CH2CC.VALUE / TARGET.VALUE ). 1571 // 1572 // When CH2CC.VALUE > 1573 // TARGET.VALUE: 1574 // Duty cycle = 0. 1575 // 1576 // Enabled events are set 1577 // when CH2CC.VALUE = 0 and CNTR.VALUE = 0. 1578 // SET_ON_CAPT Set on capture repeatedly. 1579 // 1580 // Channel function 1581 // sequence: 1582 // - Set enabled events on 1583 // capture event and copy CNTR.VALUE to 1584 // CH2CC.VALUE. 1585 // 1586 // Primary use scenario is 1587 // to select this function before you start the 1588 // timer. 1589 // Follow these steps if you 1590 // need to select this function while CTL.MODE is 1591 // different from DIS: 1592 // - Select this function 1593 // with no event enable. 1594 // - Configure CH2CCFG 1595 // (optional). 1596 // - Wait for three timer 1597 // clock periods as defined in PRECFG before you 1598 // enable events. 1599 // 1600 // These steps prevent 1601 // capture events caused by expired signal values 1602 // in edge-detection circuit. 1603 // PER_PULSE_WIDTH_MEAS Period and pulse width measurement. 1604 // 1605 // Continuously capture 1606 // period and pulse width of the signal selected 1607 // by CH2CCFG.CAPT_SRC relative to the signal edge 1608 // given by CH2CCFG.EDGE. 1609 // 1610 // Set enabled events when 1611 // CH2CC.VALUE contains signal period and 1612 // CH2PCC.VALUE contains signal pulse width. 1613 // 1614 // Notes: 1615 // - Make sure that you 1616 // configure CH2CCFG.CAPT_SRC and CCACT when 1617 // CTL.MODE equals DIS, then set CTL.MODE to 1618 // UP_ONCE or UP_PER. 1619 // - The counter restarts in 1620 // the selected timer mode when CH2CC.VALUE 1621 // contains the signal period. 1622 // - If more than one 1623 // channel uses this function, the channels will 1624 // perform this function one at a time. The 1625 // channel with lowest number has priority and 1626 // performs the function first. Next measurement 1627 // starts when current measurement completes 1628 // successfully or times out. A timeout occurs 1629 // when counter equals target. 1630 // - If you want to observe 1631 // a timeout event configure another channel to 1632 // SET_ON_CAPT. 1633 // 1634 // Signal property 1635 // requirements: 1636 // - Signal Period >= 2 * ( 1637 // 1 + PRECFG.CLKDIV ) * timer clock period. 1638 // - Signal Period <= 65535 1639 // * (1 + PRECFG.CLKDIV ) * timer clock period. 1640 // - Signal low and high 1641 // phase >= (1 + PRECFG.CLKDIV ) * timer clock 1642 // period. 1643 // PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. 1644 // 1645 // Channel function 1646 // sequence: 1647 // - Pulse enabled events 1648 // when CH2CC.VALUE = CNTR.VALUE. 1649 // - Disable channel. 1650 // 1651 // The event is high for 1652 // two timer clock periods. 1653 // TGL_ON_CMP_DIS Toggle on compare, and then disable channel. 1654 // 1655 // Channel function 1656 // sequence: 1657 // - Toggle enabled events 1658 // when CH2CC.VALUE = CNTR.VALUE. 1659 // - Disable channel. 1660 // SET_ON_CMP_DIS Set on compare, and then disable channel. 1661 // 1662 // Channel function 1663 // sequence: 1664 // - Set enabled events when 1665 // CH2CC.VALUE = CNTR.VALUE. 1666 // - Disable channel. 1667 // CLR_ON_CMP_DIS Clear on compare, and then disable channel. 1668 // 1669 // Channel function 1670 // sequence: 1671 // - Clear enabled events 1672 // when CH2CC.VALUE = CNTR.VALUE. 1673 // - Disable channel. 1674 // SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable 1675 // channel. 1676 // 1677 // Channel function 1678 // sequence: 1679 // - Set enabled events when 1680 // CNTR.VALUE = 0. 1681 // - Toggle enabled events 1682 // when CH2CC.VALUE = CNTR.VALUE. 1683 // - Disable channel. 1684 // 1685 // Enabled events are 1686 // cleared when CH2CC.VALUE = 0 and CNTR.VALUE = 1687 // 0. 1688 // CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable 1689 // channel. 1690 // 1691 // Channel function 1692 // sequence: 1693 // - Clear enabled events 1694 // when CNTR.VALUE = 0. 1695 // - Toggle enabled events 1696 // when CH2CC.VALUE = CNTR.VALUE. 1697 // - Disable channel. 1698 // 1699 // Enabled events are set 1700 // when CH2CC.VALUE = 0 and CNTR.VALUE = 0. 1701 // SET_ON_CAPT_DIS Set on capture, and then disable channel. 1702 // 1703 // Channel function 1704 // sequence: 1705 // - Set enabled events on 1706 // capture event and copy CNTR.VALUE to 1707 // CH2CC.VALUE. 1708 // - Disable channel. 1709 // 1710 // Primary use scenario is 1711 // to select this function before you start the 1712 // timer. 1713 // Follow these steps if you 1714 // need to select this function while CTL.MODE is 1715 // different from DIS: 1716 // - Set to SET_ON_CAPT 1717 // with no event enable. 1718 // - Configure CH2CCFG 1719 // (optional). 1720 // - Wait for three timer 1721 // clock periods as defined in PRECFG before you 1722 // set to SET_ON_CAPT_DIS. Event enable is 1723 // optional. 1724 // 1725 // These steps prevent 1726 // capture events caused by expired signal values 1727 // in edge-detection circuit. 1728 // DIS Disable channel. 1729 #define AUX_TIMER2_CH2EVCFG_CCACT_W 4 1730 #define AUX_TIMER2_CH2EVCFG_CCACT_M 0x0000000F 1731 #define AUX_TIMER2_CH2EVCFG_CCACT_S 0 1732 #define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP 0x0000000F 1733 #define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP 0x0000000E 1734 #define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP 0x0000000D 1735 #define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP 0x0000000C 1736 #define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B 1737 #define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A 1738 #define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT 0x00000009 1739 #define AUX_TIMER2_CH2EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 1740 #define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 1741 #define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 1742 #define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 1743 #define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 1744 #define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 1745 #define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 1746 #define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 1747 #define AUX_TIMER2_CH2EVCFG_CCACT_DIS 0x00000000 1748 1749 //***************************************************************************** 1750 // 1751 // Register: AUX_TIMER2_O_CH2CCFG 1752 // 1753 //***************************************************************************** 1754 // Field: [6:1] CAPT_SRC 1755 // 1756 // Select capture signal source from the asynchronous AUX event bus. 1757 // 1758 // The selected signal enters the edge-detection circuit. False capture events 1759 // can occur when: 1760 // - the edge-detection circuit contains expired signal samples and the circuit 1761 // is enabled without flush as described in CH2EVCFG 1762 // - this register is reconfigured while CTL.MODE is different from DIS. 1763 // 1764 // You can avoid false capture events. When wanted channel function is: 1765 // - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH2EVCFG.CCACT. 1766 // - SET_ON_CAPT, see description for SET_ON_CAPT in CH2EVCFG.CCACT. 1767 // - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in 1768 // CH2EVCFG.CCACT. 1769 // 1770 // If you write a non-enumerated value the behavior is identical to NO_EVENT. 1771 // The written value is returned when read. 1772 // ENUMs: 1773 // NO_EVENT No event. 1774 // AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 1775 // AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 1776 // AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 1777 // AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 1778 // AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 1779 // AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 1780 // AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 1781 // AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 1782 // AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 1783 // AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 1784 // AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 1785 // AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 1786 // AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 1787 // AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB 1788 // AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA 1789 // MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 1790 // MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 1791 // MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV 1792 // ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF 1793 // VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 1794 // MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE 1795 // PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN 1796 // SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF 1797 // AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 1798 // AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 1799 // AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 1800 // AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 1801 // AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 1802 // MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV 1803 // AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 1804 // AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 1805 // AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 1806 // AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 1807 // AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 1808 // AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 1809 // AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 1810 // AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 1811 // AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 1812 // AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 1813 // AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 1814 // AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 1815 // AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 1816 // AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 1817 // AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 1818 // AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 1819 // AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 1820 // AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 1821 // AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 1822 // AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 1823 // AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 1824 // AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 1825 // AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 1826 // AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 1827 // AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 1828 // AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 1829 // AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 1830 // AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 1831 // AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 1832 // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 1833 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 1834 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 1835 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_W 6 1836 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_M 0x0000007E 1837 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_S 1 1838 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_NO_EVENT 0x0000007E 1839 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A 1840 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 1841 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 1842 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 1843 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 1844 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 1845 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E 1846 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C 1847 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A 1848 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 1849 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 1850 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 1851 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 1852 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPB 0x0000005E 1853 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPA 0x0000005C 1854 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A 1855 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 1856 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_EV 0x00000056 1857 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_ACLK_REF 0x00000054 1858 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 1859 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 1860 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_PWR_DWN 0x0000004E 1861 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_SCLK_LF 0x0000004C 1862 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A 1863 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 1864 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 1865 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 1866 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 1867 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_MANUAL_EV 0x00000040 1868 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO31 0x0000003E 1869 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO30 0x0000003C 1870 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO29 0x0000003A 1871 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO28 0x00000038 1872 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO27 0x00000036 1873 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO26 0x00000034 1874 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO25 0x00000032 1875 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO24 0x00000030 1876 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO23 0x0000002E 1877 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO22 0x0000002C 1878 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO21 0x0000002A 1879 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO20 0x00000028 1880 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO19 0x00000026 1881 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO18 0x00000024 1882 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO17 0x00000022 1883 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO16 0x00000020 1884 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO15 0x0000001E 1885 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO14 0x0000001C 1886 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO13 0x0000001A 1887 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO12 0x00000018 1888 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO11 0x00000016 1889 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO10 0x00000014 1890 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO9 0x00000012 1891 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO8 0x00000010 1892 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO7 0x0000000E 1893 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO6 0x0000000C 1894 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO5 0x0000000A 1895 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO4 0x00000008 1896 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO3 0x00000006 1897 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO2 0x00000004 1898 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO1 0x00000002 1899 #define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO0 0x00000000 1900 1901 // Field: [0] EDGE 1902 // 1903 // Edge configuration. 1904 // 1905 // Channel captures counter value at selected edge on signal source selected by 1906 // CAPT_SRC. See CH2EVCFG.CCACT. 1907 // ENUMs: 1908 // RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. 1909 // FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. 1910 #define AUX_TIMER2_CH2CCFG_EDGE 0x00000001 1911 #define AUX_TIMER2_CH2CCFG_EDGE_BITN 0 1912 #define AUX_TIMER2_CH2CCFG_EDGE_M 0x00000001 1913 #define AUX_TIMER2_CH2CCFG_EDGE_S 0 1914 #define AUX_TIMER2_CH2CCFG_EDGE_RISING 0x00000001 1915 #define AUX_TIMER2_CH2CCFG_EDGE_FALLING 0x00000000 1916 1917 //***************************************************************************** 1918 // 1919 // Register: AUX_TIMER2_O_CH2PCC 1920 // 1921 //***************************************************************************** 1922 // Field: [15:0] VALUE 1923 // 1924 // Pipeline Capture Compare value. 1925 // 1926 // 16-bit user defined pipeline compare value or channel-updated capture value. 1927 // 1928 // Compare mode: 1929 // An update of VALUE will be transferred to CH2CC.VALUE when the next 1930 // CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for 1931 // PWM generation and prevents jitter on the edges of the generated signal. 1932 // 1933 // Capture mode: 1934 // When CH2EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the 1935 // width of the low or high phase of the selected signal. This is specified by 1936 // CH2CCFG.EDGE and CH2CCFG.CAPT_SRC. 1937 #define AUX_TIMER2_CH2PCC_VALUE_W 16 1938 #define AUX_TIMER2_CH2PCC_VALUE_M 0x0000FFFF 1939 #define AUX_TIMER2_CH2PCC_VALUE_S 0 1940 1941 //***************************************************************************** 1942 // 1943 // Register: AUX_TIMER2_O_CH2CC 1944 // 1945 //***************************************************************************** 1946 // Field: [15:0] VALUE 1947 // 1948 // Capture Compare value. 1949 // 1950 // 16-bit user defined compare value or channel-updated capture value. 1951 // 1952 // Compare mode: 1953 // VALUE is compared against CNTR.VALUE and an event is generated as specified 1954 // by CH2EVCFG.CCACT when these are equal. 1955 // 1956 // Capture mode: 1957 // The current counter value is stored in VALUE when a capture event occurs. 1958 // CH2EVCFG.CCACT determines if VALUE is a signal period or a regular capture 1959 // value. 1960 #define AUX_TIMER2_CH2CC_VALUE_W 16 1961 #define AUX_TIMER2_CH2CC_VALUE_M 0x0000FFFF 1962 #define AUX_TIMER2_CH2CC_VALUE_S 0 1963 1964 //***************************************************************************** 1965 // 1966 // Register: AUX_TIMER2_O_CH3EVCFG 1967 // 1968 //***************************************************************************** 1969 // Field: [7] EV3_GEN 1970 // 1971 // Event 3 enable. 1972 // 1973 // 0: Channel 3 does not control event 3. 1974 // 1: Channel 3 controls event 3. 1975 // 1976 // When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. 1977 #define AUX_TIMER2_CH3EVCFG_EV3_GEN 0x00000080 1978 #define AUX_TIMER2_CH3EVCFG_EV3_GEN_BITN 7 1979 #define AUX_TIMER2_CH3EVCFG_EV3_GEN_M 0x00000080 1980 #define AUX_TIMER2_CH3EVCFG_EV3_GEN_S 7 1981 1982 // Field: [6] EV2_GEN 1983 // 1984 // Event 2 enable. 1985 // 1986 // 0: Channel 3 does not control event 2. 1987 // 1: Channel 3 controls event 2. 1988 // 1989 // When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. 1990 #define AUX_TIMER2_CH3EVCFG_EV2_GEN 0x00000040 1991 #define AUX_TIMER2_CH3EVCFG_EV2_GEN_BITN 6 1992 #define AUX_TIMER2_CH3EVCFG_EV2_GEN_M 0x00000040 1993 #define AUX_TIMER2_CH3EVCFG_EV2_GEN_S 6 1994 1995 // Field: [5] EV1_GEN 1996 // 1997 // Event 1 enable. 1998 // 1999 // 0: Channel 3 does not control event 1. 2000 // 1: Channel 3 controls event 1. 2001 // 2002 // When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. 2003 #define AUX_TIMER2_CH3EVCFG_EV1_GEN 0x00000020 2004 #define AUX_TIMER2_CH3EVCFG_EV1_GEN_BITN 5 2005 #define AUX_TIMER2_CH3EVCFG_EV1_GEN_M 0x00000020 2006 #define AUX_TIMER2_CH3EVCFG_EV1_GEN_S 5 2007 2008 // Field: [4] EV0_GEN 2009 // 2010 // Event 0 enable. 2011 // 2012 // 0: Channel 3 does not control event 0. 2013 // 1: Channel 3 controls event 0. 2014 // 2015 // When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. 2016 #define AUX_TIMER2_CH3EVCFG_EV0_GEN 0x00000010 2017 #define AUX_TIMER2_CH3EVCFG_EV0_GEN_BITN 4 2018 #define AUX_TIMER2_CH3EVCFG_EV0_GEN_M 0x00000010 2019 #define AUX_TIMER2_CH3EVCFG_EV0_GEN_S 4 2020 2021 // Field: [3:0] CCACT 2022 // 2023 // Capture-Compare action. 2024 // 2025 // Capture-Compare action defines 15 different channel functions that utilize 2026 // capture, compare, and zero events. 2027 // ENUMs: 2028 // PULSE_ON_CMP Pulse on compare repeatedly. 2029 // 2030 // Channel function 2031 // sequence: 2032 // - Pulse enabled events 2033 // when CH3CC.VALUE = CNTR.VALUE. 2034 // 2035 // The event is high for 2036 // two timer clock periods. 2037 // TGL_ON_CMP Toggle on compare repeatedly. 2038 // 2039 // Channel function 2040 // sequence: 2041 // - Toggle enabled events 2042 // when CH3CC.VALUE = CNTR.VALUE. 2043 // SET_ON_CMP Set on compare repeatedly. 2044 // 2045 // Channel function 2046 // sequence: 2047 // - Set enabled events 2048 // when CH3CC.VALUE = CNTR.VALUE. 2049 // CLR_ON_CMP Clear on compare repeatedly. 2050 // 2051 // Channel function 2052 // sequence: 2053 // - Clear enabled events 2054 // when CH3CC.VALUE = CNTR.VALUE. 2055 // SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. 2056 // 2057 // Channel function 2058 // sequence: 2059 // - Set enabled events when 2060 // CNTR.VALUE = 0. 2061 // - Toggle enabled events 2062 // when CH3CC.VALUE = CNTR.VALUE. 2063 // 2064 // Set CTL.MODE to UP_PER 2065 // for edge-aligned PWM generation. Duty cycle is 2066 // given by: 2067 // 2068 // When CH3CC.VALUE <= 2069 // TARGET.VALUE: 2070 // Duty cycle = 2071 // CH3CC.VALUE / ( TARGET.VALUE + 1 ). 2072 // 2073 // When CH3CC.VALUE > 2074 // TARGET.VALUE: 2075 // Duty cycle = 1. 2076 // 2077 // Enabled events are 2078 // cleared when CH3CC.VALUE = 0 and CNTR.VALUE = 2079 // 0. 2080 // CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. 2081 // 2082 // Channel function 2083 // sequence: 2084 // - Clear enabled events 2085 // when CNTR.VALUE = 0. 2086 // - Toggle enabled events 2087 // when CH3CC.VALUE = CNTR.VALUE. 2088 // 2089 // Set CTL.MODE to UPDWN_PER 2090 // for center-aligned PWM generation. Duty cycle 2091 // is given by: 2092 // 2093 // When CH3CC.VALUE <= 2094 // TARGET.VALUE: 2095 // Duty cycle = 1 - ( 2096 // CH3CC.VALUE / TARGET.VALUE ). 2097 // 2098 // When CH3CC.VALUE > 2099 // TARGET.VALUE: 2100 // Duty cycle = 0. 2101 // 2102 // Enabled events are set 2103 // when CH3CC.VALUE = 0 and CNTR.VALUE = 0. 2104 // SET_ON_CAPT Set on capture repeatedly. 2105 // 2106 // Channel function 2107 // sequence: 2108 // - Set enabled events on 2109 // capture event and copy CNTR.VALUE to 2110 // CH3CC.VALUE. 2111 // 2112 // Primary use scenario is 2113 // to select this function before you start the 2114 // timer. 2115 // Follow these steps if you 2116 // need to select this function while CTL.MODE is 2117 // different from DIS: 2118 // - Select this function 2119 // with no event enable. 2120 // - Configure CH3CCFG 2121 // (optional). 2122 // - Wait for three timer 2123 // clock periods as defined in PRECFG before you 2124 // enable events. 2125 // 2126 // These steps prevent 2127 // capture events caused by expired signal values 2128 // in edge-detection circuit. 2129 // PER_PULSE_WIDTH_MEAS Period and pulse width measurement. 2130 // 2131 // Continuously capture 2132 // period and pulse width of the signal selected 2133 // by CH3CCFG.CAPT_SRC relative to the signal edge 2134 // given by CH3CCFG.EDGE. 2135 // 2136 // Set enabled events when 2137 // CH3CC.VALUE contains signal period and 2138 // CH3PCC.VALUE contains signal pulse width. 2139 // 2140 // Notes: 2141 // - Make sure that you 2142 // configure CH3CCFG.CAPT_SRC and CCACT when 2143 // CTL.MODE equals DIS, then set CTL.MODE to 2144 // UP_ONCE or UP_PER. 2145 // - The counter restarts in 2146 // the selected timer mode when CH3CC.VALUE 2147 // contains the signal period. 2148 // - If more than one 2149 // channel uses this function, the channels will 2150 // perform this function one at a time. The 2151 // channel with lowest number has priority and 2152 // performs the function first. Next measurement 2153 // starts when current measurement completes 2154 // successfully or times out. A timeout occurs 2155 // when counter equals target. 2156 // - If you want to observe 2157 // a timeout event configure another channel to 2158 // SET_ON_CAPT. 2159 // 2160 // Signal property 2161 // requirements: 2162 // - Signal Period >= 2 * ( 2163 // 1 + PRECFG.CLKDIV ) * timer clock period. 2164 // - Signal Period <= 65535 2165 // * (1 + PRECFG.CLKDIV ) * timer clock period. 2166 // - Signal low and high 2167 // phase >= (1 + PRECFG.CLKDIV ) * timer clock 2168 // period. 2169 // PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. 2170 // 2171 // Channel function 2172 // sequence: 2173 // - Pulse enabled events 2174 // when CH3CC.VALUE = CNTR.VALUE. 2175 // - Disable channel. 2176 // 2177 // The event is high for 2178 // two timer clock periods. 2179 // TGL_ON_CMP_DIS Toggle on compare, and then disable channel. 2180 // 2181 // Channel function 2182 // sequence: 2183 // - Toggle enabled events 2184 // when CH3CC.VALUE = CNTR.VALUE. 2185 // - Disable channel. 2186 // SET_ON_CMP_DIS Set on compare, and then disable channel. 2187 // 2188 // Channel function 2189 // sequence: 2190 // - Set enabled events when 2191 // CH3CC.VALUE = CNTR.VALUE. 2192 // - Disable channel. 2193 // CLR_ON_CMP_DIS Clear on compare, and then disable channel. 2194 // 2195 // Channel function 2196 // sequence: 2197 // - Clear enabled events 2198 // when CH3CC.VALUE = CNTR.VALUE. 2199 // - Disable channel. 2200 // SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable 2201 // channel. 2202 // 2203 // Channel function 2204 // sequence: 2205 // - Set enabled events when 2206 // CNTR.VALUE = 0. 2207 // - Toggle enabled events 2208 // when CH3CC.VALUE = CNTR.VALUE. 2209 // - Disable channel. 2210 // 2211 // Enabled events are 2212 // cleared when CH3CC.VALUE = 0 and CNTR.VALUE = 2213 // 0. 2214 // CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable 2215 // channel. 2216 // 2217 // Channel function 2218 // sequence: 2219 // - Clear enabled events 2220 // when CNTR.VALUE = 0. 2221 // - Toggle enabled events 2222 // when CH3CC.VALUE = CNTR.VALUE. 2223 // - Disable channel. 2224 // 2225 // Enabled events are set 2226 // when CH3CC.VALUE = 0 and CNTR.VALUE = 0. 2227 // SET_ON_CAPT_DIS Set on capture, and then disable channel. 2228 // 2229 // Channel function 2230 // sequence: 2231 // - Set enabled events on 2232 // capture event and copy CNTR.VALUE to 2233 // CH3CC.VALUE. 2234 // - Disable channel. 2235 // 2236 // Primary use scenario is 2237 // to select this function before you start the 2238 // timer. 2239 // Follow these steps if you 2240 // need to select this function while CTL.MODE is 2241 // different from DIS: 2242 // - Set CCACT to 2243 // SET_ON_CAPT with no event enable. 2244 // - Configure CH3CCFG 2245 // (optional). 2246 // - Wait for three timer 2247 // clock periods as defined in PRECFG before you 2248 // set CCACT to SET_ON_CAPT_DIS. Event enable is 2249 // optional. 2250 // 2251 // These steps prevent 2252 // capture events caused by expired signal values 2253 // in edge-detection circuit. 2254 // DIS Disable channel. 2255 #define AUX_TIMER2_CH3EVCFG_CCACT_W 4 2256 #define AUX_TIMER2_CH3EVCFG_CCACT_M 0x0000000F 2257 #define AUX_TIMER2_CH3EVCFG_CCACT_S 0 2258 #define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP 0x0000000F 2259 #define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP 0x0000000E 2260 #define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP 0x0000000D 2261 #define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP 0x0000000C 2262 #define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B 2263 #define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A 2264 #define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT 0x00000009 2265 #define AUX_TIMER2_CH3EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 2266 #define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 2267 #define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 2268 #define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 2269 #define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 2270 #define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 2271 #define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 2272 #define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 2273 #define AUX_TIMER2_CH3EVCFG_CCACT_DIS 0x00000000 2274 2275 //***************************************************************************** 2276 // 2277 // Register: AUX_TIMER2_O_CH3CCFG 2278 // 2279 //***************************************************************************** 2280 // Field: [6:1] CAPT_SRC 2281 // 2282 // Select capture signal source from the asynchronous AUX event bus. 2283 // 2284 // The selected signal enters the edge-detection circuit. False capture events 2285 // can occur when: 2286 // - the edge-detection circuit contains expired signal samples and the circuit 2287 // is enabled without flush as described in CH3EVCFG 2288 // - this register is reconfigured while CTL.MODE is different from DIS. 2289 // 2290 // You can avoid false capture events. When wanted channel function: 2291 // - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH3EVCFG.CCACT. 2292 // - SET_ON_CAPT, see description for SET_ON_CAPT in CH3EVCFG.CCACT. 2293 // - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in 2294 // CH3EVCFG.CCACT. 2295 // 2296 // If you write a non-enumerated value the behavior is identical to NO_EVENT. 2297 // The written value is returned when read. 2298 // ENUMs: 2299 // NO_EVENT No event. 2300 // AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 2301 // AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 2302 // AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 2303 // AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 2304 // AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 2305 // AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 2306 // AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 2307 // AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 2308 // AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 2309 // AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 2310 // AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 2311 // AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 2312 // AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 2313 // AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB 2314 // AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA 2315 // MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 2316 // MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 2317 // MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV 2318 // ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF 2319 // VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 2320 // MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE 2321 // PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN 2322 // SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF 2323 // AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 2324 // AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 2325 // AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 2326 // AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 2327 // AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 2328 // MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV 2329 // AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 2330 // AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 2331 // AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 2332 // AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 2333 // AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 2334 // AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 2335 // AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 2336 // AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 2337 // AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 2338 // AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 2339 // AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 2340 // AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 2341 // AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 2342 // AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 2343 // AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 2344 // AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 2345 // AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 2346 // AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 2347 // AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 2348 // AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 2349 // AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 2350 // AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 2351 // AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 2352 // AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 2353 // AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 2354 // AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 2355 // AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 2356 // AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 2357 // AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 2358 // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 2359 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 2360 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 2361 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_W 6 2362 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_M 0x0000007E 2363 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_S 1 2364 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_NO_EVENT 0x0000007E 2365 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A 2366 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 2367 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 2368 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 2369 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 2370 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 2371 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E 2372 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C 2373 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A 2374 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 2375 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 2376 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 2377 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 2378 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPB 0x0000005E 2379 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPA 0x0000005C 2380 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A 2381 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 2382 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_EV 0x00000056 2383 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_ACLK_REF 0x00000054 2384 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 2385 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 2386 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_PWR_DWN 0x0000004E 2387 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_SCLK_LF 0x0000004C 2388 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A 2389 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 2390 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 2391 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 2392 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 2393 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_MANUAL_EV 0x00000040 2394 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO31 0x0000003E 2395 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO30 0x0000003C 2396 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO29 0x0000003A 2397 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO28 0x00000038 2398 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO27 0x00000036 2399 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO26 0x00000034 2400 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO25 0x00000032 2401 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO24 0x00000030 2402 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO23 0x0000002E 2403 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO22 0x0000002C 2404 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO21 0x0000002A 2405 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO20 0x00000028 2406 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO19 0x00000026 2407 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO18 0x00000024 2408 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO17 0x00000022 2409 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO16 0x00000020 2410 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO15 0x0000001E 2411 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO14 0x0000001C 2412 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO13 0x0000001A 2413 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO12 0x00000018 2414 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO11 0x00000016 2415 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO10 0x00000014 2416 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO9 0x00000012 2417 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO8 0x00000010 2418 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO7 0x0000000E 2419 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO6 0x0000000C 2420 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO5 0x0000000A 2421 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO4 0x00000008 2422 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO3 0x00000006 2423 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO2 0x00000004 2424 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO1 0x00000002 2425 #define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO0 0x00000000 2426 2427 // Field: [0] EDGE 2428 // 2429 // Edge configuration. 2430 // 2431 // Channel captures counter value at selected edge on signal source selected by 2432 // CAPT_SRC. See CH3EVCFG.CCACT. 2433 // ENUMs: 2434 // RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. 2435 // FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. 2436 #define AUX_TIMER2_CH3CCFG_EDGE 0x00000001 2437 #define AUX_TIMER2_CH3CCFG_EDGE_BITN 0 2438 #define AUX_TIMER2_CH3CCFG_EDGE_M 0x00000001 2439 #define AUX_TIMER2_CH3CCFG_EDGE_S 0 2440 #define AUX_TIMER2_CH3CCFG_EDGE_RISING 0x00000001 2441 #define AUX_TIMER2_CH3CCFG_EDGE_FALLING 0x00000000 2442 2443 //***************************************************************************** 2444 // 2445 // Register: AUX_TIMER2_O_CH3PCC 2446 // 2447 //***************************************************************************** 2448 // Field: [15:0] VALUE 2449 // 2450 // Pipeline Capture Compare value. 2451 // 2452 // 16-bit user defined pipeline compare value or channel-updated capture value. 2453 // 2454 // Compare mode: 2455 // An update of VALUE will be transferred to CH3CC.VALUE when the next 2456 // CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for 2457 // PWM generation and prevents jitter on the edges of the generated signal. 2458 // 2459 // Capture mode: 2460 // When CH3EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the 2461 // width of the low or high phase of the selected signal. This is specified by 2462 // CH3CCFG.EDGE and CH3CCFG.CAPT_SRC. 2463 #define AUX_TIMER2_CH3PCC_VALUE_W 16 2464 #define AUX_TIMER2_CH3PCC_VALUE_M 0x0000FFFF 2465 #define AUX_TIMER2_CH3PCC_VALUE_S 0 2466 2467 //***************************************************************************** 2468 // 2469 // Register: AUX_TIMER2_O_CH3CC 2470 // 2471 //***************************************************************************** 2472 // Field: [15:0] VALUE 2473 // 2474 // Capture Compare value. 2475 // 2476 // 16-bit user defined compare value or channel-updated capture value. 2477 // 2478 // Compare mode: 2479 // VALUE is compared against CNTR.VALUE and an event is generated as specified 2480 // by CH3EVCFG.CCACT when these are equal. 2481 // 2482 // Capture mode: 2483 // The current counter value is stored in VALUE when a capture event occurs. 2484 // CH3EVCFG.CCACT determines if VALUE is a signal period or a regular capture 2485 // value. 2486 #define AUX_TIMER2_CH3CC_VALUE_W 16 2487 #define AUX_TIMER2_CH3CC_VALUE_M 0x0000FFFF 2488 #define AUX_TIMER2_CH3CC_VALUE_S 0 2489 2490 2491 #endif // __AUX_TIMER2__ 2492
