1 /****************************************************************************** 2 * Filename: hw_aux_timer01_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AUX_TIMER01_H__ 38 #define __HW_AUX_TIMER01_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AUX_TIMER01 component 44 // 45 //***************************************************************************** 46 // Timer 0 Configuration 47 #define AUX_TIMER01_O_T0CFG 0x00000000 48 49 // Timer 0 Control 50 #define AUX_TIMER01_O_T0CTL 0x00000004 51 52 // Timer 0 Target 53 #define AUX_TIMER01_O_T0TARGET 0x00000008 54 55 // Timer 0 Counter 56 #define AUX_TIMER01_O_T0CNTR 0x0000000C 57 58 // Timer 1 Configuration 59 #define AUX_TIMER01_O_T1CFG 0x00000010 60 61 // Timer 1 Control 62 #define AUX_TIMER01_O_T1CTL 0x00000014 63 64 // Timer 1 Target 65 #define AUX_TIMER01_O_T1TARGET 0x00000018 66 67 // Timer 1 Counter 68 #define AUX_TIMER01_O_T1CNTR 0x0000001C 69 70 //***************************************************************************** 71 // 72 // Register: AUX_TIMER01_O_T0CFG 73 // 74 //***************************************************************************** 75 // Field: [14] TICK_SRC_POL 76 // 77 // Tick source polarity for Timer 0. 78 // ENUMs: 79 // FALL Count on falling edges of TICK_SRC. 80 // RISE Count on rising edges of TICK_SRC. 81 #define AUX_TIMER01_T0CFG_TICK_SRC_POL 0x00004000 82 #define AUX_TIMER01_T0CFG_TICK_SRC_POL_BITN 14 83 #define AUX_TIMER01_T0CFG_TICK_SRC_POL_M 0x00004000 84 #define AUX_TIMER01_T0CFG_TICK_SRC_POL_S 14 85 #define AUX_TIMER01_T0CFG_TICK_SRC_POL_FALL 0x00004000 86 #define AUX_TIMER01_T0CFG_TICK_SRC_POL_RISE 0x00000000 87 88 // Field: [13:8] TICK_SRC 89 // 90 // Select Timer 0 tick source from the synchronous event bus. 91 // ENUMs: 92 // AUX_TIMER2_CLKSW_RDY AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY 93 // AUX_DAC_HOLD_ACTIVE AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE 94 // AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 95 // AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 96 // AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 97 // AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 98 // AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 99 // AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 100 // AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 101 // NO_EVENT No event. 102 // AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 103 // AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 104 // AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 105 // AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 106 // AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 107 // AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 108 // AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB 109 // AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA 110 // MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 111 // MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 112 // MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV 113 // ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF 114 // VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 115 // MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE 116 // PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN 117 // SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF 118 // AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 119 // AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 120 // AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 121 // AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 122 // AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 123 // MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV 124 // AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 125 // AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 126 // AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 127 // AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 128 // AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 129 // AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 130 // AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 131 // AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 132 // AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 133 // AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 134 // AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 135 // AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 136 // AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 137 // AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 138 // AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 139 // AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 140 // AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 141 // AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 142 // AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 143 // AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 144 // AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 145 // AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 146 // AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 147 // AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 148 // AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 149 // AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 150 // AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 151 // AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 152 // AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 153 // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 154 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 155 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 156 #define AUX_TIMER01_T0CFG_TICK_SRC_W 6 157 #define AUX_TIMER01_T0CFG_TICK_SRC_M 0x00003F00 158 #define AUX_TIMER01_T0CFG_TICK_SRC_S 8 159 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 160 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 161 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 162 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 163 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 164 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 165 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 166 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 167 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 168 #define AUX_TIMER01_T0CFG_TICK_SRC_NO_EVENT 0x00003600 169 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER1_EV 0x00003500 170 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 171 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 172 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 173 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 174 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 175 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPB 0x00002F00 176 #define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPA 0x00002E00 177 #define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 178 #define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 179 #define AUX_TIMER01_T0CFG_TICK_SRC_MCU_EV 0x00002B00 180 #define AUX_TIMER01_T0CFG_TICK_SRC_ACLK_REF 0x00002A00 181 #define AUX_TIMER01_T0CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 182 #define AUX_TIMER01_T0CFG_TICK_SRC_MCU_ACTIVE 0x00002800 183 #define AUX_TIMER01_T0CFG_TICK_SRC_PWR_DWN 0x00002700 184 #define AUX_TIMER01_T0CFG_TICK_SRC_SCLK_LF 0x00002600 185 #define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 186 #define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 187 #define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 188 #define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 189 #define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2 0x00002100 190 #define AUX_TIMER01_T0CFG_TICK_SRC_MANUAL_EV 0x00002000 191 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO31 0x00001F00 192 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO30 0x00001E00 193 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO29 0x00001D00 194 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO28 0x00001C00 195 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO27 0x00001B00 196 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO26 0x00001A00 197 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO25 0x00001900 198 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO24 0x00001800 199 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO23 0x00001700 200 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO22 0x00001600 201 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO21 0x00001500 202 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO20 0x00001400 203 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO19 0x00001300 204 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO18 0x00001200 205 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO17 0x00001100 206 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO16 0x00001000 207 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO15 0x00000F00 208 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO14 0x00000E00 209 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO13 0x00000D00 210 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO12 0x00000C00 211 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO11 0x00000B00 212 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO10 0x00000A00 213 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO9 0x00000900 214 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO8 0x00000800 215 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO7 0x00000700 216 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO6 0x00000600 217 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO5 0x00000500 218 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO4 0x00000400 219 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO3 0x00000300 220 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO2 0x00000200 221 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO1 0x00000100 222 #define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO0 0x00000000 223 224 // Field: [7:4] PRE 225 // 226 // Prescaler division ratio is 2^PRE: 227 // 228 // 0x0: Divide by 1. 229 // 0x1: Divide by 2. 230 // 0x2: Divide by 4. 231 // ... 232 // 0xF: Divide by 32,768. 233 #define AUX_TIMER01_T0CFG_PRE_W 4 234 #define AUX_TIMER01_T0CFG_PRE_M 0x000000F0 235 #define AUX_TIMER01_T0CFG_PRE_S 4 236 237 // Field: [1] MODE 238 // 239 // Timer 0 mode. 240 // 241 // Configure source for Timer 0 prescaler. 242 // ENUMs: 243 // TICK Use event set by TICK_SRC as source for prescaler. 244 // CLK Use clock as source for prescaler. Note that 245 // AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the 246 // clock frequency. 247 #define AUX_TIMER01_T0CFG_MODE 0x00000002 248 #define AUX_TIMER01_T0CFG_MODE_BITN 1 249 #define AUX_TIMER01_T0CFG_MODE_M 0x00000002 250 #define AUX_TIMER01_T0CFG_MODE_S 1 251 #define AUX_TIMER01_T0CFG_MODE_TICK 0x00000002 252 #define AUX_TIMER01_T0CFG_MODE_CLK 0x00000000 253 254 // Field: [0] RELOAD 255 // 256 // Timer 0 reload mode. 257 // ENUMs: 258 // CONT Continuous mode. 259 // 260 // Timer 0 restarts when the 261 // counter value becomes equal to or greater than 262 // ( T0TARGET.VALUE - 1). 263 // MAN Manual mode. 264 // 265 // Timer 0 stops and 266 // T0CTL.EN becomes 0 when the counter value 267 // becomes equal to or greater than 268 // T0TARGET.VALUE. 269 #define AUX_TIMER01_T0CFG_RELOAD 0x00000001 270 #define AUX_TIMER01_T0CFG_RELOAD_BITN 0 271 #define AUX_TIMER01_T0CFG_RELOAD_M 0x00000001 272 #define AUX_TIMER01_T0CFG_RELOAD_S 0 273 #define AUX_TIMER01_T0CFG_RELOAD_CONT 0x00000001 274 #define AUX_TIMER01_T0CFG_RELOAD_MAN 0x00000000 275 276 //***************************************************************************** 277 // 278 // Register: AUX_TIMER01_O_T0CTL 279 // 280 //***************************************************************************** 281 // Field: [0] EN 282 // 283 // Timer 0 enable. 284 // 285 // 0: Disable Timer 0. 286 // 1: Enable Timer 0. 287 // 288 // The counter restarts from 0 when you enable Timer 0. 289 #define AUX_TIMER01_T0CTL_EN 0x00000001 290 #define AUX_TIMER01_T0CTL_EN_BITN 0 291 #define AUX_TIMER01_T0CTL_EN_M 0x00000001 292 #define AUX_TIMER01_T0CTL_EN_S 0 293 294 //***************************************************************************** 295 // 296 // Register: AUX_TIMER01_O_T0TARGET 297 // 298 //***************************************************************************** 299 // Field: [15:0] VALUE 300 // 301 // Timer 0 target value. 302 // 303 // Manual Reload Mode: 304 // - Timer 0 increments until the counter value becomes equal to or greater 305 // than VALUE. 306 // - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter 307 // value is equal to or greater than VALUE. 308 // 309 // Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1 310 // peripheral clock period. 311 // 312 // Continuous Reload Mode: 313 // - Timer 0 increments until the counter value becomes equal to or greater 314 // than ( VALUE - 1), then restarts from 0. 315 // - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter 316 // value is 0, except for when you enable the timer. 317 // 318 // Note: When VALUE is less than 2, Timer 0 counter value remains 0. 319 // AUX_TIMER0_EV goes high and remains high 1 peripheral clock period after you 320 // enable the timer. 321 // 322 // 323 // It is allowed to update the VALUE while the timer runs. 324 #define AUX_TIMER01_T0TARGET_VALUE_W 16 325 #define AUX_TIMER01_T0TARGET_VALUE_M 0x0000FFFF 326 #define AUX_TIMER01_T0TARGET_VALUE_S 0 327 328 //***************************************************************************** 329 // 330 // Register: AUX_TIMER01_O_T0CNTR 331 // 332 //***************************************************************************** 333 // Field: [15:0] VALUE 334 // 335 // Timer 0 counter value. 336 #define AUX_TIMER01_T0CNTR_VALUE_W 16 337 #define AUX_TIMER01_T0CNTR_VALUE_M 0x0000FFFF 338 #define AUX_TIMER01_T0CNTR_VALUE_S 0 339 340 //***************************************************************************** 341 // 342 // Register: AUX_TIMER01_O_T1CFG 343 // 344 //***************************************************************************** 345 // Field: [14] TICK_SRC_POL 346 // 347 // Tick source polarity for Timer 1. 348 // ENUMs: 349 // FALL Count on falling edges of TICK_SRC. 350 // RISE Count on rising edges of TICK_SRC. 351 #define AUX_TIMER01_T1CFG_TICK_SRC_POL 0x00004000 352 #define AUX_TIMER01_T1CFG_TICK_SRC_POL_BITN 14 353 #define AUX_TIMER01_T1CFG_TICK_SRC_POL_M 0x00004000 354 #define AUX_TIMER01_T1CFG_TICK_SRC_POL_S 14 355 #define AUX_TIMER01_T1CFG_TICK_SRC_POL_FALL 0x00004000 356 #define AUX_TIMER01_T1CFG_TICK_SRC_POL_RISE 0x00000000 357 358 // Field: [13:8] TICK_SRC 359 // 360 // Select Timer 1 tick source from the synchronous event bus. 361 // ENUMs: 362 // AUX_TIMER2_CLKSW_RDY AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY 363 // AUX_DAC_HOLD_ACTIVE AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE 364 // AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 365 // AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY 366 // AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL 367 // AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ 368 // AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE 369 // AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 370 // AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 371 // AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 372 // NO_EVENT No event. 373 // AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 374 // AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 375 // AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 376 // AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 377 // AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 378 // AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB 379 // AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA 380 // MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 381 // MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 382 // MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV 383 // ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF 384 // VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 385 // MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE 386 // PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN 387 // SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF 388 // AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 389 // AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 390 // AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 391 // AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 392 // AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 393 // MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV 394 // AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 395 // AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 396 // AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 397 // AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 398 // AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 399 // AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 400 // AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 401 // AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 402 // AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 403 // AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 404 // AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 405 // AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 406 // AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 407 // AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 408 // AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 409 // AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 410 // AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 411 // AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 412 // AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 413 // AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 414 // AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 415 // AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 416 // AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 417 // AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 418 // AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 419 // AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 420 // AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 421 // AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 422 // AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 423 // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 424 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 425 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 426 #define AUX_TIMER01_T1CFG_TICK_SRC_W 6 427 #define AUX_TIMER01_T1CFG_TICK_SRC_M 0x00003F00 428 #define AUX_TIMER01_T1CFG_TICK_SRC_S 8 429 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 430 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 431 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 432 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 433 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 434 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 435 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 436 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 437 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 438 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER0_EV 0x00003600 439 #define AUX_TIMER01_T1CFG_TICK_SRC_NO_EVENT 0x00003500 440 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 441 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 442 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 443 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 444 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 445 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPB 0x00002F00 446 #define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPA 0x00002E00 447 #define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 448 #define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 449 #define AUX_TIMER01_T1CFG_TICK_SRC_MCU_EV 0x00002B00 450 #define AUX_TIMER01_T1CFG_TICK_SRC_ACLK_REF 0x00002A00 451 #define AUX_TIMER01_T1CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 452 #define AUX_TIMER01_T1CFG_TICK_SRC_MCU_ACTIVE 0x00002800 453 #define AUX_TIMER01_T1CFG_TICK_SRC_PWR_DWN 0x00002700 454 #define AUX_TIMER01_T1CFG_TICK_SRC_SCLK_LF 0x00002600 455 #define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 456 #define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 457 #define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 458 #define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 459 #define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2 0x00002100 460 #define AUX_TIMER01_T1CFG_TICK_SRC_MANUAL_EV 0x00002000 461 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO31 0x00001F00 462 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO30 0x00001E00 463 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO29 0x00001D00 464 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO28 0x00001C00 465 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO27 0x00001B00 466 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO26 0x00001A00 467 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO25 0x00001900 468 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO24 0x00001800 469 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO23 0x00001700 470 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO22 0x00001600 471 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO21 0x00001500 472 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO20 0x00001400 473 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO19 0x00001300 474 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO18 0x00001200 475 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO17 0x00001100 476 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO16 0x00001000 477 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO15 0x00000F00 478 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO14 0x00000E00 479 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO13 0x00000D00 480 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO12 0x00000C00 481 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO11 0x00000B00 482 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO10 0x00000A00 483 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO9 0x00000900 484 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO8 0x00000800 485 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO7 0x00000700 486 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO6 0x00000600 487 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO5 0x00000500 488 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO4 0x00000400 489 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO3 0x00000300 490 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO2 0x00000200 491 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO1 0x00000100 492 #define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO0 0x00000000 493 494 // Field: [7:4] PRE 495 // 496 // Prescaler division ratio is 2^PRE: 497 // 498 // 0x0: Divide by 1. 499 // 0x1: Divide by 2. 500 // 0x2: Divide by 4. 501 // ... 502 // 0xF: Divide by 32,768. 503 #define AUX_TIMER01_T1CFG_PRE_W 4 504 #define AUX_TIMER01_T1CFG_PRE_M 0x000000F0 505 #define AUX_TIMER01_T1CFG_PRE_S 4 506 507 // Field: [1] MODE 508 // 509 // Timer 1 mode. 510 // 511 // Configure source for Timer 1 prescaler. 512 // ENUMs: 513 // TICK Use event set by TICK_SRC as source for prescaler. 514 // CLK Use clock as source for prescaler. Note that 515 // AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the 516 // clock frequency. 517 #define AUX_TIMER01_T1CFG_MODE 0x00000002 518 #define AUX_TIMER01_T1CFG_MODE_BITN 1 519 #define AUX_TIMER01_T1CFG_MODE_M 0x00000002 520 #define AUX_TIMER01_T1CFG_MODE_S 1 521 #define AUX_TIMER01_T1CFG_MODE_TICK 0x00000002 522 #define AUX_TIMER01_T1CFG_MODE_CLK 0x00000000 523 524 // Field: [0] RELOAD 525 // 526 // Timer 1 reload mode. 527 // ENUMs: 528 // CONT Continuous mode. 529 // 530 // Timer 1 restarts when the 531 // counter value becomes equal to or greater than 532 // ( T1TARGET.VALUE - 1). 533 // MAN Manual mode. 534 // 535 // Timer 1 stops and 536 // T1CTL.EN becomes 0 when the counter value 537 // becomes equal to or greater than 538 // T1TARGET.VALUE. 539 #define AUX_TIMER01_T1CFG_RELOAD 0x00000001 540 #define AUX_TIMER01_T1CFG_RELOAD_BITN 0 541 #define AUX_TIMER01_T1CFG_RELOAD_M 0x00000001 542 #define AUX_TIMER01_T1CFG_RELOAD_S 0 543 #define AUX_TIMER01_T1CFG_RELOAD_CONT 0x00000001 544 #define AUX_TIMER01_T1CFG_RELOAD_MAN 0x00000000 545 546 //***************************************************************************** 547 // 548 // Register: AUX_TIMER01_O_T1CTL 549 // 550 //***************************************************************************** 551 // Field: [0] EN 552 // 553 // Timer 1 enable. 554 // 555 // 0: Disable Timer 1. 556 // 1: Enable Timer 1. 557 // 558 // The counter restarts from 0 when you enable Timer 1. 559 #define AUX_TIMER01_T1CTL_EN 0x00000001 560 #define AUX_TIMER01_T1CTL_EN_BITN 0 561 #define AUX_TIMER01_T1CTL_EN_M 0x00000001 562 #define AUX_TIMER01_T1CTL_EN_S 0 563 564 //***************************************************************************** 565 // 566 // Register: AUX_TIMER01_O_T1TARGET 567 // 568 //***************************************************************************** 569 // Field: [15:0] VALUE 570 // 571 // Timer 1 target value. 572 // 573 // Manual Reload Mode: 574 // - Timer 1 increments until the counter value becomes equal to or greater 575 // than VALUE. 576 // - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter 577 // value is equal to or greater than VALUE. 578 // 579 // Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1 580 // peripheral clock period. 581 // 582 // Continuous Reload Mode: 583 // - Timer 1 increments until the counter value becomes equal to or greater 584 // than ( VALUE - 1), then restarts from 0. 585 // - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter 586 // value is 0, except for when you enable the timer. 587 // 588 // Note: When VALUE is less than 2, Timer 1 counter value remains 0. 589 // AUX_TIMER1_EV goes high and remains high 1 peripheral clock period after you 590 // enable the timer. 591 // 592 // 593 // It is allowed to update the VALUE while the timer runs. 594 #define AUX_TIMER01_T1TARGET_VALUE_W 16 595 #define AUX_TIMER01_T1TARGET_VALUE_M 0x0000FFFF 596 #define AUX_TIMER01_T1TARGET_VALUE_S 0 597 598 //***************************************************************************** 599 // 600 // Register: AUX_TIMER01_O_T1CNTR 601 // 602 //***************************************************************************** 603 // Field: [15:0] VALUE 604 // 605 // Timer 1 counter value. 606 #define AUX_TIMER01_T1CNTR_VALUE_W 16 607 #define AUX_TIMER01_T1CNTR_VALUE_M 0x0000FFFF 608 #define AUX_TIMER01_T1CNTR_VALUE_S 0 609 610 611 #endif // __AUX_TIMER01__ 612
