1 /****************************************************************************** 2 * 3 * Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the 15 * distribution. 16 * 17 * Neither the name of Texas Instruments Incorporated nor the names of 18 * its contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * MSP432P4111 Register Definitions 34 * 35 * This file includes CMSIS compliant component and register definitions 36 * 37 * For legacy components the definitions that are compatible with MSP430 code, 38 * are included with msp432p4111_classic.h 39 * 40 * With CMSIS definitions, the register defines have been reformatted: 41 * ModuleName[ModuleInstance]->RegisterName 42 * 43 * Writing to CMSIS bit fields can be done through register level 44 * or via bitband area access: 45 * - ADC14->CTL0 |= ADC14_CTL0_ENC; 46 * - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1; 47 * 48 * File creation date: 2017-08-03 49 * 50 ******************************************************************************/ 51 52 #ifndef __MSP432P4111_H__ 53 #define __MSP432P4111_H__ 54 55 /* Use standard integer types with explicit width */ 56 #include <stdint.h> 57 58 #ifdef __cplusplus 59 extern "C" { 60 #endif 61 62 #define __MSP432_HEADER_VERSION__ 3202 63 64 /* Remap MSP432 intrinsics to ARM equivalents */ 65 #include "msp_compatibility.h" 66 67 #ifndef __CMSIS_CONFIG__ 68 #define __CMSIS_CONFIG__ 69 70 /** @addtogroup MSP432P4111_Definitions MSP432P4111 Definitions 71 This file defines all structures and symbols for MSP432P4111: 72 - components and registers 73 - peripheral base address 74 - peripheral ID 75 - Peripheral definitions 76 @{ 77 */ 78 79 /****************************************************************************** 80 * Processor and Core Peripherals * 81 ******************************************************************************/ 82 /** @addtogroup MSP432P4111_CMSIS Device CMSIS Definitions 83 Configuration of the Cortex-M4 Processor and Core Peripherals 84 @{ 85 */ 86 87 /****************************************************************************** 88 * CMSIS-compatible Interrupt Number Definition * 89 ******************************************************************************/ 90 typedef enum IRQn 91 { 92 /* Cortex-M4 Processor Exceptions Numbers */ 93 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ 94 HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ 95 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ 96 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ 97 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ 98 SVCall_IRQn = -5, /* 11 SV Call Interrupt */ 99 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ 100 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ 101 SysTick_IRQn = -1, /* 15 System Tick Interrupt */ 102 /* Peripheral Exceptions Numbers */ 103 PSS_IRQn = 0, /* 16 PSS Interrupt */ 104 CS_IRQn = 1, /* 17 CS Interrupt */ 105 PCM_IRQn = 2, /* 18 PCM Interrupt */ 106 WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */ 107 FPU_IRQn = 4, /* 20 FPU Interrupt */ 108 FLCTL_A_IRQn = 5, /* 21 Flash Controller Interrupt*/ 109 COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */ 110 COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */ 111 TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ 112 TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ 113 TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ 114 TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ 115 TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ 116 TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ 117 TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ 118 TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ 119 EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */ 120 EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */ 121 EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */ 122 EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */ 123 EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */ 124 EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */ 125 EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */ 126 EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */ 127 ADC14_IRQn = 24, /* 40 ADC14 Interrupt */ 128 T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */ 129 T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */ 130 T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */ 131 AES256_IRQn = 28, /* 44 AES256 Interrupt */ 132 RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */ 133 DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */ 134 DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */ 135 DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */ 136 DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */ 137 DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */ 138 PORT1_IRQn = 35, /* 51 Port1 Interrupt */ 139 PORT2_IRQn = 36, /* 52 Port2 Interrupt */ 140 PORT3_IRQn = 37, /* 53 Port3 Interrupt */ 141 PORT4_IRQn = 38, /* 54 Port4 Interrupt */ 142 PORT5_IRQn = 39, /* 55 Port5 Interrupt */ 143 PORT6_IRQn = 40, /* 56 Port6 Interrupt */ 144 LCD_F_IRQn = 41 /* 57 LCD_F Interrupt */ 145 } IRQn_Type; 146 147 /****************************************************************************** 148 * Processor and Core Peripheral Section * 149 ******************************************************************************/ 150 #define __CM4_REV 0x0001 /* Core revision r0p1 */ 151 #define __MPU_PRESENT 1 /* MPU present or not */ 152 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */ 153 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ 154 #define __FPU_PRESENT 1 /* FPU present or not */ 155 156 /****************************************************************************** 157 * Available Peripherals * 158 ******************************************************************************/ 159 #define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */ 160 #define __MCU_HAS_AES256__ /*!< Module AES256 is available */ 161 #define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */ 162 #define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */ 163 #define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */ 164 #define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */ 165 #define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */ 166 #define __MCU_HAS_CS__ /*!< Module CS is available */ 167 #define __MCU_HAS_DIO__ /*!< Module DIO is available */ 168 #define __MCU_HAS_DMA__ /*!< Module DMA is available */ 169 #define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */ 170 #define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */ 171 #define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */ 172 #define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */ 173 #define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */ 174 #define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */ 175 #define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */ 176 #define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */ 177 #define __MCU_HAS_FLCTL_A__ /*!< Module FLCTL_A is available */ 178 #define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */ 179 #define __MCU_HAS_LCD_F__ /*!< Module LCD_F is available */ 180 #define __MCU_HAS_PCM__ /*!< Module PCM is available */ 181 #define __MCU_HAS_PMAP__ /*!< Module PMAP is available */ 182 #define __MCU_HAS_PSS__ /*!< Module PSS is available */ 183 #define __MCU_HAS_REF_A__ /*!< Module REF_A is available */ 184 #define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */ 185 #define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */ 186 #define __MCU_HAS_SYSCTL_A__ /*!< Module SYSCTL_A is available */ 187 #define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */ 188 #define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */ 189 #define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */ 190 #define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */ 191 #define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */ 192 #define __MCU_HAS_TLV__ /*!< Module TLV is available */ 193 #define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */ 194 195 /* Definitions to show that specific ports are available */ 196 197 #define __MSP432_HAS_PORTA_R__ 198 #define __MSP432_HAS_PORTB_R__ 199 #define __MSP432_HAS_PORTC_R__ 200 #define __MSP432_HAS_PORTD_R__ 201 #define __MSP432_HAS_PORTE_R__ 202 #define __MSP432_HAS_PORTJ_R__ 203 204 #define __MSP432_HAS_PORT1_R__ 205 #define __MSP432_HAS_PORT2_R__ 206 #define __MSP432_HAS_PORT3_R__ 207 #define __MSP432_HAS_PORT4_R__ 208 #define __MSP432_HAS_PORT5_R__ 209 #define __MSP432_HAS_PORT6_R__ 210 #define __MSP432_HAS_PORT7_R__ 211 #define __MSP432_HAS_PORT8_R__ 212 #define __MSP432_HAS_PORT9_R__ 213 #define __MSP432_HAS_PORT10_R__ 214 215 216 /*@}*/ /* end of group MSP432P4111_CMSIS */ 217 218 /* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */ 219 #ifdef __TI_ARM__ 220 /* disable the TI ULP advisor check for the core header file definitions */ 221 #pragma diag_push 222 #pragma CHECK_ULP("none") 223 #include "core_cm4.h" 224 #pragma diag_pop 225 #else 226 #include "core_cm4.h" 227 #endif 228 229 /* System Header */ 230 #include "system_msp432p4111.h" 231 232 /****************************************************************************** 233 * Definition of standard bits * 234 ******************************************************************************/ 235 #define BIT0 (uint16_t)(0x0001) 236 #define BIT1 (uint16_t)(0x0002) 237 #define BIT2 (uint16_t)(0x0004) 238 #define BIT3 (uint16_t)(0x0008) 239 #define BIT4 (uint16_t)(0x0010) 240 #define BIT5 (uint16_t)(0x0020) 241 #define BIT6 (uint16_t)(0x0040) 242 #define BIT7 (uint16_t)(0x0080) 243 #define BIT8 (uint16_t)(0x0100) 244 #define BIT9 (uint16_t)(0x0200) 245 #define BITA (uint16_t)(0x0400) 246 #define BITB (uint16_t)(0x0800) 247 #define BITC (uint16_t)(0x1000) 248 #define BITD (uint16_t)(0x2000) 249 #define BITE (uint16_t)(0x4000) 250 #define BITF (uint16_t)(0x8000) 251 252 /****************************************************************************** 253 * Device and peripheral memory map * 254 ******************************************************************************/ 255 /** @addtogroup MSP432P4111_MemoryMap MSP432P4111 Memory Mapping 256 @{ 257 */ 258 259 #define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */ 260 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */ 261 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */ 262 #define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */ 263 264 #define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */ 265 #define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */ 266 #define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */ 267 #define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */ 268 #define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */ 269 #define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */ 270 #define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */ 271 #define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */ 272 #define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */ 273 #define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */ 274 #define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ 275 #define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ 276 #define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ 277 #define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ 278 #define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ 279 #define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ 280 #define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ 281 #define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ 282 #define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ 283 #define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ 284 #define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ 285 #define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ 286 #define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ 287 #define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ 288 #define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ 289 #define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ 290 #define FLCTL_A_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL_A registers */ 291 #define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */ 292 #define LCD_F_BASE (PERIPH_BASE +0x00012400) /*!< Base address of module LCD_F registers */ 293 #define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */ 294 #define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */ 295 #define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */ 296 #define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */ 297 #define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */ 298 #define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ 299 #define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ 300 #define SYSCTL_A_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL_A registers */ 301 #define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */ 302 #define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */ 303 #define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */ 304 #define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */ 305 #define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */ 306 #define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */ 307 #define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */ 308 309 310 /*@}*/ /* end of group MSP432P4111_MemoryMap */ 311 312 /****************************************************************************** 313 * Definitions for bit band access * 314 ******************************************************************************/ 315 #define BITBAND_SRAM_BASE ((uint32_t)(0x22000000)) 316 #define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) 317 318 /* SRAM allows 32 bit bit band access */ 319 #define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4))) 320 /* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */ 321 #define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) 322 323 /****************************************************************************** 324 * Peripheral register definitions * 325 ******************************************************************************/ 326 /** @addtogroup MSP432P4111_Peripherals MSP432P4111 Peripherals 327 MSP432P4111 Device Specific Peripheral registers structures 328 @{ 329 */ 330 331 #if defined ( __CC_ARM ) 332 #pragma anon_unions 333 #endif 334 335 336 /****************************************************************************** 337 * ADC14 Registers 338 ******************************************************************************/ 339 /** @addtogroup ADC14 MSP432P4111 (ADC14) 340 @{ 341 */ 342 typedef struct { 343 __IO uint32_t CTL0; /*!< Control 0 Register */ 344 __IO uint32_t CTL1; /*!< Control 1 Register */ 345 __IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */ 346 __IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */ 347 __IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */ 348 __IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */ 349 __IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */ 350 __IO uint32_t MEM[32]; /*!< Conversion Memory Register */ 351 uint32_t RESERVED0[9]; 352 __IO uint32_t IER0; /*!< Interrupt Enable 0 Register */ 353 __IO uint32_t IER1; /*!< Interrupt Enable 1 Register */ 354 __I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */ 355 __I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */ 356 __O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */ 357 __IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */ 358 __IO uint32_t IV; /*!< Interrupt Vector Register */ 359 } ADC14_Type; 360 361 /*@}*/ /* end of group ADC14 */ 362 363 364 /****************************************************************************** 365 * AES256 Registers 366 ******************************************************************************/ 367 /** @addtogroup AES256 MSP432P4111 (AES256) 368 @{ 369 */ 370 typedef struct { 371 __IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */ 372 __IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */ 373 __IO uint16_t STAT; /*!< AES Accelerator Status Register */ 374 __O uint16_t KEY; /*!< AES Accelerator Key Register */ 375 __O uint16_t DIN; /*!< AES Accelerator Data In Register */ 376 __O uint16_t DOUT; /*!< AES Accelerator Data Out Register */ 377 __O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */ 378 __O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */ 379 } AES256_Type; 380 381 /*@}*/ /* end of group AES256 */ 382 383 384 /****************************************************************************** 385 * CAPTIO Registers 386 ******************************************************************************/ 387 /** @addtogroup CAPTIO MSP432P4111 (CAPTIO) 388 @{ 389 */ 390 typedef struct { 391 uint16_t RESERVED0[7]; 392 __IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */ 393 } CAPTIO_Type; 394 395 /*@}*/ /* end of group CAPTIO */ 396 397 398 /****************************************************************************** 399 * COMP_E Registers 400 ******************************************************************************/ 401 /** @addtogroup COMP_E MSP432P4111 (COMP_E) 402 @{ 403 */ 404 typedef struct { 405 __IO uint16_t CTL0; /*!< Comparator Control Register 0 */ 406 __IO uint16_t CTL1; /*!< Comparator Control Register 1 */ 407 __IO uint16_t CTL2; /*!< Comparator Control Register 2 */ 408 __IO uint16_t CTL3; /*!< Comparator Control Register 3 */ 409 uint16_t RESERVED0[2]; 410 __IO uint16_t INT; /*!< Comparator Interrupt Control Register */ 411 __I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */ 412 } COMP_E_Type; 413 414 /*@}*/ /* end of group COMP_E */ 415 416 417 /****************************************************************************** 418 * CRC32 Registers 419 ******************************************************************************/ 420 /** @addtogroup CRC32 MSP432P4111 (CRC32) 421 @{ 422 */ 423 typedef struct { 424 __IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */ 425 uint16_t RESERVED0; 426 __IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */ 427 uint16_t RESERVED1; 428 __IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */ 429 __IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */ 430 __IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */ 431 __IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */ 432 __IO uint16_t DI16; /*!< Data Input for CRC16 computation */ 433 uint16_t RESERVED2; 434 __IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */ 435 uint16_t RESERVED3; 436 __IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */ 437 uint16_t RESERVED4[2]; 438 __IO uint16_t RESR16; /*!< CRC16 Result Reverse */ 439 } CRC32_Type; 440 441 /*@}*/ /* end of group CRC32 */ 442 443 444 /****************************************************************************** 445 * CS Registers 446 ******************************************************************************/ 447 /** @addtogroup CS MSP432P4111 (CS) 448 @{ 449 */ 450 typedef struct { 451 __IO uint32_t KEY; /*!< Key Register */ 452 __IO uint32_t CTL0; /*!< Control 0 Register */ 453 __IO uint32_t CTL1; /*!< Control 1 Register */ 454 __IO uint32_t CTL2; /*!< Control 2 Register */ 455 __IO uint32_t CTL3; /*!< Control 3 Register */ 456 uint32_t RESERVED0[7]; 457 __IO uint32_t CLKEN; /*!< Clock Enable Register */ 458 __I uint32_t STAT; /*!< Status Register */ 459 uint32_t RESERVED1[2]; 460 __IO uint32_t IE; /*!< Interrupt Enable Register */ 461 uint32_t RESERVED2; 462 __I uint32_t IFG; /*!< Interrupt Flag Register */ 463 uint32_t RESERVED3; 464 __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 465 uint32_t RESERVED4; 466 __O uint32_t SETIFG; /*!< Set Interrupt Flag Register */ 467 uint32_t RESERVED5; 468 __IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */ 469 __IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */ 470 } CS_Type; 471 472 /*@}*/ /* end of group CS */ 473 474 475 /****************************************************************************** 476 * DIO Registers 477 ******************************************************************************/ 478 /** @addtogroup DIO MSP432P4111 (DIO) 479 @{ 480 */ 481 typedef struct { 482 union { 483 __I uint16_t IN; /*!< Port Pair Input */ 484 struct { 485 __I uint8_t IN_L; /*!< Low Port Input */ 486 __I uint8_t IN_H; /*!< High Port Input */ 487 }; 488 }; 489 union { 490 __IO uint16_t OUT; /*!< Port Pair Output */ 491 struct { 492 __IO uint8_t OUT_L; /*!< Low Port Output */ 493 __IO uint8_t OUT_H; /*!< High Port Output */ 494 }; 495 }; 496 union { 497 __IO uint16_t DIR; /*!< Port Pair Direction */ 498 struct { 499 __IO uint8_t DIR_L; /*!< Low Port Direction */ 500 __IO uint8_t DIR_H; /*!< High Port Direction */ 501 }; 502 }; 503 union { 504 __IO uint16_t REN; /*!< Port Pair Resistor Enable */ 505 struct { 506 __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ 507 __IO uint8_t REN_H; /*!< High Port Resistor Enable */ 508 }; 509 }; 510 union { 511 __IO uint16_t DS; /*!< Port Pair Drive Strength */ 512 struct { 513 __IO uint8_t DS_L; /*!< Low Port Drive Strength */ 514 __IO uint8_t DS_H; /*!< High Port Drive Strength */ 515 }; 516 }; 517 union { 518 __IO uint16_t SEL0; /*!< Port Pair Select 0 */ 519 struct { 520 __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ 521 __IO uint8_t SEL0_H; /*!< High Port Select 0 */ 522 }; 523 }; 524 union { 525 __IO uint16_t SEL1; /*!< Port Pair Select 1 */ 526 struct { 527 __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ 528 __IO uint8_t SEL1_H; /*!< High Port Select 1 */ 529 }; 530 }; 531 __I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */ 532 uint16_t RESERVED0[3]; 533 union { 534 __IO uint16_t SELC; /*!< Port Pair Complement Select */ 535 struct { 536 __IO uint8_t SELC_L; /*!< Low Port Complement Select */ 537 __IO uint8_t SELC_H; /*!< High Port Complement Select */ 538 }; 539 }; 540 union { 541 __IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */ 542 struct { 543 __IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */ 544 __IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */ 545 }; 546 }; 547 union { 548 __IO uint16_t IE; /*!< Port Pair Interrupt Enable */ 549 struct { 550 __IO uint8_t IE_L; /*!< Low Port Interrupt Enable */ 551 __IO uint8_t IE_H; /*!< High Port Interrupt Enable */ 552 }; 553 }; 554 union { 555 __IO uint16_t IFG; /*!< Port Pair Interrupt Flag */ 556 struct { 557 __IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */ 558 __IO uint8_t IFG_H; /*!< High Port Interrupt Flag */ 559 }; 560 }; 561 __I uint16_t IV_H; /*!< High Port Interrupt Vector Value */ 562 } DIO_PORT_Interruptable_Type; 563 564 typedef struct { 565 union { 566 __I uint16_t IN; /*!< Port Pair Input */ 567 struct { 568 __I uint8_t IN_L; /*!< Low Port Input */ 569 __I uint8_t IN_H; /*!< High Port Input */ 570 }; 571 }; 572 union { 573 __IO uint16_t OUT; /*!< Port Pair Output */ 574 struct { 575 __IO uint8_t OUT_L; /*!< Low Port Output */ 576 __IO uint8_t OUT_H; /*!< High Port Output */ 577 }; 578 }; 579 union { 580 __IO uint16_t DIR; /*!< Port Pair Direction */ 581 struct { 582 __IO uint8_t DIR_L; /*!< Low Port Direction */ 583 __IO uint8_t DIR_H; /*!< High Port Direction */ 584 }; 585 }; 586 union { 587 __IO uint16_t REN; /*!< Port Pair Resistor Enable */ 588 struct { 589 __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ 590 __IO uint8_t REN_H; /*!< High Port Resistor Enable */ 591 }; 592 }; 593 union { 594 __IO uint16_t DS; /*!< Port Pair Drive Strength */ 595 struct { 596 __IO uint8_t DS_L; /*!< Low Port Drive Strength */ 597 __IO uint8_t DS_H; /*!< High Port Drive Strength */ 598 }; 599 }; 600 union { 601 __IO uint16_t SEL0; /*!< Port Pair Select 0 */ 602 struct { 603 __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ 604 __IO uint8_t SEL0_H; /*!< High Port Select 0 */ 605 }; 606 }; 607 union { 608 __IO uint16_t SEL1; /*!< Port Pair Select 1 */ 609 struct { 610 __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ 611 __IO uint8_t SEL1_H; /*!< High Port Select 1 */ 612 }; 613 }; 614 uint16_t RESERVED0[4]; 615 union { 616 __IO uint16_t SELC; /*!< Port Pair Complement Select */ 617 struct { 618 __IO uint8_t SELC_L; /*!< Low Port Complement Select */ 619 __IO uint8_t SELC_H; /*!< High Port Complement Select */ 620 }; 621 }; 622 } DIO_PORT_Not_Interruptable_Type; 623 624 625 typedef struct { 626 __I uint8_t IN; /*!< Port Input */ 627 uint8_t RESERVED0; 628 __IO uint8_t OUT; /*!< Port Output */ 629 uint8_t RESERVED1; 630 __IO uint8_t DIR; /*!< Port Direction */ 631 uint8_t RESERVED2; 632 __IO uint8_t REN; /*!< Port Resistor Enable */ 633 uint8_t RESERVED3; 634 __IO uint8_t DS; /*!< Port Drive Strength */ 635 uint8_t RESERVED4; 636 __IO uint8_t SEL0; /*!< Port Select 0 */ 637 uint8_t RESERVED5; 638 __IO uint8_t SEL1; /*!< Port Select 1 */ 639 uint8_t RESERVED6; 640 __I uint16_t IV; /*!< Port Interrupt Vector Value */ 641 uint8_t RESERVED7[6]; 642 __IO uint8_t SELC; /*!< Port Complement Select */ 643 uint8_t RESERVED8; 644 __IO uint8_t IES; /*!< Port Interrupt Edge Select */ 645 uint8_t RESERVED9; 646 __IO uint8_t IE; /*!< Port Interrupt Enable */ 647 uint8_t RESERVED10; 648 __IO uint8_t IFG; /*!< Port Interrupt Flag */ 649 } DIO_PORT_Odd_Interruptable_Type; 650 651 typedef struct { 652 uint8_t RESERVED0; 653 __I uint8_t IN; /*!< Port Input */ 654 uint8_t RESERVED1; 655 __IO uint8_t OUT; /*!< Port Output */ 656 uint8_t RESERVED2; 657 __IO uint8_t DIR; /*!< Port Direction */ 658 uint8_t RESERVED3; 659 __IO uint8_t REN; /*!< Port Resistor Enable */ 660 uint8_t RESERVED4; 661 __IO uint8_t DS; /*!< Port Drive Strength */ 662 uint8_t RESERVED5; 663 __IO uint8_t SEL0; /*!< Port Select 0 */ 664 uint8_t RESERVED6; 665 __IO uint8_t SEL1; /*!< Port Select 1 */ 666 uint8_t RESERVED7[9]; 667 __IO uint8_t SELC; /*!< Port Complement Select */ 668 uint8_t RESERVED8; 669 __IO uint8_t IES; /*!< Port Interrupt Edge Select */ 670 uint8_t RESERVED9; 671 __IO uint8_t IE; /*!< Port Interrupt Enable */ 672 uint8_t RESERVED10; 673 __IO uint8_t IFG; /*!< Port Interrupt Flag */ 674 __I uint16_t IV; /*!< Port Interrupt Vector Value */ 675 } DIO_PORT_Even_Interruptable_Type; 676 677 /*@}*/ /* end of group MSP432P4111_DIO */ 678 679 680 /****************************************************************************** 681 * DMA Registers 682 ******************************************************************************/ 683 /** @addtogroup DMA MSP432P4111 (DMA) 684 @{ 685 */ 686 typedef struct { 687 __I uint32_t DEVICE_CFG; /*!< Device Configuration Status */ 688 __IO uint32_t SW_CHTRIG; /*!< Software Channel Trigger Register */ 689 uint32_t RESERVED0[2]; 690 __IO uint32_t CH_SRCCFG[32]; /*!< Channel n Source Configuration Register */ 691 uint32_t RESERVED1[28]; 692 __IO uint32_t INT1_SRCCFG; /*!< Interrupt 1 Source Channel Configuration */ 693 __IO uint32_t INT2_SRCCFG; /*!< Interrupt 2 Source Channel Configuration Register */ 694 __IO uint32_t INT3_SRCCFG; /*!< Interrupt 3 Source Channel Configuration Register */ 695 uint32_t RESERVED2; 696 __I uint32_t INT0_SRCFLG; /*!< Interrupt 0 Source Channel Flag Register */ 697 __O uint32_t INT0_CLRFLG; /*!< Interrupt 0 Source Channel Clear Flag Register */ 698 } DMA_Channel_Type; 699 700 typedef struct { 701 __I uint32_t STAT; /*!< Status Register */ 702 __O uint32_t CFG; /*!< Configuration Register */ 703 __IO uint32_t CTLBASE; /*!< Channel Control Data Base Pointer Register */ 704 __I uint32_t ALTBASE; /*!< Channel Alternate Control Data Base Pointer Register */ 705 __I uint32_t WAITSTAT; /*!< Channel Wait on Request Status Register */ 706 __O uint32_t SWREQ; /*!< Channel Software Request Register */ 707 __IO uint32_t USEBURSTSET; /*!< Channel Useburst Set Register */ 708 __O uint32_t USEBURSTCLR; /*!< Channel Useburst Clear Register */ 709 __IO uint32_t REQMASKSET; /*!< Channel Request Mask Set Register */ 710 __O uint32_t REQMASKCLR; /*!< Channel Request Mask Clear Register */ 711 __IO uint32_t ENASET; /*!< Channel Enable Set Register */ 712 __O uint32_t ENACLR; /*!< Channel Enable Clear Register */ 713 __IO uint32_t ALTSET; /*!< Channel Primary-Alternate Set Register */ 714 __O uint32_t ALTCLR; /*!< Channel Primary-Alternate Clear Register */ 715 __IO uint32_t PRIOSET; /*!< Channel Priority Set Register */ 716 __O uint32_t PRIOCLR; /*!< Channel Priority Clear Register */ 717 uint32_t RESERVED4[3]; 718 __IO uint32_t ERRCLR; /*!< Bus Error Clear Register */ 719 } DMA_Control_Type; 720 721 /*@}*/ /* end of group DMA */ 722 723 724 /****************************************************************************** 725 * EUSCI_A Registers 726 ******************************************************************************/ 727 /** @addtogroup EUSCI_A MSP432P4111 (EUSCI_A) 728 @{ 729 */ 730 typedef struct { 731 __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ 732 __IO uint16_t CTLW1; /*!< eUSCI_Ax Control Word Register 1 */ 733 uint16_t RESERVED0; 734 __IO uint16_t BRW; /*!< eUSCI_Ax Baud Rate Control Word Register */ 735 __IO uint16_t MCTLW; /*!< eUSCI_Ax Modulation Control Word Register */ 736 __IO uint16_t STATW; /*!< eUSCI_Ax Status Register */ 737 __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ 738 __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ 739 __IO uint16_t ABCTL; /*!< eUSCI_Ax Auto Baud Rate Control Register */ 740 __IO uint16_t IRCTL; /*!< eUSCI_Ax IrDA Control Word Register */ 741 uint16_t RESERVED1[3]; 742 __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ 743 __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ 744 __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ 745 } EUSCI_A_Type; 746 747 /*@}*/ /* end of group EUSCI_A */ 748 749 /** @addtogroup EUSCI_A_SPI MSP432P4111 (EUSCI_A_SPI) 750 @{ 751 */ 752 typedef struct { 753 __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ 754 uint16_t RESERVED0[2]; 755 __IO uint16_t BRW; /*!< eUSCI_Ax Bit Rate Control Register 1 */ 756 uint16_t RESERVED1; 757 __IO uint16_t STATW; 758 __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ 759 __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ 760 uint16_t RESERVED2[5]; 761 __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ 762 __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ 763 __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ 764 } EUSCI_A_SPI_Type; 765 766 /*@}*/ /* end of group EUSCI_A_SPI */ 767 768 769 /****************************************************************************** 770 * EUSCI_B Registers 771 ******************************************************************************/ 772 /** @addtogroup EUSCI_B MSP432P4111 (EUSCI_B) 773 @{ 774 */ 775 typedef struct { 776 __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ 777 __IO uint16_t CTLW1; /*!< eUSCI_Bx Control Word Register 1 */ 778 uint16_t RESERVED0; 779 __IO uint16_t BRW; /*!< eUSCI_Bx Baud Rate Control Word Register */ 780 __IO uint16_t STATW; /*!< eUSCI_Bx Status Register */ 781 __IO uint16_t TBCNT; /*!< eUSCI_Bx Byte Counter Threshold Register */ 782 __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ 783 __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ 784 uint16_t RESERVED1[2]; 785 __IO uint16_t I2COA0; /*!< eUSCI_Bx I2C Own Address 0 Register */ 786 __IO uint16_t I2COA1; /*!< eUSCI_Bx I2C Own Address 1 Register */ 787 __IO uint16_t I2COA2; /*!< eUSCI_Bx I2C Own Address 2 Register */ 788 __IO uint16_t I2COA3; /*!< eUSCI_Bx I2C Own Address 3 Register */ 789 __I uint16_t ADDRX; /*!< eUSCI_Bx I2C Received Address Register */ 790 __IO uint16_t ADDMASK; /*!< eUSCI_Bx I2C Address Mask Register */ 791 __IO uint16_t I2CSA; /*!< eUSCI_Bx I2C Slave Address Register */ 792 uint16_t RESERVED2[4]; 793 __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ 794 __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ 795 __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ 796 } EUSCI_B_Type; 797 798 /*@}*/ /* end of group EUSCI_B */ 799 800 /** @addtogroup EUSCI_B_SPI MSP432P4111 (EUSCI_B_SPI) 801 @{ 802 */ 803 typedef struct { 804 __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ 805 uint16_t RESERVED0[2]; 806 __IO uint16_t BRW; /*!< eUSCI_Bx Bit Rate Control Register 1 */ 807 __IO uint16_t STATW; 808 uint16_t RESERVED1; 809 __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ 810 __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ 811 uint16_t RESERVED2[13]; 812 __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ 813 __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ 814 __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ 815 } EUSCI_B_SPI_Type; 816 817 /*@}*/ /* end of group EUSCI_B_SPI */ 818 819 820 /****************************************************************************** 821 * FLCTL_A Registers 822 ******************************************************************************/ 823 /** @addtogroup FLCTL_A MSP432P4111 (FLCTL_A) 824 @{ 825 */ 826 typedef struct { 827 __I uint32_t POWER_STAT; /*!< Power Status Register */ 828 uint32_t RESERVED0[3]; 829 __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ 830 __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ 831 uint32_t RESERVED1[2]; 832 __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ 833 __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ 834 __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ 835 uint32_t RESERVED2[4]; 836 __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ 837 __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ 838 uint32_t RESERVED3[3]; 839 __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ 840 __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ 841 __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ 842 uint32_t RESERVED4; 843 __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ 844 __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ 845 __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ 846 __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ 847 __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ 848 __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ 849 __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ 850 __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ 851 __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ 852 __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ 853 __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ 854 __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ 855 __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ 856 __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ 857 __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ 858 __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ 859 __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ 860 __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ 861 uint32_t RESERVED5[2]; 862 __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ 863 __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ 864 uint32_t RESERVED6[2]; 865 __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ 866 __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ 867 uint32_t RESERVED7[2]; 868 __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ 869 __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ 870 __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ 871 __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ 872 uint32_t RESERVED8[4]; 873 __IO uint32_t IFG; /*!< Interrupt Flag Register */ 874 __IO uint32_t IE; /*!< Interrupt Enable Register */ 875 __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 876 __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ 877 __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ 878 __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ 879 __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ 880 __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ 881 __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ 882 __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ 883 __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ 884 __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ 885 __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ 886 uint32_t RESERVED9[55]; 887 __IO uint32_t BANK0_MAIN_WEPROT0; /*!< Main Memory Bank0 Write/Erase Protection Register 0 */ 888 __IO uint32_t BANK0_MAIN_WEPROT1; /*!< Main Memory Bank0 Write/Erase Protection Register 1 */ 889 __IO uint32_t BANK0_MAIN_WEPROT2; /*!< Main Memory Bank0 Write/Erase Protection Register 2 */ 890 __IO uint32_t BANK0_MAIN_WEPROT3; /*!< Main Memory Bank0 Write/Erase Protection Register 3 */ 891 __IO uint32_t BANK0_MAIN_WEPROT4; /*!< Main Memory Bank0 Write/Erase Protection Register 4 */ 892 __IO uint32_t BANK0_MAIN_WEPROT5; /*!< Main Memory Bank0 Write/Erase Protection Register 5 */ 893 __IO uint32_t BANK0_MAIN_WEPROT6; /*!< Main Memory Bank0 Write/Erase Protection Register 6 */ 894 __IO uint32_t BANK0_MAIN_WEPROT7; /*!< Main Memory Bank0 Write/Erase Protection Register 7 */ 895 uint32_t RESERVED10[8]; 896 __IO uint32_t BANK1_MAIN_WEPROT0; /*!< Main Memory Bank1 Write/Erase Protection Register 0 */ 897 __IO uint32_t BANK1_MAIN_WEPROT1; /*!< Main Memory Bank1 Write/Erase Protection Register 1 */ 898 __IO uint32_t BANK1_MAIN_WEPROT2; /*!< Main Memory Bank1 Write/Erase Protection Register 2 */ 899 __IO uint32_t BANK1_MAIN_WEPROT3; /*!< Main Memory Bank1 Write/Erase Protection Register 3 */ 900 __IO uint32_t BANK1_MAIN_WEPROT4; /*!< Main Memory Bank1 Write/Erase Protection Register 4 */ 901 __IO uint32_t BANK1_MAIN_WEPROT5; /*!< Main Memory Bank1 Write/Erase Protection Register 5 */ 902 __IO uint32_t BANK1_MAIN_WEPROT6; /*!< Main Memory Bank1 Write/Erase Protection Register 6 */ 903 __IO uint32_t BANK1_MAIN_WEPROT7; /*!< Main Memory Bank1 Write/Erase Protection Register 7 */ 904 } FLCTL_A_Type; 905 906 /*@}*/ /* end of group FLCTL_A */ 907 908 909 /****************************************************************************** 910 * FL_BOOTOVER_MAILBOX Registers 911 ******************************************************************************/ 912 /** @addtogroup SEC_ZONE_PARAMS MSP432P4111 (FL_BOOTOVER_MAILBOX) 913 @{ 914 */ 915 typedef struct { 916 __IO uint32_t SEC_ZONE_SECEN; /*!< IP Protection Secure Zone Enable. */ 917 __IO uint32_t SEC_ZONE_START_ADDR; /*!< Start address of IP protected secure zone. */ 918 __IO uint32_t SEC_ZONE_LENGTH; /*!< Length of IP protected secure zone in number of bytes. */ 919 __IO uint32_t SEC_ZONE_AESINIT_VECT[4]; /*!< IP protected secure zone 0 AES initialization vector */ 920 __IO uint32_t SEC_ZONE_SECKEYS[8]; /*!< AES-CBC security keys. */ 921 __IO uint32_t SEC_ZONE_UNENC_PWD[4]; /*!< Unencrypted password for authentication. */ 922 __IO uint32_t SEC_ZONE_ENCUPDATE_EN; /*!< IP Protected Secure Zone Encrypted In-field Update Enable */ 923 __IO uint32_t SEC_ZONE_DATA_EN; /*!< IP Protected Secure Zone Data Access Enable */ 924 __IO uint32_t SEC_ZONE_ACK; /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */ 925 uint32_t RESERVED0[2]; 926 } SEC_ZONE_PARAMS_Type; 927 928 /*@}*/ /* end of group SEC_ZONE_PARAMS */ 929 930 /** @addtogroup SEC_ZONE_UPDATE MSP432P4111 (FL_BOOTOVER_MAILBOX) 931 @{ 932 */ 933 typedef struct { 934 __IO uint32_t SEC_ZONE_PAYLOADADDR; /*!< Start address where the payload is loaded in the device. */ 935 __IO uint32_t SEC_ZONE_PAYLOADLEN; /*!< Length of the payload in bytes. */ 936 __IO uint32_t SEC_ZONE_UPDATE_ACK; /*!< Acknowledgment for the IP Protected Secure Zone Update Command */ 937 uint32_t RESERVED0; 938 } SEC_ZONE_UPDATE_Type; 939 940 /*@}*/ /* end of group SEC_ZONE_UPDATE */ 941 942 /** @addtogroup FL_BOOTOVER_MAILBOX MSP432P4111 (FL_BOOTOVER_MAILBOX) 943 @{ 944 */ 945 typedef struct { 946 __IO uint32_t MB_START; /*!< Flash MailBox start: 0x0115ACF6 */ 947 __IO uint32_t CMD; /*!< Command for Boot override operations. */ 948 uint32_t RESERVED0[2]; 949 __IO uint32_t JTAG_SWD_LOCK_SECEN; /*!< JTAG and SWD Lock Enable */ 950 __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4]; /*!< JTAG and SWD lock AES initialization vector for AES-CBC */ 951 __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8]; /*!< JTAG and SWD lock AES CBC security Keys 0-7. */ 952 __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4]; /*!< JTAG and SWD lock unencrypted password */ 953 __IO uint32_t JTAG_SWD_LOCK_ACK; /*!< Acknowledgment for JTAG and SWD Lock command */ 954 uint32_t RESERVED1[2]; 955 SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4]; 956 __IO uint32_t BSL_ENABLE; /*!< BSL Enable. */ 957 __IO uint32_t BSL_START_ADDRESS; /*!< Contains the pointer to the BSL function. */ 958 __IO uint32_t BSL_PARAMETERS; /*!< BSL hardware invoke conifguration field. */ 959 uint32_t RESERVED2[2]; 960 __IO uint32_t BSL_ACK; /*!< Acknowledgment for the BSL Configuration Command */ 961 __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD; /*!< Start address where the payload is loaded in the device. */ 962 __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN; /*!< Length of the encrypted payload in bytes */ 963 __IO uint32_t JTAG_SWD_LOCK_DST_ADDR; /*!< Destination address where the final data needs to be stored into the device. */ 964 __IO uint32_t ENC_UPDATE_ACK; /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */ 965 uint32_t RESERVED3; 966 SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4]; 967 uint32_t RESERVED4; 968 __IO uint32_t FACTORY_RESET_ENABLE; /*!< Enable/Disable Factory Reset */ 969 __IO uint32_t FACTORY_RESET_PWDEN; /*!< Factory reset password enable */ 970 __IO uint32_t FACTORY_RESET_PWD[4]; /*!< 128-bit Password for factory reset to be saved into the device. */ 971 __IO uint32_t FACTORY_RESET_PARAMS_ACK; /*!< Acknowledgment for the Factory Reset Params Command */ 972 uint32_t RESERVED5; 973 __IO uint32_t FACTORY_RESET_PASSWORD[4]; /*!< 128-bit Password for factory reset. */ 974 __IO uint32_t FACTORY_RESET_ACK; /*!< Acknowledgment for the Factory Reset Command */ 975 uint32_t RESERVED6[2]; 976 __IO uint32_t MB_END; /*!< Mailbox end */ 977 } FL_BOOTOVER_MAILBOX_Type; 978 979 /*@}*/ /* end of group FL_BOOTOVER_MAILBOX */ 980 981 982 /****************************************************************************** 983 * LCD_F Registers 984 ******************************************************************************/ 985 /** @addtogroup LCD_F MSP432P4111 (LCD_F) 986 @{ 987 */ 988 typedef struct { 989 __IO uint32_t CTL; /*!< LCD_F control */ 990 __IO uint32_t BMCTL; /*!< LCD_F blinking and memory control */ 991 __IO uint32_t VCTL; /*!< LCD_F voltage control */ 992 __IO uint32_t PCTL0; /*!< LCD_F port control 0 */ 993 __IO uint32_t PCTL1; /*!< LCD_F port control 1 */ 994 __IO uint32_t CSSEL0; /*!< LCD_F COM/SEG select register 0 */ 995 __IO uint32_t CSSEL1; /*!< LCD_F COM/SEG select register 1 */ 996 __IO uint32_t ANMCTL; /*!< LCD_F Animation Control Register */ 997 uint32_t RESERVED0[60]; 998 __IO uint32_t IE; /*!< LCD_F interrupt enable register */ 999 __I uint32_t IFG; /*!< LCD_F interrupt flag register */ 1000 __O uint32_t SETIFG; /*!< LCD_F set interrupt flag register */ 1001 __O uint32_t CLRIFG; /*!< LCD_F clear interrupt flag register */ 1002 __IO uint8_t M[48]; /*!< LCD memory registers */ 1003 uint8_t RESERVED1[16]; 1004 __IO uint8_t BM[48]; /*!< LCD Blinking memory registers */ 1005 uint8_t RESERVED2[16]; 1006 __IO uint8_t ANM[8]; /*!< LCD Animation memory registers */ 1007 } LCD_F_Type; 1008 1009 /*@}*/ /* end of group LCD_F */ 1010 1011 1012 /****************************************************************************** 1013 * PCM Registers 1014 ******************************************************************************/ 1015 /** @addtogroup PCM MSP432P4111 (PCM) 1016 @{ 1017 */ 1018 typedef struct { 1019 __IO uint32_t CTL0; /*!< Control 0 Register */ 1020 __IO uint32_t CTL1; /*!< Control 1 Register */ 1021 __IO uint32_t IE; /*!< Interrupt Enable Register */ 1022 __I uint32_t IFG; /*!< Interrupt Flag Register */ 1023 __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 1024 } PCM_Type; 1025 1026 /*@}*/ /* end of group PCM */ 1027 1028 1029 /****************************************************************************** 1030 * PMAP Registers 1031 ******************************************************************************/ 1032 /** @addtogroup PMAP MSP432P4111 (PMAP) 1033 @{ 1034 */ 1035 typedef struct { 1036 __IO uint16_t KEYID; /*!< Port Mapping Key Register */ 1037 __IO uint16_t CTL; /*!< Port Mapping Control Register */ 1038 } PMAP_COMMON_Type; 1039 1040 typedef struct { 1041 union { 1042 __IO uint16_t PMAP_REGISTER[4]; /*!< Port Mapping Registers */ 1043 struct { 1044 __IO uint8_t PMAP_REGISTER0; /*!< Port Mapping Register Bit 0 */ 1045 __IO uint8_t PMAP_REGISTER1; /*!< Port Mapping Register Bit 1 */ 1046 __IO uint8_t PMAP_REGISTER2; /*!< Port Mapping Register Bit 2 */ 1047 __IO uint8_t PMAP_REGISTER3; /*!< Port Mapping Register Bit 3 */ 1048 __IO uint8_t PMAP_REGISTER4; /*!< Port Mapping Register Bit 4 */ 1049 __IO uint8_t PMAP_REGISTER5; /*!< Port Mapping Register Bit 5 */ 1050 __IO uint8_t PMAP_REGISTER6; /*!< Port Mapping Register Bit 6 */ 1051 __IO uint8_t PMAP_REGISTER7; /*!< Port Mapping Register Bit 7 */ 1052 }; 1053 }; 1054 } PMAP_REGISTER_Type; 1055 1056 /*@}*/ /* end of group PMAP */ 1057 1058 1059 /****************************************************************************** 1060 * PSS Registers 1061 ******************************************************************************/ 1062 /** @addtogroup PSS MSP432P4111 (PSS) 1063 @{ 1064 */ 1065 typedef struct { 1066 __IO uint32_t KEY; /*!< Key Register */ 1067 __IO uint32_t CTL0; /*!< Control 0 Register */ 1068 uint32_t RESERVED0[11]; 1069 __IO uint32_t IE; /*!< Interrupt Enable Register */ 1070 __I uint32_t IFG; /*!< Interrupt Flag Register */ 1071 __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 1072 } PSS_Type; 1073 1074 /*@}*/ /* end of group PSS */ 1075 1076 1077 /****************************************************************************** 1078 * REF_A Registers 1079 ******************************************************************************/ 1080 /** @addtogroup REF_A MSP432P4111 (REF_A) 1081 @{ 1082 */ 1083 typedef struct { 1084 __IO uint16_t CTL0; /*!< REF Control Register 0 */ 1085 } REF_A_Type; 1086 1087 /*@}*/ /* end of group REF_A */ 1088 1089 1090 /****************************************************************************** 1091 * RSTCTL Registers 1092 ******************************************************************************/ 1093 /** @addtogroup RSTCTL MSP432P4111 (RSTCTL) 1094 @{ 1095 */ 1096 typedef struct { 1097 __IO uint32_t RESET_REQ; /*!< Reset Request Register */ 1098 __I uint32_t HARDRESET_STAT; /*!< Hard Reset Status Register */ 1099 __IO uint32_t HARDRESET_CLR; /*!< Hard Reset Status Clear Register */ 1100 __IO uint32_t HARDRESET_SET; /*!< Hard Reset Status Set Register */ 1101 __I uint32_t SOFTRESET_STAT; /*!< Soft Reset Status Register */ 1102 __IO uint32_t SOFTRESET_CLR; /*!< Soft Reset Status Clear Register */ 1103 __IO uint32_t SOFTRESET_SET; /*!< Soft Reset Status Set Register */ 1104 uint32_t RESERVED0[57]; 1105 __I uint32_t PSSRESET_STAT; /*!< PSS Reset Status Register */ 1106 __IO uint32_t PSSRESET_CLR; /*!< PSS Reset Status Clear Register */ 1107 __I uint32_t PCMRESET_STAT; /*!< PCM Reset Status Register */ 1108 __IO uint32_t PCMRESET_CLR; /*!< PCM Reset Status Clear Register */ 1109 __I uint32_t PINRESET_STAT; /*!< Pin Reset Status Register */ 1110 __IO uint32_t PINRESET_CLR; /*!< Pin Reset Status Clear Register */ 1111 __I uint32_t REBOOTRESET_STAT; /*!< Reboot Reset Status Register */ 1112 __IO uint32_t REBOOTRESET_CLR; /*!< Reboot Reset Status Clear Register */ 1113 __I uint32_t CSRESET_STAT; /*!< CS Reset Status Register */ 1114 __IO uint32_t CSRESET_CLR; /*!< CS Reset Status Clear Register */ 1115 } RSTCTL_Type; 1116 1117 /*@}*/ /* end of group RSTCTL */ 1118 1119 1120 /****************************************************************************** 1121 * RTC_C Registers 1122 ******************************************************************************/ 1123 /** @addtogroup RTC_C MSP432P4111 (RTC_C) 1124 @{ 1125 */ 1126 typedef struct { 1127 __IO uint16_t CTL0; /*!< RTCCTL0 Register */ 1128 __IO uint16_t CTL13; /*!< RTCCTL13 Register */ 1129 __IO uint16_t OCAL; /*!< RTCOCAL Register */ 1130 __IO uint16_t TCMP; /*!< RTCTCMP Register */ 1131 __IO uint16_t PS0CTL; /*!< Real-Time Clock Prescale Timer 0 Control Register */ 1132 __IO uint16_t PS1CTL; /*!< Real-Time Clock Prescale Timer 1 Control Register */ 1133 __IO uint16_t PS; /*!< Real-Time Clock Prescale Timer Counter Register */ 1134 __I uint16_t IV; /*!< Real-Time Clock Interrupt Vector Register */ 1135 __IO uint16_t TIM0; /*!< RTCTIM0 Register Hexadecimal Format */ 1136 __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week */ 1137 __IO uint16_t DATE; /*!< RTCDATE - Hexadecimal Format */ 1138 __IO uint16_t YEAR; /*!< RTCYEAR Register Hexadecimal Format */ 1139 __IO uint16_t AMINHR; /*!< RTCMINHR - Hexadecimal Format */ 1140 __IO uint16_t ADOWDAY; /*!< RTCADOWDAY - Hexadecimal Format */ 1141 __IO uint16_t BIN2BCD; /*!< Binary-to-BCD Conversion Register */ 1142 __IO uint16_t BCD2BIN; /*!< BCD-to-Binary Conversion Register */ 1143 } RTC_C_Type; 1144 1145 /*@}*/ /* end of group RTC_C */ 1146 1147 /** @addtogroup RTC_C_BCD MSP432P4111 (RTC_C_BCD) 1148 @{ 1149 */ 1150 typedef struct { 1151 uint16_t RESERVED0[8]; 1152 __IO uint16_t TIM0; /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */ 1153 __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week - BCD Format */ 1154 __IO uint16_t DATE; /*!< Real-Time Clock Date - BCD Format */ 1155 __IO uint16_t YEAR; /*!< Real-Time Clock Year Register - BCD Format */ 1156 __IO uint16_t AMINHR; /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */ 1157 __IO uint16_t ADOWDAY; /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */ 1158 } RTC_C_BCD_Type; 1159 1160 /*@}*/ /* end of group RTC_C_BCD */ 1161 1162 1163 /****************************************************************************** 1164 * SYSCTL_A Registers 1165 ******************************************************************************/ 1166 /** @addtogroup SYSCTL_A MSP432P4111 (SYSCTL_A) 1167 @{ 1168 */ 1169 typedef struct { 1170 __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ 1171 __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ 1172 __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ 1173 __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ 1174 __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ 1175 __I uint32_t SRAM_NUMBANKS; /*!< SRAM Number of Banks Register */ 1176 __I uint32_t SRAM_NUMBLOCKS; /*!< SRAM Number of Blocks Register */ 1177 uint32_t RESERVED0; 1178 __I uint32_t MAINFLASH_SIZE; /*!< Flash Main Memory Size Register */ 1179 __I uint32_t INFOFLASH_SIZE; /*!< Flash Information Memory Size Register */ 1180 uint32_t RESERVED1[2]; 1181 __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ 1182 uint32_t RESERVED2[3]; 1183 __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ 1184 uint32_t RESERVED3[3]; 1185 __IO uint32_t SRAM_BANKEN_CTL0; /*!< SRAM Bank Enable Control Register 0 */ 1186 __IO uint32_t SRAM_BANKEN_CTL1; /*!< SRAM Bank Enable Control Register 1 */ 1187 __IO uint32_t SRAM_BANKEN_CTL2; /*!< SRAM Bank Enable Control Register 2 */ 1188 __IO uint32_t SRAM_BANKEN_CTL3; /*!< SRAM Bank Enable Control Register 3 */ 1189 uint32_t RESERVED4[4]; 1190 __IO uint32_t SRAM_BLKRET_CTL0; /*!< SRAM Block Retention Control Register 0 */ 1191 __IO uint32_t SRAM_BLKRET_CTL1; /*!< SRAM Block Retention Control Register 1 */ 1192 __IO uint32_t SRAM_BLKRET_CTL2; /*!< SRAM Block Retention Control Register 2 */ 1193 __IO uint32_t SRAM_BLKRET_CTL3; /*!< SRAM Block Retention Control Register 3 */ 1194 uint32_t RESERVED5[4]; 1195 __I uint32_t SRAM_STAT; /*!< SRAM Status Register */ 1196 } SYSCTL_A_Type; 1197 1198 typedef struct { 1199 __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ 1200 __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ 1201 __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ 1202 __IO uint32_t RESET_REQ; /*!< Reset Request Register */ 1203 __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ 1204 uint32_t RESERVED10[2]; 1205 __I uint32_t SYSTEM_STAT; /*!< System Status Register */ 1206 } SYSCTL_A_Boot_Type; 1207 1208 /*@}*/ /* end of group SYSCTL_A */ 1209 1210 1211 /****************************************************************************** 1212 * Timer32 Registers 1213 ******************************************************************************/ 1214 /** @addtogroup Timer32 MSP432P4111 (Timer32) 1215 @{ 1216 */ 1217 typedef struct { 1218 __IO uint32_t LOAD; /*!< Timer Load Register */ 1219 __I uint32_t VALUE; /*!< Timer Current Value Register */ 1220 __IO uint32_t CONTROL; /*!< Timer Timer Control Register */ 1221 __O uint32_t INTCLR; /*!< Timer Interrupt Clear Register */ 1222 __I uint32_t RIS; /*!< Timer Raw Interrupt Status Register */ 1223 __I uint32_t MIS; /*!< Timer Interrupt Status Register */ 1224 __IO uint32_t BGLOAD; /*!< Timer Background Load Register */ 1225 } Timer32_Type; 1226 1227 /*@}*/ /* end of group Timer32 */ 1228 1229 1230 /****************************************************************************** 1231 * Timer_A Registers 1232 ******************************************************************************/ 1233 /** @addtogroup Timer_A MSP432P4111 (Timer_A) 1234 @{ 1235 */ 1236 typedef struct { 1237 __IO uint16_t CTL; /*!< TimerAx Control Register */ 1238 __IO uint16_t CCTL[5]; /*!< Timer_A Capture/Compare Control Register */ 1239 uint16_t RESERVED0[2]; 1240 __IO uint16_t R; /*!< TimerA register */ 1241 __IO uint16_t CCR[5]; /*!< Timer_A Capture/Compare Register */ 1242 uint16_t RESERVED1[2]; 1243 __IO uint16_t EX0; /*!< TimerAx Expansion 0 Register */ 1244 uint16_t RESERVED2[6]; 1245 __I uint16_t IV; /*!< TimerAx Interrupt Vector Register */ 1246 } Timer_A_Type; 1247 1248 /*@}*/ /* end of group Timer_A */ 1249 1250 1251 /****************************************************************************** 1252 * TLV Registers 1253 ******************************************************************************/ 1254 /** @addtogroup TLV MSP432P4111 (TLV) 1255 @{ 1256 */ 1257 typedef struct { 1258 __I uint32_t TLV_CHECKSUM; /*!< TLV Checksum */ 1259 __I uint32_t DEVICE_INFO_TAG; /*!< Device Info Tag */ 1260 __I uint32_t DEVICE_INFO_LEN; /*!< Device Info Length */ 1261 __I uint32_t DEVICE_ID; /*!< Device ID */ 1262 __I uint32_t HWREV; /*!< HW Revision */ 1263 __I uint32_t BCREV; /*!< Boot Code Revision */ 1264 __I uint32_t ROM_DRVLIB_REV; /*!< ROM Driver Library Revision */ 1265 __I uint32_t DIE_REC_TAG; /*!< Die Record Tag */ 1266 __I uint32_t DIE_REC_LEN; /*!< Die Record Length */ 1267 __I uint32_t DIE_XPOS; /*!< Die X-Position */ 1268 __I uint32_t DIE_YPOS; /*!< Die Y-Position */ 1269 __I uint32_t WAFER_ID; /*!< Wafer ID */ 1270 __I uint32_t LOT_ID; /*!< Lot ID */ 1271 __I uint32_t RESERVED0; /*!< Reserved */ 1272 __I uint32_t RESERVED1; /*!< Reserved */ 1273 __I uint32_t RESERVED2; /*!< Reserved */ 1274 __I uint32_t TEST_RESULTS; /*!< Test Results */ 1275 __I uint32_t CS_CAL_TAG; /*!< Clock System Calibration Tag */ 1276 __I uint32_t CS_CAL_LEN; /*!< Clock System Calibration Length */ 1277 __I uint32_t DCOIR_FCAL_RSEL04; /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */ 1278 __I uint32_t DCOIR_FCAL_RSEL5; /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */ 1279 __I uint32_t RESERVED3; /*!< Reserved */ 1280 __I uint32_t RESERVED4; /*!< Reserved */ 1281 __I uint32_t RESERVED5; /*!< Reserved */ 1282 __I uint32_t RESERVED6; /*!< Reserved */ 1283 __I uint32_t DCOIR_CONSTK_RSEL04; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */ 1284 __I uint32_t DCOIR_CONSTK_RSEL5; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */ 1285 __I uint32_t DCOER_FCAL_RSEL04; /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */ 1286 __I uint32_t DCOER_FCAL_RSEL5; /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */ 1287 __I uint32_t RESERVED7; /*!< Reserved */ 1288 __I uint32_t RESERVED8; /*!< Reserved */ 1289 __I uint32_t RESERVED9; /*!< Reserved */ 1290 __I uint32_t RESERVED10; /*!< Reserved */ 1291 __I uint32_t DCOER_CONSTK_RSEL04; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */ 1292 __I uint32_t DCOER_CONSTK_RSEL5; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */ 1293 __I uint32_t ADC14_CAL_TAG; /*!< ADC14 Calibration Tag */ 1294 __I uint32_t ADC14_CAL_LEN; /*!< ADC14 Calibration Length */ 1295 __I uint32_t ADC_GAIN_FACTOR; /*!< ADC Gain Factor */ 1296 __I uint32_t ADC_OFFSET; /*!< ADC Offset */ 1297 __I uint32_t RESERVED11; /*!< Reserved */ 1298 __I uint32_t RESERVED12; /*!< Reserved */ 1299 __I uint32_t RESERVED13; /*!< Reserved */ 1300 __I uint32_t RESERVED14; /*!< Reserved */ 1301 __I uint32_t RESERVED15; /*!< Reserved */ 1302 __I uint32_t RESERVED16; /*!< Reserved */ 1303 __I uint32_t RESERVED17; /*!< Reserved */ 1304 __I uint32_t RESERVED18; /*!< Reserved */ 1305 __I uint32_t RESERVED19; /*!< Reserved */ 1306 __I uint32_t RESERVED20; /*!< Reserved */ 1307 __I uint32_t RESERVED21; /*!< Reserved */ 1308 __I uint32_t RESERVED22; /*!< Reserved */ 1309 __I uint32_t RESERVED23; /*!< Reserved */ 1310 __I uint32_t RESERVED24; /*!< Reserved */ 1311 __I uint32_t RESERVED25; /*!< Reserved */ 1312 __I uint32_t RESERVED26; /*!< Reserved */ 1313 __I uint32_t ADC14_REF1P2V_TS30C; /*!< ADC14 1.2V Reference Temp. Sensor 30C */ 1314 __I uint32_t ADC14_REF1P2V_TS85C; /*!< ADC14 1.2V Reference Temp. Sensor 85C */ 1315 __I uint32_t ADC14_REF1P45V_TS30C; /*!< ADC14 1.45V Reference Temp. Sensor 30C */ 1316 __I uint32_t ADC14_REF1P45V_TS85C; /*!< ADC14 1.45V Reference Temp. Sensor 85C */ 1317 __I uint32_t ADC14_REF2P5V_TS30C; /*!< ADC14 2.5V Reference Temp. Sensor 30C */ 1318 __I uint32_t ADC14_REF2P5V_TS85C; /*!< ADC14 2.5V Reference Temp. Sensor 85C */ 1319 __I uint32_t REF_CAL_TAG; /*!< REF Calibration Tag */ 1320 __I uint32_t REF_CAL_LEN; /*!< REF Calibration Length */ 1321 __I uint32_t REF_1P2V; /*!< REF 1.2V Reference */ 1322 __I uint32_t REF_1P45V; /*!< REF 1.45V Reference */ 1323 __I uint32_t REF_2P5V; /*!< REF 2.5V Reference */ 1324 __I uint32_t FLASH_INFO_TAG; /*!< Flash Info Tag */ 1325 __I uint32_t FLASH_INFO_LEN; /*!< Flash Info Length */ 1326 __I uint32_t FLASH_MAX_PROG_PULSES; /*!< Flash Maximum Programming Pulses */ 1327 __I uint32_t FLASH_MAX_ERASE_PULSES; /*!< Flash Maximum Erase Pulses */ 1328 __I uint32_t RANDOM_NUM_TAG; /*!< 128-bit Random Number Tag */ 1329 __I uint32_t RANDOM_NUM_LEN; /*!< 128-bit Random Number Length */ 1330 __I uint32_t RANDOM_NUM_1; /*!< 32-bit Random Number 1 */ 1331 __I uint32_t RANDOM_NUM_2; /*!< 32-bit Random Number 2 */ 1332 __I uint32_t RANDOM_NUM_3; /*!< 32-bit Random Number 3 */ 1333 __I uint32_t RANDOM_NUM_4; /*!< 32-bit Random Number 4 */ 1334 __I uint32_t BSL_CFG_TAG; /*!< BSL Configuration Tag */ 1335 __I uint32_t BSL_CFG_LEN; /*!< BSL Configuration Length */ 1336 __I uint32_t BSL_PERIPHIF_SEL; /*!< BSL Peripheral Interface Selection */ 1337 __I uint32_t BSL_PORTIF_CFG_UART; /*!< BSL Port Interface Configuration for UART */ 1338 __I uint32_t BSL_PORTIF_CFG_SPI; /*!< BSL Port Interface Configuration for SPI */ 1339 __I uint32_t BSL_PORTIF_CFG_I2C; /*!< BSL Port Interface Configuration for I2C */ 1340 __I uint32_t TLV_END; /*!< TLV End Word */ 1341 } TLV_Type; 1342 1343 /*@}*/ /* end of group TLV */ 1344 1345 1346 /****************************************************************************** 1347 * WDT_A Registers 1348 ******************************************************************************/ 1349 /** @addtogroup WDT_A MSP432P4111 (WDT_A) 1350 @{ 1351 */ 1352 typedef struct { 1353 uint16_t RESERVED0[6]; 1354 __IO uint16_t CTL; /*!< Watchdog Timer Control Register */ 1355 } WDT_A_Type; 1356 1357 /*@}*/ /* end of group WDT_A */ 1358 1359 1360 #if defined ( __CC_ARM ) 1361 #pragma no_anon_unions 1362 #endif 1363 1364 /*@}*/ /* end of group MSP432P4111_Peripherals */ 1365 1366 /****************************************************************************** 1367 * Peripheral declaration * 1368 ******************************************************************************/ 1369 /** @addtogroup MSP432P4111_PeripheralDecl MSP432P4111 Peripheral Declaration 1370 @{ 1371 */ 1372 1373 #define ADC14 ((ADC14_Type *) ADC14_BASE) 1374 #define AES256 ((AES256_Type *) AES256_BASE) 1375 #define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE) 1376 #define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE) 1377 #define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE) 1378 #define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE) 1379 #define CRC32 ((CRC32_Type *) CRC32_BASE) 1380 #define CS ((CS_Type *) CS_BASE) 1381 #define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000)) 1382 #define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020)) 1383 #define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040)) 1384 #define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060)) 1385 #define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080)) 1386 #define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120)) 1387 #define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000)) 1388 #define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000)) 1389 #define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020)) 1390 #define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020)) 1391 #define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040)) 1392 #define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040)) 1393 #define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060)) 1394 #define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060)) 1395 #define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080)) 1396 #define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080)) 1397 #define DMA_Channel ((DMA_Channel_Type *) DMA_BASE) 1398 #define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000)) 1399 #define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE) 1400 #define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE) 1401 #define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE) 1402 #define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE) 1403 #define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE) 1404 #define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE) 1405 #define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE) 1406 #define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE) 1407 #define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE) 1408 #define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE) 1409 #define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE) 1410 #define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE) 1411 #define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE) 1412 #define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE) 1413 #define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE) 1414 #define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE) 1415 #define FLCTL_A ((FLCTL_A_Type *) FLCTL_A_BASE) 1416 #define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE) 1417 #define LCD_F ((LCD_F_Type *) LCD_F_BASE) 1418 #define PCM ((PCM_Type *) PCM_BASE) 1419 #define PMAP ((PMAP_COMMON_Type*) PMAP_BASE) 1420 #define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008)) 1421 #define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010)) 1422 #define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018)) 1423 #define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020)) 1424 #define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028)) 1425 #define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030)) 1426 #define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038)) 1427 #define PSS ((PSS_Type *) PSS_BASE) 1428 #define REF_A ((REF_A_Type *) REF_A_BASE) 1429 #define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) 1430 #define RTC_C ((RTC_C_Type *) RTC_C_BASE) 1431 #define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE) 1432 #define SYSCTL_A ((SYSCTL_A_Type *) SYSCTL_A_BASE) 1433 #define SYSCTL_A_Boot ((SYSCTL_A_Boot_Type *) (SYSCTL_A_BASE + 0x1000)) 1434 #define TIMER32_1 ((Timer32_Type *) TIMER32_BASE) 1435 #define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020)) 1436 #define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE) 1437 #define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE) 1438 #define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE) 1439 #define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE) 1440 #define TLV ((TLV_Type *) TLV_BASE) 1441 #define WDT_A ((WDT_A_Type *) WDT_A_BASE) 1442 1443 1444 /*@}*/ /* end of group MSP432P4111_PeripheralDecl */ 1445 1446 /*@}*/ /* end of group MSP432P4111_Definitions */ 1447 1448 #endif /* __CMSIS_CONFIG__ */ 1449 1450 /****************************************************************************** 1451 * Peripheral register control bits * 1452 ******************************************************************************/ 1453 1454 /****************************************************************************** 1455 * ADC14 Bits 1456 ******************************************************************************/ 1457 /* ADC14_CTL0[SC] Bits */ 1458 #define ADC14_CTL0_SC_OFS ( 0) /*!< ADC14SC Bit Offset */ 1459 #define ADC14_CTL0_SC ((uint32_t)0x00000001) /*!< ADC14 start conversion */ 1460 /* ADC14_CTL0[ENC] Bits */ 1461 #define ADC14_CTL0_ENC_OFS ( 1) /*!< ADC14ENC Bit Offset */ 1462 #define ADC14_CTL0_ENC ((uint32_t)0x00000002) /*!< ADC14 enable conversion */ 1463 /* ADC14_CTL0[ON] Bits */ 1464 #define ADC14_CTL0_ON_OFS ( 4) /*!< ADC14ON Bit Offset */ 1465 #define ADC14_CTL0_ON ((uint32_t)0x00000010) /*!< ADC14 on */ 1466 /* ADC14_CTL0[MSC] Bits */ 1467 #define ADC14_CTL0_MSC_OFS ( 7) /*!< ADC14MSC Bit Offset */ 1468 #define ADC14_CTL0_MSC ((uint32_t)0x00000080) /*!< ADC14 multiple sample and conversion */ 1469 /* ADC14_CTL0[SHT0] Bits */ 1470 #define ADC14_CTL0_SHT0_OFS ( 8) /*!< ADC14SHT0 Bit Offset */ 1471 #define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /*!< ADC14SHT0 Bit Mask */ 1472 #define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /*!< SHT0 Bit 0 */ 1473 #define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /*!< SHT0 Bit 1 */ 1474 #define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /*!< SHT0 Bit 2 */ 1475 #define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /*!< SHT0 Bit 3 */ 1476 #define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /*!< 4 */ 1477 #define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /*!< 8 */ 1478 #define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /*!< 16 */ 1479 #define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /*!< 32 */ 1480 #define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /*!< 64 */ 1481 #define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /*!< 96 */ 1482 #define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /*!< 128 */ 1483 #define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /*!< 192 */ 1484 #define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /*!< 4 */ 1485 #define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /*!< 8 */ 1486 #define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /*!< 16 */ 1487 #define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /*!< 32 */ 1488 #define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /*!< 64 */ 1489 #define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /*!< 96 */ 1490 #define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /*!< 128 */ 1491 #define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /*!< 192 */ 1492 /* ADC14_CTL0[SHT1] Bits */ 1493 #define ADC14_CTL0_SHT1_OFS (12) /*!< ADC14SHT1 Bit Offset */ 1494 #define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /*!< ADC14SHT1 Bit Mask */ 1495 #define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /*!< SHT1 Bit 0 */ 1496 #define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /*!< SHT1 Bit 1 */ 1497 #define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /*!< SHT1 Bit 2 */ 1498 #define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /*!< SHT1 Bit 3 */ 1499 #define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /*!< 4 */ 1500 #define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /*!< 8 */ 1501 #define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /*!< 16 */ 1502 #define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /*!< 32 */ 1503 #define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /*!< 64 */ 1504 #define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /*!< 96 */ 1505 #define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /*!< 128 */ 1506 #define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /*!< 192 */ 1507 #define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /*!< 4 */ 1508 #define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /*!< 8 */ 1509 #define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /*!< 16 */ 1510 #define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /*!< 32 */ 1511 #define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /*!< 64 */ 1512 #define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /*!< 96 */ 1513 #define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /*!< 128 */ 1514 #define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /*!< 192 */ 1515 /* ADC14_CTL0[BUSY] Bits */ 1516 #define ADC14_CTL0_BUSY_OFS (16) /*!< ADC14BUSY Bit Offset */ 1517 #define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /*!< ADC14 busy */ 1518 /* ADC14_CTL0[CONSEQ] Bits */ 1519 #define ADC14_CTL0_CONSEQ_OFS (17) /*!< ADC14CONSEQ Bit Offset */ 1520 #define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /*!< ADC14CONSEQ Bit Mask */ 1521 #define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /*!< CONSEQ Bit 0 */ 1522 #define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /*!< CONSEQ Bit 1 */ 1523 #define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /*!< Single-channel, single-conversion */ 1524 #define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /*!< Sequence-of-channels */ 1525 #define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /*!< Repeat-single-channel */ 1526 #define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /*!< Repeat-sequence-of-channels */ 1527 /* ADC14_CTL0[SSEL] Bits */ 1528 #define ADC14_CTL0_SSEL_OFS (19) /*!< ADC14SSEL Bit Offset */ 1529 #define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /*!< ADC14SSEL Bit Mask */ 1530 #define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /*!< SSEL Bit 0 */ 1531 #define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /*!< SSEL Bit 1 */ 1532 #define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /*!< SSEL Bit 2 */ 1533 #define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /*!< MODCLK */ 1534 #define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /*!< SYSCLK */ 1535 #define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /*!< ACLK */ 1536 #define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /*!< MCLK */ 1537 #define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /*!< SMCLK */ 1538 #define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /*!< HSMCLK */ 1539 #define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /*!< MODCLK */ 1540 #define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /*!< SYSCLK */ 1541 #define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /*!< ACLK */ 1542 #define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /*!< MCLK */ 1543 #define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /*!< SMCLK */ 1544 #define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /*!< HSMCLK */ 1545 /* ADC14_CTL0[DIV] Bits */ 1546 #define ADC14_CTL0_DIV_OFS (22) /*!< ADC14DIV Bit Offset */ 1547 #define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /*!< ADC14DIV Bit Mask */ 1548 #define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /*!< DIV Bit 0 */ 1549 #define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /*!< DIV Bit 1 */ 1550 #define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /*!< DIV Bit 2 */ 1551 #define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /*!< /1 */ 1552 #define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /*!< /2 */ 1553 #define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /*!< /3 */ 1554 #define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /*!< /4 */ 1555 #define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /*!< /5 */ 1556 #define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /*!< /6 */ 1557 #define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /*!< /7 */ 1558 #define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /*!< /8 */ 1559 #define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /*!< /1 */ 1560 #define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /*!< /2 */ 1561 #define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /*!< /3 */ 1562 #define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /*!< /4 */ 1563 #define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /*!< /5 */ 1564 #define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /*!< /6 */ 1565 #define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /*!< /7 */ 1566 #define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /*!< /8 */ 1567 /* ADC14_CTL0[ISSH] Bits */ 1568 #define ADC14_CTL0_ISSH_OFS (25) /*!< ADC14ISSH Bit Offset */ 1569 #define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /*!< ADC14 invert signal sample-and-hold */ 1570 /* ADC14_CTL0[SHP] Bits */ 1571 #define ADC14_CTL0_SHP_OFS (26) /*!< ADC14SHP Bit Offset */ 1572 #define ADC14_CTL0_SHP ((uint32_t)0x04000000) /*!< ADC14 sample-and-hold pulse-mode select */ 1573 /* ADC14_CTL0[SHS] Bits */ 1574 #define ADC14_CTL0_SHS_OFS (27) /*!< ADC14SHS Bit Offset */ 1575 #define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /*!< ADC14SHS Bit Mask */ 1576 #define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /*!< SHS Bit 0 */ 1577 #define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /*!< SHS Bit 1 */ 1578 #define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /*!< SHS Bit 2 */ 1579 #define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /*!< ADC14SC bit */ 1580 #define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /*!< See device-specific data sheet for source */ 1581 #define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /*!< See device-specific data sheet for source */ 1582 #define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /*!< See device-specific data sheet for source */ 1583 #define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /*!< See device-specific data sheet for source */ 1584 #define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /*!< See device-specific data sheet for source */ 1585 #define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /*!< See device-specific data sheet for source */ 1586 #define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /*!< See device-specific data sheet for source */ 1587 /* ADC14_CTL0[PDIV] Bits */ 1588 #define ADC14_CTL0_PDIV_OFS (30) /*!< ADC14PDIV Bit Offset */ 1589 #define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /*!< ADC14PDIV Bit Mask */ 1590 #define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /*!< PDIV Bit 0 */ 1591 #define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /*!< PDIV Bit 1 */ 1592 #define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /*!< Predivide by 1 */ 1593 #define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /*!< Predivide by 4 */ 1594 #define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /*!< Predivide by 32 */ 1595 #define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ 1596 #define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /*!< Predivide by 1 */ 1597 #define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /*!< Predivide by 4 */ 1598 #define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /*!< Predivide by 32 */ 1599 #define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ 1600 /* ADC14_CTL1[PWRMD] Bits */ 1601 #define ADC14_CTL1_PWRMD_OFS ( 0) /*!< ADC14PWRMD Bit Offset */ 1602 #define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /*!< ADC14PWRMD Bit Mask */ 1603 #define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /*!< PWRMD Bit 0 */ 1604 #define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /*!< PWRMD Bit 1 */ 1605 #define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /*!< Regular power mode for use with any resolution setting. Sample rate can be */ 1606 /* up to 1 Msps. */ 1607 #define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample */ 1608 /* rate must not exceed 200 ksps. */ 1609 /* ADC14_CTL1[REFBURST] Bits */ 1610 #define ADC14_CTL1_REFBURST_OFS ( 2) /*!< ADC14REFBURST Bit Offset */ 1611 #define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /*!< ADC14 reference buffer burst */ 1612 /* ADC14_CTL1[DF] Bits */ 1613 #define ADC14_CTL1_DF_OFS ( 3) /*!< ADC14DF Bit Offset */ 1614 #define ADC14_CTL1_DF ((uint32_t)0x00000008) /*!< ADC14 data read-back format */ 1615 /* ADC14_CTL1[RES] Bits */ 1616 #define ADC14_CTL1_RES_OFS ( 4) /*!< ADC14RES Bit Offset */ 1617 #define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /*!< ADC14RES Bit Mask */ 1618 #define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /*!< RES Bit 0 */ 1619 #define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /*!< RES Bit 1 */ 1620 #define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ 1621 #define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ 1622 #define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ 1623 #define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ 1624 #define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ 1625 #define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ 1626 #define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ 1627 #define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ 1628 /* ADC14_CTL1[CSTARTADD] Bits */ 1629 #define ADC14_CTL1_CSTARTADD_OFS (16) /*!< ADC14CSTARTADD Bit Offset */ 1630 #define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /*!< ADC14CSTARTADD Bit Mask */ 1631 /* ADC14_CTL1[BATMAP] Bits */ 1632 #define ADC14_CTL1_BATMAP_OFS (22) /*!< ADC14BATMAP Bit Offset */ 1633 #define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /*!< Controls 1/2 AVCC ADC input channel selection */ 1634 /* ADC14_CTL1[TCMAP] Bits */ 1635 #define ADC14_CTL1_TCMAP_OFS (23) /*!< ADC14TCMAP Bit Offset */ 1636 #define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /*!< Controls temperature sensor ADC input channel selection */ 1637 /* ADC14_CTL1[CH0MAP] Bits */ 1638 #define ADC14_CTL1_CH0MAP_OFS (24) /*!< ADC14CH0MAP Bit Offset */ 1639 #define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */ 1640 /* ADC14_CTL1[CH1MAP] Bits */ 1641 #define ADC14_CTL1_CH1MAP_OFS (25) /*!< ADC14CH1MAP Bit Offset */ 1642 #define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */ 1643 /* ADC14_CTL1[CH2MAP] Bits */ 1644 #define ADC14_CTL1_CH2MAP_OFS (26) /*!< ADC14CH2MAP Bit Offset */ 1645 #define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */ 1646 /* ADC14_CTL1[CH3MAP] Bits */ 1647 #define ADC14_CTL1_CH3MAP_OFS (27) /*!< ADC14CH3MAP Bit Offset */ 1648 #define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */ 1649 /* ADC14_LO0[LO0] Bits */ 1650 #define ADC14_LO0_LO0_OFS ( 0) /*!< ADC14LO0 Bit Offset */ 1651 #define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO0 Bit Mask */ 1652 /* ADC14_HI0[HI0] Bits */ 1653 #define ADC14_HI0_HI0_OFS ( 0) /*!< ADC14HI0 Bit Offset */ 1654 #define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI0 Bit Mask */ 1655 /* ADC14_LO1[LO1] Bits */ 1656 #define ADC14_LO1_LO1_OFS ( 0) /*!< ADC14LO1 Bit Offset */ 1657 #define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO1 Bit Mask */ 1658 /* ADC14_HI1[HI1] Bits */ 1659 #define ADC14_HI1_HI1_OFS ( 0) /*!< ADC14HI1 Bit Offset */ 1660 #define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI1 Bit Mask */ 1661 /* ADC14_MCTLN[INCH] Bits */ 1662 #define ADC14_MCTLN_INCH_OFS ( 0) /*!< ADC14INCH Bit Offset */ 1663 #define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /*!< ADC14INCH Bit Mask */ 1664 #define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /*!< INCH Bit 0 */ 1665 #define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /*!< INCH Bit 1 */ 1666 #define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /*!< INCH Bit 2 */ 1667 #define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /*!< INCH Bit 3 */ 1668 #define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /*!< INCH Bit 4 */ 1669 #define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ 1670 #define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ 1671 #define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ 1672 #define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ 1673 #define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ 1674 #define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ 1675 #define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ 1676 #define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ 1677 #define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ 1678 #define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ 1679 #define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ 1680 #define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ 1681 #define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ 1682 #define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ 1683 #define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ 1684 #define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ 1685 #define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ 1686 #define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ 1687 #define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ 1688 #define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ 1689 #define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ 1690 #define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ 1691 #define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ 1692 #define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ 1693 #define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ 1694 #define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ 1695 #define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ 1696 #define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ 1697 #define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ 1698 #define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ 1699 #define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ 1700 #define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ 1701 /* ADC14_MCTLN[EOS] Bits */ 1702 #define ADC14_MCTLN_EOS_OFS ( 7) /*!< ADC14EOS Bit Offset */ 1703 #define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /*!< End of sequence */ 1704 /* ADC14_MCTLN[VRSEL] Bits */ 1705 #define ADC14_MCTLN_VRSEL_OFS ( 8) /*!< ADC14VRSEL Bit Offset */ 1706 #define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /*!< ADC14VRSEL Bit Mask */ 1707 #define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /*!< VRSEL Bit 0 */ 1708 #define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /*!< VRSEL Bit 1 */ 1709 #define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /*!< VRSEL Bit 2 */ 1710 #define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /*!< VRSEL Bit 3 */ 1711 #define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /*!< V(R+) = AVCC, V(R-) = AVSS */ 1712 #define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /*!< V(R+) = VREF buffered, V(R-) = AVSS */ 1713 #define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /*!< V(R+) = VeREF+, V(R-) = VeREF- */ 1714 #define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */ 1715 /* ADC14_MCTLN[DIF] Bits */ 1716 #define ADC14_MCTLN_DIF_OFS (13) /*!< ADC14DIF Bit Offset */ 1717 #define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /*!< Differential mode */ 1718 /* ADC14_MCTLN[WINC] Bits */ 1719 #define ADC14_MCTLN_WINC_OFS (14) /*!< ADC14WINC Bit Offset */ 1720 #define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /*!< Comparator window enable */ 1721 /* ADC14_MCTLN[WINCTH] Bits */ 1722 #define ADC14_MCTLN_WINCTH_OFS (15) /*!< ADC14WINCTH Bit Offset */ 1723 #define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /*!< Window comparator threshold register selection */ 1724 /* ADC14_MEMN[CONVRES] Bits */ 1725 #define ADC14_MEMN_CONVRES_OFS ( 0) /*!< Conversion_Results Bit Offset */ 1726 #define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /*!< Conversion_Results Bit Mask */ 1727 /* ADC14_IER0[IE0] Bits */ 1728 #define ADC14_IER0_IE0_OFS ( 0) /*!< ADC14IE0 Bit Offset */ 1729 #define ADC14_IER0_IE0 ((uint32_t)0x00000001) /*!< Interrupt enable */ 1730 /* ADC14_IER0[IE1] Bits */ 1731 #define ADC14_IER0_IE1_OFS ( 1) /*!< ADC14IE1 Bit Offset */ 1732 #define ADC14_IER0_IE1 ((uint32_t)0x00000002) /*!< Interrupt enable */ 1733 /* ADC14_IER0[IE2] Bits */ 1734 #define ADC14_IER0_IE2_OFS ( 2) /*!< ADC14IE2 Bit Offset */ 1735 #define ADC14_IER0_IE2 ((uint32_t)0x00000004) /*!< Interrupt enable */ 1736 /* ADC14_IER0[IE3] Bits */ 1737 #define ADC14_IER0_IE3_OFS ( 3) /*!< ADC14IE3 Bit Offset */ 1738 #define ADC14_IER0_IE3 ((uint32_t)0x00000008) /*!< Interrupt enable */ 1739 /* ADC14_IER0[IE4] Bits */ 1740 #define ADC14_IER0_IE4_OFS ( 4) /*!< ADC14IE4 Bit Offset */ 1741 #define ADC14_IER0_IE4 ((uint32_t)0x00000010) /*!< Interrupt enable */ 1742 /* ADC14_IER0[IE5] Bits */ 1743 #define ADC14_IER0_IE5_OFS ( 5) /*!< ADC14IE5 Bit Offset */ 1744 #define ADC14_IER0_IE5 ((uint32_t)0x00000020) /*!< Interrupt enable */ 1745 /* ADC14_IER0[IE6] Bits */ 1746 #define ADC14_IER0_IE6_OFS ( 6) /*!< ADC14IE6 Bit Offset */ 1747 #define ADC14_IER0_IE6 ((uint32_t)0x00000040) /*!< Interrupt enable */ 1748 /* ADC14_IER0[IE7] Bits */ 1749 #define ADC14_IER0_IE7_OFS ( 7) /*!< ADC14IE7 Bit Offset */ 1750 #define ADC14_IER0_IE7 ((uint32_t)0x00000080) /*!< Interrupt enable */ 1751 /* ADC14_IER0[IE8] Bits */ 1752 #define ADC14_IER0_IE8_OFS ( 8) /*!< ADC14IE8 Bit Offset */ 1753 #define ADC14_IER0_IE8 ((uint32_t)0x00000100) /*!< Interrupt enable */ 1754 /* ADC14_IER0[IE9] Bits */ 1755 #define ADC14_IER0_IE9_OFS ( 9) /*!< ADC14IE9 Bit Offset */ 1756 #define ADC14_IER0_IE9 ((uint32_t)0x00000200) /*!< Interrupt enable */ 1757 /* ADC14_IER0[IE10] Bits */ 1758 #define ADC14_IER0_IE10_OFS (10) /*!< ADC14IE10 Bit Offset */ 1759 #define ADC14_IER0_IE10 ((uint32_t)0x00000400) /*!< Interrupt enable */ 1760 /* ADC14_IER0[IE11] Bits */ 1761 #define ADC14_IER0_IE11_OFS (11) /*!< ADC14IE11 Bit Offset */ 1762 #define ADC14_IER0_IE11 ((uint32_t)0x00000800) /*!< Interrupt enable */ 1763 /* ADC14_IER0[IE12] Bits */ 1764 #define ADC14_IER0_IE12_OFS (12) /*!< ADC14IE12 Bit Offset */ 1765 #define ADC14_IER0_IE12 ((uint32_t)0x00001000) /*!< Interrupt enable */ 1766 /* ADC14_IER0[IE13] Bits */ 1767 #define ADC14_IER0_IE13_OFS (13) /*!< ADC14IE13 Bit Offset */ 1768 #define ADC14_IER0_IE13 ((uint32_t)0x00002000) /*!< Interrupt enable */ 1769 /* ADC14_IER0[IE14] Bits */ 1770 #define ADC14_IER0_IE14_OFS (14) /*!< ADC14IE14 Bit Offset */ 1771 #define ADC14_IER0_IE14 ((uint32_t)0x00004000) /*!< Interrupt enable */ 1772 /* ADC14_IER0[IE15] Bits */ 1773 #define ADC14_IER0_IE15_OFS (15) /*!< ADC14IE15 Bit Offset */ 1774 #define ADC14_IER0_IE15 ((uint32_t)0x00008000) /*!< Interrupt enable */ 1775 /* ADC14_IER0[IE16] Bits */ 1776 #define ADC14_IER0_IE16_OFS (16) /*!< ADC14IE16 Bit Offset */ 1777 #define ADC14_IER0_IE16 ((uint32_t)0x00010000) /*!< Interrupt enable */ 1778 /* ADC14_IER0[IE17] Bits */ 1779 #define ADC14_IER0_IE17_OFS (17) /*!< ADC14IE17 Bit Offset */ 1780 #define ADC14_IER0_IE17 ((uint32_t)0x00020000) /*!< Interrupt enable */ 1781 /* ADC14_IER0[IE19] Bits */ 1782 #define ADC14_IER0_IE19_OFS (19) /*!< ADC14IE19 Bit Offset */ 1783 #define ADC14_IER0_IE19 ((uint32_t)0x00080000) /*!< Interrupt enable */ 1784 /* ADC14_IER0[IE18] Bits */ 1785 #define ADC14_IER0_IE18_OFS (18) /*!< ADC14IE18 Bit Offset */ 1786 #define ADC14_IER0_IE18 ((uint32_t)0x00040000) /*!< Interrupt enable */ 1787 /* ADC14_IER0[IE20] Bits */ 1788 #define ADC14_IER0_IE20_OFS (20) /*!< ADC14IE20 Bit Offset */ 1789 #define ADC14_IER0_IE20 ((uint32_t)0x00100000) /*!< Interrupt enable */ 1790 /* ADC14_IER0[IE21] Bits */ 1791 #define ADC14_IER0_IE21_OFS (21) /*!< ADC14IE21 Bit Offset */ 1792 #define ADC14_IER0_IE21 ((uint32_t)0x00200000) /*!< Interrupt enable */ 1793 /* ADC14_IER0[IE22] Bits */ 1794 #define ADC14_IER0_IE22_OFS (22) /*!< ADC14IE22 Bit Offset */ 1795 #define ADC14_IER0_IE22 ((uint32_t)0x00400000) /*!< Interrupt enable */ 1796 /* ADC14_IER0[IE23] Bits */ 1797 #define ADC14_IER0_IE23_OFS (23) /*!< ADC14IE23 Bit Offset */ 1798 #define ADC14_IER0_IE23 ((uint32_t)0x00800000) /*!< Interrupt enable */ 1799 /* ADC14_IER0[IE24] Bits */ 1800 #define ADC14_IER0_IE24_OFS (24) /*!< ADC14IE24 Bit Offset */ 1801 #define ADC14_IER0_IE24 ((uint32_t)0x01000000) /*!< Interrupt enable */ 1802 /* ADC14_IER0[IE25] Bits */ 1803 #define ADC14_IER0_IE25_OFS (25) /*!< ADC14IE25 Bit Offset */ 1804 #define ADC14_IER0_IE25 ((uint32_t)0x02000000) /*!< Interrupt enable */ 1805 /* ADC14_IER0[IE26] Bits */ 1806 #define ADC14_IER0_IE26_OFS (26) /*!< ADC14IE26 Bit Offset */ 1807 #define ADC14_IER0_IE26 ((uint32_t)0x04000000) /*!< Interrupt enable */ 1808 /* ADC14_IER0[IE27] Bits */ 1809 #define ADC14_IER0_IE27_OFS (27) /*!< ADC14IE27 Bit Offset */ 1810 #define ADC14_IER0_IE27 ((uint32_t)0x08000000) /*!< Interrupt enable */ 1811 /* ADC14_IER0[IE28] Bits */ 1812 #define ADC14_IER0_IE28_OFS (28) /*!< ADC14IE28 Bit Offset */ 1813 #define ADC14_IER0_IE28 ((uint32_t)0x10000000) /*!< Interrupt enable */ 1814 /* ADC14_IER0[IE29] Bits */ 1815 #define ADC14_IER0_IE29_OFS (29) /*!< ADC14IE29 Bit Offset */ 1816 #define ADC14_IER0_IE29 ((uint32_t)0x20000000) /*!< Interrupt enable */ 1817 /* ADC14_IER0[IE30] Bits */ 1818 #define ADC14_IER0_IE30_OFS (30) /*!< ADC14IE30 Bit Offset */ 1819 #define ADC14_IER0_IE30 ((uint32_t)0x40000000) /*!< Interrupt enable */ 1820 /* ADC14_IER0[IE31] Bits */ 1821 #define ADC14_IER0_IE31_OFS (31) /*!< ADC14IE31 Bit Offset */ 1822 #define ADC14_IER0_IE31 ((uint32_t)0x80000000) /*!< Interrupt enable */ 1823 /* ADC14_IER1[INIE] Bits */ 1824 #define ADC14_IER1_INIE_OFS ( 1) /*!< ADC14INIE Bit Offset */ 1825 #define ADC14_IER1_INIE ((uint32_t)0x00000002) /*!< Interrupt enable for ADC14MEMx within comparator window */ 1826 /* ADC14_IER1[LOIE] Bits */ 1827 #define ADC14_IER1_LOIE_OFS ( 2) /*!< ADC14LOIE Bit Offset */ 1828 #define ADC14_IER1_LOIE ((uint32_t)0x00000004) /*!< Interrupt enable for ADC14MEMx below comparator window */ 1829 /* ADC14_IER1[HIIE] Bits */ 1830 #define ADC14_IER1_HIIE_OFS ( 3) /*!< ADC14HIIE Bit Offset */ 1831 #define ADC14_IER1_HIIE ((uint32_t)0x00000008) /*!< Interrupt enable for ADC14MEMx above comparator window */ 1832 /* ADC14_IER1[OVIE] Bits */ 1833 #define ADC14_IER1_OVIE_OFS ( 4) /*!< ADC14OVIE Bit Offset */ 1834 #define ADC14_IER1_OVIE ((uint32_t)0x00000010) /*!< ADC14MEMx overflow-interrupt enable */ 1835 /* ADC14_IER1[TOVIE] Bits */ 1836 #define ADC14_IER1_TOVIE_OFS ( 5) /*!< ADC14TOVIE Bit Offset */ 1837 #define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /*!< ADC14 conversion-time-overflow interrupt enable */ 1838 /* ADC14_IER1[RDYIE] Bits */ 1839 #define ADC14_IER1_RDYIE_OFS ( 6) /*!< ADC14RDYIE Bit Offset */ 1840 #define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt enable */ 1841 /* ADC14_IFGR0[IFG0] Bits */ 1842 #define ADC14_IFGR0_IFG0_OFS ( 0) /*!< ADC14IFG0 Bit Offset */ 1843 #define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /*!< ADC14MEM0 interrupt flag */ 1844 /* ADC14_IFGR0[IFG1] Bits */ 1845 #define ADC14_IFGR0_IFG1_OFS ( 1) /*!< ADC14IFG1 Bit Offset */ 1846 #define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /*!< ADC14MEM1 interrupt flag */ 1847 /* ADC14_IFGR0[IFG2] Bits */ 1848 #define ADC14_IFGR0_IFG2_OFS ( 2) /*!< ADC14IFG2 Bit Offset */ 1849 #define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /*!< ADC14MEM2 interrupt flag */ 1850 /* ADC14_IFGR0[IFG3] Bits */ 1851 #define ADC14_IFGR0_IFG3_OFS ( 3) /*!< ADC14IFG3 Bit Offset */ 1852 #define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /*!< ADC14MEM3 interrupt flag */ 1853 /* ADC14_IFGR0[IFG4] Bits */ 1854 #define ADC14_IFGR0_IFG4_OFS ( 4) /*!< ADC14IFG4 Bit Offset */ 1855 #define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /*!< ADC14MEM4 interrupt flag */ 1856 /* ADC14_IFGR0[IFG5] Bits */ 1857 #define ADC14_IFGR0_IFG5_OFS ( 5) /*!< ADC14IFG5 Bit Offset */ 1858 #define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /*!< ADC14MEM5 interrupt flag */ 1859 /* ADC14_IFGR0[IFG6] Bits */ 1860 #define ADC14_IFGR0_IFG6_OFS ( 6) /*!< ADC14IFG6 Bit Offset */ 1861 #define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /*!< ADC14MEM6 interrupt flag */ 1862 /* ADC14_IFGR0[IFG7] Bits */ 1863 #define ADC14_IFGR0_IFG7_OFS ( 7) /*!< ADC14IFG7 Bit Offset */ 1864 #define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /*!< ADC14MEM7 interrupt flag */ 1865 /* ADC14_IFGR0[IFG8] Bits */ 1866 #define ADC14_IFGR0_IFG8_OFS ( 8) /*!< ADC14IFG8 Bit Offset */ 1867 #define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /*!< ADC14MEM8 interrupt flag */ 1868 /* ADC14_IFGR0[IFG9] Bits */ 1869 #define ADC14_IFGR0_IFG9_OFS ( 9) /*!< ADC14IFG9 Bit Offset */ 1870 #define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /*!< ADC14MEM9 interrupt flag */ 1871 /* ADC14_IFGR0[IFG10] Bits */ 1872 #define ADC14_IFGR0_IFG10_OFS (10) /*!< ADC14IFG10 Bit Offset */ 1873 #define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /*!< ADC14MEM10 interrupt flag */ 1874 /* ADC14_IFGR0[IFG11] Bits */ 1875 #define ADC14_IFGR0_IFG11_OFS (11) /*!< ADC14IFG11 Bit Offset */ 1876 #define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /*!< ADC14MEM11 interrupt flag */ 1877 /* ADC14_IFGR0[IFG12] Bits */ 1878 #define ADC14_IFGR0_IFG12_OFS (12) /*!< ADC14IFG12 Bit Offset */ 1879 #define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /*!< ADC14MEM12 interrupt flag */ 1880 /* ADC14_IFGR0[IFG13] Bits */ 1881 #define ADC14_IFGR0_IFG13_OFS (13) /*!< ADC14IFG13 Bit Offset */ 1882 #define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /*!< ADC14MEM13 interrupt flag */ 1883 /* ADC14_IFGR0[IFG14] Bits */ 1884 #define ADC14_IFGR0_IFG14_OFS (14) /*!< ADC14IFG14 Bit Offset */ 1885 #define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /*!< ADC14MEM14 interrupt flag */ 1886 /* ADC14_IFGR0[IFG15] Bits */ 1887 #define ADC14_IFGR0_IFG15_OFS (15) /*!< ADC14IFG15 Bit Offset */ 1888 #define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /*!< ADC14MEM15 interrupt flag */ 1889 /* ADC14_IFGR0[IFG16] Bits */ 1890 #define ADC14_IFGR0_IFG16_OFS (16) /*!< ADC14IFG16 Bit Offset */ 1891 #define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /*!< ADC14MEM16 interrupt flag */ 1892 /* ADC14_IFGR0[IFG17] Bits */ 1893 #define ADC14_IFGR0_IFG17_OFS (17) /*!< ADC14IFG17 Bit Offset */ 1894 #define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /*!< ADC14MEM17 interrupt flag */ 1895 /* ADC14_IFGR0[IFG18] Bits */ 1896 #define ADC14_IFGR0_IFG18_OFS (18) /*!< ADC14IFG18 Bit Offset */ 1897 #define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /*!< ADC14MEM18 interrupt flag */ 1898 /* ADC14_IFGR0[IFG19] Bits */ 1899 #define ADC14_IFGR0_IFG19_OFS (19) /*!< ADC14IFG19 Bit Offset */ 1900 #define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /*!< ADC14MEM19 interrupt flag */ 1901 /* ADC14_IFGR0[IFG20] Bits */ 1902 #define ADC14_IFGR0_IFG20_OFS (20) /*!< ADC14IFG20 Bit Offset */ 1903 #define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /*!< ADC14MEM20 interrupt flag */ 1904 /* ADC14_IFGR0[IFG21] Bits */ 1905 #define ADC14_IFGR0_IFG21_OFS (21) /*!< ADC14IFG21 Bit Offset */ 1906 #define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /*!< ADC14MEM21 interrupt flag */ 1907 /* ADC14_IFGR0[IFG22] Bits */ 1908 #define ADC14_IFGR0_IFG22_OFS (22) /*!< ADC14IFG22 Bit Offset */ 1909 #define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /*!< ADC14MEM22 interrupt flag */ 1910 /* ADC14_IFGR0[IFG23] Bits */ 1911 #define ADC14_IFGR0_IFG23_OFS (23) /*!< ADC14IFG23 Bit Offset */ 1912 #define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /*!< ADC14MEM23 interrupt flag */ 1913 /* ADC14_IFGR0[IFG24] Bits */ 1914 #define ADC14_IFGR0_IFG24_OFS (24) /*!< ADC14IFG24 Bit Offset */ 1915 #define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /*!< ADC14MEM24 interrupt flag */ 1916 /* ADC14_IFGR0[IFG25] Bits */ 1917 #define ADC14_IFGR0_IFG25_OFS (25) /*!< ADC14IFG25 Bit Offset */ 1918 #define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /*!< ADC14MEM25 interrupt flag */ 1919 /* ADC14_IFGR0[IFG26] Bits */ 1920 #define ADC14_IFGR0_IFG26_OFS (26) /*!< ADC14IFG26 Bit Offset */ 1921 #define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /*!< ADC14MEM26 interrupt flag */ 1922 /* ADC14_IFGR0[IFG27] Bits */ 1923 #define ADC14_IFGR0_IFG27_OFS (27) /*!< ADC14IFG27 Bit Offset */ 1924 #define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /*!< ADC14MEM27 interrupt flag */ 1925 /* ADC14_IFGR0[IFG28] Bits */ 1926 #define ADC14_IFGR0_IFG28_OFS (28) /*!< ADC14IFG28 Bit Offset */ 1927 #define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /*!< ADC14MEM28 interrupt flag */ 1928 /* ADC14_IFGR0[IFG29] Bits */ 1929 #define ADC14_IFGR0_IFG29_OFS (29) /*!< ADC14IFG29 Bit Offset */ 1930 #define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /*!< ADC14MEM29 interrupt flag */ 1931 /* ADC14_IFGR0[IFG30] Bits */ 1932 #define ADC14_IFGR0_IFG30_OFS (30) /*!< ADC14IFG30 Bit Offset */ 1933 #define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /*!< ADC14MEM30 interrupt flag */ 1934 /* ADC14_IFGR0[IFG31] Bits */ 1935 #define ADC14_IFGR0_IFG31_OFS (31) /*!< ADC14IFG31 Bit Offset */ 1936 #define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /*!< ADC14MEM31 interrupt flag */ 1937 /* ADC14_IFGR1[INIFG] Bits */ 1938 #define ADC14_IFGR1_INIFG_OFS ( 1) /*!< ADC14INIFG Bit Offset */ 1939 #define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /*!< Interrupt flag for ADC14MEMx within comparator window */ 1940 /* ADC14_IFGR1[LOIFG] Bits */ 1941 #define ADC14_IFGR1_LOIFG_OFS ( 2) /*!< ADC14LOIFG Bit Offset */ 1942 #define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /*!< Interrupt flag for ADC14MEMx below comparator window */ 1943 /* ADC14_IFGR1[HIIFG] Bits */ 1944 #define ADC14_IFGR1_HIIFG_OFS ( 3) /*!< ADC14HIIFG Bit Offset */ 1945 #define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /*!< Interrupt flag for ADC14MEMx above comparator window */ 1946 /* ADC14_IFGR1[OVIFG] Bits */ 1947 #define ADC14_IFGR1_OVIFG_OFS ( 4) /*!< ADC14OVIFG Bit Offset */ 1948 #define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /*!< ADC14MEMx overflow interrupt flag */ 1949 /* ADC14_IFGR1[TOVIFG] Bits */ 1950 #define ADC14_IFGR1_TOVIFG_OFS ( 5) /*!< ADC14TOVIFG Bit Offset */ 1951 #define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /*!< ADC14 conversion time overflow interrupt flag */ 1952 /* ADC14_IFGR1[RDYIFG] Bits */ 1953 #define ADC14_IFGR1_RDYIFG_OFS ( 6) /*!< ADC14RDYIFG Bit Offset */ 1954 #define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt flag */ 1955 /* ADC14_CLRIFGR0[CLRIFG0] Bits */ 1956 #define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /*!< CLRADC14IFG0 Bit Offset */ 1957 #define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /*!< clear ADC14IFG0 */ 1958 /* ADC14_CLRIFGR0[CLRIFG1] Bits */ 1959 #define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /*!< CLRADC14IFG1 Bit Offset */ 1960 #define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /*!< clear ADC14IFG1 */ 1961 /* ADC14_CLRIFGR0[CLRIFG2] Bits */ 1962 #define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /*!< CLRADC14IFG2 Bit Offset */ 1963 #define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /*!< clear ADC14IFG2 */ 1964 /* ADC14_CLRIFGR0[CLRIFG3] Bits */ 1965 #define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /*!< CLRADC14IFG3 Bit Offset */ 1966 #define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /*!< clear ADC14IFG3 */ 1967 /* ADC14_CLRIFGR0[CLRIFG4] Bits */ 1968 #define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /*!< CLRADC14IFG4 Bit Offset */ 1969 #define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /*!< clear ADC14IFG4 */ 1970 /* ADC14_CLRIFGR0[CLRIFG5] Bits */ 1971 #define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /*!< CLRADC14IFG5 Bit Offset */ 1972 #define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /*!< clear ADC14IFG5 */ 1973 /* ADC14_CLRIFGR0[CLRIFG6] Bits */ 1974 #define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /*!< CLRADC14IFG6 Bit Offset */ 1975 #define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /*!< clear ADC14IFG6 */ 1976 /* ADC14_CLRIFGR0[CLRIFG7] Bits */ 1977 #define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /*!< CLRADC14IFG7 Bit Offset */ 1978 #define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /*!< clear ADC14IFG7 */ 1979 /* ADC14_CLRIFGR0[CLRIFG8] Bits */ 1980 #define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /*!< CLRADC14IFG8 Bit Offset */ 1981 #define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /*!< clear ADC14IFG8 */ 1982 /* ADC14_CLRIFGR0[CLRIFG9] Bits */ 1983 #define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /*!< CLRADC14IFG9 Bit Offset */ 1984 #define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /*!< clear ADC14IFG9 */ 1985 /* ADC14_CLRIFGR0[CLRIFG10] Bits */ 1986 #define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /*!< CLRADC14IFG10 Bit Offset */ 1987 #define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /*!< clear ADC14IFG10 */ 1988 /* ADC14_CLRIFGR0[CLRIFG11] Bits */ 1989 #define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /*!< CLRADC14IFG11 Bit Offset */ 1990 #define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /*!< clear ADC14IFG11 */ 1991 /* ADC14_CLRIFGR0[CLRIFG12] Bits */ 1992 #define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /*!< CLRADC14IFG12 Bit Offset */ 1993 #define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /*!< clear ADC14IFG12 */ 1994 /* ADC14_CLRIFGR0[CLRIFG13] Bits */ 1995 #define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /*!< CLRADC14IFG13 Bit Offset */ 1996 #define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /*!< clear ADC14IFG13 */ 1997 /* ADC14_CLRIFGR0[CLRIFG14] Bits */ 1998 #define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /*!< CLRADC14IFG14 Bit Offset */ 1999 #define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /*!< clear ADC14IFG14 */ 2000 /* ADC14_CLRIFGR0[CLRIFG15] Bits */ 2001 #define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /*!< CLRADC14IFG15 Bit Offset */ 2002 #define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /*!< clear ADC14IFG15 */ 2003 /* ADC14_CLRIFGR0[CLRIFG16] Bits */ 2004 #define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /*!< CLRADC14IFG16 Bit Offset */ 2005 #define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /*!< clear ADC14IFG16 */ 2006 /* ADC14_CLRIFGR0[CLRIFG17] Bits */ 2007 #define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /*!< CLRADC14IFG17 Bit Offset */ 2008 #define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /*!< clear ADC14IFG17 */ 2009 /* ADC14_CLRIFGR0[CLRIFG18] Bits */ 2010 #define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /*!< CLRADC14IFG18 Bit Offset */ 2011 #define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /*!< clear ADC14IFG18 */ 2012 /* ADC14_CLRIFGR0[CLRIFG19] Bits */ 2013 #define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /*!< CLRADC14IFG19 Bit Offset */ 2014 #define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /*!< clear ADC14IFG19 */ 2015 /* ADC14_CLRIFGR0[CLRIFG20] Bits */ 2016 #define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /*!< CLRADC14IFG20 Bit Offset */ 2017 #define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /*!< clear ADC14IFG20 */ 2018 /* ADC14_CLRIFGR0[CLRIFG21] Bits */ 2019 #define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /*!< CLRADC14IFG21 Bit Offset */ 2020 #define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /*!< clear ADC14IFG21 */ 2021 /* ADC14_CLRIFGR0[CLRIFG22] Bits */ 2022 #define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /*!< CLRADC14IFG22 Bit Offset */ 2023 #define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /*!< clear ADC14IFG22 */ 2024 /* ADC14_CLRIFGR0[CLRIFG23] Bits */ 2025 #define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /*!< CLRADC14IFG23 Bit Offset */ 2026 #define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /*!< clear ADC14IFG23 */ 2027 /* ADC14_CLRIFGR0[CLRIFG24] Bits */ 2028 #define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /*!< CLRADC14IFG24 Bit Offset */ 2029 #define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /*!< clear ADC14IFG24 */ 2030 /* ADC14_CLRIFGR0[CLRIFG25] Bits */ 2031 #define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /*!< CLRADC14IFG25 Bit Offset */ 2032 #define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /*!< clear ADC14IFG25 */ 2033 /* ADC14_CLRIFGR0[CLRIFG26] Bits */ 2034 #define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /*!< CLRADC14IFG26 Bit Offset */ 2035 #define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /*!< clear ADC14IFG26 */ 2036 /* ADC14_CLRIFGR0[CLRIFG27] Bits */ 2037 #define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /*!< CLRADC14IFG27 Bit Offset */ 2038 #define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /*!< clear ADC14IFG27 */ 2039 /* ADC14_CLRIFGR0[CLRIFG28] Bits */ 2040 #define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /*!< CLRADC14IFG28 Bit Offset */ 2041 #define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /*!< clear ADC14IFG28 */ 2042 /* ADC14_CLRIFGR0[CLRIFG29] Bits */ 2043 #define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /*!< CLRADC14IFG29 Bit Offset */ 2044 #define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /*!< clear ADC14IFG29 */ 2045 /* ADC14_CLRIFGR0[CLRIFG30] Bits */ 2046 #define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /*!< CLRADC14IFG30 Bit Offset */ 2047 #define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /*!< clear ADC14IFG30 */ 2048 /* ADC14_CLRIFGR0[CLRIFG31] Bits */ 2049 #define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /*!< CLRADC14IFG31 Bit Offset */ 2050 #define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /*!< clear ADC14IFG31 */ 2051 /* ADC14_CLRIFGR1[CLRINIFG] Bits */ 2052 #define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /*!< CLRADC14INIFG Bit Offset */ 2053 #define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /*!< clear ADC14INIFG */ 2054 /* ADC14_CLRIFGR1[CLRLOIFG] Bits */ 2055 #define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /*!< CLRADC14LOIFG Bit Offset */ 2056 #define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /*!< clear ADC14LOIFG */ 2057 /* ADC14_CLRIFGR1[CLRHIIFG] Bits */ 2058 #define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /*!< CLRADC14HIIFG Bit Offset */ 2059 #define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /*!< clear ADC14HIIFG */ 2060 /* ADC14_CLRIFGR1[CLROVIFG] Bits */ 2061 #define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /*!< CLRADC14OVIFG Bit Offset */ 2062 #define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /*!< clear ADC14OVIFG */ 2063 /* ADC14_CLRIFGR1[CLRTOVIFG] Bits */ 2064 #define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /*!< CLRADC14TOVIFG Bit Offset */ 2065 #define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /*!< clear ADC14TOVIFG */ 2066 /* ADC14_CLRIFGR1[CLRRDYIFG] Bits */ 2067 #define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /*!< CLRADC14RDYIFG Bit Offset */ 2068 #define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /*!< clear ADC14RDYIFG */ 2069 2070 /****************************************************************************** 2071 * AES256 Bits 2072 ******************************************************************************/ 2073 /* AES256_CTL0[OP] Bits */ 2074 #define AES256_CTL0_OP_OFS ( 0) /*!< AESOPx Bit Offset */ 2075 #define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /*!< AESOPx Bit Mask */ 2076 #define AES256_CTL0_OP0 ((uint16_t)0x0001) /*!< OP Bit 0 */ 2077 #define AES256_CTL0_OP1 ((uint16_t)0x0002) /*!< OP Bit 1 */ 2078 #define AES256_CTL0_OP_0 ((uint16_t)0x0000) /*!< Encryption */ 2079 #define AES256_CTL0_OP_1 ((uint16_t)0x0001) /*!< Decryption. The provided key is the same key used for encryption */ 2080 #define AES256_CTL0_OP_2 ((uint16_t)0x0002) /*!< Generate first round key required for decryption */ 2081 #define AES256_CTL0_OP_3 ((uint16_t)0x0003) /*!< Decryption. The provided key is the first round key required for decryption */ 2082 /* AES256_CTL0[KL] Bits */ 2083 #define AES256_CTL0_KL_OFS ( 2) /*!< AESKLx Bit Offset */ 2084 #define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /*!< AESKLx Bit Mask */ 2085 #define AES256_CTL0_KL0 ((uint16_t)0x0004) /*!< KL Bit 0 */ 2086 #define AES256_CTL0_KL1 ((uint16_t)0x0008) /*!< KL Bit 1 */ 2087 #define AES256_CTL0_KL_0 ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ 2088 #define AES256_CTL0_KL_1 ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ 2089 #define AES256_CTL0_KL_2 ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ 2090 #define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ 2091 #define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ 2092 #define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ 2093 /* AES256_CTL0[CM] Bits */ 2094 #define AES256_CTL0_CM_OFS ( 5) /*!< AESCMx Bit Offset */ 2095 #define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /*!< AESCMx Bit Mask */ 2096 #define AES256_CTL0_CM0 ((uint16_t)0x0020) /*!< CM Bit 0 */ 2097 #define AES256_CTL0_CM1 ((uint16_t)0x0040) /*!< CM Bit 1 */ 2098 #define AES256_CTL0_CM_0 ((uint16_t)0x0000) /*!< ECB */ 2099 #define AES256_CTL0_CM_1 ((uint16_t)0x0020) /*!< CBC */ 2100 #define AES256_CTL0_CM_2 ((uint16_t)0x0040) /*!< OFB */ 2101 #define AES256_CTL0_CM_3 ((uint16_t)0x0060) /*!< CFB */ 2102 #define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /*!< ECB */ 2103 #define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /*!< CBC */ 2104 #define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /*!< OFB */ 2105 #define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /*!< CFB */ 2106 /* AES256_CTL0[SWRST] Bits */ 2107 #define AES256_CTL0_SWRST_OFS ( 7) /*!< AESSWRST Bit Offset */ 2108 #define AES256_CTL0_SWRST ((uint16_t)0x0080) /*!< AES software reset */ 2109 /* AES256_CTL0[RDYIFG] Bits */ 2110 #define AES256_CTL0_RDYIFG_OFS ( 8) /*!< AESRDYIFG Bit Offset */ 2111 #define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /*!< AES ready interrupt flag */ 2112 /* AES256_CTL0[ERRFG] Bits */ 2113 #define AES256_CTL0_ERRFG_OFS (11) /*!< AESERRFG Bit Offset */ 2114 #define AES256_CTL0_ERRFG ((uint16_t)0x0800) /*!< AES error flag */ 2115 /* AES256_CTL0[RDYIE] Bits */ 2116 #define AES256_CTL0_RDYIE_OFS (12) /*!< AESRDYIE Bit Offset */ 2117 #define AES256_CTL0_RDYIE ((uint16_t)0x1000) /*!< AES ready interrupt enable */ 2118 /* AES256_CTL0[CMEN] Bits */ 2119 #define AES256_CTL0_CMEN_OFS (15) /*!< AESCMEN Bit Offset */ 2120 #define AES256_CTL0_CMEN ((uint16_t)0x8000) /*!< AES cipher mode enable */ 2121 /* AES256_CTL1[BLKCNT] Bits */ 2122 #define AES256_CTL1_BLKCNT_OFS ( 0) /*!< AESBLKCNTx Bit Offset */ 2123 #define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /*!< AESBLKCNTx Bit Mask */ 2124 #define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /*!< BLKCNT Bit 0 */ 2125 #define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /*!< BLKCNT Bit 1 */ 2126 #define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /*!< BLKCNT Bit 2 */ 2127 #define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /*!< BLKCNT Bit 3 */ 2128 #define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /*!< BLKCNT Bit 4 */ 2129 #define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /*!< BLKCNT Bit 5 */ 2130 #define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /*!< BLKCNT Bit 6 */ 2131 #define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /*!< BLKCNT Bit 7 */ 2132 /* AES256_STAT[BUSY] Bits */ 2133 #define AES256_STAT_BUSY_OFS ( 0) /*!< AESBUSY Bit Offset */ 2134 #define AES256_STAT_BUSY ((uint16_t)0x0001) /*!< AES accelerator module busy */ 2135 /* AES256_STAT[KEYWR] Bits */ 2136 #define AES256_STAT_KEYWR_OFS ( 1) /*!< AESKEYWR Bit Offset */ 2137 #define AES256_STAT_KEYWR ((uint16_t)0x0002) /*!< All 16 bytes written to AESAKEY */ 2138 /* AES256_STAT[DINWR] Bits */ 2139 #define AES256_STAT_DINWR_OFS ( 2) /*!< AESDINWR Bit Offset */ 2140 #define AES256_STAT_DINWR ((uint16_t)0x0004) /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ 2141 /* AES256_STAT[DOUTRD] Bits */ 2142 #define AES256_STAT_DOUTRD_OFS ( 3) /*!< AESDOUTRD Bit Offset */ 2143 #define AES256_STAT_DOUTRD ((uint16_t)0x0008) /*!< All 16 bytes read from AESADOUT */ 2144 /* AES256_STAT[KEYCNT] Bits */ 2145 #define AES256_STAT_KEYCNT_OFS ( 4) /*!< AESKEYCNTx Bit Offset */ 2146 #define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /*!< AESKEYCNTx Bit Mask */ 2147 #define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /*!< KEYCNT Bit 0 */ 2148 #define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /*!< KEYCNT Bit 1 */ 2149 #define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /*!< KEYCNT Bit 2 */ 2150 #define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /*!< KEYCNT Bit 3 */ 2151 /* AES256_STAT[DINCNT] Bits */ 2152 #define AES256_STAT_DINCNT_OFS ( 8) /*!< AESDINCNTx Bit Offset */ 2153 #define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /*!< AESDINCNTx Bit Mask */ 2154 #define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /*!< DINCNT Bit 0 */ 2155 #define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /*!< DINCNT Bit 1 */ 2156 #define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /*!< DINCNT Bit 2 */ 2157 #define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /*!< DINCNT Bit 3 */ 2158 /* AES256_STAT[DOUTCNT] Bits */ 2159 #define AES256_STAT_DOUTCNT_OFS (12) /*!< AESDOUTCNTx Bit Offset */ 2160 #define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /*!< AESDOUTCNTx Bit Mask */ 2161 #define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /*!< DOUTCNT Bit 0 */ 2162 #define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /*!< DOUTCNT Bit 1 */ 2163 #define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /*!< DOUTCNT Bit 2 */ 2164 #define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /*!< DOUTCNT Bit 3 */ 2165 /* AES256_KEY[KEY0] Bits */ 2166 #define AES256_KEY_KEY0_OFS ( 0) /*!< AESKEY0x Bit Offset */ 2167 #define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /*!< AESKEY0x Bit Mask */ 2168 #define AES256_KEY_KEY00 ((uint16_t)0x0001) /*!< KEY0 Bit 0 */ 2169 #define AES256_KEY_KEY01 ((uint16_t)0x0002) /*!< KEY0 Bit 1 */ 2170 #define AES256_KEY_KEY02 ((uint16_t)0x0004) /*!< KEY0 Bit 2 */ 2171 #define AES256_KEY_KEY03 ((uint16_t)0x0008) /*!< KEY0 Bit 3 */ 2172 #define AES256_KEY_KEY04 ((uint16_t)0x0010) /*!< KEY0 Bit 4 */ 2173 #define AES256_KEY_KEY05 ((uint16_t)0x0020) /*!< KEY0 Bit 5 */ 2174 #define AES256_KEY_KEY06 ((uint16_t)0x0040) /*!< KEY0 Bit 6 */ 2175 #define AES256_KEY_KEY07 ((uint16_t)0x0080) /*!< KEY0 Bit 7 */ 2176 /* AES256_KEY[KEY1] Bits */ 2177 #define AES256_KEY_KEY1_OFS ( 8) /*!< AESKEY1x Bit Offset */ 2178 #define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /*!< AESKEY1x Bit Mask */ 2179 #define AES256_KEY_KEY10 ((uint16_t)0x0100) /*!< KEY1 Bit 0 */ 2180 #define AES256_KEY_KEY11 ((uint16_t)0x0200) /*!< KEY1 Bit 1 */ 2181 #define AES256_KEY_KEY12 ((uint16_t)0x0400) /*!< KEY1 Bit 2 */ 2182 #define AES256_KEY_KEY13 ((uint16_t)0x0800) /*!< KEY1 Bit 3 */ 2183 #define AES256_KEY_KEY14 ((uint16_t)0x1000) /*!< KEY1 Bit 4 */ 2184 #define AES256_KEY_KEY15 ((uint16_t)0x2000) /*!< KEY1 Bit 5 */ 2185 #define AES256_KEY_KEY16 ((uint16_t)0x4000) /*!< KEY1 Bit 6 */ 2186 #define AES256_KEY_KEY17 ((uint16_t)0x8000) /*!< KEY1 Bit 7 */ 2187 /* AES256_DIN[DIN0] Bits */ 2188 #define AES256_DIN_DIN0_OFS ( 0) /*!< AESDIN0x Bit Offset */ 2189 #define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /*!< AESDIN0x Bit Mask */ 2190 #define AES256_DIN_DIN00 ((uint16_t)0x0001) /*!< DIN0 Bit 0 */ 2191 #define AES256_DIN_DIN01 ((uint16_t)0x0002) /*!< DIN0 Bit 1 */ 2192 #define AES256_DIN_DIN02 ((uint16_t)0x0004) /*!< DIN0 Bit 2 */ 2193 #define AES256_DIN_DIN03 ((uint16_t)0x0008) /*!< DIN0 Bit 3 */ 2194 #define AES256_DIN_DIN04 ((uint16_t)0x0010) /*!< DIN0 Bit 4 */ 2195 #define AES256_DIN_DIN05 ((uint16_t)0x0020) /*!< DIN0 Bit 5 */ 2196 #define AES256_DIN_DIN06 ((uint16_t)0x0040) /*!< DIN0 Bit 6 */ 2197 #define AES256_DIN_DIN07 ((uint16_t)0x0080) /*!< DIN0 Bit 7 */ 2198 /* AES256_DIN[DIN1] Bits */ 2199 #define AES256_DIN_DIN1_OFS ( 8) /*!< AESDIN1x Bit Offset */ 2200 #define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /*!< AESDIN1x Bit Mask */ 2201 #define AES256_DIN_DIN10 ((uint16_t)0x0100) /*!< DIN1 Bit 0 */ 2202 #define AES256_DIN_DIN11 ((uint16_t)0x0200) /*!< DIN1 Bit 1 */ 2203 #define AES256_DIN_DIN12 ((uint16_t)0x0400) /*!< DIN1 Bit 2 */ 2204 #define AES256_DIN_DIN13 ((uint16_t)0x0800) /*!< DIN1 Bit 3 */ 2205 #define AES256_DIN_DIN14 ((uint16_t)0x1000) /*!< DIN1 Bit 4 */ 2206 #define AES256_DIN_DIN15 ((uint16_t)0x2000) /*!< DIN1 Bit 5 */ 2207 #define AES256_DIN_DIN16 ((uint16_t)0x4000) /*!< DIN1 Bit 6 */ 2208 #define AES256_DIN_DIN17 ((uint16_t)0x8000) /*!< DIN1 Bit 7 */ 2209 /* AES256_DOUT[DOUT0] Bits */ 2210 #define AES256_DOUT_DOUT0_OFS ( 0) /*!< AESDOUT0x Bit Offset */ 2211 #define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /*!< AESDOUT0x Bit Mask */ 2212 #define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /*!< DOUT0 Bit 0 */ 2213 #define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /*!< DOUT0 Bit 1 */ 2214 #define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /*!< DOUT0 Bit 2 */ 2215 #define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /*!< DOUT0 Bit 3 */ 2216 #define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /*!< DOUT0 Bit 4 */ 2217 #define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /*!< DOUT0 Bit 5 */ 2218 #define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /*!< DOUT0 Bit 6 */ 2219 #define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /*!< DOUT0 Bit 7 */ 2220 /* AES256_DOUT[DOUT1] Bits */ 2221 #define AES256_DOUT_DOUT1_OFS ( 8) /*!< AESDOUT1x Bit Offset */ 2222 #define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /*!< AESDOUT1x Bit Mask */ 2223 #define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /*!< DOUT1 Bit 0 */ 2224 #define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /*!< DOUT1 Bit 1 */ 2225 #define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /*!< DOUT1 Bit 2 */ 2226 #define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /*!< DOUT1 Bit 3 */ 2227 #define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /*!< DOUT1 Bit 4 */ 2228 #define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /*!< DOUT1 Bit 5 */ 2229 #define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /*!< DOUT1 Bit 6 */ 2230 #define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /*!< DOUT1 Bit 7 */ 2231 /* AES256_XDIN[XDIN0] Bits */ 2232 #define AES256_XDIN_XDIN0_OFS ( 0) /*!< AESXDIN0x Bit Offset */ 2233 #define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /*!< AESXDIN0x Bit Mask */ 2234 #define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /*!< XDIN0 Bit 0 */ 2235 #define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /*!< XDIN0 Bit 1 */ 2236 #define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /*!< XDIN0 Bit 2 */ 2237 #define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /*!< XDIN0 Bit 3 */ 2238 #define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /*!< XDIN0 Bit 4 */ 2239 #define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /*!< XDIN0 Bit 5 */ 2240 #define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /*!< XDIN0 Bit 6 */ 2241 #define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /*!< XDIN0 Bit 7 */ 2242 /* AES256_XDIN[XDIN1] Bits */ 2243 #define AES256_XDIN_XDIN1_OFS ( 8) /*!< AESXDIN1x Bit Offset */ 2244 #define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /*!< AESXDIN1x Bit Mask */ 2245 #define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /*!< XDIN1 Bit 0 */ 2246 #define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /*!< XDIN1 Bit 1 */ 2247 #define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /*!< XDIN1 Bit 2 */ 2248 #define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /*!< XDIN1 Bit 3 */ 2249 #define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /*!< XDIN1 Bit 4 */ 2250 #define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /*!< XDIN1 Bit 5 */ 2251 #define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /*!< XDIN1 Bit 6 */ 2252 #define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /*!< XDIN1 Bit 7 */ 2253 /* AES256_XIN[XIN0] Bits */ 2254 #define AES256_XIN_XIN0_OFS ( 0) /*!< AESXIN0x Bit Offset */ 2255 #define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /*!< AESXIN0x Bit Mask */ 2256 #define AES256_XIN_XIN00 ((uint16_t)0x0001) /*!< XIN0 Bit 0 */ 2257 #define AES256_XIN_XIN01 ((uint16_t)0x0002) /*!< XIN0 Bit 1 */ 2258 #define AES256_XIN_XIN02 ((uint16_t)0x0004) /*!< XIN0 Bit 2 */ 2259 #define AES256_XIN_XIN03 ((uint16_t)0x0008) /*!< XIN0 Bit 3 */ 2260 #define AES256_XIN_XIN04 ((uint16_t)0x0010) /*!< XIN0 Bit 4 */ 2261 #define AES256_XIN_XIN05 ((uint16_t)0x0020) /*!< XIN0 Bit 5 */ 2262 #define AES256_XIN_XIN06 ((uint16_t)0x0040) /*!< XIN0 Bit 6 */ 2263 #define AES256_XIN_XIN07 ((uint16_t)0x0080) /*!< XIN0 Bit 7 */ 2264 /* AES256_XIN[XIN1] Bits */ 2265 #define AES256_XIN_XIN1_OFS ( 8) /*!< AESXIN1x Bit Offset */ 2266 #define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /*!< AESXIN1x Bit Mask */ 2267 #define AES256_XIN_XIN10 ((uint16_t)0x0100) /*!< XIN1 Bit 0 */ 2268 #define AES256_XIN_XIN11 ((uint16_t)0x0200) /*!< XIN1 Bit 1 */ 2269 #define AES256_XIN_XIN12 ((uint16_t)0x0400) /*!< XIN1 Bit 2 */ 2270 #define AES256_XIN_XIN13 ((uint16_t)0x0800) /*!< XIN1 Bit 3 */ 2271 #define AES256_XIN_XIN14 ((uint16_t)0x1000) /*!< XIN1 Bit 4 */ 2272 #define AES256_XIN_XIN15 ((uint16_t)0x2000) /*!< XIN1 Bit 5 */ 2273 #define AES256_XIN_XIN16 ((uint16_t)0x4000) /*!< XIN1 Bit 6 */ 2274 #define AES256_XIN_XIN17 ((uint16_t)0x8000) /*!< XIN1 Bit 7 */ 2275 2276 /****************************************************************************** 2277 * CAPTIO Bits 2278 ******************************************************************************/ 2279 /* CAPTIO_CTL[PISEL] Bits */ 2280 #define CAPTIO_CTL_PISEL_OFS ( 1) /*!< CAPTIOPISELx Bit Offset */ 2281 #define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /*!< CAPTIOPISELx Bit Mask */ 2282 #define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /*!< PISEL Bit 0 */ 2283 #define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /*!< PISEL Bit 1 */ 2284 #define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /*!< PISEL Bit 2 */ 2285 #define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /*!< Px.0 */ 2286 #define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /*!< Px.1 */ 2287 #define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /*!< Px.2 */ 2288 #define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /*!< Px.3 */ 2289 #define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /*!< Px.4 */ 2290 #define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /*!< Px.5 */ 2291 #define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /*!< Px.6 */ 2292 #define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /*!< Px.7 */ 2293 /* CAPTIO_CTL[POSEL] Bits */ 2294 #define CAPTIO_CTL_POSEL_OFS ( 4) /*!< CAPTIOPOSELx Bit Offset */ 2295 #define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /*!< CAPTIOPOSELx Bit Mask */ 2296 #define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /*!< POSEL Bit 0 */ 2297 #define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /*!< POSEL Bit 1 */ 2298 #define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /*!< POSEL Bit 2 */ 2299 #define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /*!< POSEL Bit 3 */ 2300 #define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /*!< Px = PJ */ 2301 #define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /*!< Px = P1 */ 2302 #define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /*!< Px = P2 */ 2303 #define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /*!< Px = P3 */ 2304 #define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /*!< Px = P4 */ 2305 #define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /*!< Px = P5 */ 2306 #define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /*!< Px = P6 */ 2307 #define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /*!< Px = P7 */ 2308 #define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /*!< Px = P8 */ 2309 #define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /*!< Px = P9 */ 2310 #define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /*!< Px = P10 */ 2311 #define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /*!< Px = P11 */ 2312 #define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /*!< Px = P12 */ 2313 #define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /*!< Px = P13 */ 2314 #define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /*!< Px = P14 */ 2315 #define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /*!< Px = P15 */ 2316 #define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /*!< Px = PJ */ 2317 #define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /*!< Px = P1 */ 2318 #define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /*!< Px = P2 */ 2319 #define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /*!< Px = P3 */ 2320 #define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /*!< Px = P4 */ 2321 #define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /*!< Px = P5 */ 2322 #define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /*!< Px = P6 */ 2323 #define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /*!< Px = P7 */ 2324 #define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /*!< Px = P8 */ 2325 #define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /*!< Px = P9 */ 2326 #define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /*!< Px = P10 */ 2327 #define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /*!< Px = P11 */ 2328 #define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /*!< Px = P12 */ 2329 #define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /*!< Px = P13 */ 2330 #define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /*!< Px = P14 */ 2331 #define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /*!< Px = P15 */ 2332 /* CAPTIO_CTL[EN] Bits */ 2333 #define CAPTIO_CTL_EN_OFS ( 8) /*!< CAPTIOEN Bit Offset */ 2334 #define CAPTIO_CTL_EN ((uint16_t)0x0100) /*!< Capacitive Touch IO enable */ 2335 /* CAPTIO_CTL[STATE] Bits */ 2336 #define CAPTIO_CTL_STATE_OFS ( 9) /*!< CAPTIOSTATE Bit Offset */ 2337 #define CAPTIO_CTL_STATE ((uint16_t)0x0200) /*!< Capacitive Touch IO state */ 2338 2339 /****************************************************************************** 2340 * COMP_E Bits 2341 ******************************************************************************/ 2342 /* COMP_E_CTL0[IPSEL] Bits */ 2343 #define COMP_E_CTL0_IPSEL_OFS ( 0) /*!< CEIPSEL Bit Offset */ 2344 #define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /*!< CEIPSEL Bit Mask */ 2345 #define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /*!< IPSEL Bit 0 */ 2346 #define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /*!< IPSEL Bit 1 */ 2347 #define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /*!< IPSEL Bit 2 */ 2348 #define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /*!< IPSEL Bit 3 */ 2349 #define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ 2350 #define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /*!< Channel 1 selected */ 2351 #define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /*!< Channel 2 selected */ 2352 #define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /*!< Channel 3 selected */ 2353 #define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /*!< Channel 4 selected */ 2354 #define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /*!< Channel 5 selected */ 2355 #define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /*!< Channel 6 selected */ 2356 #define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /*!< Channel 7 selected */ 2357 #define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /*!< Channel 8 selected */ 2358 #define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /*!< Channel 9 selected */ 2359 #define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /*!< Channel 10 selected */ 2360 #define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /*!< Channel 11 selected */ 2361 #define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /*!< Channel 12 selected */ 2362 #define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /*!< Channel 13 selected */ 2363 #define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /*!< Channel 14 selected */ 2364 #define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /*!< Channel 15 selected */ 2365 /* COMP_E_CTL0[IPEN] Bits */ 2366 #define COMP_E_CTL0_IPEN_OFS ( 7) /*!< CEIPEN Bit Offset */ 2367 #define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /*!< Channel input enable for the V+ terminal */ 2368 /* COMP_E_CTL0[IMSEL] Bits */ 2369 #define COMP_E_CTL0_IMSEL_OFS ( 8) /*!< CEIMSEL Bit Offset */ 2370 #define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /*!< CEIMSEL Bit Mask */ 2371 #define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /*!< IMSEL Bit 0 */ 2372 #define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /*!< IMSEL Bit 1 */ 2373 #define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /*!< IMSEL Bit 2 */ 2374 #define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /*!< IMSEL Bit 3 */ 2375 #define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ 2376 #define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /*!< Channel 1 selected */ 2377 #define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /*!< Channel 2 selected */ 2378 #define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /*!< Channel 3 selected */ 2379 #define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /*!< Channel 4 selected */ 2380 #define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /*!< Channel 5 selected */ 2381 #define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /*!< Channel 6 selected */ 2382 #define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /*!< Channel 7 selected */ 2383 #define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /*!< Channel 8 selected */ 2384 #define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /*!< Channel 9 selected */ 2385 #define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /*!< Channel 10 selected */ 2386 #define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /*!< Channel 11 selected */ 2387 #define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /*!< Channel 12 selected */ 2388 #define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /*!< Channel 13 selected */ 2389 #define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /*!< Channel 14 selected */ 2390 #define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /*!< Channel 15 selected */ 2391 /* COMP_E_CTL0[IMEN] Bits */ 2392 #define COMP_E_CTL0_IMEN_OFS (15) /*!< CEIMEN Bit Offset */ 2393 #define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /*!< Channel input enable for the - terminal */ 2394 /* COMP_E_CTL1[OUT] Bits */ 2395 #define COMP_E_CTL1_OUT_OFS ( 0) /*!< CEOUT Bit Offset */ 2396 #define COMP_E_CTL1_OUT ((uint16_t)0x0001) /*!< Comparator output value */ 2397 /* COMP_E_CTL1[OUTPOL] Bits */ 2398 #define COMP_E_CTL1_OUTPOL_OFS ( 1) /*!< CEOUTPOL Bit Offset */ 2399 #define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /*!< Comparator output polarity */ 2400 /* COMP_E_CTL1[F] Bits */ 2401 #define COMP_E_CTL1_F_OFS ( 2) /*!< CEF Bit Offset */ 2402 #define COMP_E_CTL1_F ((uint16_t)0x0004) /*!< Comparator output filter */ 2403 /* COMP_E_CTL1[IES] Bits */ 2404 #define COMP_E_CTL1_IES_OFS ( 3) /*!< CEIES Bit Offset */ 2405 #define COMP_E_CTL1_IES ((uint16_t)0x0008) /*!< Interrupt edge select for CEIIFG and CEIFG */ 2406 /* COMP_E_CTL1[SHORT] Bits */ 2407 #define COMP_E_CTL1_SHORT_OFS ( 4) /*!< CESHORT Bit Offset */ 2408 #define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /*!< Input short */ 2409 /* COMP_E_CTL1[EX] Bits */ 2410 #define COMP_E_CTL1_EX_OFS ( 5) /*!< CEEX Bit Offset */ 2411 #define COMP_E_CTL1_EX ((uint16_t)0x0020) /*!< Exchange */ 2412 /* COMP_E_CTL1[FDLY] Bits */ 2413 #define COMP_E_CTL1_FDLY_OFS ( 6) /*!< CEFDLY Bit Offset */ 2414 #define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /*!< CEFDLY Bit Mask */ 2415 #define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /*!< FDLY Bit 0 */ 2416 #define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /*!< FDLY Bit 1 */ 2417 #define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /*!< Typical filter delay of TBD (450) ns */ 2418 #define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /*!< Typical filter delay of TBD (900) ns */ 2419 #define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /*!< Typical filter delay of TBD (1800) ns */ 2420 #define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /*!< Typical filter delay of TBD (3600) ns */ 2421 /* COMP_E_CTL1[PWRMD] Bits */ 2422 #define COMP_E_CTL1_PWRMD_OFS ( 8) /*!< CEPWRMD Bit Offset */ 2423 #define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /*!< CEPWRMD Bit Mask */ 2424 #define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /*!< PWRMD Bit 0 */ 2425 #define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /*!< PWRMD Bit 1 */ 2426 #define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /*!< High-speed mode */ 2427 #define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /*!< Normal mode */ 2428 #define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /*!< Ultra-low power mode */ 2429 /* COMP_E_CTL1[ON] Bits */ 2430 #define COMP_E_CTL1_ON_OFS (10) /*!< CEON Bit Offset */ 2431 #define COMP_E_CTL1_ON ((uint16_t)0x0400) /*!< Comparator On */ 2432 /* COMP_E_CTL1[MRVL] Bits */ 2433 #define COMP_E_CTL1_MRVL_OFS (11) /*!< CEMRVL Bit Offset */ 2434 #define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /*!< This bit is valid of CEMRVS is set to 1 */ 2435 /* COMP_E_CTL1[MRVS] Bits */ 2436 #define COMP_E_CTL1_MRVS_OFS (12) /*!< CEMRVS Bit Offset */ 2437 #define COMP_E_CTL1_MRVS ((uint16_t)0x1000) 2438 /* COMP_E_CTL2[REF0] Bits */ 2439 #define COMP_E_CTL2_REF0_OFS ( 0) /*!< CEREF0 Bit Offset */ 2440 #define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /*!< CEREF0 Bit Mask */ 2441 /* COMP_E_CTL2[RSEL] Bits */ 2442 #define COMP_E_CTL2_RSEL_OFS ( 5) /*!< CERSEL Bit Offset */ 2443 #define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /*!< Reference select */ 2444 /* COMP_E_CTL2[RS] Bits */ 2445 #define COMP_E_CTL2_RS_OFS ( 6) /*!< CERS Bit Offset */ 2446 #define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /*!< CERS Bit Mask */ 2447 #define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /*!< RS Bit 0 */ 2448 #define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /*!< RS Bit 1 */ 2449 #define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /*!< No current is drawn by the reference circuitry */ 2450 #define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /*!< VCC applied to the resistor ladder */ 2451 #define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /*!< Shared reference voltage applied to the resistor ladder */ 2452 #define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ 2453 /* COMP_E_CTL2[REF1] Bits */ 2454 #define COMP_E_CTL2_REF1_OFS ( 8) /*!< CEREF1 Bit Offset */ 2455 #define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /*!< CEREF1 Bit Mask */ 2456 /* COMP_E_CTL2[REFL] Bits */ 2457 #define COMP_E_CTL2_REFL_OFS (13) /*!< CEREFL Bit Offset */ 2458 #define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /*!< CEREFL Bit Mask */ 2459 #define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /*!< REFL Bit 0 */ 2460 #define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /*!< REFL Bit 1 */ 2461 #define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ 2462 #define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ 2463 #define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ 2464 #define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ 2465 #define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ 2466 #define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ 2467 #define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ 2468 #define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ 2469 /* COMP_E_CTL2[REFACC] Bits */ 2470 #define COMP_E_CTL2_REFACC_OFS (15) /*!< CEREFACC Bit Offset */ 2471 #define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /*!< Reference accuracy */ 2472 /* COMP_E_CTL3[PD0] Bits */ 2473 #define COMP_E_CTL3_PD0_OFS ( 0) /*!< CEPD0 Bit Offset */ 2474 #define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /*!< Port disable */ 2475 /* COMP_E_CTL3[PD1] Bits */ 2476 #define COMP_E_CTL3_PD1_OFS ( 1) /*!< CEPD1 Bit Offset */ 2477 #define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /*!< Port disable */ 2478 /* COMP_E_CTL3[PD2] Bits */ 2479 #define COMP_E_CTL3_PD2_OFS ( 2) /*!< CEPD2 Bit Offset */ 2480 #define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /*!< Port disable */ 2481 /* COMP_E_CTL3[PD3] Bits */ 2482 #define COMP_E_CTL3_PD3_OFS ( 3) /*!< CEPD3 Bit Offset */ 2483 #define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /*!< Port disable */ 2484 /* COMP_E_CTL3[PD4] Bits */ 2485 #define COMP_E_CTL3_PD4_OFS ( 4) /*!< CEPD4 Bit Offset */ 2486 #define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /*!< Port disable */ 2487 /* COMP_E_CTL3[PD5] Bits */ 2488 #define COMP_E_CTL3_PD5_OFS ( 5) /*!< CEPD5 Bit Offset */ 2489 #define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /*!< Port disable */ 2490 /* COMP_E_CTL3[PD6] Bits */ 2491 #define COMP_E_CTL3_PD6_OFS ( 6) /*!< CEPD6 Bit Offset */ 2492 #define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /*!< Port disable */ 2493 /* COMP_E_CTL3[PD7] Bits */ 2494 #define COMP_E_CTL3_PD7_OFS ( 7) /*!< CEPD7 Bit Offset */ 2495 #define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /*!< Port disable */ 2496 /* COMP_E_CTL3[PD8] Bits */ 2497 #define COMP_E_CTL3_PD8_OFS ( 8) /*!< CEPD8 Bit Offset */ 2498 #define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /*!< Port disable */ 2499 /* COMP_E_CTL3[PD9] Bits */ 2500 #define COMP_E_CTL3_PD9_OFS ( 9) /*!< CEPD9 Bit Offset */ 2501 #define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /*!< Port disable */ 2502 /* COMP_E_CTL3[PD10] Bits */ 2503 #define COMP_E_CTL3_PD10_OFS (10) /*!< CEPD10 Bit Offset */ 2504 #define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /*!< Port disable */ 2505 /* COMP_E_CTL3[PD11] Bits */ 2506 #define COMP_E_CTL3_PD11_OFS (11) /*!< CEPD11 Bit Offset */ 2507 #define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /*!< Port disable */ 2508 /* COMP_E_CTL3[PD12] Bits */ 2509 #define COMP_E_CTL3_PD12_OFS (12) /*!< CEPD12 Bit Offset */ 2510 #define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /*!< Port disable */ 2511 /* COMP_E_CTL3[PD13] Bits */ 2512 #define COMP_E_CTL3_PD13_OFS (13) /*!< CEPD13 Bit Offset */ 2513 #define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /*!< Port disable */ 2514 /* COMP_E_CTL3[PD14] Bits */ 2515 #define COMP_E_CTL3_PD14_OFS (14) /*!< CEPD14 Bit Offset */ 2516 #define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /*!< Port disable */ 2517 /* COMP_E_CTL3[PD15] Bits */ 2518 #define COMP_E_CTL3_PD15_OFS (15) /*!< CEPD15 Bit Offset */ 2519 #define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /*!< Port disable */ 2520 /* COMP_E_INT[IFG] Bits */ 2521 #define COMP_E_INT_IFG_OFS ( 0) /*!< CEIFG Bit Offset */ 2522 #define COMP_E_INT_IFG ((uint16_t)0x0001) /*!< Comparator output interrupt flag */ 2523 /* COMP_E_INT[IIFG] Bits */ 2524 #define COMP_E_INT_IIFG_OFS ( 1) /*!< CEIIFG Bit Offset */ 2525 #define COMP_E_INT_IIFG ((uint16_t)0x0002) /*!< Comparator output inverted interrupt flag */ 2526 /* COMP_E_INT[RDYIFG] Bits */ 2527 #define COMP_E_INT_RDYIFG_OFS ( 4) /*!< CERDYIFG Bit Offset */ 2528 #define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /*!< Comparator ready interrupt flag */ 2529 /* COMP_E_INT[IE] Bits */ 2530 #define COMP_E_INT_IE_OFS ( 8) /*!< CEIE Bit Offset */ 2531 #define COMP_E_INT_IE ((uint16_t)0x0100) /*!< Comparator output interrupt enable */ 2532 /* COMP_E_INT[IIE] Bits */ 2533 #define COMP_E_INT_IIE_OFS ( 9) /*!< CEIIE Bit Offset */ 2534 #define COMP_E_INT_IIE ((uint16_t)0x0200) /*!< Comparator output interrupt enable inverted polarity */ 2535 /* COMP_E_INT[RDYIE] Bits */ 2536 #define COMP_E_INT_RDYIE_OFS (12) /*!< CERDYIE Bit Offset */ 2537 #define COMP_E_INT_RDYIE ((uint16_t)0x1000) /*!< Comparator ready interrupt enable */ 2538 2539 /****************************************************************************** 2540 * COREDEBUG Bits 2541 ******************************************************************************/ 2542 2543 2544 /****************************************************************************** 2545 * CRC32 Bits 2546 ******************************************************************************/ 2547 2548 /****************************************************************************** 2549 * CS Bits 2550 ******************************************************************************/ 2551 /* CS_KEY[KEY] Bits */ 2552 #define CS_KEY_KEY_OFS ( 0) /*!< CSKEY Bit Offset */ 2553 #define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< CSKEY Bit Mask */ 2554 /* CS_CTL0[DCOTUNE] Bits */ 2555 #define CS_CTL0_DCOTUNE_OFS ( 0) /*!< DCOTUNE Bit Offset */ 2556 #define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /*!< DCOTUNE Bit Mask */ 2557 /* CS_CTL0[DCORSEL] Bits */ 2558 #define CS_CTL0_DCORSEL_OFS (16) /*!< DCORSEL Bit Offset */ 2559 #define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /*!< DCORSEL Bit Mask */ 2560 #define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /*!< DCORSEL Bit 0 */ 2561 #define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /*!< DCORSEL Bit 1 */ 2562 #define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /*!< DCORSEL Bit 2 */ 2563 #define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */ 2564 #define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */ 2565 #define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */ 2566 #define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */ 2567 #define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */ 2568 #define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */ 2569 /* CS_CTL0[DCORES] Bits */ 2570 #define CS_CTL0_DCORES_OFS (22) /*!< DCORES Bit Offset */ 2571 #define CS_CTL0_DCORES ((uint32_t)0x00400000) /*!< Enables the DCO external resistor mode */ 2572 /* CS_CTL0[DCOEN] Bits */ 2573 #define CS_CTL0_DCOEN_OFS (23) /*!< DCOEN Bit Offset */ 2574 #define CS_CTL0_DCOEN ((uint32_t)0x00800000) /*!< Enables the DCO oscillator */ 2575 /* CS_CTL1[SELM] Bits */ 2576 #define CS_CTL1_SELM_OFS ( 0) /*!< SELM Bit Offset */ 2577 #define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /*!< SELM Bit Mask */ 2578 #define CS_CTL1_SELM0 ((uint32_t)0x00000001) /*!< SELM Bit 0 */ 2579 #define CS_CTL1_SELM1 ((uint32_t)0x00000002) /*!< SELM Bit 1 */ 2580 #define CS_CTL1_SELM2 ((uint32_t)0x00000004) /*!< SELM Bit 2 */ 2581 #define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2582 #define CS_CTL1_SELM_1 ((uint32_t)0x00000001) 2583 #define CS_CTL1_SELM_2 ((uint32_t)0x00000002) 2584 #define CS_CTL1_SELM_3 ((uint32_t)0x00000003) 2585 #define CS_CTL1_SELM_4 ((uint32_t)0x00000004) 2586 #define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ 2587 #define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ 2588 #define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2589 #define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001) 2590 #define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002) 2591 #define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003) 2592 #define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004) 2593 #define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ 2594 #define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ 2595 /* CS_CTL1[SELS] Bits */ 2596 #define CS_CTL1_SELS_OFS ( 4) /*!< SELS Bit Offset */ 2597 #define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /*!< SELS Bit Mask */ 2598 #define CS_CTL1_SELS0 ((uint32_t)0x00000010) /*!< SELS Bit 0 */ 2599 #define CS_CTL1_SELS1 ((uint32_t)0x00000020) /*!< SELS Bit 1 */ 2600 #define CS_CTL1_SELS2 ((uint32_t)0x00000040) /*!< SELS Bit 2 */ 2601 #define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2602 #define CS_CTL1_SELS_1 ((uint32_t)0x00000010) 2603 #define CS_CTL1_SELS_2 ((uint32_t)0x00000020) 2604 #define CS_CTL1_SELS_3 ((uint32_t)0x00000030) 2605 #define CS_CTL1_SELS_4 ((uint32_t)0x00000040) 2606 #define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ 2607 #define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ 2608 #define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2609 #define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010) 2610 #define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020) 2611 #define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030) 2612 #define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040) 2613 #define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ 2614 #define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ 2615 /* CS_CTL1[SELA] Bits */ 2616 #define CS_CTL1_SELA_OFS ( 8) /*!< SELA Bit Offset */ 2617 #define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /*!< SELA Bit Mask */ 2618 #define CS_CTL1_SELA0 ((uint32_t)0x00000100) /*!< SELA Bit 0 */ 2619 #define CS_CTL1_SELA1 ((uint32_t)0x00000200) /*!< SELA Bit 1 */ 2620 #define CS_CTL1_SELA2 ((uint32_t)0x00000400) /*!< SELA Bit 2 */ 2621 #define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2622 #define CS_CTL1_SELA_1 ((uint32_t)0x00000100) 2623 #define CS_CTL1_SELA_2 ((uint32_t)0x00000200) 2624 #define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2625 #define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100) 2626 #define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200) 2627 /* CS_CTL1[SELB] Bits */ 2628 #define CS_CTL1_SELB_OFS (12) /*!< SELB Bit Offset */ 2629 #define CS_CTL1_SELB ((uint32_t)0x00001000) /*!< Selects the BCLK source */ 2630 /* CS_CTL1[DIVM] Bits */ 2631 #define CS_CTL1_DIVM_OFS (16) /*!< DIVM Bit Offset */ 2632 #define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /*!< DIVM Bit Mask */ 2633 #define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /*!< DIVM Bit 0 */ 2634 #define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /*!< DIVM Bit 1 */ 2635 #define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /*!< DIVM Bit 2 */ 2636 #define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ 2637 #define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ 2638 #define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ 2639 #define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ 2640 #define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ 2641 #define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ 2642 #define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ 2643 #define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ 2644 #define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ 2645 #define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ 2646 #define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ 2647 #define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ 2648 #define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ 2649 #define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ 2650 #define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ 2651 #define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ 2652 /* CS_CTL1[DIVHS] Bits */ 2653 #define CS_CTL1_DIVHS_OFS (20) /*!< DIVHS Bit Offset */ 2654 #define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /*!< DIVHS Bit Mask */ 2655 #define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /*!< DIVHS Bit 0 */ 2656 #define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /*!< DIVHS Bit 1 */ 2657 #define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /*!< DIVHS Bit 2 */ 2658 #define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ 2659 #define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ 2660 #define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ 2661 #define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ 2662 #define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ 2663 #define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ 2664 #define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ 2665 #define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ 2666 #define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ 2667 #define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ 2668 #define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ 2669 #define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ 2670 #define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ 2671 #define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ 2672 #define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ 2673 #define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ 2674 /* CS_CTL1[DIVA] Bits */ 2675 #define CS_CTL1_DIVA_OFS (24) /*!< DIVA Bit Offset */ 2676 #define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /*!< DIVA Bit Mask */ 2677 #define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /*!< DIVA Bit 0 */ 2678 #define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /*!< DIVA Bit 1 */ 2679 #define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /*!< DIVA Bit 2 */ 2680 #define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ 2681 #define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ 2682 #define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ 2683 #define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ 2684 #define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ 2685 #define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ 2686 #define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ 2687 #define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ 2688 #define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ 2689 #define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ 2690 #define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ 2691 #define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ 2692 #define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ 2693 #define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ 2694 #define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ 2695 #define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ 2696 /* CS_CTL1[DIVS] Bits */ 2697 #define CS_CTL1_DIVS_OFS (28) /*!< DIVS Bit Offset */ 2698 #define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /*!< DIVS Bit Mask */ 2699 #define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /*!< DIVS Bit 0 */ 2700 #define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /*!< DIVS Bit 1 */ 2701 #define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /*!< DIVS Bit 2 */ 2702 #define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ 2703 #define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ 2704 #define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ 2705 #define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ 2706 #define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ 2707 #define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ 2708 #define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ 2709 #define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ 2710 #define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ 2711 #define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ 2712 #define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ 2713 #define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ 2714 #define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ 2715 #define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ 2716 #define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ 2717 #define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ 2718 /* CS_CTL2[LFXTDRIVE] Bits */ 2719 #define CS_CTL2_LFXTDRIVE_OFS ( 0) /*!< LFXTDRIVE Bit Offset */ 2720 #define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /*!< LFXTDRIVE Bit Mask */ 2721 #define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /*!< LFXTDRIVE Bit 0 */ 2722 #define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /*!< LFXTDRIVE Bit 1 */ 2723 #define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /*!< Lowest drive strength and current consumption LFXT oscillator. */ 2724 #define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /*!< Increased drive strength LFXT oscillator. */ 2725 #define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /*!< Increased drive strength LFXT oscillator. */ 2726 #define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */ 2727 /* CS_CTL2[LFXT_EN] Bits */ 2728 #define CS_CTL2_LFXT_EN_OFS ( 8) /*!< LFXT_EN Bit Offset */ 2729 #define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /*!< Turns on the LFXT oscillator regardless if used as a clock resource */ 2730 /* CS_CTL2[LFXTBYPASS] Bits */ 2731 #define CS_CTL2_LFXTBYPASS_OFS ( 9) /*!< LFXTBYPASS Bit Offset */ 2732 #define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /*!< LFXT bypass select */ 2733 /* CS_CTL2[HFXTDRIVE] Bits */ 2734 #define CS_CTL2_HFXTDRIVE_OFS (16) /*!< HFXTDRIVE Bit Offset */ 2735 #define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /*!< HFXT oscillator drive selection */ 2736 /* CS_CTL2[HFXTFREQ] Bits */ 2737 #define CS_CTL2_HFXTFREQ_OFS (20) /*!< HFXTFREQ Bit Offset */ 2738 #define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /*!< HFXTFREQ Bit Mask */ 2739 #define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /*!< HFXTFREQ Bit 0 */ 2740 #define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /*!< HFXTFREQ Bit 1 */ 2741 #define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /*!< HFXTFREQ Bit 2 */ 2742 #define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /*!< 1 MHz to 4 MHz */ 2743 #define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /*!< >4 MHz to 8 MHz */ 2744 #define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /*!< >8 MHz to 16 MHz */ 2745 #define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /*!< >16 MHz to 24 MHz */ 2746 #define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /*!< >24 MHz to 32 MHz */ 2747 #define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /*!< >32 MHz to 40 MHz */ 2748 #define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /*!< >40 MHz to 48 MHz */ 2749 #define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /*!< Reserved for future use. */ 2750 /* CS_CTL2[HFXT_EN] Bits */ 2751 #define CS_CTL2_HFXT_EN_OFS (24) /*!< HFXT_EN Bit Offset */ 2752 #define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /*!< Turns on the HFXT oscillator regardless if used as a clock resource */ 2753 /* CS_CTL2[HFXTBYPASS] Bits */ 2754 #define CS_CTL2_HFXTBYPASS_OFS (25) /*!< HFXTBYPASS Bit Offset */ 2755 #define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /*!< HFXT bypass select */ 2756 /* CS_CTL3[FCNTLF] Bits */ 2757 #define CS_CTL3_FCNTLF_OFS ( 0) /*!< FCNTLF Bit Offset */ 2758 #define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /*!< FCNTLF Bit Mask */ 2759 #define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /*!< FCNTLF Bit 0 */ 2760 #define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /*!< FCNTLF Bit 1 */ 2761 #define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /*!< 4096 cycles */ 2762 #define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /*!< 8192 cycles */ 2763 #define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /*!< 16384 cycles */ 2764 #define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /*!< 32768 cycles */ 2765 #define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /*!< 4096 cycles */ 2766 #define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /*!< 8192 cycles */ 2767 #define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /*!< 16384 cycles */ 2768 #define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /*!< 32768 cycles */ 2769 /* CS_CTL3[RFCNTLF] Bits */ 2770 #define CS_CTL3_RFCNTLF_OFS ( 2) /*!< RFCNTLF Bit Offset */ 2771 #define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /*!< Reset start fault counter for LFXT */ 2772 /* CS_CTL3[FCNTLF_EN] Bits */ 2773 #define CS_CTL3_FCNTLF_EN_OFS ( 3) /*!< FCNTLF_EN Bit Offset */ 2774 #define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /*!< Enable start fault counter for LFXT */ 2775 /* CS_CTL3[FCNTHF] Bits */ 2776 #define CS_CTL3_FCNTHF_OFS ( 4) /*!< FCNTHF Bit Offset */ 2777 #define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /*!< FCNTHF Bit Mask */ 2778 #define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /*!< FCNTHF Bit 0 */ 2779 #define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /*!< FCNTHF Bit 1 */ 2780 #define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ 2781 #define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /*!< 4096 cycles */ 2782 #define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /*!< 8192 cycles */ 2783 #define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /*!< 16384 cycles */ 2784 #define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ 2785 #define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /*!< 4096 cycles */ 2786 #define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /*!< 8192 cycles */ 2787 #define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /*!< 16384 cycles */ 2788 /* CS_CTL3[RFCNTHF] Bits */ 2789 #define CS_CTL3_RFCNTHF_OFS ( 6) /*!< RFCNTHF Bit Offset */ 2790 #define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /*!< Reset start fault counter for HFXT */ 2791 /* CS_CTL3[FCNTHF_EN] Bits */ 2792 #define CS_CTL3_FCNTHF_EN_OFS ( 7) /*!< FCNTHF_EN Bit Offset */ 2793 #define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /*!< Enable start fault counter for HFXT */ 2794 /* CS_CLKEN[ACLK_EN] Bits */ 2795 #define CS_CLKEN_ACLK_EN_OFS ( 0) /*!< ACLK_EN Bit Offset */ 2796 #define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /*!< ACLK system clock conditional request enable */ 2797 /* CS_CLKEN[MCLK_EN] Bits */ 2798 #define CS_CLKEN_MCLK_EN_OFS ( 1) /*!< MCLK_EN Bit Offset */ 2799 #define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /*!< MCLK system clock conditional request enable */ 2800 /* CS_CLKEN[HSMCLK_EN] Bits */ 2801 #define CS_CLKEN_HSMCLK_EN_OFS ( 2) /*!< HSMCLK_EN Bit Offset */ 2802 #define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /*!< HSMCLK system clock conditional request enable */ 2803 /* CS_CLKEN[SMCLK_EN] Bits */ 2804 #define CS_CLKEN_SMCLK_EN_OFS ( 3) /*!< SMCLK_EN Bit Offset */ 2805 #define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /*!< SMCLK system clock conditional request enable */ 2806 /* CS_CLKEN[VLO_EN] Bits */ 2807 #define CS_CLKEN_VLO_EN_OFS ( 8) /*!< VLO_EN Bit Offset */ 2808 #define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /*!< Turns on the VLO oscillator */ 2809 /* CS_CLKEN[REFO_EN] Bits */ 2810 #define CS_CLKEN_REFO_EN_OFS ( 9) /*!< REFO_EN Bit Offset */ 2811 #define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /*!< Turns on the REFO oscillator */ 2812 /* CS_CLKEN[MODOSC_EN] Bits */ 2813 #define CS_CLKEN_MODOSC_EN_OFS (10) /*!< MODOSC_EN Bit Offset */ 2814 #define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /*!< Turns on the MODOSC oscillator */ 2815 /* CS_CLKEN[REFOFSEL] Bits */ 2816 #define CS_CLKEN_REFOFSEL_OFS (15) /*!< REFOFSEL Bit Offset */ 2817 #define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /*!< Selects REFO nominal frequency */ 2818 /* CS_STAT[DCO_ON] Bits */ 2819 #define CS_STAT_DCO_ON_OFS ( 0) /*!< DCO_ON Bit Offset */ 2820 #define CS_STAT_DCO_ON ((uint32_t)0x00000001) /*!< DCO status */ 2821 /* CS_STAT[DCOBIAS_ON] Bits */ 2822 #define CS_STAT_DCOBIAS_ON_OFS ( 1) /*!< DCOBIAS_ON Bit Offset */ 2823 #define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /*!< DCO bias status */ 2824 /* CS_STAT[HFXT_ON] Bits */ 2825 #define CS_STAT_HFXT_ON_OFS ( 2) /*!< HFXT_ON Bit Offset */ 2826 #define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /*!< HFXT status */ 2827 /* CS_STAT[MODOSC_ON] Bits */ 2828 #define CS_STAT_MODOSC_ON_OFS ( 4) /*!< MODOSC_ON Bit Offset */ 2829 #define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /*!< MODOSC status */ 2830 /* CS_STAT[VLO_ON] Bits */ 2831 #define CS_STAT_VLO_ON_OFS ( 5) /*!< VLO_ON Bit Offset */ 2832 #define CS_STAT_VLO_ON ((uint32_t)0x00000020) /*!< VLO status */ 2833 /* CS_STAT[LFXT_ON] Bits */ 2834 #define CS_STAT_LFXT_ON_OFS ( 6) /*!< LFXT_ON Bit Offset */ 2835 #define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /*!< LFXT status */ 2836 /* CS_STAT[REFO_ON] Bits */ 2837 #define CS_STAT_REFO_ON_OFS ( 7) /*!< REFO_ON Bit Offset */ 2838 #define CS_STAT_REFO_ON ((uint32_t)0x00000080) /*!< REFO status */ 2839 /* CS_STAT[ACLK_ON] Bits */ 2840 #define CS_STAT_ACLK_ON_OFS (16) /*!< ACLK_ON Bit Offset */ 2841 #define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /*!< ACLK system clock status */ 2842 /* CS_STAT[MCLK_ON] Bits */ 2843 #define CS_STAT_MCLK_ON_OFS (17) /*!< MCLK_ON Bit Offset */ 2844 #define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /*!< MCLK system clock status */ 2845 /* CS_STAT[HSMCLK_ON] Bits */ 2846 #define CS_STAT_HSMCLK_ON_OFS (18) /*!< HSMCLK_ON Bit Offset */ 2847 #define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /*!< HSMCLK system clock status */ 2848 /* CS_STAT[SMCLK_ON] Bits */ 2849 #define CS_STAT_SMCLK_ON_OFS (19) /*!< SMCLK_ON Bit Offset */ 2850 #define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /*!< SMCLK system clock status */ 2851 /* CS_STAT[MODCLK_ON] Bits */ 2852 #define CS_STAT_MODCLK_ON_OFS (20) /*!< MODCLK_ON Bit Offset */ 2853 #define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /*!< MODCLK system clock status */ 2854 /* CS_STAT[VLOCLK_ON] Bits */ 2855 #define CS_STAT_VLOCLK_ON_OFS (21) /*!< VLOCLK_ON Bit Offset */ 2856 #define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /*!< VLOCLK system clock status */ 2857 /* CS_STAT[LFXTCLK_ON] Bits */ 2858 #define CS_STAT_LFXTCLK_ON_OFS (22) /*!< LFXTCLK_ON Bit Offset */ 2859 #define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /*!< LFXTCLK system clock status */ 2860 /* CS_STAT[REFOCLK_ON] Bits */ 2861 #define CS_STAT_REFOCLK_ON_OFS (23) /*!< REFOCLK_ON Bit Offset */ 2862 #define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /*!< REFOCLK system clock status */ 2863 /* CS_STAT[ACLK_READY] Bits */ 2864 #define CS_STAT_ACLK_READY_OFS (24) /*!< ACLK_READY Bit Offset */ 2865 #define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /*!< ACLK Ready status */ 2866 /* CS_STAT[MCLK_READY] Bits */ 2867 #define CS_STAT_MCLK_READY_OFS (25) /*!< MCLK_READY Bit Offset */ 2868 #define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /*!< MCLK Ready status */ 2869 /* CS_STAT[HSMCLK_READY] Bits */ 2870 #define CS_STAT_HSMCLK_READY_OFS (26) /*!< HSMCLK_READY Bit Offset */ 2871 #define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /*!< HSMCLK Ready status */ 2872 /* CS_STAT[SMCLK_READY] Bits */ 2873 #define CS_STAT_SMCLK_READY_OFS (27) /*!< SMCLK_READY Bit Offset */ 2874 #define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /*!< SMCLK Ready status */ 2875 /* CS_STAT[BCLK_READY] Bits */ 2876 #define CS_STAT_BCLK_READY_OFS (28) /*!< BCLK_READY Bit Offset */ 2877 #define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /*!< BCLK Ready status */ 2878 /* CS_IE[LFXTIE] Bits */ 2879 #define CS_IE_LFXTIE_OFS ( 0) /*!< LFXTIE Bit Offset */ 2880 #define CS_IE_LFXTIE ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag interrupt enable */ 2881 /* CS_IE[HFXTIE] Bits */ 2882 #define CS_IE_HFXTIE_OFS ( 1) /*!< HFXTIE Bit Offset */ 2883 #define CS_IE_HFXTIE ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag interrupt enable */ 2884 /* CS_IE[DCOR_OPNIE] Bits */ 2885 #define CS_IE_DCOR_OPNIE_OFS ( 6) /*!< DCOR_OPNIE Bit Offset */ 2886 #define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag interrupt enable. */ 2887 /* CS_IE[FCNTLFIE] Bits */ 2888 #define CS_IE_FCNTLFIE_OFS ( 8) /*!< FCNTLFIE Bit Offset */ 2889 #define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /*!< Start fault counter interrupt enable LFXT */ 2890 /* CS_IE[FCNTHFIE] Bits */ 2891 #define CS_IE_FCNTHFIE_OFS ( 9) /*!< FCNTHFIE Bit Offset */ 2892 #define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /*!< Start fault counter interrupt enable HFXT */ 2893 /* CS_IFG[LFXTIFG] Bits */ 2894 #define CS_IFG_LFXTIFG_OFS ( 0) /*!< LFXTIFG Bit Offset */ 2895 #define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag */ 2896 /* CS_IFG[HFXTIFG] Bits */ 2897 #define CS_IFG_HFXTIFG_OFS ( 1) /*!< HFXTIFG Bit Offset */ 2898 #define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag */ 2899 /* CS_IFG[DCOR_SHTIFG] Bits */ 2900 #define CS_IFG_DCOR_SHTIFG_OFS ( 5) /*!< DCOR_SHTIFG Bit Offset */ 2901 #define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /*!< DCO external resistor short circuit fault flag. */ 2902 /* CS_IFG[DCOR_OPNIFG] Bits */ 2903 #define CS_IFG_DCOR_OPNIFG_OFS ( 6) /*!< DCOR_OPNIFG Bit Offset */ 2904 #define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag. */ 2905 /* CS_IFG[FCNTLFIFG] Bits */ 2906 #define CS_IFG_FCNTLFIFG_OFS ( 8) /*!< FCNTLFIFG Bit Offset */ 2907 #define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter interrupt flag LFXT */ 2908 /* CS_IFG[FCNTHFIFG] Bits */ 2909 #define CS_IFG_FCNTHFIFG_OFS ( 9) /*!< FCNTHFIFG Bit Offset */ 2910 #define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter interrupt flag HFXT */ 2911 /* CS_CLRIFG[CLR_LFXTIFG] Bits */ 2912 #define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /*!< CLR_LFXTIFG Bit Offset */ 2913 #define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /*!< Clear LFXT oscillator fault interrupt flag */ 2914 /* CS_CLRIFG[CLR_HFXTIFG] Bits */ 2915 #define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /*!< CLR_HFXTIFG Bit Offset */ 2916 #define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /*!< Clear HFXT oscillator fault interrupt flag */ 2917 /* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */ 2918 #define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /*!< CLR_DCOR_OPNIFG Bit Offset */ 2919 #define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Clear DCO external resistor open circuit fault interrupt flag. */ 2920 /* CS_CLRIFG[CLR_FCNTLFIFG] Bits */ 2921 #define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /*!< CLR_FCNTLFIFG Bit Offset */ 2922 #define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter clear interrupt flag LFXT */ 2923 /* CS_CLRIFG[CLR_FCNTHFIFG] Bits */ 2924 #define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /*!< CLR_FCNTHFIFG Bit Offset */ 2925 #define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter clear interrupt flag HFXT */ 2926 /* CS_SETIFG[SET_LFXTIFG] Bits */ 2927 #define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /*!< SET_LFXTIFG Bit Offset */ 2928 #define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /*!< Set LFXT oscillator fault interrupt flag */ 2929 /* CS_SETIFG[SET_HFXTIFG] Bits */ 2930 #define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /*!< SET_HFXTIFG Bit Offset */ 2931 #define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /*!< Set HFXT oscillator fault interrupt flag */ 2932 /* CS_SETIFG[SET_DCOR_OPNIFG] Bits */ 2933 #define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /*!< SET_DCOR_OPNIFG Bit Offset */ 2934 #define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Set DCO external resistor open circuit fault interrupt flag. */ 2935 /* CS_SETIFG[SET_FCNTHFIFG] Bits */ 2936 #define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /*!< SET_FCNTHFIFG Bit Offset */ 2937 #define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter set interrupt flag HFXT */ 2938 /* CS_SETIFG[SET_FCNTLFIFG] Bits */ 2939 #define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /*!< SET_FCNTLFIFG Bit Offset */ 2940 #define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter set interrupt flag LFXT */ 2941 /* CS_DCOERCAL0[DCO_TCCAL] Bits */ 2942 #define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /*!< DCO_TCCAL Bit Offset */ 2943 #define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /*!< DCO_TCCAL Bit Mask */ 2944 /* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */ 2945 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /*!< DCO_FCAL_RSEL04 Bit Offset */ 2946 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /*!< DCO_FCAL_RSEL04 Bit Mask */ 2947 /* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */ 2948 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /*!< DCO_FCAL_RSEL5 Bit Offset */ 2949 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /*!< DCO_FCAL_RSEL5 Bit Mask */ 2950 /* Pre-defined bitfield values */ 2951 #define CS_KEY_VAL ((uint32_t)0x0000695A) /*!< CS control key value */ 2952 2953 /****************************************************************************** 2954 * DIO Bits 2955 ******************************************************************************/ 2956 /* DIO_IV[IV] Bits */ 2957 #define DIO_PORT_IV_OFS ( 0) /*!< DIO Port IV Bit Offset */ 2958 #define DIO_PORT_IV_MASK ((uint16_t)0x001F) /*!< DIO Port IV Bit Mask */ 2959 #define DIO_PORT_IV0 ((uint16_t)0x0001) /*!< DIO Port IV Bit 0 */ 2960 #define DIO_PORT_IV1 ((uint16_t)0x0002) /*!< DIO Port IV Bit 1 */ 2961 #define DIO_PORT_IV2 ((uint16_t)0x0004) /*!< DIO Port IV Bit 2 */ 2962 #define DIO_PORT_IV3 ((uint16_t)0x0008) /*!< DIO Port IV Bit 3 */ 2963 #define DIO_PORT_IV4 ((uint16_t)0x0010) /*!< DIO Port IV Bit 4 */ 2964 #define DIO_PORT_IV_0 ((uint16_t)0x0000) /*!< No interrupt pending */ 2965 #define DIO_PORT_IV_2 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ 2966 /* Priority: Highest */ 2967 #define DIO_PORT_IV_4 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ 2968 #define DIO_PORT_IV_6 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ 2969 #define DIO_PORT_IV_8 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ 2970 #define DIO_PORT_IV_10 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ 2971 #define DIO_PORT_IV_12 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ 2972 #define DIO_PORT_IV_14 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ 2973 #define DIO_PORT_IV_16 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ 2974 /* Priority: Lowest */ 2975 #define DIO_PORT_IV__NONE ((uint16_t)0x0000) /*!< No interrupt pending */ 2976 #define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ 2977 /* Priority: Highest */ 2978 #define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ 2979 #define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ 2980 #define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ 2981 #define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ 2982 #define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ 2983 #define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ 2984 #define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ 2985 /* Priority: Lowest */ 2986 2987 2988 /****************************************************************************** 2989 * DMA Bits 2990 ******************************************************************************/ 2991 /* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */ 2992 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /*!< NUM_DMA_CHANNELS Bit Offset */ 2993 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /*!< NUM_DMA_CHANNELS Bit Mask */ 2994 /* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */ 2995 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /*!< NUM_SRC_PER_CHANNEL Bit Offset */ 2996 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /*!< NUM_SRC_PER_CHANNEL Bit Mask */ 2997 /* DMA_SW_CHTRIG[CH0] Bits */ 2998 #define DMA_SW_CHTRIG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ 2999 #define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /*!< Write 1, triggers DMA_CHANNEL0 */ 3000 /* DMA_SW_CHTRIG[CH1] Bits */ 3001 #define DMA_SW_CHTRIG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ 3002 #define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /*!< Write 1, triggers DMA_CHANNEL1 */ 3003 /* DMA_SW_CHTRIG[CH2] Bits */ 3004 #define DMA_SW_CHTRIG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ 3005 #define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /*!< Write 1, triggers DMA_CHANNEL2 */ 3006 /* DMA_SW_CHTRIG[CH3] Bits */ 3007 #define DMA_SW_CHTRIG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ 3008 #define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /*!< Write 1, triggers DMA_CHANNEL3 */ 3009 /* DMA_SW_CHTRIG[CH4] Bits */ 3010 #define DMA_SW_CHTRIG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ 3011 #define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /*!< Write 1, triggers DMA_CHANNEL4 */ 3012 /* DMA_SW_CHTRIG[CH5] Bits */ 3013 #define DMA_SW_CHTRIG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ 3014 #define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /*!< Write 1, triggers DMA_CHANNEL5 */ 3015 /* DMA_SW_CHTRIG[CH6] Bits */ 3016 #define DMA_SW_CHTRIG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ 3017 #define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /*!< Write 1, triggers DMA_CHANNEL6 */ 3018 /* DMA_SW_CHTRIG[CH7] Bits */ 3019 #define DMA_SW_CHTRIG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ 3020 #define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /*!< Write 1, triggers DMA_CHANNEL7 */ 3021 /* DMA_SW_CHTRIG[CH8] Bits */ 3022 #define DMA_SW_CHTRIG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ 3023 #define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /*!< Write 1, triggers DMA_CHANNEL8 */ 3024 /* DMA_SW_CHTRIG[CH9] Bits */ 3025 #define DMA_SW_CHTRIG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ 3026 #define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /*!< Write 1, triggers DMA_CHANNEL9 */ 3027 /* DMA_SW_CHTRIG[CH10] Bits */ 3028 #define DMA_SW_CHTRIG_CH10_OFS (10) /*!< CH10 Bit Offset */ 3029 #define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /*!< Write 1, triggers DMA_CHANNEL10 */ 3030 /* DMA_SW_CHTRIG[CH11] Bits */ 3031 #define DMA_SW_CHTRIG_CH11_OFS (11) /*!< CH11 Bit Offset */ 3032 #define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /*!< Write 1, triggers DMA_CHANNEL11 */ 3033 /* DMA_SW_CHTRIG[CH12] Bits */ 3034 #define DMA_SW_CHTRIG_CH12_OFS (12) /*!< CH12 Bit Offset */ 3035 #define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /*!< Write 1, triggers DMA_CHANNEL12 */ 3036 /* DMA_SW_CHTRIG[CH13] Bits */ 3037 #define DMA_SW_CHTRIG_CH13_OFS (13) /*!< CH13 Bit Offset */ 3038 #define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /*!< Write 1, triggers DMA_CHANNEL13 */ 3039 /* DMA_SW_CHTRIG[CH14] Bits */ 3040 #define DMA_SW_CHTRIG_CH14_OFS (14) /*!< CH14 Bit Offset */ 3041 #define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /*!< Write 1, triggers DMA_CHANNEL14 */ 3042 /* DMA_SW_CHTRIG[CH15] Bits */ 3043 #define DMA_SW_CHTRIG_CH15_OFS (15) /*!< CH15 Bit Offset */ 3044 #define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /*!< Write 1, triggers DMA_CHANNEL15 */ 3045 /* DMA_SW_CHTRIG[CH16] Bits */ 3046 #define DMA_SW_CHTRIG_CH16_OFS (16) /*!< CH16 Bit Offset */ 3047 #define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /*!< Write 1, triggers DMA_CHANNEL16 */ 3048 /* DMA_SW_CHTRIG[CH17] Bits */ 3049 #define DMA_SW_CHTRIG_CH17_OFS (17) /*!< CH17 Bit Offset */ 3050 #define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /*!< Write 1, triggers DMA_CHANNEL17 */ 3051 /* DMA_SW_CHTRIG[CH18] Bits */ 3052 #define DMA_SW_CHTRIG_CH18_OFS (18) /*!< CH18 Bit Offset */ 3053 #define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /*!< Write 1, triggers DMA_CHANNEL18 */ 3054 /* DMA_SW_CHTRIG[CH19] Bits */ 3055 #define DMA_SW_CHTRIG_CH19_OFS (19) /*!< CH19 Bit Offset */ 3056 #define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /*!< Write 1, triggers DMA_CHANNEL19 */ 3057 /* DMA_SW_CHTRIG[CH20] Bits */ 3058 #define DMA_SW_CHTRIG_CH20_OFS (20) /*!< CH20 Bit Offset */ 3059 #define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /*!< Write 1, triggers DMA_CHANNEL20 */ 3060 /* DMA_SW_CHTRIG[CH21] Bits */ 3061 #define DMA_SW_CHTRIG_CH21_OFS (21) /*!< CH21 Bit Offset */ 3062 #define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /*!< Write 1, triggers DMA_CHANNEL21 */ 3063 /* DMA_SW_CHTRIG[CH22] Bits */ 3064 #define DMA_SW_CHTRIG_CH22_OFS (22) /*!< CH22 Bit Offset */ 3065 #define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /*!< Write 1, triggers DMA_CHANNEL22 */ 3066 /* DMA_SW_CHTRIG[CH23] Bits */ 3067 #define DMA_SW_CHTRIG_CH23_OFS (23) /*!< CH23 Bit Offset */ 3068 #define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /*!< Write 1, triggers DMA_CHANNEL23 */ 3069 /* DMA_SW_CHTRIG[CH24] Bits */ 3070 #define DMA_SW_CHTRIG_CH24_OFS (24) /*!< CH24 Bit Offset */ 3071 #define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /*!< Write 1, triggers DMA_CHANNEL24 */ 3072 /* DMA_SW_CHTRIG[CH25] Bits */ 3073 #define DMA_SW_CHTRIG_CH25_OFS (25) /*!< CH25 Bit Offset */ 3074 #define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /*!< Write 1, triggers DMA_CHANNEL25 */ 3075 /* DMA_SW_CHTRIG[CH26] Bits */ 3076 #define DMA_SW_CHTRIG_CH26_OFS (26) /*!< CH26 Bit Offset */ 3077 #define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /*!< Write 1, triggers DMA_CHANNEL26 */ 3078 /* DMA_SW_CHTRIG[CH27] Bits */ 3079 #define DMA_SW_CHTRIG_CH27_OFS (27) /*!< CH27 Bit Offset */ 3080 #define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /*!< Write 1, triggers DMA_CHANNEL27 */ 3081 /* DMA_SW_CHTRIG[CH28] Bits */ 3082 #define DMA_SW_CHTRIG_CH28_OFS (28) /*!< CH28 Bit Offset */ 3083 #define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /*!< Write 1, triggers DMA_CHANNEL28 */ 3084 /* DMA_SW_CHTRIG[CH29] Bits */ 3085 #define DMA_SW_CHTRIG_CH29_OFS (29) /*!< CH29 Bit Offset */ 3086 #define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /*!< Write 1, triggers DMA_CHANNEL29 */ 3087 /* DMA_SW_CHTRIG[CH30] Bits */ 3088 #define DMA_SW_CHTRIG_CH30_OFS (30) /*!< CH30 Bit Offset */ 3089 #define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /*!< Write 1, triggers DMA_CHANNEL30 */ 3090 /* DMA_SW_CHTRIG[CH31] Bits */ 3091 #define DMA_SW_CHTRIG_CH31_OFS (31) /*!< CH31 Bit Offset */ 3092 #define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /*!< Write 1, triggers DMA_CHANNEL31 */ 3093 /* DMA_CHN_SRCCFG[DMA_SRC] Bits */ 3094 #define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /*!< DMA_SRC Bit Offset */ 3095 #define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /*!< DMA_SRC Bit Mask */ 3096 /* DMA_INT1_SRCCFG[INT_SRC] Bits */ 3097 #define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ 3098 #define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ 3099 /* DMA_INT1_SRCCFG[EN] Bits */ 3100 #define DMA_INT1_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ 3101 #define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT1 mapping */ 3102 /* DMA_INT2_SRCCFG[INT_SRC] Bits */ 3103 #define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ 3104 #define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ 3105 /* DMA_INT2_SRCCFG[EN] Bits */ 3106 #define DMA_INT2_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ 3107 #define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT2 mapping */ 3108 /* DMA_INT3_SRCCFG[INT_SRC] Bits */ 3109 #define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ 3110 #define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ 3111 /* DMA_INT3_SRCCFG[EN] Bits */ 3112 #define DMA_INT3_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ 3113 #define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT3 mapping */ 3114 /* DMA_INT0_SRCFLG[CH0] Bits */ 3115 #define DMA_INT0_SRCFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ 3116 #define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /*!< Channel 0 was the source of DMA_INT0 */ 3117 /* DMA_INT0_SRCFLG[CH1] Bits */ 3118 #define DMA_INT0_SRCFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ 3119 #define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /*!< Channel 1 was the source of DMA_INT0 */ 3120 /* DMA_INT0_SRCFLG[CH2] Bits */ 3121 #define DMA_INT0_SRCFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ 3122 #define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /*!< Channel 2 was the source of DMA_INT0 */ 3123 /* DMA_INT0_SRCFLG[CH3] Bits */ 3124 #define DMA_INT0_SRCFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ 3125 #define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /*!< Channel 3 was the source of DMA_INT0 */ 3126 /* DMA_INT0_SRCFLG[CH4] Bits */ 3127 #define DMA_INT0_SRCFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ 3128 #define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /*!< Channel 4 was the source of DMA_INT0 */ 3129 /* DMA_INT0_SRCFLG[CH5] Bits */ 3130 #define DMA_INT0_SRCFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ 3131 #define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /*!< Channel 5 was the source of DMA_INT0 */ 3132 /* DMA_INT0_SRCFLG[CH6] Bits */ 3133 #define DMA_INT0_SRCFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ 3134 #define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /*!< Channel 6 was the source of DMA_INT0 */ 3135 /* DMA_INT0_SRCFLG[CH7] Bits */ 3136 #define DMA_INT0_SRCFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ 3137 #define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /*!< Channel 7 was the source of DMA_INT0 */ 3138 /* DMA_INT0_SRCFLG[CH8] Bits */ 3139 #define DMA_INT0_SRCFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ 3140 #define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /*!< Channel 8 was the source of DMA_INT0 */ 3141 /* DMA_INT0_SRCFLG[CH9] Bits */ 3142 #define DMA_INT0_SRCFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ 3143 #define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /*!< Channel 9 was the source of DMA_INT0 */ 3144 /* DMA_INT0_SRCFLG[CH10] Bits */ 3145 #define DMA_INT0_SRCFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ 3146 #define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /*!< Channel 10 was the source of DMA_INT0 */ 3147 /* DMA_INT0_SRCFLG[CH11] Bits */ 3148 #define DMA_INT0_SRCFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ 3149 #define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /*!< Channel 11 was the source of DMA_INT0 */ 3150 /* DMA_INT0_SRCFLG[CH12] Bits */ 3151 #define DMA_INT0_SRCFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ 3152 #define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /*!< Channel 12 was the source of DMA_INT0 */ 3153 /* DMA_INT0_SRCFLG[CH13] Bits */ 3154 #define DMA_INT0_SRCFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ 3155 #define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /*!< Channel 13 was the source of DMA_INT0 */ 3156 /* DMA_INT0_SRCFLG[CH14] Bits */ 3157 #define DMA_INT0_SRCFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ 3158 #define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /*!< Channel 14 was the source of DMA_INT0 */ 3159 /* DMA_INT0_SRCFLG[CH15] Bits */ 3160 #define DMA_INT0_SRCFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ 3161 #define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /*!< Channel 15 was the source of DMA_INT0 */ 3162 /* DMA_INT0_SRCFLG[CH16] Bits */ 3163 #define DMA_INT0_SRCFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ 3164 #define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /*!< Channel 16 was the source of DMA_INT0 */ 3165 /* DMA_INT0_SRCFLG[CH17] Bits */ 3166 #define DMA_INT0_SRCFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ 3167 #define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /*!< Channel 17 was the source of DMA_INT0 */ 3168 /* DMA_INT0_SRCFLG[CH18] Bits */ 3169 #define DMA_INT0_SRCFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ 3170 #define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /*!< Channel 18 was the source of DMA_INT0 */ 3171 /* DMA_INT0_SRCFLG[CH19] Bits */ 3172 #define DMA_INT0_SRCFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ 3173 #define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /*!< Channel 19 was the source of DMA_INT0 */ 3174 /* DMA_INT0_SRCFLG[CH20] Bits */ 3175 #define DMA_INT0_SRCFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ 3176 #define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /*!< Channel 20 was the source of DMA_INT0 */ 3177 /* DMA_INT0_SRCFLG[CH21] Bits */ 3178 #define DMA_INT0_SRCFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ 3179 #define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /*!< Channel 21 was the source of DMA_INT0 */ 3180 /* DMA_INT0_SRCFLG[CH22] Bits */ 3181 #define DMA_INT0_SRCFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ 3182 #define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /*!< Channel 22 was the source of DMA_INT0 */ 3183 /* DMA_INT0_SRCFLG[CH23] Bits */ 3184 #define DMA_INT0_SRCFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ 3185 #define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /*!< Channel 23 was the source of DMA_INT0 */ 3186 /* DMA_INT0_SRCFLG[CH24] Bits */ 3187 #define DMA_INT0_SRCFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ 3188 #define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /*!< Channel 24 was the source of DMA_INT0 */ 3189 /* DMA_INT0_SRCFLG[CH25] Bits */ 3190 #define DMA_INT0_SRCFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ 3191 #define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /*!< Channel 25 was the source of DMA_INT0 */ 3192 /* DMA_INT0_SRCFLG[CH26] Bits */ 3193 #define DMA_INT0_SRCFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ 3194 #define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /*!< Channel 26 was the source of DMA_INT0 */ 3195 /* DMA_INT0_SRCFLG[CH27] Bits */ 3196 #define DMA_INT0_SRCFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ 3197 #define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /*!< Channel 27 was the source of DMA_INT0 */ 3198 /* DMA_INT0_SRCFLG[CH28] Bits */ 3199 #define DMA_INT0_SRCFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ 3200 #define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /*!< Channel 28 was the source of DMA_INT0 */ 3201 /* DMA_INT0_SRCFLG[CH29] Bits */ 3202 #define DMA_INT0_SRCFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ 3203 #define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /*!< Channel 29 was the source of DMA_INT0 */ 3204 /* DMA_INT0_SRCFLG[CH30] Bits */ 3205 #define DMA_INT0_SRCFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ 3206 #define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /*!< Channel 30 was the source of DMA_INT0 */ 3207 /* DMA_INT0_SRCFLG[CH31] Bits */ 3208 #define DMA_INT0_SRCFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ 3209 #define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /*!< Channel 31 was the source of DMA_INT0 */ 3210 /* DMA_INT0_CLRFLG[CH0] Bits */ 3211 #define DMA_INT0_CLRFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ 3212 #define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3213 /* DMA_INT0_CLRFLG[CH1] Bits */ 3214 #define DMA_INT0_CLRFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ 3215 #define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3216 /* DMA_INT0_CLRFLG[CH2] Bits */ 3217 #define DMA_INT0_CLRFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ 3218 #define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3219 /* DMA_INT0_CLRFLG[CH3] Bits */ 3220 #define DMA_INT0_CLRFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ 3221 #define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3222 /* DMA_INT0_CLRFLG[CH4] Bits */ 3223 #define DMA_INT0_CLRFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ 3224 #define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3225 /* DMA_INT0_CLRFLG[CH5] Bits */ 3226 #define DMA_INT0_CLRFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ 3227 #define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3228 /* DMA_INT0_CLRFLG[CH6] Bits */ 3229 #define DMA_INT0_CLRFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ 3230 #define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3231 /* DMA_INT0_CLRFLG[CH7] Bits */ 3232 #define DMA_INT0_CLRFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ 3233 #define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3234 /* DMA_INT0_CLRFLG[CH8] Bits */ 3235 #define DMA_INT0_CLRFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ 3236 #define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3237 /* DMA_INT0_CLRFLG[CH9] Bits */ 3238 #define DMA_INT0_CLRFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ 3239 #define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3240 /* DMA_INT0_CLRFLG[CH10] Bits */ 3241 #define DMA_INT0_CLRFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ 3242 #define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3243 /* DMA_INT0_CLRFLG[CH11] Bits */ 3244 #define DMA_INT0_CLRFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ 3245 #define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3246 /* DMA_INT0_CLRFLG[CH12] Bits */ 3247 #define DMA_INT0_CLRFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ 3248 #define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3249 /* DMA_INT0_CLRFLG[CH13] Bits */ 3250 #define DMA_INT0_CLRFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ 3251 #define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3252 /* DMA_INT0_CLRFLG[CH14] Bits */ 3253 #define DMA_INT0_CLRFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ 3254 #define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3255 /* DMA_INT0_CLRFLG[CH15] Bits */ 3256 #define DMA_INT0_CLRFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ 3257 #define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3258 /* DMA_INT0_CLRFLG[CH16] Bits */ 3259 #define DMA_INT0_CLRFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ 3260 #define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3261 /* DMA_INT0_CLRFLG[CH17] Bits */ 3262 #define DMA_INT0_CLRFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ 3263 #define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3264 /* DMA_INT0_CLRFLG[CH18] Bits */ 3265 #define DMA_INT0_CLRFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ 3266 #define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3267 /* DMA_INT0_CLRFLG[CH19] Bits */ 3268 #define DMA_INT0_CLRFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ 3269 #define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3270 /* DMA_INT0_CLRFLG[CH20] Bits */ 3271 #define DMA_INT0_CLRFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ 3272 #define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3273 /* DMA_INT0_CLRFLG[CH21] Bits */ 3274 #define DMA_INT0_CLRFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ 3275 #define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3276 /* DMA_INT0_CLRFLG[CH22] Bits */ 3277 #define DMA_INT0_CLRFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ 3278 #define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3279 /* DMA_INT0_CLRFLG[CH23] Bits */ 3280 #define DMA_INT0_CLRFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ 3281 #define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3282 /* DMA_INT0_CLRFLG[CH24] Bits */ 3283 #define DMA_INT0_CLRFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ 3284 #define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3285 /* DMA_INT0_CLRFLG[CH25] Bits */ 3286 #define DMA_INT0_CLRFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ 3287 #define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3288 /* DMA_INT0_CLRFLG[CH26] Bits */ 3289 #define DMA_INT0_CLRFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ 3290 #define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3291 /* DMA_INT0_CLRFLG[CH27] Bits */ 3292 #define DMA_INT0_CLRFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ 3293 #define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3294 /* DMA_INT0_CLRFLG[CH28] Bits */ 3295 #define DMA_INT0_CLRFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ 3296 #define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3297 /* DMA_INT0_CLRFLG[CH29] Bits */ 3298 #define DMA_INT0_CLRFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ 3299 #define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3300 /* DMA_INT0_CLRFLG[CH30] Bits */ 3301 #define DMA_INT0_CLRFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ 3302 #define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3303 /* DMA_INT0_CLRFLG[CH31] Bits */ 3304 #define DMA_INT0_CLRFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ 3305 #define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3306 /* DMA_STAT[MASTEN] Bits */ 3307 #define DMA_STAT_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ 3308 #define DMA_STAT_MASTEN ((uint32_t)0x00000001) 3309 /* DMA_STAT[STATE] Bits */ 3310 #define DMA_STAT_STATE_OFS ( 4) /*!< STATE Bit Offset */ 3311 #define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /*!< STATE Bit Mask */ 3312 #define DMA_STAT_STATE0 ((uint32_t)0x00000010) /*!< STATE Bit 0 */ 3313 #define DMA_STAT_STATE1 ((uint32_t)0x00000020) /*!< STATE Bit 1 */ 3314 #define DMA_STAT_STATE2 ((uint32_t)0x00000040) /*!< STATE Bit 2 */ 3315 #define DMA_STAT_STATE3 ((uint32_t)0x00000080) /*!< STATE Bit 3 */ 3316 #define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /*!< idle */ 3317 #define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /*!< reading channel controller data */ 3318 #define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /*!< reading source data end pointer */ 3319 #define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /*!< reading destination data end pointer */ 3320 #define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /*!< reading source data */ 3321 #define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /*!< writing destination data */ 3322 #define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /*!< waiting for DMA request to clear */ 3323 #define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /*!< writing channel controller data */ 3324 #define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /*!< stalled */ 3325 #define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /*!< done */ 3326 #define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /*!< peripheral scatter-gather transition */ 3327 #define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /*!< Reserved */ 3328 #define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /*!< Reserved */ 3329 #define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /*!< Reserved */ 3330 #define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /*!< Reserved */ 3331 #define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /*!< Reserved */ 3332 /* DMA_STAT[DMACHANS] Bits */ 3333 #define DMA_STAT_DMACHANS_OFS (16) /*!< DMACHANS Bit Offset */ 3334 #define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /*!< DMACHANS Bit Mask */ 3335 #define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /*!< DMACHANS Bit 0 */ 3336 #define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /*!< DMACHANS Bit 1 */ 3337 #define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /*!< DMACHANS Bit 2 */ 3338 #define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /*!< DMACHANS Bit 3 */ 3339 #define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /*!< DMACHANS Bit 4 */ 3340 #define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /*!< Controller configured to use 1 DMA channel */ 3341 #define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /*!< Controller configured to use 2 DMA channels */ 3342 #define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /*!< Controller configured to use 31 DMA channels */ 3343 #define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /*!< Controller configured to use 32 DMA channels */ 3344 /* DMA_STAT[TESTSTAT] Bits */ 3345 #define DMA_STAT_TESTSTAT_OFS (28) /*!< TESTSTAT Bit Offset */ 3346 #define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /*!< TESTSTAT Bit Mask */ 3347 #define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /*!< TESTSTAT Bit 0 */ 3348 #define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /*!< TESTSTAT Bit 1 */ 3349 #define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /*!< TESTSTAT Bit 2 */ 3350 #define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /*!< TESTSTAT Bit 3 */ 3351 #define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /*!< Controller does not include the integration test logic */ 3352 #define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /*!< Controller includes the integration test logic */ 3353 /* DMA_CFG[MASTEN] Bits */ 3354 #define DMA_CFG_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ 3355 #define DMA_CFG_MASTEN ((uint32_t)0x00000001) 3356 /* DMA_CFG[CHPROTCTRL] Bits */ 3357 #define DMA_CFG_CHPROTCTRL_OFS ( 5) /*!< CHPROTCTRL Bit Offset */ 3358 #define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /*!< CHPROTCTRL Bit Mask */ 3359 /* DMA_CTLBASE[ADDR] Bits */ 3360 #define DMA_CTLBASE_ADDR_OFS ( 5) /*!< ADDR Bit Offset */ 3361 #define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /*!< ADDR Bit Mask */ 3362 /* DMA_ERRCLR[ERRCLR] Bits */ 3363 #define DMA_ERRCLR_ERRCLR_OFS ( 0) /*!< ERRCLR Bit Offset */ 3364 #define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) 3365 /* DMA channel definitions and memory structure alignment */ 3366 #define __MCU_NUM_DMA_CHANNELS__ 8 3367 #define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10 3368 #define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE) 3369 3370 /* UDMA_STAT Control Bits */ 3371 #define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /*!< Available uDMA Channels Minus 1 */ 3372 #define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /*!< Control State Machine Status */ 3373 #define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /*!< Idle */ 3374 #define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /*!< Reading channel controller data */ 3375 #define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /*!< Reading source end pointer */ 3376 #define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /*!< Reading destination end pointer */ 3377 #define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /*!< Reading source data */ 3378 #define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /*!< Writing destination data */ 3379 #define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /*!< Waiting for uDMA request to clear */ 3380 #define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /*!< Writing channel controller data */ 3381 #define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /*!< Stalled */ 3382 #define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /*!< Done */ 3383 #define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /*!< Undefined */ 3384 #define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /*!< Master Enable Status */ 3385 #define UDMA_STAT_DMACHANS_S (16) 3386 3387 /* UDMA_CFG Control Bits */ 3388 #define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /*!< Controller Master Enable */ 3389 3390 /* UDMA_CTLBASE Control Bits */ 3391 #define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /*!< Channel Control Base Address */ 3392 #define UDMA_CTLBASE_ADDR_S (10) 3393 3394 /* UDMA_ALTBASE Control Bits */ 3395 #define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Alternate Channel Address Pointer */ 3396 #define UDMA_ALTBASE_ADDR_S ( 0) 3397 3398 /* UDMA_WAITSTAT Control Bits */ 3399 #define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Wait Status */ 3400 3401 /* UDMA_SWREQ Control Bits */ 3402 #define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Software Request */ 3403 3404 /* UDMA_USEBURSTSET Control Bits */ 3405 #define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Set */ 3406 3407 /* UDMA_USEBURSTCLR Control Bits */ 3408 #define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Clear */ 3409 3410 /* UDMA_REQMASKSET Control Bits */ 3411 #define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Set */ 3412 3413 /* UDMA_REQMASKCLR Control Bits */ 3414 #define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Clear */ 3415 3416 /* UDMA_ENASET Control Bits */ 3417 #define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Enable Set */ 3418 3419 /* UDMA_ENACLR Control Bits */ 3420 #define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Clear Channel [n] Enable Clear */ 3421 3422 /* UDMA_ALTSET Control Bits */ 3423 #define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Set */ 3424 3425 /* UDMA_ALTCLR Control Bits */ 3426 #define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Clear */ 3427 3428 /* UDMA_PRIOSET Control Bits */ 3429 #define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Set */ 3430 3431 /* UDMA_PRIOCLR Control Bits */ 3432 #define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Clear */ 3433 3434 /* UDMA_ERRCLR Control Bits */ 3435 #define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /*!< uDMA Bus Error Status */ 3436 3437 /* UDMA_CHASGN Control Bits */ 3438 #define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Assignment Select */ 3439 #define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /*!< Use the primary channel assignment */ 3440 #define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /*!< Use the secondary channel assignment */ 3441 3442 /* Micro Direct Memory Access (uDMA) offsets */ 3443 #define UDMA_O_SRCENDP ((uint32_t)0x00000000) /*!< DMA Channel Source Address End Pointer */ 3444 #define UDMA_O_DSTENDP ((uint32_t)0x00000004) /*!< DMA Channel Destination Address End Pointer */ 3445 #define UDMA_O_CHCTL ((uint32_t)0x00000008) /*!< DMA Channel Control Word */ 3446 3447 /* UDMA_O_SRCENDP Control Bits */ 3448 #define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Source Address End Pointer */ 3449 #define UDMA_SRCENDP_ADDR_S ( 0) 3450 3451 /* UDMA_O_DSTENDP Control Bits */ 3452 #define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Destination Address End Pointer */ 3453 #define UDMA_DSTENDP_ADDR_S ( 0) 3454 3455 /* UDMA_O_CHCTL Control Bits */ 3456 #define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /*!< Destination Address Increment */ 3457 #define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /*!< Byte */ 3458 #define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /*!< Half-word */ 3459 #define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /*!< Word */ 3460 #define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /*!< No increment */ 3461 #define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /*!< Destination Data Size */ 3462 #define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ 3463 #define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /*!< Half-word */ 3464 #define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /*!< Word */ 3465 #define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /*!< Source Address Increment */ 3466 #define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /*!< Byte */ 3467 #define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /*!< Half-word */ 3468 #define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /*!< Word */ 3469 #define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /*!< No increment */ 3470 #define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /*!< Source Data Size */ 3471 #define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ 3472 #define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /*!< Half-word */ 3473 #define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /*!< Word */ 3474 #define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /*!< Arbitration Size */ 3475 #define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /*!< 1 Transfer */ 3476 #define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /*!< 2 Transfers */ 3477 #define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /*!< 4 Transfers */ 3478 #define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /*!< 8 Transfers */ 3479 #define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /*!< 16 Transfers */ 3480 #define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /*!< 32 Transfers */ 3481 #define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /*!< 64 Transfers */ 3482 #define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /*!< 128 Transfers */ 3483 #define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /*!< 256 Transfers */ 3484 #define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /*!< 512 Transfers */ 3485 #define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /*!< 1024 Transfers */ 3486 #define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /*!< Transfer Size (minus 1) */ 3487 #define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /*!< Next Useburst */ 3488 #define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /*!< uDMA Transfer Mode */ 3489 #define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /*!< Stop */ 3490 #define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /*!< Basic */ 3491 #define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /*!< Auto-Request */ 3492 #define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /*!< Ping-Pong */ 3493 #define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /*!< Memory Scatter-Gather */ 3494 #define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /*!< Alternate Memory Scatter-Gather */ 3495 #define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /*!< Peripheral Scatter-Gather */ 3496 #define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /*!< Alternate Peripheral Scatter-Gather */ 3497 3498 #define UDMA_CHCTL_XFERSIZE_S ( 4) 3499 3500 3501 /****************************************************************************** 3502 * DWT Bits 3503 ******************************************************************************/ 3504 3505 3506 /****************************************************************************** 3507 * EUSCI_A Bits 3508 ******************************************************************************/ 3509 /* EUSCI_A_CTLW0[SWRST] Bits */ 3510 #define EUSCI_A_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ 3511 #define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ 3512 /* EUSCI_A_CTLW0[TXBRK] Bits */ 3513 #define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /*!< UCTXBRK Bit Offset */ 3514 #define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /*!< Transmit break */ 3515 /* EUSCI_A_CTLW0[TXADDR] Bits */ 3516 #define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /*!< UCTXADDR Bit Offset */ 3517 #define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /*!< Transmit address */ 3518 /* EUSCI_A_CTLW0[DORM] Bits */ 3519 #define EUSCI_A_CTLW0_DORM_OFS ( 3) /*!< UCDORM Bit Offset */ 3520 #define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /*!< Dormant */ 3521 /* EUSCI_A_CTLW0[BRKIE] Bits */ 3522 #define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /*!< UCBRKIE Bit Offset */ 3523 #define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /*!< Receive break character interrupt enable */ 3524 /* EUSCI_A_CTLW0[RXEIE] Bits */ 3525 #define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /*!< UCRXEIE Bit Offset */ 3526 #define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /*!< Receive erroneous-character interrupt enable */ 3527 /* EUSCI_A_CTLW0[SSEL] Bits */ 3528 #define EUSCI_A_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ 3529 #define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ 3530 #define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ 3531 #define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ 3532 #define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLK */ 3533 #define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ 3534 #define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ 3535 #define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /*!< UCLK */ 3536 #define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ 3537 #define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ 3538 /* EUSCI_A_CTLW0[SYNC] Bits */ 3539 #define EUSCI_A_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ 3540 #define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ 3541 /* EUSCI_A_CTLW0[MODE] Bits */ 3542 #define EUSCI_A_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ 3543 #define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ 3544 #define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ 3545 #define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ 3546 #define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< UART mode */ 3547 #define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< Idle-line multiprocessor mode */ 3548 #define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< Address-bit multiprocessor mode */ 3549 #define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< UART mode with automatic baud-rate detection */ 3550 /* EUSCI_A_CTLW0[SPB] Bits */ 3551 #define EUSCI_A_CTLW0_SPB_OFS (11) /*!< UCSPB Bit Offset */ 3552 #define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /*!< Stop bit select */ 3553 /* EUSCI_A_CTLW0[SEVENBIT] Bits */ 3554 #define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ 3555 #define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ 3556 /* EUSCI_A_CTLW0[MSB] Bits */ 3557 #define EUSCI_A_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ 3558 #define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ 3559 /* EUSCI_A_CTLW0[PAR] Bits */ 3560 #define EUSCI_A_CTLW0_PAR_OFS (14) /*!< UCPAR Bit Offset */ 3561 #define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /*!< Parity select */ 3562 /* EUSCI_A_CTLW0[PEN] Bits */ 3563 #define EUSCI_A_CTLW0_PEN_OFS (15) /*!< UCPEN Bit Offset */ 3564 #define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /*!< Parity enable */ 3565 /* EUSCI_A_CTLW0[STEM] Bits */ 3566 #define EUSCI_A_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ 3567 #define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ 3568 /* EUSCI_A_CTLW0[MST] Bits */ 3569 #define EUSCI_A_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ 3570 #define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ 3571 /* EUSCI_A_CTLW0[CKPL] Bits */ 3572 #define EUSCI_A_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ 3573 #define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ 3574 /* EUSCI_A_CTLW0[CKPH] Bits */ 3575 #define EUSCI_A_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ 3576 #define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ 3577 /* EUSCI_A_CTLW1[GLIT] Bits */ 3578 #define EUSCI_A_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ 3579 #define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ 3580 #define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ 3581 #define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ 3582 #define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< Approximately 2 ns (equivalent of 1 delay element) */ 3583 #define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< Approximately 50 ns */ 3584 #define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< Approximately 100 ns */ 3585 #define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< Approximately 200 ns */ 3586 /* EUSCI_A_MCTLW[OS16] Bits */ 3587 #define EUSCI_A_MCTLW_OS16_OFS ( 0) /*!< UCOS16 Bit Offset */ 3588 #define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /*!< Oversampling mode enabled */ 3589 /* EUSCI_A_MCTLW[BRF] Bits */ 3590 #define EUSCI_A_MCTLW_BRF_OFS ( 4) /*!< UCBRF Bit Offset */ 3591 #define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /*!< UCBRF Bit Mask */ 3592 /* EUSCI_A_MCTLW[BRS] Bits */ 3593 #define EUSCI_A_MCTLW_BRS_OFS ( 8) /*!< UCBRS Bit Offset */ 3594 #define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /*!< UCBRS Bit Mask */ 3595 /* EUSCI_A_STATW[BUSY] Bits */ 3596 #define EUSCI_A_STATW_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ 3597 #define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ 3598 /* EUSCI_A_STATW[ADDR_IDLE] Bits */ 3599 #define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /*!< UCADDR_UCIDLE Bit Offset */ 3600 #define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /*!< Address received / Idle line detected */ 3601 /* EUSCI_A_STATW[RXERR] Bits */ 3602 #define EUSCI_A_STATW_RXERR_OFS ( 2) /*!< UCRXERR Bit Offset */ 3603 #define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /*!< Receive error flag */ 3604 /* EUSCI_A_STATW[BRK] Bits */ 3605 #define EUSCI_A_STATW_BRK_OFS ( 3) /*!< UCBRK Bit Offset */ 3606 #define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /*!< Break detect flag */ 3607 /* EUSCI_A_STATW[PE] Bits */ 3608 #define EUSCI_A_STATW_PE_OFS ( 4) /*!< UCPE Bit Offset */ 3609 #define EUSCI_A_STATW_PE ((uint16_t)0x0010) 3610 /* EUSCI_A_STATW[OE] Bits */ 3611 #define EUSCI_A_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ 3612 #define EUSCI_A_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ 3613 /* EUSCI_A_STATW[FE] Bits */ 3614 #define EUSCI_A_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ 3615 #define EUSCI_A_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ 3616 /* EUSCI_A_STATW[LISTEN] Bits */ 3617 #define EUSCI_A_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ 3618 #define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ 3619 /* EUSCI_A_STATW[SPI_BUSY] Bits */ 3620 #define EUSCI_A_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ 3621 #define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ 3622 /* EUSCI_A_RXBUF[RXBUF] Bits */ 3623 #define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ 3624 #define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ 3625 /* EUSCI_A_TXBUF[TXBUF] Bits */ 3626 #define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ 3627 #define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ 3628 /* EUSCI_A_ABCTL[ABDEN] Bits */ 3629 #define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /*!< UCABDEN Bit Offset */ 3630 #define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /*!< Automatic baud-rate detect enable */ 3631 /* EUSCI_A_ABCTL[BTOE] Bits */ 3632 #define EUSCI_A_ABCTL_BTOE_OFS ( 2) /*!< UCBTOE Bit Offset */ 3633 #define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /*!< Break time out error */ 3634 /* EUSCI_A_ABCTL[STOE] Bits */ 3635 #define EUSCI_A_ABCTL_STOE_OFS ( 3) /*!< UCSTOE Bit Offset */ 3636 #define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /*!< Synch field time out error */ 3637 /* EUSCI_A_ABCTL[DELIM] Bits */ 3638 #define EUSCI_A_ABCTL_DELIM_OFS ( 4) /*!< UCDELIM Bit Offset */ 3639 #define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /*!< UCDELIM Bit Mask */ 3640 #define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /*!< DELIM Bit 0 */ 3641 #define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /*!< DELIM Bit 1 */ 3642 #define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /*!< 1 bit time */ 3643 #define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /*!< 2 bit times */ 3644 #define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /*!< 3 bit times */ 3645 #define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /*!< 4 bit times */ 3646 /* EUSCI_A_IRCTL[IREN] Bits */ 3647 #define EUSCI_A_IRCTL_IREN_OFS ( 0) /*!< UCIREN Bit Offset */ 3648 #define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /*!< IrDA encoder/decoder enable */ 3649 /* EUSCI_A_IRCTL[IRTXCLK] Bits */ 3650 #define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /*!< UCIRTXCLK Bit Offset */ 3651 #define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /*!< IrDA transmit pulse clock select */ 3652 /* EUSCI_A_IRCTL[IRTXPL] Bits */ 3653 #define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /*!< UCIRTXPL Bit Offset */ 3654 #define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /*!< UCIRTXPL Bit Mask */ 3655 /* EUSCI_A_IRCTL[IRRXFE] Bits */ 3656 #define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /*!< UCIRRXFE Bit Offset */ 3657 #define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /*!< IrDA receive filter enabled */ 3658 /* EUSCI_A_IRCTL[IRRXPL] Bits */ 3659 #define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /*!< UCIRRXPL Bit Offset */ 3660 #define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /*!< IrDA receive input UCAxRXD polarity */ 3661 /* EUSCI_A_IRCTL[IRRXFL] Bits */ 3662 #define EUSCI_A_IRCTL_IRRXFL_OFS (10) /*!< UCIRRXFL Bit Offset */ 3663 #define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /*!< UCIRRXFL Bit Mask */ 3664 /* EUSCI_A_IE[RXIE] Bits */ 3665 #define EUSCI_A_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ 3666 #define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ 3667 /* EUSCI_A_IE[TXIE] Bits */ 3668 #define EUSCI_A_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ 3669 #define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ 3670 /* EUSCI_A_IE[STTIE] Bits */ 3671 #define EUSCI_A_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ 3672 #define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /*!< Start bit interrupt enable */ 3673 /* EUSCI_A_IE[TXCPTIE] Bits */ 3674 #define EUSCI_A_IE_TXCPTIE_OFS ( 3) /*!< UCTXCPTIE Bit Offset */ 3675 #define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /*!< Transmit complete interrupt enable */ 3676 /* EUSCI_A_IFG[RXIFG] Bits */ 3677 #define EUSCI_A_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ 3678 #define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ 3679 /* EUSCI_A_IFG[TXIFG] Bits */ 3680 #define EUSCI_A_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ 3681 #define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ 3682 /* EUSCI_A_IFG[STTIFG] Bits */ 3683 #define EUSCI_A_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ 3684 #define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /*!< Start bit interrupt flag */ 3685 /* EUSCI_A_IFG[TXCPTIFG] Bits */ 3686 #define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /*!< UCTXCPTIFG Bit Offset */ 3687 #define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /*!< Transmit ready interrupt enable */ 3688 /* legacy definitions for backward compatibility to version 2100 */ 3689 #define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ 3690 #define EUSCI_A__RXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ 3691 #define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ 3692 #define EUSCI_A__TXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ 3693 3694 3695 /****************************************************************************** 3696 * EUSCI_B Bits 3697 ******************************************************************************/ 3698 /* EUSCI_B_CTLW0[SWRST] Bits */ 3699 #define EUSCI_B_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ 3700 #define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ 3701 /* EUSCI_B_CTLW0[TXSTT] Bits */ 3702 #define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /*!< UCTXSTT Bit Offset */ 3703 #define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /*!< Transmit START condition in master mode */ 3704 /* EUSCI_B_CTLW0[TXSTP] Bits */ 3705 #define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /*!< UCTXSTP Bit Offset */ 3706 #define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /*!< Transmit STOP condition in master mode */ 3707 /* EUSCI_B_CTLW0[TXNACK] Bits */ 3708 #define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /*!< UCTXNACK Bit Offset */ 3709 #define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /*!< Transmit a NACK */ 3710 /* EUSCI_B_CTLW0[TR] Bits */ 3711 #define EUSCI_B_CTLW0_TR_OFS ( 4) /*!< UCTR Bit Offset */ 3712 #define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /*!< Transmitter/receiver */ 3713 /* EUSCI_B_CTLW0[TXACK] Bits */ 3714 #define EUSCI_B_CTLW0_TXACK_OFS ( 5) /*!< UCTXACK Bit Offset */ 3715 #define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /*!< Transmit ACK condition in slave mode */ 3716 /* EUSCI_B_CTLW0[SSEL] Bits */ 3717 #define EUSCI_B_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ 3718 #define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ 3719 #define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ 3720 #define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ 3721 #define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLKI */ 3722 #define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ 3723 #define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ 3724 #define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ 3725 #define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /*!< UCLKI */ 3726 #define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ 3727 #define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ 3728 /* EUSCI_B_CTLW0[SYNC] Bits */ 3729 #define EUSCI_B_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ 3730 #define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ 3731 /* EUSCI_B_CTLW0[MODE] Bits */ 3732 #define EUSCI_B_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ 3733 #define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ 3734 #define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ 3735 #define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ 3736 #define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< 3-pin SPI */ 3737 #define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< 4-pin SPI (master or slave enabled if STE = 1) */ 3738 #define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< 4-pin SPI (master or slave enabled if STE = 0) */ 3739 #define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< I2C mode */ 3740 /* EUSCI_B_CTLW0[MST] Bits */ 3741 #define EUSCI_B_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ 3742 #define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ 3743 /* EUSCI_B_CTLW0[MM] Bits */ 3744 #define EUSCI_B_CTLW0_MM_OFS (13) /*!< UCMM Bit Offset */ 3745 #define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /*!< Multi-master environment select */ 3746 /* EUSCI_B_CTLW0[SLA10] Bits */ 3747 #define EUSCI_B_CTLW0_SLA10_OFS (14) /*!< UCSLA10 Bit Offset */ 3748 #define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /*!< Slave addressing mode select */ 3749 /* EUSCI_B_CTLW0[A10] Bits */ 3750 #define EUSCI_B_CTLW0_A10_OFS (15) /*!< UCA10 Bit Offset */ 3751 #define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /*!< Own addressing mode select */ 3752 /* EUSCI_B_CTLW0[STEM] Bits */ 3753 #define EUSCI_B_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ 3754 #define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ 3755 /* EUSCI_B_CTLW0[SEVENBIT] Bits */ 3756 #define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ 3757 #define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ 3758 /* EUSCI_B_CTLW0[MSB] Bits */ 3759 #define EUSCI_B_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ 3760 #define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ 3761 /* EUSCI_B_CTLW0[CKPL] Bits */ 3762 #define EUSCI_B_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ 3763 #define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ 3764 /* EUSCI_B_CTLW0[CKPH] Bits */ 3765 #define EUSCI_B_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ 3766 #define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ 3767 /* EUSCI_B_CTLW1[GLIT] Bits */ 3768 #define EUSCI_B_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ 3769 #define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ 3770 #define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ 3771 #define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ 3772 #define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< 50 ns */ 3773 #define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< 25 ns */ 3774 #define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< 12.5 ns */ 3775 #define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< 6.25 ns */ 3776 /* EUSCI_B_CTLW1[ASTP] Bits */ 3777 #define EUSCI_B_CTLW1_ASTP_OFS ( 2) /*!< UCASTP Bit Offset */ 3778 #define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /*!< UCASTP Bit Mask */ 3779 #define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /*!< ASTP Bit 0 */ 3780 #define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /*!< ASTP Bit 1 */ 3781 #define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /*!< No automatic STOP generation. The STOP condition is generated after the user */ 3782 /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ 3783 #define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ 3784 /* UCBxTBCNT */ 3785 #define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /*!< A STOP condition is generated automatically after the byte counter value */ 3786 /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ 3787 /* threshold */ 3788 /* EUSCI_B_CTLW1[SWACK] Bits */ 3789 #define EUSCI_B_CTLW1_SWACK_OFS ( 4) /*!< UCSWACK Bit Offset */ 3790 #define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /*!< SW or HW ACK control */ 3791 /* EUSCI_B_CTLW1[STPNACK] Bits */ 3792 #define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /*!< UCSTPNACK Bit Offset */ 3793 #define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /*!< ACK all master bytes */ 3794 /* EUSCI_B_CTLW1[CLTO] Bits */ 3795 #define EUSCI_B_CTLW1_CLTO_OFS ( 6) /*!< UCCLTO Bit Offset */ 3796 #define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /*!< UCCLTO Bit Mask */ 3797 #define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /*!< CLTO Bit 0 */ 3798 #define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /*!< CLTO Bit 1 */ 3799 #define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /*!< Disable clock low timeout counter */ 3800 #define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ 3801 #define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ 3802 #define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ 3803 /* EUSCI_B_CTLW1[ETXINT] Bits */ 3804 #define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /*!< UCETXINT Bit Offset */ 3805 #define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /*!< Early UCTXIFG0 */ 3806 /* EUSCI_B_STATW[BBUSY] Bits */ 3807 #define EUSCI_B_STATW_BBUSY_OFS ( 4) /*!< UCBBUSY Bit Offset */ 3808 #define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /*!< Bus busy */ 3809 /* EUSCI_B_STATW[GC] Bits */ 3810 #define EUSCI_B_STATW_GC_OFS ( 5) /*!< UCGC Bit Offset */ 3811 #define EUSCI_B_STATW_GC ((uint16_t)0x0020) /*!< General call address received */ 3812 /* EUSCI_B_STATW[SCLLOW] Bits */ 3813 #define EUSCI_B_STATW_SCLLOW_OFS ( 6) /*!< UCSCLLOW Bit Offset */ 3814 #define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /*!< SCL low */ 3815 /* EUSCI_B_STATW[BCNT] Bits */ 3816 #define EUSCI_B_STATW_BCNT_OFS ( 8) /*!< UCBCNT Bit Offset */ 3817 #define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /*!< UCBCNT Bit Mask */ 3818 /* EUSCI_B_STATW[SPI_BUSY] Bits */ 3819 #define EUSCI_B_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ 3820 #define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_B busy */ 3821 /* EUSCI_B_STATW[OE] Bits */ 3822 #define EUSCI_B_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ 3823 #define EUSCI_B_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ 3824 /* EUSCI_B_STATW[FE] Bits */ 3825 #define EUSCI_B_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ 3826 #define EUSCI_B_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ 3827 /* EUSCI_B_STATW[LISTEN] Bits */ 3828 #define EUSCI_B_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ 3829 #define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ 3830 /* EUSCI_B_TBCNT[TBCNT] Bits */ 3831 #define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /*!< UCTBCNT Bit Offset */ 3832 #define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /*!< UCTBCNT Bit Mask */ 3833 /* EUSCI_B_RXBUF[RXBUF] Bits */ 3834 #define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ 3835 #define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ 3836 /* EUSCI_B_TXBUF[TXBUF] Bits */ 3837 #define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ 3838 #define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ 3839 /* EUSCI_B_I2COA0[I2COA0] Bits */ 3840 #define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /*!< I2COA0 Bit Offset */ 3841 #define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /*!< I2COA0 Bit Mask */ 3842 /* EUSCI_B_I2COA0[OAEN] Bits */ 3843 #define EUSCI_B_I2COA0_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3844 #define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3845 /* EUSCI_B_I2COA0[GCEN] Bits */ 3846 #define EUSCI_B_I2COA0_GCEN_OFS (15) /*!< UCGCEN Bit Offset */ 3847 #define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /*!< General call response enable */ 3848 /* EUSCI_B_I2COA1[I2COA1] Bits */ 3849 #define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /*!< I2COA1 Bit Offset */ 3850 #define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /*!< I2COA1 Bit Mask */ 3851 /* EUSCI_B_I2COA1[OAEN] Bits */ 3852 #define EUSCI_B_I2COA1_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3853 #define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3854 /* EUSCI_B_I2COA2[I2COA2] Bits */ 3855 #define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /*!< I2COA2 Bit Offset */ 3856 #define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /*!< I2COA2 Bit Mask */ 3857 /* EUSCI_B_I2COA2[OAEN] Bits */ 3858 #define EUSCI_B_I2COA2_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3859 #define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3860 /* EUSCI_B_I2COA3[I2COA3] Bits */ 3861 #define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /*!< I2COA3 Bit Offset */ 3862 #define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /*!< I2COA3 Bit Mask */ 3863 /* EUSCI_B_I2COA3[OAEN] Bits */ 3864 #define EUSCI_B_I2COA3_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3865 #define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3866 /* EUSCI_B_ADDRX[ADDRX] Bits */ 3867 #define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /*!< ADDRX Bit Offset */ 3868 #define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /*!< ADDRX Bit Mask */ 3869 #define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001) /*!< ADDRX Bit 0 */ 3870 #define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002) /*!< ADDRX Bit 1 */ 3871 #define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004) /*!< ADDRX Bit 2 */ 3872 #define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008) /*!< ADDRX Bit 3 */ 3873 #define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010) /*!< ADDRX Bit 4 */ 3874 #define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020) /*!< ADDRX Bit 5 */ 3875 #define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040) /*!< ADDRX Bit 6 */ 3876 #define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080) /*!< ADDRX Bit 7 */ 3877 #define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100) /*!< ADDRX Bit 8 */ 3878 #define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200) /*!< ADDRX Bit 9 */ 3879 /* EUSCI_B_ADDMASK[ADDMASK] Bits */ 3880 #define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /*!< ADDMASK Bit Offset */ 3881 #define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /*!< ADDMASK Bit Mask */ 3882 /* EUSCI_B_I2CSA[I2CSA] Bits */ 3883 #define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /*!< I2CSA Bit Offset */ 3884 #define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /*!< I2CSA Bit Mask */ 3885 /* EUSCI_B_IE[RXIE0] Bits */ 3886 #define EUSCI_B_IE_RXIE0_OFS ( 0) /*!< UCRXIE0 Bit Offset */ 3887 #define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /*!< Receive interrupt enable 0 */ 3888 /* EUSCI_B_IE[TXIE0] Bits */ 3889 #define EUSCI_B_IE_TXIE0_OFS ( 1) /*!< UCTXIE0 Bit Offset */ 3890 #define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /*!< Transmit interrupt enable 0 */ 3891 /* EUSCI_B_IE[STTIE] Bits */ 3892 #define EUSCI_B_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ 3893 #define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /*!< START condition interrupt enable */ 3894 /* EUSCI_B_IE[STPIE] Bits */ 3895 #define EUSCI_B_IE_STPIE_OFS ( 3) /*!< UCSTPIE Bit Offset */ 3896 #define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /*!< STOP condition interrupt enable */ 3897 /* EUSCI_B_IE[ALIE] Bits */ 3898 #define EUSCI_B_IE_ALIE_OFS ( 4) /*!< UCALIE Bit Offset */ 3899 #define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /*!< Arbitration lost interrupt enable */ 3900 /* EUSCI_B_IE[NACKIE] Bits */ 3901 #define EUSCI_B_IE_NACKIE_OFS ( 5) /*!< UCNACKIE Bit Offset */ 3902 #define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /*!< Not-acknowledge interrupt enable */ 3903 /* EUSCI_B_IE[BCNTIE] Bits */ 3904 #define EUSCI_B_IE_BCNTIE_OFS ( 6) /*!< UCBCNTIE Bit Offset */ 3905 #define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /*!< Byte counter interrupt enable */ 3906 /* EUSCI_B_IE[CLTOIE] Bits */ 3907 #define EUSCI_B_IE_CLTOIE_OFS ( 7) /*!< UCCLTOIE Bit Offset */ 3908 #define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /*!< Clock low timeout interrupt enable */ 3909 /* EUSCI_B_IE[RXIE1] Bits */ 3910 #define EUSCI_B_IE_RXIE1_OFS ( 8) /*!< UCRXIE1 Bit Offset */ 3911 #define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /*!< Receive interrupt enable 1 */ 3912 /* EUSCI_B_IE[TXIE1] Bits */ 3913 #define EUSCI_B_IE_TXIE1_OFS ( 9) /*!< UCTXIE1 Bit Offset */ 3914 #define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /*!< Transmit interrupt enable 1 */ 3915 /* EUSCI_B_IE[RXIE2] Bits */ 3916 #define EUSCI_B_IE_RXIE2_OFS (10) /*!< UCRXIE2 Bit Offset */ 3917 #define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /*!< Receive interrupt enable 2 */ 3918 /* EUSCI_B_IE[TXIE2] Bits */ 3919 #define EUSCI_B_IE_TXIE2_OFS (11) /*!< UCTXIE2 Bit Offset */ 3920 #define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /*!< Transmit interrupt enable 2 */ 3921 /* EUSCI_B_IE[RXIE3] Bits */ 3922 #define EUSCI_B_IE_RXIE3_OFS (12) /*!< UCRXIE3 Bit Offset */ 3923 #define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /*!< Receive interrupt enable 3 */ 3924 /* EUSCI_B_IE[TXIE3] Bits */ 3925 #define EUSCI_B_IE_TXIE3_OFS (13) /*!< UCTXIE3 Bit Offset */ 3926 #define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /*!< Transmit interrupt enable 3 */ 3927 /* EUSCI_B_IE[BIT9IE] Bits */ 3928 #define EUSCI_B_IE_BIT9IE_OFS (14) /*!< UCBIT9IE Bit Offset */ 3929 #define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /*!< Bit position 9 interrupt enable */ 3930 /* EUSCI_B_IE[RXIE] Bits */ 3931 #define EUSCI_B_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ 3932 #define EUSCI_B_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ 3933 /* EUSCI_B_IE[TXIE] Bits */ 3934 #define EUSCI_B_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ 3935 #define EUSCI_B_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ 3936 /* EUSCI_B_IFG[RXIFG0] Bits */ 3937 #define EUSCI_B_IFG_RXIFG0_OFS ( 0) /*!< UCRXIFG0 Bit Offset */ 3938 #define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /*!< eUSCI_B receive interrupt flag 0 */ 3939 /* EUSCI_B_IFG[TXIFG0] Bits */ 3940 #define EUSCI_B_IFG_TXIFG0_OFS ( 1) /*!< UCTXIFG0 Bit Offset */ 3941 #define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /*!< eUSCI_B transmit interrupt flag 0 */ 3942 /* EUSCI_B_IFG[STTIFG] Bits */ 3943 #define EUSCI_B_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ 3944 #define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /*!< START condition interrupt flag */ 3945 /* EUSCI_B_IFG[STPIFG] Bits */ 3946 #define EUSCI_B_IFG_STPIFG_OFS ( 3) /*!< UCSTPIFG Bit Offset */ 3947 #define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /*!< STOP condition interrupt flag */ 3948 /* EUSCI_B_IFG[ALIFG] Bits */ 3949 #define EUSCI_B_IFG_ALIFG_OFS ( 4) /*!< UCALIFG Bit Offset */ 3950 #define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /*!< Arbitration lost interrupt flag */ 3951 /* EUSCI_B_IFG[NACKIFG] Bits */ 3952 #define EUSCI_B_IFG_NACKIFG_OFS ( 5) /*!< UCNACKIFG Bit Offset */ 3953 #define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /*!< Not-acknowledge received interrupt flag */ 3954 /* EUSCI_B_IFG[BCNTIFG] Bits */ 3955 #define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /*!< UCBCNTIFG Bit Offset */ 3956 #define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /*!< Byte counter interrupt flag */ 3957 /* EUSCI_B_IFG[CLTOIFG] Bits */ 3958 #define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /*!< UCCLTOIFG Bit Offset */ 3959 #define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /*!< Clock low timeout interrupt flag */ 3960 /* EUSCI_B_IFG[RXIFG1] Bits */ 3961 #define EUSCI_B_IFG_RXIFG1_OFS ( 8) /*!< UCRXIFG1 Bit Offset */ 3962 #define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /*!< eUSCI_B receive interrupt flag 1 */ 3963 /* EUSCI_B_IFG[TXIFG1] Bits */ 3964 #define EUSCI_B_IFG_TXIFG1_OFS ( 9) /*!< UCTXIFG1 Bit Offset */ 3965 #define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /*!< eUSCI_B transmit interrupt flag 1 */ 3966 /* EUSCI_B_IFG[RXIFG2] Bits */ 3967 #define EUSCI_B_IFG_RXIFG2_OFS (10) /*!< UCRXIFG2 Bit Offset */ 3968 #define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /*!< eUSCI_B receive interrupt flag 2 */ 3969 /* EUSCI_B_IFG[TXIFG2] Bits */ 3970 #define EUSCI_B_IFG_TXIFG2_OFS (11) /*!< UCTXIFG2 Bit Offset */ 3971 #define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /*!< eUSCI_B transmit interrupt flag 2 */ 3972 /* EUSCI_B_IFG[RXIFG3] Bits */ 3973 #define EUSCI_B_IFG_RXIFG3_OFS (12) /*!< UCRXIFG3 Bit Offset */ 3974 #define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /*!< eUSCI_B receive interrupt flag 3 */ 3975 /* EUSCI_B_IFG[TXIFG3] Bits */ 3976 #define EUSCI_B_IFG_TXIFG3_OFS (13) /*!< UCTXIFG3 Bit Offset */ 3977 #define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /*!< eUSCI_B transmit interrupt flag 3 */ 3978 /* EUSCI_B_IFG[BIT9IFG] Bits */ 3979 #define EUSCI_B_IFG_BIT9IFG_OFS (14) /*!< UCBIT9IFG Bit Offset */ 3980 #define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /*!< Bit position 9 interrupt flag */ 3981 /* EUSCI_B_IFG[RXIFG] Bits */ 3982 #define EUSCI_B_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ 3983 #define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ 3984 /* EUSCI_B_IFG[TXIFG] Bits */ 3985 #define EUSCI_B_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ 3986 #define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ 3987 /* legacy definitions for backward compatibility to version 2100 */ 3988 #define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ 3989 #define EUSCI_B__RXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ 3990 #define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ 3991 #define EUSCI_B__TXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ 3992 3993 3994 /****************************************************************************** 3995 * FLCTL_A Bits 3996 ******************************************************************************/ 3997 /* FLCTL_A_POWER_STAT[PSTAT] Bits */ 3998 #define FLCTL_A_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ 3999 #define FLCTL_A_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ 4000 #define FLCTL_A_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ 4001 #define FLCTL_A_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ 4002 #define FLCTL_A_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ 4003 #define FLCTL_A_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ 4004 #define FLCTL_A_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ 4005 #define FLCTL_A_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ 4006 #define FLCTL_A_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ 4007 #define FLCTL_A_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ 4008 #define FLCTL_A_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ 4009 #define FLCTL_A_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ 4010 #define FLCTL_A_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ 4011 /* FLCTL_A_POWER_STAT[LDOSTAT] Bits */ 4012 #define FLCTL_A_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ 4013 #define FLCTL_A_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ 4014 /* FLCTL_A_POWER_STAT[VREFSTAT] Bits */ 4015 #define FLCTL_A_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ 4016 #define FLCTL_A_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ 4017 /* FLCTL_A_POWER_STAT[IREFSTAT] Bits */ 4018 #define FLCTL_A_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ 4019 #define FLCTL_A_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ 4020 /* FLCTL_A_POWER_STAT[TRIMSTAT] Bits */ 4021 #define FLCTL_A_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ 4022 #define FLCTL_A_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ 4023 /* FLCTL_A_POWER_STAT[RD_2T] Bits */ 4024 #define FLCTL_A_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ 4025 #define FLCTL_A_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ 4026 /* FLCTL_A_BANK0_RDCTL[RD_MODE] Bits */ 4027 #define FLCTL_A_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ 4028 #define FLCTL_A_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ 4029 #define FLCTL_A_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ 4030 #define FLCTL_A_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ 4031 #define FLCTL_A_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ 4032 #define FLCTL_A_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ 4033 #define FLCTL_A_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4034 #define FLCTL_A_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ 4035 #define FLCTL_A_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ 4036 #define FLCTL_A_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ 4037 #define FLCTL_A_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ 4038 #define FLCTL_A_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ 4039 #define FLCTL_A_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ 4040 #define FLCTL_A_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ 4041 /* FLCTL_A_BANK0_RDCTL[BUFI] Bits */ 4042 #define FLCTL_A_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ 4043 #define FLCTL_A_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ 4044 /* FLCTL_A_BANK0_RDCTL[BUFD] Bits */ 4045 #define FLCTL_A_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ 4046 #define FLCTL_A_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ 4047 /* FLCTL_A_BANK0_RDCTL[WAIT] Bits */ 4048 #define FLCTL_A_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ 4049 #define FLCTL_A_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ 4050 #define FLCTL_A_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ 4051 #define FLCTL_A_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ 4052 #define FLCTL_A_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ 4053 #define FLCTL_A_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ 4054 #define FLCTL_A_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ 4055 #define FLCTL_A_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ 4056 #define FLCTL_A_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ 4057 #define FLCTL_A_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ 4058 #define FLCTL_A_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ 4059 #define FLCTL_A_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ 4060 #define FLCTL_A_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ 4061 #define FLCTL_A_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ 4062 #define FLCTL_A_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ 4063 #define FLCTL_A_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ 4064 #define FLCTL_A_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ 4065 #define FLCTL_A_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ 4066 #define FLCTL_A_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ 4067 #define FLCTL_A_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ 4068 #define FLCTL_A_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ 4069 #define FLCTL_A_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ 4070 /* FLCTL_A_BANK0_RDCTL[RD_MODE_STATUS] Bits */ 4071 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ 4072 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ 4073 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ 4074 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ 4075 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ 4076 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ 4077 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4078 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ 4079 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ 4080 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ 4081 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ 4082 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ 4083 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ 4084 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ 4085 /* FLCTL_A_BANK1_RDCTL[RD_MODE] Bits */ 4086 #define FLCTL_A_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ 4087 #define FLCTL_A_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ 4088 #define FLCTL_A_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ 4089 #define FLCTL_A_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ 4090 #define FLCTL_A_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ 4091 #define FLCTL_A_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ 4092 #define FLCTL_A_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4093 #define FLCTL_A_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ 4094 #define FLCTL_A_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ 4095 #define FLCTL_A_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ 4096 #define FLCTL_A_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ 4097 #define FLCTL_A_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ 4098 #define FLCTL_A_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ 4099 #define FLCTL_A_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ 4100 /* FLCTL_A_BANK1_RDCTL[BUFI] Bits */ 4101 #define FLCTL_A_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ 4102 #define FLCTL_A_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ 4103 /* FLCTL_A_BANK1_RDCTL[BUFD] Bits */ 4104 #define FLCTL_A_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ 4105 #define FLCTL_A_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ 4106 /* FLCTL_A_BANK1_RDCTL[RD_MODE_STATUS] Bits */ 4107 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ 4108 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ 4109 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ 4110 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ 4111 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ 4112 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ 4113 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4114 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ 4115 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ 4116 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ 4117 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ 4118 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ 4119 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ 4120 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ 4121 /* FLCTL_A_BANK1_RDCTL[WAIT] Bits */ 4122 #define FLCTL_A_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ 4123 #define FLCTL_A_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ 4124 #define FLCTL_A_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ 4125 #define FLCTL_A_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ 4126 #define FLCTL_A_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ 4127 #define FLCTL_A_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ 4128 #define FLCTL_A_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ 4129 #define FLCTL_A_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ 4130 #define FLCTL_A_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ 4131 #define FLCTL_A_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ 4132 #define FLCTL_A_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ 4133 #define FLCTL_A_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ 4134 #define FLCTL_A_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ 4135 #define FLCTL_A_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ 4136 #define FLCTL_A_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ 4137 #define FLCTL_A_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ 4138 #define FLCTL_A_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ 4139 #define FLCTL_A_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ 4140 #define FLCTL_A_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ 4141 #define FLCTL_A_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ 4142 #define FLCTL_A_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ 4143 #define FLCTL_A_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ 4144 /* FLCTL_A_RDBRST_CTLSTAT[START] Bits */ 4145 #define FLCTL_A_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ 4146 #define FLCTL_A_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ 4147 /* FLCTL_A_RDBRST_CTLSTAT[MEM_TYPE] Bits */ 4148 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ 4149 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ 4150 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ 4151 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ 4152 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ 4153 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ 4154 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ 4155 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ 4156 /* FLCTL_A_RDBRST_CTLSTAT[STOP_FAIL] Bits */ 4157 #define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ 4158 #define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ 4159 /* FLCTL_A_RDBRST_CTLSTAT[DATA_CMP] Bits */ 4160 #define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ 4161 #define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ 4162 /* FLCTL_A_RDBRST_CTLSTAT[TEST_EN] Bits */ 4163 #define FLCTL_A_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ 4164 #define FLCTL_A_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ 4165 /* FLCTL_A_RDBRST_CTLSTAT[BRST_STAT] Bits */ 4166 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ 4167 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ 4168 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ 4169 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ 4170 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ 4171 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ 4172 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ 4173 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ 4174 /* explicitly cleared by SW) */ 4175 /* FLCTL_A_RDBRST_CTLSTAT[CMP_ERR] Bits */ 4176 #define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ 4177 #define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ 4178 /* FLCTL_A_RDBRST_CTLSTAT[ADDR_ERR] Bits */ 4179 #define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ 4180 #define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ 4181 /* FLCTL_A_RDBRST_CTLSTAT[CLR_STAT] Bits */ 4182 #define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ 4183 #define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ 4184 /* FLCTL_A_RDBRST_STARTADDR[START_ADDRESS] Bits */ 4185 #define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ 4186 #define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ 4187 /* FLCTL_A_RDBRST_LEN[BURST_LENGTH] Bits */ 4188 #define FLCTL_A_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ 4189 #define FLCTL_A_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ 4190 /* FLCTL_A_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */ 4191 #define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ 4192 #define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ 4193 /* FLCTL_A_RDBRST_FAILCNT[FAIL_COUNT] Bits */ 4194 #define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ 4195 #define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ 4196 /* FLCTL_A_PRG_CTLSTAT[ENABLE] Bits */ 4197 #define FLCTL_A_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ 4198 #define FLCTL_A_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ 4199 /* FLCTL_A_PRG_CTLSTAT[MODE] Bits */ 4200 #define FLCTL_A_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ 4201 #define FLCTL_A_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ 4202 /* FLCTL_A_PRG_CTLSTAT[VER_PRE] Bits */ 4203 #define FLCTL_A_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ 4204 #define FLCTL_A_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ 4205 /* FLCTL_A_PRG_CTLSTAT[VER_PST] Bits */ 4206 #define FLCTL_A_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ 4207 #define FLCTL_A_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ 4208 /* FLCTL_A_PRG_CTLSTAT[STATUS] Bits */ 4209 #define FLCTL_A_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ 4210 #define FLCTL_A_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ 4211 #define FLCTL_A_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ 4212 #define FLCTL_A_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ 4213 #define FLCTL_A_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ 4214 #define FLCTL_A_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ 4215 #define FLCTL_A_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ 4216 #define FLCTL_A_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ 4217 /* FLCTL_A_PRG_CTLSTAT[BNK_ACT] Bits */ 4218 #define FLCTL_A_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ 4219 #define FLCTL_A_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ 4220 /* FLCTL_A_PRGBRST_CTLSTAT[START] Bits */ 4221 #define FLCTL_A_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ 4222 #define FLCTL_A_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ 4223 /* FLCTL_A_PRGBRST_CTLSTAT[TYPE] Bits */ 4224 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ 4225 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ 4226 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ 4227 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ 4228 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ 4229 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ 4230 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ 4231 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ 4232 /* FLCTL_A_PRGBRST_CTLSTAT[LEN] Bits */ 4233 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ 4234 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ 4235 #define FLCTL_A_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ 4236 #define FLCTL_A_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ 4237 #define FLCTL_A_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ 4238 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ 4239 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ 4240 /* FLCTL_PRGBRST_STARTADDR Register */ 4241 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ 4242 /* Register */ 4243 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ 4244 /* Register */ 4245 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ 4246 /* Register */ 4247 /* FLCTL_A_PRGBRST_CTLSTAT[AUTO_PRE] Bits */ 4248 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ 4249 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ 4250 /* FLCTL_A_PRGBRST_CTLSTAT[AUTO_PST] Bits */ 4251 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ 4252 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ 4253 /* FLCTL_A_PRGBRST_CTLSTAT[BURST_STATUS] Bits */ 4254 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ 4255 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ 4256 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ 4257 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ 4258 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ 4259 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ 4260 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ 4261 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ 4262 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ 4263 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ 4264 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ 4265 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ 4266 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ 4267 /* explicitly cleared by SW) */ 4268 /* FLCTL_A_PRGBRST_CTLSTAT[PRE_ERR] Bits */ 4269 #define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ 4270 #define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ 4271 /* FLCTL_A_PRGBRST_CTLSTAT[PST_ERR] Bits */ 4272 #define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ 4273 #define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ 4274 /* FLCTL_A_PRGBRST_CTLSTAT[ADDR_ERR] Bits */ 4275 #define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ 4276 #define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ 4277 /* FLCTL_A_PRGBRST_CTLSTAT[CLR_STAT] Bits */ 4278 #define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ 4279 #define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ 4280 /* FLCTL_A_PRGBRST_STARTADDR[START_ADDRESS] Bits */ 4281 #define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ 4282 #define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ 4283 /* FLCTL_A_ERASE_CTLSTAT[START] Bits */ 4284 #define FLCTL_A_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ 4285 #define FLCTL_A_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ 4286 /* FLCTL_A_ERASE_CTLSTAT[MODE] Bits */ 4287 #define FLCTL_A_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ 4288 #define FLCTL_A_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ 4289 /* FLCTL_A_ERASE_CTLSTAT[TYPE] Bits */ 4290 #define FLCTL_A_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ 4291 #define FLCTL_A_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ 4292 #define FLCTL_A_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ 4293 #define FLCTL_A_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ 4294 #define FLCTL_A_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ 4295 #define FLCTL_A_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ 4296 #define FLCTL_A_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ 4297 #define FLCTL_A_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ 4298 /* FLCTL_A_ERASE_CTLSTAT[STATUS] Bits */ 4299 #define FLCTL_A_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ 4300 #define FLCTL_A_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ 4301 #define FLCTL_A_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ 4302 #define FLCTL_A_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ 4303 #define FLCTL_A_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ 4304 #define FLCTL_A_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ 4305 #define FLCTL_A_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ 4306 #define FLCTL_A_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ 4307 /* unless explicitly cleared by SW) */ 4308 /* FLCTL_A_ERASE_CTLSTAT[ADDR_ERR] Bits */ 4309 #define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ 4310 #define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ 4311 /* address */ 4312 /* FLCTL_A_ERASE_CTLSTAT[CLR_STAT] Bits */ 4313 #define FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ 4314 #define FLCTL_A_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ 4315 /* FLCTL_A_ERASE_SECTADDR[SECT_ADDRESS] Bits */ 4316 #define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ 4317 #define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ 4318 /* FLCTL_A_BANK0_INFO_WEPROT[PROT0] Bits */ 4319 #define FLCTL_A_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4320 #define FLCTL_A_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ 4321 /* FLCTL_A_BANK0_INFO_WEPROT[PROT1] Bits */ 4322 #define FLCTL_A_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4323 #define FLCTL_A_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ 4324 /* FLCTL_A_BANK0_INFO_WEPROT[PROT2] Bits */ 4325 #define FLCTL_A_BANK0_INFO_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ 4326 #define FLCTL_A_BANK0_INFO_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ 4327 /* FLCTL_A_BANK0_INFO_WEPROT[PROT3] Bits */ 4328 #define FLCTL_A_BANK0_INFO_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ 4329 #define FLCTL_A_BANK0_INFO_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ 4330 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT0] Bits */ 4331 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4332 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ 4333 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT1] Bits */ 4334 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4335 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ 4336 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT2] Bits */ 4337 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ 4338 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ 4339 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT3] Bits */ 4340 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ 4341 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ 4342 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT4] Bits */ 4343 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ 4344 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ 4345 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT5] Bits */ 4346 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ 4347 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ 4348 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT6] Bits */ 4349 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ 4350 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ 4351 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT7] Bits */ 4352 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ 4353 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ 4354 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT8] Bits */ 4355 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ 4356 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ 4357 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT9] Bits */ 4358 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ 4359 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ 4360 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT10] Bits */ 4361 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ 4362 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ 4363 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT11] Bits */ 4364 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ 4365 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ 4366 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT12] Bits */ 4367 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ 4368 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ 4369 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT13] Bits */ 4370 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ 4371 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ 4372 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT14] Bits */ 4373 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ 4374 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ 4375 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT15] Bits */ 4376 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ 4377 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ 4378 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT16] Bits */ 4379 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ 4380 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ 4381 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT17] Bits */ 4382 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ 4383 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ 4384 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT18] Bits */ 4385 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ 4386 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ 4387 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT19] Bits */ 4388 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ 4389 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ 4390 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT20] Bits */ 4391 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ 4392 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ 4393 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT21] Bits */ 4394 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ 4395 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ 4396 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT22] Bits */ 4397 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ 4398 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ 4399 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT23] Bits */ 4400 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ 4401 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ 4402 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT24] Bits */ 4403 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ 4404 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ 4405 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT25] Bits */ 4406 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ 4407 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ 4408 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT26] Bits */ 4409 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ 4410 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ 4411 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT27] Bits */ 4412 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ 4413 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ 4414 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT28] Bits */ 4415 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ 4416 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ 4417 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT29] Bits */ 4418 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ 4419 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ 4420 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT30] Bits */ 4421 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ 4422 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ 4423 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT31] Bits */ 4424 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ 4425 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ 4426 /* FLCTL_A_BANK1_INFO_WEPROT[PROT0] Bits */ 4427 #define FLCTL_A_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4428 #define FLCTL_A_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ 4429 /* FLCTL_A_BANK1_INFO_WEPROT[PROT1] Bits */ 4430 #define FLCTL_A_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4431 #define FLCTL_A_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ 4432 /* FLCTL_A_BANK1_INFO_WEPROT[PROT2] Bits */ 4433 #define FLCTL_A_BANK1_INFO_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ 4434 #define FLCTL_A_BANK1_INFO_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ 4435 /* FLCTL_A_BANK1_INFO_WEPROT[PROT3] Bits */ 4436 #define FLCTL_A_BANK1_INFO_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ 4437 #define FLCTL_A_BANK1_INFO_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ 4438 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT0] Bits */ 4439 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4440 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ 4441 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT1] Bits */ 4442 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4443 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ 4444 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT2] Bits */ 4445 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ 4446 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ 4447 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT3] Bits */ 4448 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ 4449 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ 4450 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT4] Bits */ 4451 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ 4452 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ 4453 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT5] Bits */ 4454 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ 4455 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ 4456 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT6] Bits */ 4457 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ 4458 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ 4459 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT7] Bits */ 4460 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ 4461 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ 4462 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT8] Bits */ 4463 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ 4464 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ 4465 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT9] Bits */ 4466 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ 4467 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ 4468 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT10] Bits */ 4469 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ 4470 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ 4471 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT11] Bits */ 4472 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ 4473 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ 4474 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT12] Bits */ 4475 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ 4476 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ 4477 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT13] Bits */ 4478 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ 4479 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ 4480 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT14] Bits */ 4481 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ 4482 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ 4483 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT15] Bits */ 4484 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ 4485 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ 4486 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT16] Bits */ 4487 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ 4488 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ 4489 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT17] Bits */ 4490 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ 4491 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ 4492 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT18] Bits */ 4493 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ 4494 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ 4495 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT19] Bits */ 4496 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ 4497 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ 4498 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT20] Bits */ 4499 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ 4500 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ 4501 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT21] Bits */ 4502 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ 4503 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ 4504 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT22] Bits */ 4505 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ 4506 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ 4507 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT23] Bits */ 4508 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ 4509 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ 4510 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT24] Bits */ 4511 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ 4512 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ 4513 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT25] Bits */ 4514 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ 4515 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ 4516 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT26] Bits */ 4517 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ 4518 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ 4519 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT27] Bits */ 4520 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ 4521 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ 4522 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT28] Bits */ 4523 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ 4524 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ 4525 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT29] Bits */ 4526 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ 4527 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ 4528 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT30] Bits */ 4529 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ 4530 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ 4531 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT31] Bits */ 4532 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ 4533 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ 4534 /* FLCTL_A_BMRK_CTLSTAT[I_BMRK] Bits */ 4535 #define FLCTL_A_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ 4536 #define FLCTL_A_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) 4537 /* FLCTL_A_BMRK_CTLSTAT[D_BMRK] Bits */ 4538 #define FLCTL_A_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ 4539 #define FLCTL_A_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) 4540 /* FLCTL_A_BMRK_CTLSTAT[CMP_EN] Bits */ 4541 #define FLCTL_A_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ 4542 #define FLCTL_A_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) 4543 /* FLCTL_A_BMRK_CTLSTAT[CMP_SEL] Bits */ 4544 #define FLCTL_A_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ 4545 #define FLCTL_A_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) 4546 /* FLCTL_A_IFG[RDBRST] Bits */ 4547 #define FLCTL_A_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4548 #define FLCTL_A_IFG_RDBRST ((uint32_t)0x00000001) 4549 /* FLCTL_A_IFG[AVPRE] Bits */ 4550 #define FLCTL_A_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4551 #define FLCTL_A_IFG_AVPRE ((uint32_t)0x00000002) 4552 /* FLCTL_A_IFG[AVPST] Bits */ 4553 #define FLCTL_A_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4554 #define FLCTL_A_IFG_AVPST ((uint32_t)0x00000004) 4555 /* FLCTL_A_IFG[PRG] Bits */ 4556 #define FLCTL_A_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4557 #define FLCTL_A_IFG_PRG ((uint32_t)0x00000008) 4558 /* FLCTL_A_IFG[PRGB] Bits */ 4559 #define FLCTL_A_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4560 #define FLCTL_A_IFG_PRGB ((uint32_t)0x00000010) 4561 /* FLCTL_A_IFG[ERASE] Bits */ 4562 #define FLCTL_A_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4563 #define FLCTL_A_IFG_ERASE ((uint32_t)0x00000020) 4564 /* FLCTL_A_IFG[BMRK] Bits */ 4565 #define FLCTL_A_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4566 #define FLCTL_A_IFG_BMRK ((uint32_t)0x00000100) 4567 /* FLCTL_A_IFG[PRG_ERR] Bits */ 4568 #define FLCTL_A_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4569 #define FLCTL_A_IFG_PRG_ERR ((uint32_t)0x00000200) 4570 /* FLCTL_A_IE[RDBRST] Bits */ 4571 #define FLCTL_A_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4572 #define FLCTL_A_IE_RDBRST ((uint32_t)0x00000001) 4573 /* FLCTL_A_IE[AVPRE] Bits */ 4574 #define FLCTL_A_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4575 #define FLCTL_A_IE_AVPRE ((uint32_t)0x00000002) 4576 /* FLCTL_A_IE[AVPST] Bits */ 4577 #define FLCTL_A_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4578 #define FLCTL_A_IE_AVPST ((uint32_t)0x00000004) 4579 /* FLCTL_A_IE[PRG] Bits */ 4580 #define FLCTL_A_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4581 #define FLCTL_A_IE_PRG ((uint32_t)0x00000008) 4582 /* FLCTL_A_IE[PRGB] Bits */ 4583 #define FLCTL_A_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4584 #define FLCTL_A_IE_PRGB ((uint32_t)0x00000010) 4585 /* FLCTL_A_IE[ERASE] Bits */ 4586 #define FLCTL_A_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4587 #define FLCTL_A_IE_ERASE ((uint32_t)0x00000020) 4588 /* FLCTL_A_IE[BMRK] Bits */ 4589 #define FLCTL_A_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4590 #define FLCTL_A_IE_BMRK ((uint32_t)0x00000100) 4591 /* FLCTL_A_IE[PRG_ERR] Bits */ 4592 #define FLCTL_A_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4593 #define FLCTL_A_IE_PRG_ERR ((uint32_t)0x00000200) 4594 /* FLCTL_A_CLRIFG[RDBRST] Bits */ 4595 #define FLCTL_A_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4596 #define FLCTL_A_CLRIFG_RDBRST ((uint32_t)0x00000001) 4597 /* FLCTL_A_CLRIFG[AVPRE] Bits */ 4598 #define FLCTL_A_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4599 #define FLCTL_A_CLRIFG_AVPRE ((uint32_t)0x00000002) 4600 /* FLCTL_A_CLRIFG[AVPST] Bits */ 4601 #define FLCTL_A_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4602 #define FLCTL_A_CLRIFG_AVPST ((uint32_t)0x00000004) 4603 /* FLCTL_A_CLRIFG[PRG] Bits */ 4604 #define FLCTL_A_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4605 #define FLCTL_A_CLRIFG_PRG ((uint32_t)0x00000008) 4606 /* FLCTL_A_CLRIFG[PRGB] Bits */ 4607 #define FLCTL_A_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4608 #define FLCTL_A_CLRIFG_PRGB ((uint32_t)0x00000010) 4609 /* FLCTL_A_CLRIFG[ERASE] Bits */ 4610 #define FLCTL_A_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4611 #define FLCTL_A_CLRIFG_ERASE ((uint32_t)0x00000020) 4612 /* FLCTL_A_CLRIFG[BMRK] Bits */ 4613 #define FLCTL_A_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4614 #define FLCTL_A_CLRIFG_BMRK ((uint32_t)0x00000100) 4615 /* FLCTL_A_CLRIFG[PRG_ERR] Bits */ 4616 #define FLCTL_A_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4617 #define FLCTL_A_CLRIFG_PRG_ERR ((uint32_t)0x00000200) 4618 /* FLCTL_A_SETIFG[RDBRST] Bits */ 4619 #define FLCTL_A_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4620 #define FLCTL_A_SETIFG_RDBRST ((uint32_t)0x00000001) 4621 /* FLCTL_A_SETIFG[AVPRE] Bits */ 4622 #define FLCTL_A_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4623 #define FLCTL_A_SETIFG_AVPRE ((uint32_t)0x00000002) 4624 /* FLCTL_A_SETIFG[AVPST] Bits */ 4625 #define FLCTL_A_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4626 #define FLCTL_A_SETIFG_AVPST ((uint32_t)0x00000004) 4627 /* FLCTL_A_SETIFG[PRG] Bits */ 4628 #define FLCTL_A_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4629 #define FLCTL_A_SETIFG_PRG ((uint32_t)0x00000008) 4630 /* FLCTL_A_SETIFG[PRGB] Bits */ 4631 #define FLCTL_A_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4632 #define FLCTL_A_SETIFG_PRGB ((uint32_t)0x00000010) 4633 /* FLCTL_A_SETIFG[ERASE] Bits */ 4634 #define FLCTL_A_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4635 #define FLCTL_A_SETIFG_ERASE ((uint32_t)0x00000020) 4636 /* FLCTL_A_SETIFG[BMRK] Bits */ 4637 #define FLCTL_A_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4638 #define FLCTL_A_SETIFG_BMRK ((uint32_t)0x00000100) 4639 /* FLCTL_A_SETIFG[PRG_ERR] Bits */ 4640 #define FLCTL_A_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4641 #define FLCTL_A_SETIFG_PRG_ERR ((uint32_t)0x00000200) 4642 /* FLCTL_A_READ_TIMCTL[SETUP] Bits */ 4643 #define FLCTL_A_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4644 #define FLCTL_A_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4645 /* FLCTL_A_READ_TIMCTL[IREF_BOOST1] Bits */ 4646 #define FLCTL_A_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ 4647 #define FLCTL_A_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ 4648 /* FLCTL_A_READ_TIMCTL[SETUP_LONG] Bits */ 4649 #define FLCTL_A_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ 4650 #define FLCTL_A_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ 4651 /* FLCTL_A_READMARGIN_TIMCTL[SETUP] Bits */ 4652 #define FLCTL_A_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4653 #define FLCTL_A_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4654 /* FLCTL_A_PRGVER_TIMCTL[SETUP] Bits */ 4655 #define FLCTL_A_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4656 #define FLCTL_A_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4657 /* FLCTL_A_PRGVER_TIMCTL[ACTIVE] Bits */ 4658 #define FLCTL_A_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4659 #define FLCTL_A_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ 4660 /* FLCTL_A_PRGVER_TIMCTL[HOLD] Bits */ 4661 #define FLCTL_A_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ 4662 #define FLCTL_A_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ 4663 /* FLCTL_A_ERSVER_TIMCTL[SETUP] Bits */ 4664 #define FLCTL_A_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4665 #define FLCTL_A_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4666 /* FLCTL_A_LKGVER_TIMCTL[SETUP] Bits */ 4667 #define FLCTL_A_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4668 #define FLCTL_A_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4669 /* FLCTL_A_PROGRAM_TIMCTL[SETUP] Bits */ 4670 #define FLCTL_A_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4671 #define FLCTL_A_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4672 /* FLCTL_A_PROGRAM_TIMCTL[ACTIVE] Bits */ 4673 #define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4674 #define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ 4675 /* FLCTL_A_PROGRAM_TIMCTL[HOLD] Bits */ 4676 #define FLCTL_A_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ 4677 #define FLCTL_A_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ 4678 /* FLCTL_A_ERASE_TIMCTL[SETUP] Bits */ 4679 #define FLCTL_A_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4680 #define FLCTL_A_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4681 /* FLCTL_A_ERASE_TIMCTL[ACTIVE] Bits */ 4682 #define FLCTL_A_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4683 #define FLCTL_A_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ 4684 /* FLCTL_A_ERASE_TIMCTL[HOLD] Bits */ 4685 #define FLCTL_A_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ 4686 #define FLCTL_A_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ 4687 /* FLCTL_A_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */ 4688 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ 4689 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ 4690 /* FLCTL_A_MASSERASE_TIMCTL[BOOST_HOLD] Bits */ 4691 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ 4692 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ 4693 /* FLCTL_A_BURSTPRG_TIMCTL[ACTIVE] Bits */ 4694 #define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4695 #define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ 4696 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT0] Bits */ 4697 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4698 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ 4699 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT1] Bits */ 4700 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4701 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ 4702 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT2] Bits */ 4703 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ 4704 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ 4705 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT3] Bits */ 4706 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ 4707 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ 4708 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT4] Bits */ 4709 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ 4710 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ 4711 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT5] Bits */ 4712 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ 4713 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ 4714 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT6] Bits */ 4715 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ 4716 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ 4717 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT7] Bits */ 4718 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ 4719 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ 4720 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT8] Bits */ 4721 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ 4722 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ 4723 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT9] Bits */ 4724 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ 4725 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ 4726 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT10] Bits */ 4727 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10_OFS (10) /*!< PROT10 Bit Offset */ 4728 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ 4729 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT11] Bits */ 4730 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11_OFS (11) /*!< PROT11 Bit Offset */ 4731 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ 4732 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT12] Bits */ 4733 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12_OFS (12) /*!< PROT12 Bit Offset */ 4734 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ 4735 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT13] Bits */ 4736 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13_OFS (13) /*!< PROT13 Bit Offset */ 4737 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ 4738 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT14] Bits */ 4739 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14_OFS (14) /*!< PROT14 Bit Offset */ 4740 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ 4741 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT15] Bits */ 4742 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15_OFS (15) /*!< PROT15 Bit Offset */ 4743 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ 4744 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT16] Bits */ 4745 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16_OFS (16) /*!< PROT16 Bit Offset */ 4746 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ 4747 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT17] Bits */ 4748 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17_OFS (17) /*!< PROT17 Bit Offset */ 4749 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ 4750 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT18] Bits */ 4751 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18_OFS (18) /*!< PROT18 Bit Offset */ 4752 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ 4753 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT19] Bits */ 4754 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19_OFS (19) /*!< PROT19 Bit Offset */ 4755 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ 4756 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT20] Bits */ 4757 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20_OFS (20) /*!< PROT20 Bit Offset */ 4758 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ 4759 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT21] Bits */ 4760 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21_OFS (21) /*!< PROT21 Bit Offset */ 4761 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ 4762 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT22] Bits */ 4763 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22_OFS (22) /*!< PROT22 Bit Offset */ 4764 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ 4765 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT23] Bits */ 4766 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23_OFS (23) /*!< PROT23 Bit Offset */ 4767 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ 4768 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT24] Bits */ 4769 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24_OFS (24) /*!< PROT24 Bit Offset */ 4770 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ 4771 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT25] Bits */ 4772 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25_OFS (25) /*!< PROT25 Bit Offset */ 4773 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ 4774 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT26] Bits */ 4775 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26_OFS (26) /*!< PROT26 Bit Offset */ 4776 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ 4777 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT27] Bits */ 4778 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27_OFS (27) /*!< PROT27 Bit Offset */ 4779 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ 4780 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT28] Bits */ 4781 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28_OFS (28) /*!< PROT28 Bit Offset */ 4782 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ 4783 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT29] Bits */ 4784 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29_OFS (29) /*!< PROT29 Bit Offset */ 4785 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ 4786 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT30] Bits */ 4787 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30_OFS (30) /*!< PROT30 Bit Offset */ 4788 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ 4789 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT31] Bits */ 4790 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31_OFS (31) /*!< PROT31 Bit Offset */ 4791 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ 4792 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT32] Bits */ 4793 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32_OFS ( 0) /*!< PROT32 Bit Offset */ 4794 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32 ((uint32_t)0x00000001) /*!< Protects Sector 32 from program or erase */ 4795 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT33] Bits */ 4796 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33_OFS ( 1) /*!< PROT33 Bit Offset */ 4797 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33 ((uint32_t)0x00000002) /*!< Protects Sector 33 from program or erase */ 4798 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT34] Bits */ 4799 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34_OFS ( 2) /*!< PROT34 Bit Offset */ 4800 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34 ((uint32_t)0x00000004) /*!< Protects Sector 34 from program or erase */ 4801 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT35] Bits */ 4802 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35_OFS ( 3) /*!< PROT35 Bit Offset */ 4803 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35 ((uint32_t)0x00000008) /*!< Protects Sector 35 from program or erase */ 4804 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT36] Bits */ 4805 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36_OFS ( 4) /*!< PROT36 Bit Offset */ 4806 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36 ((uint32_t)0x00000010) /*!< Protects Sector 36 from program or erase */ 4807 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT37] Bits */ 4808 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37_OFS ( 5) /*!< PROT37 Bit Offset */ 4809 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37 ((uint32_t)0x00000020) /*!< Protects Sector 37 from program or erase */ 4810 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT38] Bits */ 4811 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38_OFS ( 6) /*!< PROT38 Bit Offset */ 4812 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38 ((uint32_t)0x00000040) /*!< Protects Sector 38 from program or erase */ 4813 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT39] Bits */ 4814 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39_OFS ( 7) /*!< PROT39 Bit Offset */ 4815 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39 ((uint32_t)0x00000080) /*!< Protects Sector 39 from program or erase */ 4816 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT40] Bits */ 4817 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40_OFS ( 8) /*!< PROT40 Bit Offset */ 4818 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40 ((uint32_t)0x00000100) /*!< Protects Sector 40 from program or erase */ 4819 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT41] Bits */ 4820 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41_OFS ( 9) /*!< PROT41 Bit Offset */ 4821 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41 ((uint32_t)0x00000200) /*!< Protects Sector 41 from program or erase */ 4822 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT42] Bits */ 4823 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42_OFS (10) /*!< PROT42 Bit Offset */ 4824 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42 ((uint32_t)0x00000400) /*!< Protects Sector 42 from program or erase */ 4825 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT43] Bits */ 4826 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43_OFS (11) /*!< PROT43 Bit Offset */ 4827 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43 ((uint32_t)0x00000800) /*!< Protects Sector 43 from program or erase */ 4828 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT44] Bits */ 4829 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44_OFS (12) /*!< PROT44 Bit Offset */ 4830 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44 ((uint32_t)0x00001000) /*!< Protects Sector 44 from program or erase */ 4831 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT45] Bits */ 4832 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45_OFS (13) /*!< PROT45 Bit Offset */ 4833 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45 ((uint32_t)0x00002000) /*!< Protects Sector 45 from program or erase */ 4834 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT46] Bits */ 4835 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46_OFS (14) /*!< PROT46 Bit Offset */ 4836 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46 ((uint32_t)0x00004000) /*!< Protects Sector 46 from program or erase */ 4837 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT47] Bits */ 4838 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47_OFS (15) /*!< PROT47 Bit Offset */ 4839 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47 ((uint32_t)0x00008000) /*!< Protects Sector 47 from program or erase */ 4840 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT48] Bits */ 4841 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48_OFS (16) /*!< PROT48 Bit Offset */ 4842 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48 ((uint32_t)0x00010000) /*!< Protects Sector 48 from program or erase */ 4843 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT49] Bits */ 4844 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49_OFS (17) /*!< PROT49 Bit Offset */ 4845 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49 ((uint32_t)0x00020000) /*!< Protects Sector 49 from program or erase */ 4846 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT50] Bits */ 4847 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50_OFS (18) /*!< PROT50 Bit Offset */ 4848 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50 ((uint32_t)0x00040000) /*!< Protects Sector 50 from program or erase */ 4849 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT51] Bits */ 4850 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51_OFS (19) /*!< PROT51 Bit Offset */ 4851 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51 ((uint32_t)0x00080000) /*!< Protects Sector 51 from program or erase */ 4852 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT52] Bits */ 4853 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52_OFS (20) /*!< PROT52 Bit Offset */ 4854 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52 ((uint32_t)0x00100000) /*!< Protects Sector 52 from program or erase */ 4855 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT53] Bits */ 4856 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53_OFS (21) /*!< PROT53 Bit Offset */ 4857 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53 ((uint32_t)0x00200000) /*!< Protects Sector 53 from program or erase */ 4858 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT54] Bits */ 4859 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54_OFS (22) /*!< PROT54 Bit Offset */ 4860 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54 ((uint32_t)0x00400000) /*!< Protects Sector 54 from program or erase */ 4861 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT55] Bits */ 4862 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55_OFS (23) /*!< PROT55 Bit Offset */ 4863 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55 ((uint32_t)0x00800000) /*!< Protects Sector 55 from program or erase */ 4864 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT56] Bits */ 4865 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56_OFS (24) /*!< PROT56 Bit Offset */ 4866 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56 ((uint32_t)0x01000000) /*!< Protects Sector 56 from program or erase */ 4867 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT57] Bits */ 4868 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57_OFS (25) /*!< PROT57 Bit Offset */ 4869 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57 ((uint32_t)0x02000000) /*!< Protects Sector 57 from program or erase */ 4870 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT58] Bits */ 4871 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58_OFS (26) /*!< PROT58 Bit Offset */ 4872 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58 ((uint32_t)0x04000000) /*!< Protects Sector 58 from program or erase */ 4873 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT59] Bits */ 4874 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59_OFS (27) /*!< PROT59 Bit Offset */ 4875 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59 ((uint32_t)0x08000000) /*!< Protects Sector 59 from program or erase */ 4876 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT60] Bits */ 4877 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60_OFS (28) /*!< PROT60 Bit Offset */ 4878 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60 ((uint32_t)0x10000000) /*!< Protects Sector 60 from program or erase */ 4879 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT61] Bits */ 4880 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61_OFS (29) /*!< PROT61 Bit Offset */ 4881 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61 ((uint32_t)0x20000000) /*!< Protects Sector 61 from program or erase */ 4882 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT62] Bits */ 4883 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62_OFS (30) /*!< PROT62 Bit Offset */ 4884 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62 ((uint32_t)0x40000000) /*!< Protects Sector 62 from program or erase */ 4885 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT63] Bits */ 4886 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63_OFS (31) /*!< PROT63 Bit Offset */ 4887 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63 ((uint32_t)0x80000000) /*!< Protects Sector 63 from program or erase */ 4888 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT64] Bits */ 4889 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64_OFS ( 0) /*!< PROT64 Bit Offset */ 4890 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64 ((uint32_t)0x00000001) /*!< Protects Sector 64 from program or erase */ 4891 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT65] Bits */ 4892 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65_OFS ( 1) /*!< PROT65 Bit Offset */ 4893 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65 ((uint32_t)0x00000002) /*!< Protects Sector 65 from program or erase */ 4894 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT66] Bits */ 4895 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66_OFS ( 2) /*!< PROT66 Bit Offset */ 4896 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66 ((uint32_t)0x00000004) /*!< Protects Sector 66 from program or erase */ 4897 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT67] Bits */ 4898 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67_OFS ( 3) /*!< PROT67 Bit Offset */ 4899 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67 ((uint32_t)0x00000008) /*!< Protects Sector 67 from program or erase */ 4900 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT68] Bits */ 4901 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68_OFS ( 4) /*!< PROT68 Bit Offset */ 4902 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68 ((uint32_t)0x00000010) /*!< Protects Sector 68 from program or erase */ 4903 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT69] Bits */ 4904 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69_OFS ( 5) /*!< PROT69 Bit Offset */ 4905 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69 ((uint32_t)0x00000020) /*!< Protects Sector 69 from program or erase */ 4906 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT70] Bits */ 4907 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70_OFS ( 6) /*!< PROT70 Bit Offset */ 4908 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70 ((uint32_t)0x00000040) /*!< Protects Sector 70 from program or erase */ 4909 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT71] Bits */ 4910 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71_OFS ( 7) /*!< PROT71 Bit Offset */ 4911 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71 ((uint32_t)0x00000080) /*!< Protects Sector 71 from program or erase */ 4912 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT72] Bits */ 4913 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72_OFS ( 8) /*!< PROT72 Bit Offset */ 4914 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72 ((uint32_t)0x00000100) /*!< Protects Sector 72 from program or erase */ 4915 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT73] Bits */ 4916 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73_OFS ( 9) /*!< PROT73 Bit Offset */ 4917 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73 ((uint32_t)0x00000200) /*!< Protects Sector 73 from program or erase */ 4918 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT74] Bits */ 4919 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74_OFS (10) /*!< PROT74 Bit Offset */ 4920 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74 ((uint32_t)0x00000400) /*!< Protects Sector 74 from program or erase */ 4921 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT75] Bits */ 4922 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75_OFS (11) /*!< PROT75 Bit Offset */ 4923 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75 ((uint32_t)0x00000800) /*!< Protects Sector 75 from program or erase */ 4924 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT76] Bits */ 4925 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76_OFS (12) /*!< PROT76 Bit Offset */ 4926 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76 ((uint32_t)0x00001000) /*!< Protects Sector 76 from program or erase */ 4927 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT77] Bits */ 4928 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77_OFS (13) /*!< PROT77 Bit Offset */ 4929 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77 ((uint32_t)0x00002000) /*!< Protects Sector 77 from program or erase */ 4930 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT78] Bits */ 4931 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78_OFS (14) /*!< PROT78 Bit Offset */ 4932 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78 ((uint32_t)0x00004000) /*!< Protects Sector 78 from program or erase */ 4933 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT79] Bits */ 4934 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79_OFS (15) /*!< PROT79 Bit Offset */ 4935 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79 ((uint32_t)0x00008000) /*!< Protects Sector 79 from program or erase */ 4936 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT80] Bits */ 4937 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80_OFS (16) /*!< PROT80 Bit Offset */ 4938 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80 ((uint32_t)0x00010000) /*!< Protects Sector 80 from program or erase */ 4939 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT81] Bits */ 4940 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81_OFS (17) /*!< PROT81 Bit Offset */ 4941 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81 ((uint32_t)0x00020000) /*!< Protects Sector 81 from program or erase */ 4942 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT82] Bits */ 4943 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82_OFS (18) /*!< PROT82 Bit Offset */ 4944 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82 ((uint32_t)0x00040000) /*!< Protects Sector 82 from program or erase */ 4945 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT83] Bits */ 4946 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83_OFS (19) /*!< PROT83 Bit Offset */ 4947 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83 ((uint32_t)0x00080000) /*!< Protects Sector 83 from program or erase */ 4948 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT84] Bits */ 4949 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84_OFS (20) /*!< PROT84 Bit Offset */ 4950 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84 ((uint32_t)0x00100000) /*!< Protects Sector 84 from program or erase */ 4951 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT85] Bits */ 4952 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85_OFS (21) /*!< PROT85 Bit Offset */ 4953 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85 ((uint32_t)0x00200000) /*!< Protects Sector 85 from program or erase */ 4954 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT86] Bits */ 4955 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86_OFS (22) /*!< PROT86 Bit Offset */ 4956 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86 ((uint32_t)0x00400000) /*!< Protects Sector 86 from program or erase */ 4957 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT87] Bits */ 4958 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87_OFS (23) /*!< PROT87 Bit Offset */ 4959 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87 ((uint32_t)0x00800000) /*!< Protects Sector 87 from program or erase */ 4960 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT88] Bits */ 4961 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88_OFS (24) /*!< PROT88 Bit Offset */ 4962 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88 ((uint32_t)0x01000000) /*!< Protects Sector 88 from program or erase */ 4963 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT89] Bits */ 4964 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89_OFS (25) /*!< PROT89 Bit Offset */ 4965 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89 ((uint32_t)0x02000000) /*!< Protects Sector 89 from program or erase */ 4966 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT90] Bits */ 4967 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90_OFS (26) /*!< PROT90 Bit Offset */ 4968 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90 ((uint32_t)0x04000000) /*!< Protects Sector 90 from program or erase */ 4969 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT91] Bits */ 4970 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91_OFS (27) /*!< PROT91 Bit Offset */ 4971 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91 ((uint32_t)0x08000000) /*!< Protects Sector 91 from program or erase */ 4972 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT92] Bits */ 4973 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92_OFS (28) /*!< PROT92 Bit Offset */ 4974 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92 ((uint32_t)0x10000000) /*!< Protects Sector 92 from program or erase */ 4975 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT93] Bits */ 4976 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93_OFS (29) /*!< PROT93 Bit Offset */ 4977 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93 ((uint32_t)0x20000000) /*!< Protects Sector 93 from program or erase */ 4978 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT94] Bits */ 4979 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94_OFS (30) /*!< PROT94 Bit Offset */ 4980 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94 ((uint32_t)0x40000000) /*!< Protects Sector 94 from program or erase */ 4981 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT95] Bits */ 4982 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95_OFS (31) /*!< PROT95 Bit Offset */ 4983 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95 ((uint32_t)0x80000000) /*!< Protects Sector 95 from program or erase */ 4984 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT96] Bits */ 4985 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96_OFS ( 0) /*!< PROT96 Bit Offset */ 4986 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96 ((uint32_t)0x00000001) /*!< Protects Sector 96 from program or erase */ 4987 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT97] Bits */ 4988 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97_OFS ( 1) /*!< PROT97 Bit Offset */ 4989 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97 ((uint32_t)0x00000002) /*!< Protects Sector 97 from program or erase */ 4990 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT98] Bits */ 4991 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98_OFS ( 2) /*!< PROT98 Bit Offset */ 4992 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98 ((uint32_t)0x00000004) /*!< Protects Sector 98 from program or erase */ 4993 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT99] Bits */ 4994 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99_OFS ( 3) /*!< PROT99 Bit Offset */ 4995 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99 ((uint32_t)0x00000008) /*!< Protects Sector 99 from program or erase */ 4996 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT100] Bits */ 4997 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100_OFS ( 4) /*!< PROT100 Bit Offset */ 4998 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100 ((uint32_t)0x00000010) /*!< Protects Sector 100 from program or erase */ 4999 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT101] Bits */ 5000 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101_OFS ( 5) /*!< PROT101 Bit Offset */ 5001 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101 ((uint32_t)0x00000020) /*!< Protects Sector 101 from program or erase */ 5002 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT102] Bits */ 5003 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102_OFS ( 6) /*!< PROT102 Bit Offset */ 5004 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102 ((uint32_t)0x00000040) /*!< Protects Sector 102 from program or erase */ 5005 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT103] Bits */ 5006 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103_OFS ( 7) /*!< PROT103 Bit Offset */ 5007 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103 ((uint32_t)0x00000080) /*!< Protects Sector 103 from program or erase */ 5008 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT104] Bits */ 5009 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104_OFS ( 8) /*!< PROT104 Bit Offset */ 5010 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104 ((uint32_t)0x00000100) /*!< Protects Sector 104 from program or erase */ 5011 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT105] Bits */ 5012 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105_OFS ( 9) /*!< PROT105 Bit Offset */ 5013 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105 ((uint32_t)0x00000200) /*!< Protects Sector 105 from program or erase */ 5014 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT106] Bits */ 5015 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106_OFS (10) /*!< PROT106 Bit Offset */ 5016 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106 ((uint32_t)0x00000400) /*!< Protects Sector 106 from program or erase */ 5017 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT107] Bits */ 5018 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107_OFS (11) /*!< PROT107 Bit Offset */ 5019 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107 ((uint32_t)0x00000800) /*!< Protects Sector 107 from program or erase */ 5020 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT108] Bits */ 5021 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108_OFS (12) /*!< PROT108 Bit Offset */ 5022 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108 ((uint32_t)0x00001000) /*!< Protects Sector 108 from program or erase */ 5023 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT109] Bits */ 5024 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109_OFS (13) /*!< PROT109 Bit Offset */ 5025 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109 ((uint32_t)0x00002000) /*!< Protects Sector 109 from program or erase */ 5026 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT110] Bits */ 5027 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110_OFS (14) /*!< PROT110 Bit Offset */ 5028 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110 ((uint32_t)0x00004000) /*!< Protects Sector 110 from program or erase */ 5029 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT111] Bits */ 5030 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111_OFS (15) /*!< PROT111 Bit Offset */ 5031 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111 ((uint32_t)0x00008000) /*!< Protects Sector 111 from program or erase */ 5032 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT112] Bits */ 5033 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112_OFS (16) /*!< PROT112 Bit Offset */ 5034 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112 ((uint32_t)0x00010000) /*!< Protects Sector 112 from program or erase */ 5035 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT113] Bits */ 5036 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113_OFS (17) /*!< PROT113 Bit Offset */ 5037 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113 ((uint32_t)0x00020000) /*!< Protects Sector 113 from program or erase */ 5038 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT114] Bits */ 5039 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114_OFS (18) /*!< PROT114 Bit Offset */ 5040 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114 ((uint32_t)0x00040000) /*!< Protects Sector 114 from program or erase */ 5041 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT115] Bits */ 5042 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115_OFS (19) /*!< PROT115 Bit Offset */ 5043 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115 ((uint32_t)0x00080000) /*!< Protects Sector 115 from program or erase */ 5044 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT116] Bits */ 5045 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116_OFS (20) /*!< PROT116 Bit Offset */ 5046 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116 ((uint32_t)0x00100000) /*!< Protects Sector 116 from program or erase */ 5047 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT117] Bits */ 5048 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117_OFS (21) /*!< PROT117 Bit Offset */ 5049 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117 ((uint32_t)0x00200000) /*!< Protects Sector 117 from program or erase */ 5050 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT118] Bits */ 5051 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118_OFS (22) /*!< PROT118 Bit Offset */ 5052 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118 ((uint32_t)0x00400000) /*!< Protects Sector 118 from program or erase */ 5053 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT119] Bits */ 5054 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119_OFS (23) /*!< PROT119 Bit Offset */ 5055 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119 ((uint32_t)0x00800000) /*!< Protects Sector 119 from program or erase */ 5056 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT120] Bits */ 5057 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120_OFS (24) /*!< PROT120 Bit Offset */ 5058 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120 ((uint32_t)0x01000000) /*!< Protects Sector 120 from program or erase */ 5059 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT121] Bits */ 5060 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121_OFS (25) /*!< PROT121 Bit Offset */ 5061 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121 ((uint32_t)0x02000000) /*!< Protects Sector 121 from program or erase */ 5062 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT122] Bits */ 5063 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122_OFS (26) /*!< PROT122 Bit Offset */ 5064 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122 ((uint32_t)0x04000000) /*!< Protects Sector 122 from program or erase */ 5065 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT123] Bits */ 5066 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123_OFS (27) /*!< PROT123 Bit Offset */ 5067 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123 ((uint32_t)0x08000000) /*!< Protects Sector 123 from program or erase */ 5068 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT124] Bits */ 5069 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124_OFS (28) /*!< PROT124 Bit Offset */ 5070 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124 ((uint32_t)0x10000000) /*!< Protects Sector 124 from program or erase */ 5071 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT125] Bits */ 5072 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125_OFS (29) /*!< PROT125 Bit Offset */ 5073 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125 ((uint32_t)0x20000000) /*!< Protects Sector 125 from program or erase */ 5074 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT126] Bits */ 5075 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126_OFS (30) /*!< PROT126 Bit Offset */ 5076 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126 ((uint32_t)0x40000000) /*!< Protects Sector 126 from program or erase */ 5077 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT127] Bits */ 5078 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127_OFS (31) /*!< PROT127 Bit Offset */ 5079 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127 ((uint32_t)0x80000000) /*!< Protects Sector 127 from program or erase */ 5080 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT128] Bits */ 5081 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128_OFS ( 0) /*!< PROT128 Bit Offset */ 5082 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128 ((uint32_t)0x00000001) /*!< Protects Sector 128 from program or erase */ 5083 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT129] Bits */ 5084 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129_OFS ( 1) /*!< PROT129 Bit Offset */ 5085 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129 ((uint32_t)0x00000002) /*!< Protects Sector 129 from program or erase */ 5086 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT130] Bits */ 5087 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130_OFS ( 2) /*!< PROT130 Bit Offset */ 5088 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130 ((uint32_t)0x00000004) /*!< Protects Sector 130 from program or erase */ 5089 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT131] Bits */ 5090 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131_OFS ( 3) /*!< PROT131 Bit Offset */ 5091 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131 ((uint32_t)0x00000008) /*!< Protects Sector 131 from program or erase */ 5092 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT132] Bits */ 5093 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132_OFS ( 4) /*!< PROT132 Bit Offset */ 5094 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132 ((uint32_t)0x00000010) /*!< Protects Sector 132 from program or erase */ 5095 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT133] Bits */ 5096 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133_OFS ( 5) /*!< PROT133 Bit Offset */ 5097 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133 ((uint32_t)0x00000020) /*!< Protects Sector 133 from program or erase */ 5098 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT134] Bits */ 5099 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134_OFS ( 6) /*!< PROT134 Bit Offset */ 5100 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134 ((uint32_t)0x00000040) /*!< Protects Sector 134 from program or erase */ 5101 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT135] Bits */ 5102 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135_OFS ( 7) /*!< PROT135 Bit Offset */ 5103 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135 ((uint32_t)0x00000080) /*!< Protects Sector 135 from program or erase */ 5104 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT136] Bits */ 5105 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136_OFS ( 8) /*!< PROT136 Bit Offset */ 5106 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136 ((uint32_t)0x00000100) /*!< Protects Sector 136 from program or erase */ 5107 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT137] Bits */ 5108 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137_OFS ( 9) /*!< PROT137 Bit Offset */ 5109 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137 ((uint32_t)0x00000200) /*!< Protects Sector 137 from program or erase */ 5110 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT138] Bits */ 5111 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138_OFS (10) /*!< PROT138 Bit Offset */ 5112 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138 ((uint32_t)0x00000400) /*!< Protects Sector 138 from program or erase */ 5113 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT139] Bits */ 5114 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139_OFS (11) /*!< PROT139 Bit Offset */ 5115 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139 ((uint32_t)0x00000800) /*!< Protects Sector 139 from program or erase */ 5116 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT140] Bits */ 5117 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140_OFS (12) /*!< PROT140 Bit Offset */ 5118 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140 ((uint32_t)0x00001000) /*!< Protects Sector 140 from program or erase */ 5119 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT141] Bits */ 5120 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141_OFS (13) /*!< PROT141 Bit Offset */ 5121 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141 ((uint32_t)0x00002000) /*!< Protects Sector 141 from program or erase */ 5122 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT142] Bits */ 5123 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142_OFS (14) /*!< PROT142 Bit Offset */ 5124 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142 ((uint32_t)0x00004000) /*!< Protects Sector 142 from program or erase */ 5125 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT143] Bits */ 5126 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143_OFS (15) /*!< PROT143 Bit Offset */ 5127 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143 ((uint32_t)0x00008000) /*!< Protects Sector 143 from program or erase */ 5128 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT144] Bits */ 5129 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144_OFS (16) /*!< PROT144 Bit Offset */ 5130 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144 ((uint32_t)0x00010000) /*!< Protects Sector 144 from program or erase */ 5131 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT145] Bits */ 5132 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145_OFS (17) /*!< PROT145 Bit Offset */ 5133 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145 ((uint32_t)0x00020000) /*!< Protects Sector 145 from program or erase */ 5134 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT146] Bits */ 5135 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146_OFS (18) /*!< PROT146 Bit Offset */ 5136 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146 ((uint32_t)0x00040000) /*!< Protects Sector 146 from program or erase */ 5137 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT147] Bits */ 5138 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147_OFS (19) /*!< PROT147 Bit Offset */ 5139 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147 ((uint32_t)0x00080000) /*!< Protects Sector 147 from program or erase */ 5140 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT148] Bits */ 5141 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148_OFS (20) /*!< PROT148 Bit Offset */ 5142 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148 ((uint32_t)0x00100000) /*!< Protects Sector 148 from program or erase */ 5143 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT149] Bits */ 5144 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149_OFS (21) /*!< PROT149 Bit Offset */ 5145 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149 ((uint32_t)0x00200000) /*!< Protects Sector 149 from program or erase */ 5146 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT150] Bits */ 5147 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150_OFS (22) /*!< PROT150 Bit Offset */ 5148 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150 ((uint32_t)0x00400000) /*!< Protects Sector 150 from program or erase */ 5149 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT151] Bits */ 5150 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151_OFS (23) /*!< PROT151 Bit Offset */ 5151 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151 ((uint32_t)0x00800000) /*!< Protects Sector 151 from program or erase */ 5152 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT152] Bits */ 5153 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152_OFS (24) /*!< PROT152 Bit Offset */ 5154 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152 ((uint32_t)0x01000000) /*!< Protects Sector 152 from program or erase */ 5155 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT153] Bits */ 5156 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153_OFS (25) /*!< PROT153 Bit Offset */ 5157 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153 ((uint32_t)0x02000000) /*!< Protects Sector 153 from program or erase */ 5158 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT154] Bits */ 5159 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154_OFS (26) /*!< PROT154 Bit Offset */ 5160 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154 ((uint32_t)0x04000000) /*!< Protects Sector 154 from program or erase */ 5161 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT155] Bits */ 5162 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155_OFS (27) /*!< PROT155 Bit Offset */ 5163 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155 ((uint32_t)0x08000000) /*!< Protects Sector 155 from program or erase */ 5164 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT156] Bits */ 5165 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156_OFS (28) /*!< PROT156 Bit Offset */ 5166 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156 ((uint32_t)0x10000000) /*!< Protects Sector 156 from program or erase */ 5167 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT157] Bits */ 5168 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157_OFS (29) /*!< PROT157 Bit Offset */ 5169 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157 ((uint32_t)0x20000000) /*!< Protects Sector 157 from program or erase */ 5170 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT158] Bits */ 5171 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158_OFS (30) /*!< PROT158 Bit Offset */ 5172 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158 ((uint32_t)0x40000000) /*!< Protects Sector 158 from program or erase */ 5173 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT159] Bits */ 5174 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159_OFS (31) /*!< PROT159 Bit Offset */ 5175 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159 ((uint32_t)0x80000000) /*!< Protects Sector 159 from program or erase */ 5176 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT160] Bits */ 5177 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160_OFS ( 0) /*!< PROT160 Bit Offset */ 5178 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160 ((uint32_t)0x00000001) /*!< Protects Sector 160 from program or erase */ 5179 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT161] Bits */ 5180 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161_OFS ( 1) /*!< PROT161 Bit Offset */ 5181 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161 ((uint32_t)0x00000002) /*!< Protects Sector 161 from program or erase */ 5182 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT162] Bits */ 5183 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162_OFS ( 2) /*!< PROT162 Bit Offset */ 5184 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162 ((uint32_t)0x00000004) /*!< Protects Sector 162 from program or erase */ 5185 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT163] Bits */ 5186 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163_OFS ( 3) /*!< PROT163 Bit Offset */ 5187 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163 ((uint32_t)0x00000008) /*!< Protects Sector 163 from program or erase */ 5188 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT164] Bits */ 5189 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164_OFS ( 4) /*!< PROT164 Bit Offset */ 5190 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164 ((uint32_t)0x00000010) /*!< Protects Sector 164 from program or erase */ 5191 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT165] Bits */ 5192 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165_OFS ( 5) /*!< PROT165 Bit Offset */ 5193 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165 ((uint32_t)0x00000020) /*!< Protects Sector 165 from program or erase */ 5194 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT166] Bits */ 5195 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166_OFS ( 6) /*!< PROT166 Bit Offset */ 5196 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166 ((uint32_t)0x00000040) /*!< Protects Sector 166 from program or erase */ 5197 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT167] Bits */ 5198 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167_OFS ( 7) /*!< PROT167 Bit Offset */ 5199 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167 ((uint32_t)0x00000080) /*!< Protects Sector 167 from program or erase */ 5200 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT168] Bits */ 5201 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168_OFS ( 8) /*!< PROT168 Bit Offset */ 5202 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168 ((uint32_t)0x00000100) /*!< Protects Sector 168 from program or erase */ 5203 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT169] Bits */ 5204 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169_OFS ( 9) /*!< PROT169 Bit Offset */ 5205 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169 ((uint32_t)0x00000200) /*!< Protects Sector 169 from program or erase */ 5206 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT170] Bits */ 5207 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170_OFS (10) /*!< PROT170 Bit Offset */ 5208 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170 ((uint32_t)0x00000400) /*!< Protects Sector 170 from program or erase */ 5209 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT171] Bits */ 5210 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171_OFS (11) /*!< PROT171 Bit Offset */ 5211 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171 ((uint32_t)0x00000800) /*!< Protects Sector 171 from program or erase */ 5212 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT172] Bits */ 5213 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172_OFS (12) /*!< PROT172 Bit Offset */ 5214 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172 ((uint32_t)0x00001000) /*!< Protects Sector 172 from program or erase */ 5215 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT173] Bits */ 5216 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173_OFS (13) /*!< PROT173 Bit Offset */ 5217 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173 ((uint32_t)0x00002000) /*!< Protects Sector 173 from program or erase */ 5218 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT174] Bits */ 5219 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174_OFS (14) /*!< PROT174 Bit Offset */ 5220 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174 ((uint32_t)0x00004000) /*!< Protects Sector 174 from program or erase */ 5221 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT175] Bits */ 5222 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175_OFS (15) /*!< PROT175 Bit Offset */ 5223 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175 ((uint32_t)0x00008000) /*!< Protects Sector 175 from program or erase */ 5224 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT176] Bits */ 5225 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176_OFS (16) /*!< PROT176 Bit Offset */ 5226 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176 ((uint32_t)0x00010000) /*!< Protects Sector 176 from program or erase */ 5227 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT177] Bits */ 5228 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177_OFS (17) /*!< PROT177 Bit Offset */ 5229 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177 ((uint32_t)0x00020000) /*!< Protects Sector 177 from program or erase */ 5230 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT178] Bits */ 5231 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178_OFS (18) /*!< PROT178 Bit Offset */ 5232 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178 ((uint32_t)0x00040000) /*!< Protects Sector 178 from program or erase */ 5233 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT179] Bits */ 5234 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179_OFS (19) /*!< PROT179 Bit Offset */ 5235 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179 ((uint32_t)0x00080000) /*!< Protects Sector 179 from program or erase */ 5236 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT180] Bits */ 5237 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180_OFS (20) /*!< PROT180 Bit Offset */ 5238 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180 ((uint32_t)0x00100000) /*!< Protects Sector 180 from program or erase */ 5239 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT181] Bits */ 5240 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181_OFS (21) /*!< PROT181 Bit Offset */ 5241 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181 ((uint32_t)0x00200000) /*!< Protects Sector 181 from program or erase */ 5242 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT182] Bits */ 5243 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182_OFS (22) /*!< PROT182 Bit Offset */ 5244 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182 ((uint32_t)0x00400000) /*!< Protects Sector 182 from program or erase */ 5245 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT183] Bits */ 5246 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183_OFS (23) /*!< PROT183 Bit Offset */ 5247 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183 ((uint32_t)0x00800000) /*!< Protects Sector 183 from program or erase */ 5248 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT184] Bits */ 5249 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184_OFS (24) /*!< PROT184 Bit Offset */ 5250 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184 ((uint32_t)0x01000000) /*!< Protects Sector 184 from program or erase */ 5251 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT185] Bits */ 5252 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185_OFS (25) /*!< PROT185 Bit Offset */ 5253 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185 ((uint32_t)0x02000000) /*!< Protects Sector 185 from program or erase */ 5254 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT186] Bits */ 5255 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186_OFS (26) /*!< PROT186 Bit Offset */ 5256 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186 ((uint32_t)0x04000000) /*!< Protects Sector 186 from program or erase */ 5257 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT187] Bits */ 5258 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187_OFS (27) /*!< PROT187 Bit Offset */ 5259 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187 ((uint32_t)0x08000000) /*!< Protects Sector 187 from program or erase */ 5260 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT188] Bits */ 5261 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188_OFS (28) /*!< PROT188 Bit Offset */ 5262 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188 ((uint32_t)0x10000000) /*!< Protects Sector 188 from program or erase */ 5263 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT189] Bits */ 5264 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189_OFS (29) /*!< PROT189 Bit Offset */ 5265 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189 ((uint32_t)0x20000000) /*!< Protects Sector 189 from program or erase */ 5266 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT190] Bits */ 5267 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190_OFS (30) /*!< PROT190 Bit Offset */ 5268 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190 ((uint32_t)0x40000000) /*!< Protects Sector 190 from program or erase */ 5269 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT191] Bits */ 5270 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191_OFS (31) /*!< PROT191 Bit Offset */ 5271 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191 ((uint32_t)0x80000000) /*!< Protects Sector 191 from program or erase */ 5272 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT192] Bits */ 5273 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192_OFS ( 0) /*!< PROT192 Bit Offset */ 5274 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192 ((uint32_t)0x00000001) /*!< Protects Sector 192 from program or erase */ 5275 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT193] Bits */ 5276 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193_OFS ( 1) /*!< PROT193 Bit Offset */ 5277 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193 ((uint32_t)0x00000002) /*!< Protects Sector 193 from program or erase */ 5278 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT194] Bits */ 5279 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194_OFS ( 2) /*!< PROT194 Bit Offset */ 5280 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194 ((uint32_t)0x00000004) /*!< Protects Sector 194 from program or erase */ 5281 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT195] Bits */ 5282 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195_OFS ( 3) /*!< PROT195 Bit Offset */ 5283 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195 ((uint32_t)0x00000008) /*!< Protects Sector 195 from program or erase */ 5284 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT196] Bits */ 5285 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196_OFS ( 4) /*!< PROT196 Bit Offset */ 5286 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196 ((uint32_t)0x00000010) /*!< Protects Sector 196 from program or erase */ 5287 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT197] Bits */ 5288 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197_OFS ( 5) /*!< PROT197 Bit Offset */ 5289 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197 ((uint32_t)0x00000020) /*!< Protects Sector 197 from program or erase */ 5290 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT198] Bits */ 5291 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198_OFS ( 6) /*!< PROT198 Bit Offset */ 5292 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198 ((uint32_t)0x00000040) /*!< Protects Sector 198 from program or erase */ 5293 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT199] Bits */ 5294 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199_OFS ( 7) /*!< PROT199 Bit Offset */ 5295 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199 ((uint32_t)0x00000080) /*!< Protects Sector 199 from program or erase */ 5296 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT200] Bits */ 5297 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200_OFS ( 8) /*!< PROT200 Bit Offset */ 5298 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200 ((uint32_t)0x00000100) /*!< Protects Sector 200 from program or erase */ 5299 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT201] Bits */ 5300 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201_OFS ( 9) /*!< PROT201 Bit Offset */ 5301 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201 ((uint32_t)0x00000200) /*!< Protects Sector 201 from program or erase */ 5302 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT202] Bits */ 5303 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202_OFS (10) /*!< PROT202 Bit Offset */ 5304 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202 ((uint32_t)0x00000400) /*!< Protects Sector 202 from program or erase */ 5305 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT203] Bits */ 5306 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203_OFS (11) /*!< PROT203 Bit Offset */ 5307 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203 ((uint32_t)0x00000800) /*!< Protects Sector 203 from program or erase */ 5308 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT204] Bits */ 5309 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204_OFS (12) /*!< PROT204 Bit Offset */ 5310 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204 ((uint32_t)0x00001000) /*!< Protects Sector 204 from program or erase */ 5311 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT205] Bits */ 5312 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205_OFS (13) /*!< PROT205 Bit Offset */ 5313 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205 ((uint32_t)0x00002000) /*!< Protects Sector 205 from program or erase */ 5314 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT206] Bits */ 5315 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206_OFS (14) /*!< PROT206 Bit Offset */ 5316 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206 ((uint32_t)0x00004000) /*!< Protects Sector 206 from program or erase */ 5317 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT207] Bits */ 5318 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207_OFS (15) /*!< PROT207 Bit Offset */ 5319 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207 ((uint32_t)0x00008000) /*!< Protects Sector 207 from program or erase */ 5320 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT208] Bits */ 5321 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208_OFS (16) /*!< PROT208 Bit Offset */ 5322 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208 ((uint32_t)0x00010000) /*!< Protects Sector 208 from program or erase */ 5323 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT209] Bits */ 5324 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209_OFS (17) /*!< PROT209 Bit Offset */ 5325 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209 ((uint32_t)0x00020000) /*!< Protects Sector 209 from program or erase */ 5326 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT210] Bits */ 5327 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210_OFS (18) /*!< PROT210 Bit Offset */ 5328 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210 ((uint32_t)0x00040000) /*!< Protects Sector 210 from program or erase */ 5329 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT211] Bits */ 5330 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211_OFS (19) /*!< PROT211 Bit Offset */ 5331 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211 ((uint32_t)0x00080000) /*!< Protects Sector 211 from program or erase */ 5332 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT212] Bits */ 5333 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212_OFS (20) /*!< PROT212 Bit Offset */ 5334 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212 ((uint32_t)0x00100000) /*!< Protects Sector 212 from program or erase */ 5335 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT213] Bits */ 5336 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213_OFS (21) /*!< PROT213 Bit Offset */ 5337 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213 ((uint32_t)0x00200000) /*!< Protects Sector 213 from program or erase */ 5338 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT214] Bits */ 5339 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214_OFS (22) /*!< PROT214 Bit Offset */ 5340 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214 ((uint32_t)0x00400000) /*!< Protects Sector 214 from program or erase */ 5341 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT215] Bits */ 5342 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215_OFS (23) /*!< PROT215 Bit Offset */ 5343 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215 ((uint32_t)0x00800000) /*!< Protects Sector 215 from program or erase */ 5344 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT216] Bits */ 5345 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216_OFS (24) /*!< PROT216 Bit Offset */ 5346 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216 ((uint32_t)0x01000000) /*!< Protects Sector 216 from program or erase */ 5347 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT217] Bits */ 5348 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217_OFS (25) /*!< PROT217 Bit Offset */ 5349 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217 ((uint32_t)0x02000000) /*!< Protects Sector 217 from program or erase */ 5350 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT218] Bits */ 5351 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218_OFS (26) /*!< PROT218 Bit Offset */ 5352 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218 ((uint32_t)0x04000000) /*!< Protects Sector 218 from program or erase */ 5353 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT219] Bits */ 5354 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219_OFS (27) /*!< PROT219 Bit Offset */ 5355 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219 ((uint32_t)0x08000000) /*!< Protects Sector 219 from program or erase */ 5356 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT220] Bits */ 5357 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220_OFS (28) /*!< PROT220 Bit Offset */ 5358 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220 ((uint32_t)0x10000000) /*!< Protects Sector 220 from program or erase */ 5359 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT221] Bits */ 5360 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221_OFS (29) /*!< PROT221 Bit Offset */ 5361 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221 ((uint32_t)0x20000000) /*!< Protects Sector 221 from program or erase */ 5362 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT222] Bits */ 5363 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222_OFS (30) /*!< PROT222 Bit Offset */ 5364 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222 ((uint32_t)0x40000000) /*!< Protects Sector 222 from program or erase */ 5365 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT223] Bits */ 5366 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223_OFS (31) /*!< PROT223 Bit Offset */ 5367 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223 ((uint32_t)0x80000000) /*!< Protects Sector 223 from program or erase */ 5368 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT224] Bits */ 5369 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224_OFS ( 0) /*!< PROT224 Bit Offset */ 5370 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224 ((uint32_t)0x00000001) /*!< Protects Sector 224 from program or erase */ 5371 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT225] Bits */ 5372 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225_OFS ( 1) /*!< PROT225 Bit Offset */ 5373 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225 ((uint32_t)0x00000002) /*!< Protects Sector 225 from program or erase */ 5374 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT226] Bits */ 5375 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226_OFS ( 2) /*!< PROT226 Bit Offset */ 5376 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226 ((uint32_t)0x00000004) /*!< Protects Sector 226 from program or erase */ 5377 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT227] Bits */ 5378 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227_OFS ( 3) /*!< PROT227 Bit Offset */ 5379 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227 ((uint32_t)0x00000008) /*!< Protects Sector 227 from program or erase */ 5380 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT228] Bits */ 5381 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228_OFS ( 4) /*!< PROT228 Bit Offset */ 5382 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228 ((uint32_t)0x00000010) /*!< Protects Sector 228 from program or erase */ 5383 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT229] Bits */ 5384 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229_OFS ( 5) /*!< PROT229 Bit Offset */ 5385 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229 ((uint32_t)0x00000020) /*!< Protects Sector 229 from program or erase */ 5386 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT230] Bits */ 5387 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230_OFS ( 6) /*!< PROT230 Bit Offset */ 5388 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230 ((uint32_t)0x00000040) /*!< Protects Sector 230 from program or erase */ 5389 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT231] Bits */ 5390 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231_OFS ( 7) /*!< PROT231 Bit Offset */ 5391 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231 ((uint32_t)0x00000080) /*!< Protects Sector 231 from program or erase */ 5392 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT232] Bits */ 5393 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232_OFS ( 8) /*!< PROT232 Bit Offset */ 5394 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232 ((uint32_t)0x00000100) /*!< Protects Sector 232 from program or erase */ 5395 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT233] Bits */ 5396 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233_OFS ( 9) /*!< PROT233 Bit Offset */ 5397 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233 ((uint32_t)0x00000200) /*!< Protects Sector 233 from program or erase */ 5398 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT234] Bits */ 5399 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234_OFS (10) /*!< PROT234 Bit Offset */ 5400 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234 ((uint32_t)0x00000400) /*!< Protects Sector 234 from program or erase */ 5401 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT235] Bits */ 5402 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235_OFS (11) /*!< PROT235 Bit Offset */ 5403 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235 ((uint32_t)0x00000800) /*!< Protects Sector 235 from program or erase */ 5404 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT236] Bits */ 5405 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236_OFS (12) /*!< PROT236 Bit Offset */ 5406 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236 ((uint32_t)0x00001000) /*!< Protects Sector 236 from program or erase */ 5407 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT237] Bits */ 5408 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237_OFS (13) /*!< PROT237 Bit Offset */ 5409 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237 ((uint32_t)0x00002000) /*!< Protects Sector 237 from program or erase */ 5410 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT238] Bits */ 5411 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238_OFS (14) /*!< PROT238 Bit Offset */ 5412 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238 ((uint32_t)0x00004000) /*!< Protects Sector 238 from program or erase */ 5413 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT239] Bits */ 5414 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239_OFS (15) /*!< PROT239 Bit Offset */ 5415 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239 ((uint32_t)0x00008000) /*!< Protects Sector 239 from program or erase */ 5416 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT240] Bits */ 5417 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240_OFS (16) /*!< PROT240 Bit Offset */ 5418 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240 ((uint32_t)0x00010000) /*!< Protects Sector 240 from program or erase */ 5419 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT241] Bits */ 5420 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241_OFS (17) /*!< PROT241 Bit Offset */ 5421 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241 ((uint32_t)0x00020000) /*!< Protects Sector 241 from program or erase */ 5422 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT242] Bits */ 5423 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242_OFS (18) /*!< PROT242 Bit Offset */ 5424 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242 ((uint32_t)0x00040000) /*!< Protects Sector 242 from program or erase */ 5425 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT243] Bits */ 5426 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243_OFS (19) /*!< PROT243 Bit Offset */ 5427 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243 ((uint32_t)0x00080000) /*!< Protects Sector 243 from program or erase */ 5428 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT244] Bits */ 5429 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244_OFS (20) /*!< PROT244 Bit Offset */ 5430 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244 ((uint32_t)0x00100000) /*!< Protects Sector 244 from program or erase */ 5431 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT245] Bits */ 5432 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245_OFS (21) /*!< PROT245 Bit Offset */ 5433 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245 ((uint32_t)0x00200000) /*!< Protects Sector 245 from program or erase */ 5434 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT246] Bits */ 5435 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246_OFS (22) /*!< PROT246 Bit Offset */ 5436 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246 ((uint32_t)0x00400000) /*!< Protects Sector 246 from program or erase */ 5437 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT247] Bits */ 5438 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247_OFS (23) /*!< PROT247 Bit Offset */ 5439 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247 ((uint32_t)0x00800000) /*!< Protects Sector 247 from program or erase */ 5440 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT248] Bits */ 5441 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248_OFS (24) /*!< PROT248 Bit Offset */ 5442 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248 ((uint32_t)0x01000000) /*!< Protects Sector 248 from program or erase */ 5443 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT249] Bits */ 5444 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249_OFS (25) /*!< PROT249 Bit Offset */ 5445 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249 ((uint32_t)0x02000000) /*!< Protects Sector 249 from program or erase */ 5446 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT250] Bits */ 5447 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250_OFS (26) /*!< PROT250 Bit Offset */ 5448 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250 ((uint32_t)0x04000000) /*!< Protects Sector 250 from program or erase */ 5449 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT251] Bits */ 5450 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251_OFS (27) /*!< PROT251 Bit Offset */ 5451 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251 ((uint32_t)0x08000000) /*!< Protects Sector 251 from program or erase */ 5452 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT252] Bits */ 5453 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252_OFS (28) /*!< PROT252 Bit Offset */ 5454 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252 ((uint32_t)0x10000000) /*!< Protects Sector 252 from program or erase */ 5455 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT253] Bits */ 5456 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253_OFS (29) /*!< PROT253 Bit Offset */ 5457 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253 ((uint32_t)0x20000000) /*!< Protects Sector 253 from program or erase */ 5458 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT254] Bits */ 5459 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254_OFS (30) /*!< PROT254 Bit Offset */ 5460 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254 ((uint32_t)0x40000000) /*!< Protects Sector 254 from program or erase */ 5461 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT255] Bits */ 5462 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255_OFS (31) /*!< PROT255 Bit Offset */ 5463 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255 ((uint32_t)0x80000000) /*!< Protects Sector 255 from program or erase */ 5464 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT0] Bits */ 5465 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 5466 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ 5467 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT1] Bits */ 5468 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 5469 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ 5470 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT2] Bits */ 5471 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ 5472 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ 5473 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT3] Bits */ 5474 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ 5475 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ 5476 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT4] Bits */ 5477 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ 5478 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ 5479 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT5] Bits */ 5480 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ 5481 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ 5482 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT6] Bits */ 5483 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ 5484 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ 5485 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT7] Bits */ 5486 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ 5487 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ 5488 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT8] Bits */ 5489 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ 5490 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ 5491 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT9] Bits */ 5492 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ 5493 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ 5494 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT10] Bits */ 5495 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10_OFS (10) /*!< PROT10 Bit Offset */ 5496 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ 5497 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT11] Bits */ 5498 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11_OFS (11) /*!< PROT11 Bit Offset */ 5499 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ 5500 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT12] Bits */ 5501 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12_OFS (12) /*!< PROT12 Bit Offset */ 5502 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ 5503 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT13] Bits */ 5504 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13_OFS (13) /*!< PROT13 Bit Offset */ 5505 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ 5506 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT14] Bits */ 5507 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14_OFS (14) /*!< PROT14 Bit Offset */ 5508 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ 5509 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT15] Bits */ 5510 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15_OFS (15) /*!< PROT15 Bit Offset */ 5511 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ 5512 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT16] Bits */ 5513 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16_OFS (16) /*!< PROT16 Bit Offset */ 5514 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ 5515 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT17] Bits */ 5516 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17_OFS (17) /*!< PROT17 Bit Offset */ 5517 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ 5518 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT18] Bits */ 5519 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18_OFS (18) /*!< PROT18 Bit Offset */ 5520 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ 5521 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT19] Bits */ 5522 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19_OFS (19) /*!< PROT19 Bit Offset */ 5523 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ 5524 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT20] Bits */ 5525 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20_OFS (20) /*!< PROT20 Bit Offset */ 5526 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ 5527 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT21] Bits */ 5528 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21_OFS (21) /*!< PROT21 Bit Offset */ 5529 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ 5530 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT22] Bits */ 5531 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22_OFS (22) /*!< PROT22 Bit Offset */ 5532 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ 5533 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT23] Bits */ 5534 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23_OFS (23) /*!< PROT23 Bit Offset */ 5535 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ 5536 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT24] Bits */ 5537 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24_OFS (24) /*!< PROT24 Bit Offset */ 5538 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ 5539 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT25] Bits */ 5540 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25_OFS (25) /*!< PROT25 Bit Offset */ 5541 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ 5542 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT26] Bits */ 5543 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26_OFS (26) /*!< PROT26 Bit Offset */ 5544 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ 5545 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT27] Bits */ 5546 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27_OFS (27) /*!< PROT27 Bit Offset */ 5547 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ 5548 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT28] Bits */ 5549 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28_OFS (28) /*!< PROT28 Bit Offset */ 5550 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ 5551 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT29] Bits */ 5552 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29_OFS (29) /*!< PROT29 Bit Offset */ 5553 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ 5554 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT30] Bits */ 5555 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30_OFS (30) /*!< PROT30 Bit Offset */ 5556 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ 5557 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT31] Bits */ 5558 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31_OFS (31) /*!< PROT31 Bit Offset */ 5559 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ 5560 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT32] Bits */ 5561 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32_OFS ( 0) /*!< PROT32 Bit Offset */ 5562 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32 ((uint32_t)0x00000001) /*!< Protects Sector 32 from program or erase */ 5563 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT33] Bits */ 5564 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33_OFS ( 1) /*!< PROT33 Bit Offset */ 5565 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33 ((uint32_t)0x00000002) /*!< Protects Sector 33 from program or erase */ 5566 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT34] Bits */ 5567 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34_OFS ( 2) /*!< PROT34 Bit Offset */ 5568 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34 ((uint32_t)0x00000004) /*!< Protects Sector 34 from program or erase */ 5569 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT35] Bits */ 5570 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35_OFS ( 3) /*!< PROT35 Bit Offset */ 5571 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35 ((uint32_t)0x00000008) /*!< Protects Sector 35 from program or erase */ 5572 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT36] Bits */ 5573 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36_OFS ( 4) /*!< PROT36 Bit Offset */ 5574 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36 ((uint32_t)0x00000010) /*!< Protects Sector 36 from program or erase */ 5575 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT37] Bits */ 5576 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37_OFS ( 5) /*!< PROT37 Bit Offset */ 5577 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37 ((uint32_t)0x00000020) /*!< Protects Sector 37 from program or erase */ 5578 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT38] Bits */ 5579 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38_OFS ( 6) /*!< PROT38 Bit Offset */ 5580 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38 ((uint32_t)0x00000040) /*!< Protects Sector 38 from program or erase */ 5581 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT39] Bits */ 5582 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39_OFS ( 7) /*!< PROT39 Bit Offset */ 5583 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39 ((uint32_t)0x00000080) /*!< Protects Sector 39 from program or erase */ 5584 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT40] Bits */ 5585 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40_OFS ( 8) /*!< PROT40 Bit Offset */ 5586 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40 ((uint32_t)0x00000100) /*!< Protects Sector 40 from program or erase */ 5587 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT41] Bits */ 5588 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41_OFS ( 9) /*!< PROT41 Bit Offset */ 5589 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41 ((uint32_t)0x00000200) /*!< Protects Sector 41 from program or erase */ 5590 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT42] Bits */ 5591 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42_OFS (10) /*!< PROT42 Bit Offset */ 5592 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42 ((uint32_t)0x00000400) /*!< Protects Sector 42 from program or erase */ 5593 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT43] Bits */ 5594 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43_OFS (11) /*!< PROT43 Bit Offset */ 5595 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43 ((uint32_t)0x00000800) /*!< Protects Sector 43 from program or erase */ 5596 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT44] Bits */ 5597 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44_OFS (12) /*!< PROT44 Bit Offset */ 5598 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44 ((uint32_t)0x00001000) /*!< Protects Sector 44 from program or erase */ 5599 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT45] Bits */ 5600 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45_OFS (13) /*!< PROT45 Bit Offset */ 5601 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45 ((uint32_t)0x00002000) /*!< Protects Sector 45 from program or erase */ 5602 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT46] Bits */ 5603 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46_OFS (14) /*!< PROT46 Bit Offset */ 5604 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46 ((uint32_t)0x00004000) /*!< Protects Sector 46 from program or erase */ 5605 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT47] Bits */ 5606 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47_OFS (15) /*!< PROT47 Bit Offset */ 5607 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47 ((uint32_t)0x00008000) /*!< Protects Sector 47 from program or erase */ 5608 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT48] Bits */ 5609 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48_OFS (16) /*!< PROT48 Bit Offset */ 5610 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48 ((uint32_t)0x00010000) /*!< Protects Sector 48 from program or erase */ 5611 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT49] Bits */ 5612 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49_OFS (17) /*!< PROT49 Bit Offset */ 5613 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49 ((uint32_t)0x00020000) /*!< Protects Sector 49 from program or erase */ 5614 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT50] Bits */ 5615 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50_OFS (18) /*!< PROT50 Bit Offset */ 5616 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50 ((uint32_t)0x00040000) /*!< Protects Sector 50 from program or erase */ 5617 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT51] Bits */ 5618 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51_OFS (19) /*!< PROT51 Bit Offset */ 5619 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51 ((uint32_t)0x00080000) /*!< Protects Sector 51 from program or erase */ 5620 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT52] Bits */ 5621 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52_OFS (20) /*!< PROT52 Bit Offset */ 5622 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52 ((uint32_t)0x00100000) /*!< Protects Sector 52 from program or erase */ 5623 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT53] Bits */ 5624 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53_OFS (21) /*!< PROT53 Bit Offset */ 5625 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53 ((uint32_t)0x00200000) /*!< Protects Sector 53 from program or erase */ 5626 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT54] Bits */ 5627 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54_OFS (22) /*!< PROT54 Bit Offset */ 5628 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54 ((uint32_t)0x00400000) /*!< Protects Sector 54 from program or erase */ 5629 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT55] Bits */ 5630 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55_OFS (23) /*!< PROT55 Bit Offset */ 5631 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55 ((uint32_t)0x00800000) /*!< Protects Sector 55 from program or erase */ 5632 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT56] Bits */ 5633 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56_OFS (24) /*!< PROT56 Bit Offset */ 5634 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56 ((uint32_t)0x01000000) /*!< Protects Sector 56 from program or erase */ 5635 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT57] Bits */ 5636 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57_OFS (25) /*!< PROT57 Bit Offset */ 5637 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57 ((uint32_t)0x02000000) /*!< Protects Sector 57 from program or erase */ 5638 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT58] Bits */ 5639 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58_OFS (26) /*!< PROT58 Bit Offset */ 5640 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58 ((uint32_t)0x04000000) /*!< Protects Sector 58 from program or erase */ 5641 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT59] Bits */ 5642 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59_OFS (27) /*!< PROT59 Bit Offset */ 5643 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59 ((uint32_t)0x08000000) /*!< Protects Sector 59 from program or erase */ 5644 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT60] Bits */ 5645 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60_OFS (28) /*!< PROT60 Bit Offset */ 5646 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60 ((uint32_t)0x10000000) /*!< Protects Sector 60 from program or erase */ 5647 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT61] Bits */ 5648 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61_OFS (29) /*!< PROT61 Bit Offset */ 5649 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61 ((uint32_t)0x20000000) /*!< Protects Sector 61 from program or erase */ 5650 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT62] Bits */ 5651 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62_OFS (30) /*!< PROT62 Bit Offset */ 5652 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62 ((uint32_t)0x40000000) /*!< Protects Sector 62 from program or erase */ 5653 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT63] Bits */ 5654 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63_OFS (31) /*!< PROT63 Bit Offset */ 5655 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63 ((uint32_t)0x80000000) /*!< Protects Sector 63 from program or erase */ 5656 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT64] Bits */ 5657 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64_OFS ( 0) /*!< PROT64 Bit Offset */ 5658 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64 ((uint32_t)0x00000001) /*!< Protects Sector 64 from program or erase */ 5659 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT65] Bits */ 5660 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65_OFS ( 1) /*!< PROT65 Bit Offset */ 5661 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65 ((uint32_t)0x00000002) /*!< Protects Sector 65 from program or erase */ 5662 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT66] Bits */ 5663 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66_OFS ( 2) /*!< PROT66 Bit Offset */ 5664 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66 ((uint32_t)0x00000004) /*!< Protects Sector 66 from program or erase */ 5665 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT67] Bits */ 5666 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67_OFS ( 3) /*!< PROT67 Bit Offset */ 5667 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67 ((uint32_t)0x00000008) /*!< Protects Sector 67 from program or erase */ 5668 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT68] Bits */ 5669 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68_OFS ( 4) /*!< PROT68 Bit Offset */ 5670 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68 ((uint32_t)0x00000010) /*!< Protects Sector 68 from program or erase */ 5671 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT69] Bits */ 5672 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69_OFS ( 5) /*!< PROT69 Bit Offset */ 5673 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69 ((uint32_t)0x00000020) /*!< Protects Sector 69 from program or erase */ 5674 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT70] Bits */ 5675 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70_OFS ( 6) /*!< PROT70 Bit Offset */ 5676 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70 ((uint32_t)0x00000040) /*!< Protects Sector 70 from program or erase */ 5677 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT71] Bits */ 5678 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71_OFS ( 7) /*!< PROT71 Bit Offset */ 5679 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71 ((uint32_t)0x00000080) /*!< Protects Sector 71 from program or erase */ 5680 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT72] Bits */ 5681 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72_OFS ( 8) /*!< PROT72 Bit Offset */ 5682 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72 ((uint32_t)0x00000100) /*!< Protects Sector 72 from program or erase */ 5683 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT73] Bits */ 5684 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73_OFS ( 9) /*!< PROT73 Bit Offset */ 5685 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73 ((uint32_t)0x00000200) /*!< Protects Sector 73 from program or erase */ 5686 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT74] Bits */ 5687 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74_OFS (10) /*!< PROT74 Bit Offset */ 5688 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74 ((uint32_t)0x00000400) /*!< Protects Sector 74 from program or erase */ 5689 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT75] Bits */ 5690 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75_OFS (11) /*!< PROT75 Bit Offset */ 5691 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75 ((uint32_t)0x00000800) /*!< Protects Sector 75 from program or erase */ 5692 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT76] Bits */ 5693 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76_OFS (12) /*!< PROT76 Bit Offset */ 5694 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76 ((uint32_t)0x00001000) /*!< Protects Sector 76 from program or erase */ 5695 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT77] Bits */ 5696 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77_OFS (13) /*!< PROT77 Bit Offset */ 5697 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77 ((uint32_t)0x00002000) /*!< Protects Sector 77 from program or erase */ 5698 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT78] Bits */ 5699 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78_OFS (14) /*!< PROT78 Bit Offset */ 5700 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78 ((uint32_t)0x00004000) /*!< Protects Sector 78 from program or erase */ 5701 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT79] Bits */ 5702 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79_OFS (15) /*!< PROT79 Bit Offset */ 5703 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79 ((uint32_t)0x00008000) /*!< Protects Sector 79 from program or erase */ 5704 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT80] Bits */ 5705 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80_OFS (16) /*!< PROT80 Bit Offset */ 5706 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80 ((uint32_t)0x00010000) /*!< Protects Sector 80 from program or erase */ 5707 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT81] Bits */ 5708 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81_OFS (17) /*!< PROT81 Bit Offset */ 5709 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81 ((uint32_t)0x00020000) /*!< Protects Sector 81 from program or erase */ 5710 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT82] Bits */ 5711 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82_OFS (18) /*!< PROT82 Bit Offset */ 5712 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82 ((uint32_t)0x00040000) /*!< Protects Sector 82 from program or erase */ 5713 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT83] Bits */ 5714 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83_OFS (19) /*!< PROT83 Bit Offset */ 5715 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83 ((uint32_t)0x00080000) /*!< Protects Sector 83 from program or erase */ 5716 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT84] Bits */ 5717 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84_OFS (20) /*!< PROT84 Bit Offset */ 5718 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84 ((uint32_t)0x00100000) /*!< Protects Sector 84 from program or erase */ 5719 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT85] Bits */ 5720 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85_OFS (21) /*!< PROT85 Bit Offset */ 5721 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85 ((uint32_t)0x00200000) /*!< Protects Sector 85 from program or erase */ 5722 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT86] Bits */ 5723 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86_OFS (22) /*!< PROT86 Bit Offset */ 5724 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86 ((uint32_t)0x00400000) /*!< Protects Sector 86 from program or erase */ 5725 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT87] Bits */ 5726 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87_OFS (23) /*!< PROT87 Bit Offset */ 5727 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87 ((uint32_t)0x00800000) /*!< Protects Sector 87 from program or erase */ 5728 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT88] Bits */ 5729 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88_OFS (24) /*!< PROT88 Bit Offset */ 5730 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88 ((uint32_t)0x01000000) /*!< Protects Sector 88 from program or erase */ 5731 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT89] Bits */ 5732 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89_OFS (25) /*!< PROT89 Bit Offset */ 5733 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89 ((uint32_t)0x02000000) /*!< Protects Sector 89 from program or erase */ 5734 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT90] Bits */ 5735 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90_OFS (26) /*!< PROT90 Bit Offset */ 5736 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90 ((uint32_t)0x04000000) /*!< Protects Sector 90 from program or erase */ 5737 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT91] Bits */ 5738 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91_OFS (27) /*!< PROT91 Bit Offset */ 5739 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91 ((uint32_t)0x08000000) /*!< Protects Sector 91 from program or erase */ 5740 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT92] Bits */ 5741 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92_OFS (28) /*!< PROT92 Bit Offset */ 5742 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92 ((uint32_t)0x10000000) /*!< Protects Sector 92 from program or erase */ 5743 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT93] Bits */ 5744 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93_OFS (29) /*!< PROT93 Bit Offset */ 5745 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93 ((uint32_t)0x20000000) /*!< Protects Sector 93 from program or erase */ 5746 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT94] Bits */ 5747 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94_OFS (30) /*!< PROT94 Bit Offset */ 5748 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94 ((uint32_t)0x40000000) /*!< Protects Sector 94 from program or erase */ 5749 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT95] Bits */ 5750 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95_OFS (31) /*!< PROT95 Bit Offset */ 5751 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95 ((uint32_t)0x80000000) /*!< Protects Sector 95 from program or erase */ 5752 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT96] Bits */ 5753 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96_OFS ( 0) /*!< PROT96 Bit Offset */ 5754 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96 ((uint32_t)0x00000001) /*!< Protects Sector 96 from program or erase */ 5755 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT97] Bits */ 5756 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97_OFS ( 1) /*!< PROT97 Bit Offset */ 5757 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97 ((uint32_t)0x00000002) /*!< Protects Sector 97 from program or erase */ 5758 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT98] Bits */ 5759 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98_OFS ( 2) /*!< PROT98 Bit Offset */ 5760 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98 ((uint32_t)0x00000004) /*!< Protects Sector 98 from program or erase */ 5761 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT99] Bits */ 5762 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99_OFS ( 3) /*!< PROT99 Bit Offset */ 5763 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99 ((uint32_t)0x00000008) /*!< Protects Sector 99 from program or erase */ 5764 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT100] Bits */ 5765 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100_OFS ( 4) /*!< PROT100 Bit Offset */ 5766 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100 ((uint32_t)0x00000010) /*!< Protects Sector 100 from program or erase */ 5767 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT101] Bits */ 5768 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101_OFS ( 5) /*!< PROT101 Bit Offset */ 5769 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101 ((uint32_t)0x00000020) /*!< Protects Sector 101 from program or erase */ 5770 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT102] Bits */ 5771 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102_OFS ( 6) /*!< PROT102 Bit Offset */ 5772 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102 ((uint32_t)0x00000040) /*!< Protects Sector 102 from program or erase */ 5773 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT103] Bits */ 5774 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103_OFS ( 7) /*!< PROT103 Bit Offset */ 5775 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103 ((uint32_t)0x00000080) /*!< Protects Sector 103 from program or erase */ 5776 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT104] Bits */ 5777 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104_OFS ( 8) /*!< PROT104 Bit Offset */ 5778 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104 ((uint32_t)0x00000100) /*!< Protects Sector 104 from program or erase */ 5779 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT105] Bits */ 5780 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105_OFS ( 9) /*!< PROT105 Bit Offset */ 5781 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105 ((uint32_t)0x00000200) /*!< Protects Sector 105 from program or erase */ 5782 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT106] Bits */ 5783 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106_OFS (10) /*!< PROT106 Bit Offset */ 5784 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106 ((uint32_t)0x00000400) /*!< Protects Sector 106 from program or erase */ 5785 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT107] Bits */ 5786 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107_OFS (11) /*!< PROT107 Bit Offset */ 5787 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107 ((uint32_t)0x00000800) /*!< Protects Sector 107 from program or erase */ 5788 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT108] Bits */ 5789 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108_OFS (12) /*!< PROT108 Bit Offset */ 5790 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108 ((uint32_t)0x00001000) /*!< Protects Sector 108 from program or erase */ 5791 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT109] Bits */ 5792 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109_OFS (13) /*!< PROT109 Bit Offset */ 5793 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109 ((uint32_t)0x00002000) /*!< Protects Sector 109 from program or erase */ 5794 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT110] Bits */ 5795 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110_OFS (14) /*!< PROT110 Bit Offset */ 5796 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110 ((uint32_t)0x00004000) /*!< Protects Sector 110 from program or erase */ 5797 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT111] Bits */ 5798 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111_OFS (15) /*!< PROT111 Bit Offset */ 5799 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111 ((uint32_t)0x00008000) /*!< Protects Sector 111 from program or erase */ 5800 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT112] Bits */ 5801 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112_OFS (16) /*!< PROT112 Bit Offset */ 5802 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112 ((uint32_t)0x00010000) /*!< Protects Sector 112 from program or erase */ 5803 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT113] Bits */ 5804 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113_OFS (17) /*!< PROT113 Bit Offset */ 5805 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113 ((uint32_t)0x00020000) /*!< Protects Sector 113 from program or erase */ 5806 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT114] Bits */ 5807 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114_OFS (18) /*!< PROT114 Bit Offset */ 5808 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114 ((uint32_t)0x00040000) /*!< Protects Sector 114 from program or erase */ 5809 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT115] Bits */ 5810 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115_OFS (19) /*!< PROT115 Bit Offset */ 5811 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115 ((uint32_t)0x00080000) /*!< Protects Sector 115 from program or erase */ 5812 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT116] Bits */ 5813 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116_OFS (20) /*!< PROT116 Bit Offset */ 5814 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116 ((uint32_t)0x00100000) /*!< Protects Sector 116 from program or erase */ 5815 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT117] Bits */ 5816 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117_OFS (21) /*!< PROT117 Bit Offset */ 5817 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117 ((uint32_t)0x00200000) /*!< Protects Sector 117 from program or erase */ 5818 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT118] Bits */ 5819 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118_OFS (22) /*!< PROT118 Bit Offset */ 5820 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118 ((uint32_t)0x00400000) /*!< Protects Sector 118 from program or erase */ 5821 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT119] Bits */ 5822 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119_OFS (23) /*!< PROT119 Bit Offset */ 5823 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119 ((uint32_t)0x00800000) /*!< Protects Sector 119 from program or erase */ 5824 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT120] Bits */ 5825 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120_OFS (24) /*!< PROT120 Bit Offset */ 5826 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120 ((uint32_t)0x01000000) /*!< Protects Sector 120 from program or erase */ 5827 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT121] Bits */ 5828 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121_OFS (25) /*!< PROT121 Bit Offset */ 5829 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121 ((uint32_t)0x02000000) /*!< Protects Sector 121 from program or erase */ 5830 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT122] Bits */ 5831 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122_OFS (26) /*!< PROT122 Bit Offset */ 5832 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122 ((uint32_t)0x04000000) /*!< Protects Sector 122 from program or erase */ 5833 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT123] Bits */ 5834 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123_OFS (27) /*!< PROT123 Bit Offset */ 5835 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123 ((uint32_t)0x08000000) /*!< Protects Sector 123 from program or erase */ 5836 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT124] Bits */ 5837 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124_OFS (28) /*!< PROT124 Bit Offset */ 5838 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124 ((uint32_t)0x10000000) /*!< Protects Sector 124 from program or erase */ 5839 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT125] Bits */ 5840 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125_OFS (29) /*!< PROT125 Bit Offset */ 5841 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125 ((uint32_t)0x20000000) /*!< Protects Sector 125 from program or erase */ 5842 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT126] Bits */ 5843 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126_OFS (30) /*!< PROT126 Bit Offset */ 5844 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126 ((uint32_t)0x40000000) /*!< Protects Sector 126 from program or erase */ 5845 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT127] Bits */ 5846 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127_OFS (31) /*!< PROT127 Bit Offset */ 5847 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127 ((uint32_t)0x80000000) /*!< Protects Sector 127 from program or erase */ 5848 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT128] Bits */ 5849 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128_OFS ( 0) /*!< PROT128 Bit Offset */ 5850 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128 ((uint32_t)0x00000001) /*!< Protects Sector 128 from program or erase */ 5851 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT129] Bits */ 5852 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129_OFS ( 1) /*!< PROT129 Bit Offset */ 5853 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129 ((uint32_t)0x00000002) /*!< Protects Sector 129 from program or erase */ 5854 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT130] Bits */ 5855 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130_OFS ( 2) /*!< PROT130 Bit Offset */ 5856 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130 ((uint32_t)0x00000004) /*!< Protects Sector 130 from program or erase */ 5857 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT131] Bits */ 5858 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131_OFS ( 3) /*!< PROT131 Bit Offset */ 5859 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131 ((uint32_t)0x00000008) /*!< Protects Sector 131 from program or erase */ 5860 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT132] Bits */ 5861 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132_OFS ( 4) /*!< PROT132 Bit Offset */ 5862 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132 ((uint32_t)0x00000010) /*!< Protects Sector 132 from program or erase */ 5863 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT133] Bits */ 5864 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133_OFS ( 5) /*!< PROT133 Bit Offset */ 5865 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133 ((uint32_t)0x00000020) /*!< Protects Sector 133 from program or erase */ 5866 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT134] Bits */ 5867 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134_OFS ( 6) /*!< PROT134 Bit Offset */ 5868 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134 ((uint32_t)0x00000040) /*!< Protects Sector 134 from program or erase */ 5869 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT135] Bits */ 5870 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135_OFS ( 7) /*!< PROT135 Bit Offset */ 5871 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135 ((uint32_t)0x00000080) /*!< Protects Sector 135 from program or erase */ 5872 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT136] Bits */ 5873 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136_OFS ( 8) /*!< PROT136 Bit Offset */ 5874 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136 ((uint32_t)0x00000100) /*!< Protects Sector 136 from program or erase */ 5875 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT137] Bits */ 5876 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137_OFS ( 9) /*!< PROT137 Bit Offset */ 5877 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137 ((uint32_t)0x00000200) /*!< Protects Sector 137 from program or erase */ 5878 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT138] Bits */ 5879 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138_OFS (10) /*!< PROT138 Bit Offset */ 5880 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138 ((uint32_t)0x00000400) /*!< Protects Sector 138 from program or erase */ 5881 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT139] Bits */ 5882 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139_OFS (11) /*!< PROT139 Bit Offset */ 5883 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139 ((uint32_t)0x00000800) /*!< Protects Sector 139 from program or erase */ 5884 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT140] Bits */ 5885 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140_OFS (12) /*!< PROT140 Bit Offset */ 5886 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140 ((uint32_t)0x00001000) /*!< Protects Sector 140 from program or erase */ 5887 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT141] Bits */ 5888 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141_OFS (13) /*!< PROT141 Bit Offset */ 5889 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141 ((uint32_t)0x00002000) /*!< Protects Sector 141 from program or erase */ 5890 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT142] Bits */ 5891 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142_OFS (14) /*!< PROT142 Bit Offset */ 5892 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142 ((uint32_t)0x00004000) /*!< Protects Sector 142 from program or erase */ 5893 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT143] Bits */ 5894 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143_OFS (15) /*!< PROT143 Bit Offset */ 5895 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143 ((uint32_t)0x00008000) /*!< Protects Sector 143 from program or erase */ 5896 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT144] Bits */ 5897 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144_OFS (16) /*!< PROT144 Bit Offset */ 5898 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144 ((uint32_t)0x00010000) /*!< Protects Sector 144 from program or erase */ 5899 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT145] Bits */ 5900 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145_OFS (17) /*!< PROT145 Bit Offset */ 5901 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145 ((uint32_t)0x00020000) /*!< Protects Sector 145 from program or erase */ 5902 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT146] Bits */ 5903 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146_OFS (18) /*!< PROT146 Bit Offset */ 5904 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146 ((uint32_t)0x00040000) /*!< Protects Sector 146 from program or erase */ 5905 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT147] Bits */ 5906 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147_OFS (19) /*!< PROT147 Bit Offset */ 5907 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147 ((uint32_t)0x00080000) /*!< Protects Sector 147 from program or erase */ 5908 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT148] Bits */ 5909 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148_OFS (20) /*!< PROT148 Bit Offset */ 5910 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148 ((uint32_t)0x00100000) /*!< Protects Sector 148 from program or erase */ 5911 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT149] Bits */ 5912 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149_OFS (21) /*!< PROT149 Bit Offset */ 5913 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149 ((uint32_t)0x00200000) /*!< Protects Sector 149 from program or erase */ 5914 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT150] Bits */ 5915 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150_OFS (22) /*!< PROT150 Bit Offset */ 5916 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150 ((uint32_t)0x00400000) /*!< Protects Sector 150 from program or erase */ 5917 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT151] Bits */ 5918 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151_OFS (23) /*!< PROT151 Bit Offset */ 5919 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151 ((uint32_t)0x00800000) /*!< Protects Sector 151 from program or erase */ 5920 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT152] Bits */ 5921 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152_OFS (24) /*!< PROT152 Bit Offset */ 5922 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152 ((uint32_t)0x01000000) /*!< Protects Sector 152 from program or erase */ 5923 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT153] Bits */ 5924 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153_OFS (25) /*!< PROT153 Bit Offset */ 5925 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153 ((uint32_t)0x02000000) /*!< Protects Sector 153 from program or erase */ 5926 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT154] Bits */ 5927 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154_OFS (26) /*!< PROT154 Bit Offset */ 5928 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154 ((uint32_t)0x04000000) /*!< Protects Sector 154 from program or erase */ 5929 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT155] Bits */ 5930 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155_OFS (27) /*!< PROT155 Bit Offset */ 5931 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155 ((uint32_t)0x08000000) /*!< Protects Sector 155 from program or erase */ 5932 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT156] Bits */ 5933 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156_OFS (28) /*!< PROT156 Bit Offset */ 5934 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156 ((uint32_t)0x10000000) /*!< Protects Sector 156 from program or erase */ 5935 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT157] Bits */ 5936 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157_OFS (29) /*!< PROT157 Bit Offset */ 5937 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157 ((uint32_t)0x20000000) /*!< Protects Sector 157 from program or erase */ 5938 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT158] Bits */ 5939 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158_OFS (30) /*!< PROT158 Bit Offset */ 5940 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158 ((uint32_t)0x40000000) /*!< Protects Sector 158 from program or erase */ 5941 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT159] Bits */ 5942 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159_OFS (31) /*!< PROT159 Bit Offset */ 5943 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159 ((uint32_t)0x80000000) /*!< Protects Sector 159 from program or erase */ 5944 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT160] Bits */ 5945 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160_OFS ( 0) /*!< PROT160 Bit Offset */ 5946 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160 ((uint32_t)0x00000001) /*!< Protects Sector 160 from program or erase */ 5947 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT161] Bits */ 5948 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161_OFS ( 1) /*!< PROT161 Bit Offset */ 5949 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161 ((uint32_t)0x00000002) /*!< Protects Sector 161 from program or erase */ 5950 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT162] Bits */ 5951 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162_OFS ( 2) /*!< PROT162 Bit Offset */ 5952 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162 ((uint32_t)0x00000004) /*!< Protects Sector 162 from program or erase */ 5953 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT163] Bits */ 5954 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163_OFS ( 3) /*!< PROT163 Bit Offset */ 5955 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163 ((uint32_t)0x00000008) /*!< Protects Sector 163 from program or erase */ 5956 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT164] Bits */ 5957 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164_OFS ( 4) /*!< PROT164 Bit Offset */ 5958 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164 ((uint32_t)0x00000010) /*!< Protects Sector 164 from program or erase */ 5959 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT165] Bits */ 5960 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165_OFS ( 5) /*!< PROT165 Bit Offset */ 5961 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165 ((uint32_t)0x00000020) /*!< Protects Sector 165 from program or erase */ 5962 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT166] Bits */ 5963 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166_OFS ( 6) /*!< PROT166 Bit Offset */ 5964 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166 ((uint32_t)0x00000040) /*!< Protects Sector 166 from program or erase */ 5965 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT167] Bits */ 5966 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167_OFS ( 7) /*!< PROT167 Bit Offset */ 5967 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167 ((uint32_t)0x00000080) /*!< Protects Sector 167 from program or erase */ 5968 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT168] Bits */ 5969 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168_OFS ( 8) /*!< PROT168 Bit Offset */ 5970 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168 ((uint32_t)0x00000100) /*!< Protects Sector 168 from program or erase */ 5971 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT169] Bits */ 5972 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169_OFS ( 9) /*!< PROT169 Bit Offset */ 5973 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169 ((uint32_t)0x00000200) /*!< Protects Sector 169 from program or erase */ 5974 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT170] Bits */ 5975 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170_OFS (10) /*!< PROT170 Bit Offset */ 5976 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170 ((uint32_t)0x00000400) /*!< Protects Sector 170 from program or erase */ 5977 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT171] Bits */ 5978 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171_OFS (11) /*!< PROT171 Bit Offset */ 5979 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171 ((uint32_t)0x00000800) /*!< Protects Sector 171 from program or erase */ 5980 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT172] Bits */ 5981 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172_OFS (12) /*!< PROT172 Bit Offset */ 5982 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172 ((uint32_t)0x00001000) /*!< Protects Sector 172 from program or erase */ 5983 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT173] Bits */ 5984 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173_OFS (13) /*!< PROT173 Bit Offset */ 5985 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173 ((uint32_t)0x00002000) /*!< Protects Sector 173 from program or erase */ 5986 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT174] Bits */ 5987 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174_OFS (14) /*!< PROT174 Bit Offset */ 5988 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174 ((uint32_t)0x00004000) /*!< Protects Sector 174 from program or erase */ 5989 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT175] Bits */ 5990 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175_OFS (15) /*!< PROT175 Bit Offset */ 5991 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175 ((uint32_t)0x00008000) /*!< Protects Sector 175 from program or erase */ 5992 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT176] Bits */ 5993 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176_OFS (16) /*!< PROT176 Bit Offset */ 5994 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176 ((uint32_t)0x00010000) /*!< Protects Sector 176 from program or erase */ 5995 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT177] Bits */ 5996 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177_OFS (17) /*!< PROT177 Bit Offset */ 5997 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177 ((uint32_t)0x00020000) /*!< Protects Sector 177 from program or erase */ 5998 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT178] Bits */ 5999 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178_OFS (18) /*!< PROT178 Bit Offset */ 6000 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178 ((uint32_t)0x00040000) /*!< Protects Sector 178 from program or erase */ 6001 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT179] Bits */ 6002 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179_OFS (19) /*!< PROT179 Bit Offset */ 6003 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179 ((uint32_t)0x00080000) /*!< Protects Sector 179 from program or erase */ 6004 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT180] Bits */ 6005 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180_OFS (20) /*!< PROT180 Bit Offset */ 6006 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180 ((uint32_t)0x00100000) /*!< Protects Sector 180 from program or erase */ 6007 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT181] Bits */ 6008 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181_OFS (21) /*!< PROT181 Bit Offset */ 6009 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181 ((uint32_t)0x00200000) /*!< Protects Sector 181 from program or erase */ 6010 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT182] Bits */ 6011 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182_OFS (22) /*!< PROT182 Bit Offset */ 6012 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182 ((uint32_t)0x00400000) /*!< Protects Sector 182 from program or erase */ 6013 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT183] Bits */ 6014 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183_OFS (23) /*!< PROT183 Bit Offset */ 6015 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183 ((uint32_t)0x00800000) /*!< Protects Sector 183 from program or erase */ 6016 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT184] Bits */ 6017 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184_OFS (24) /*!< PROT184 Bit Offset */ 6018 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184 ((uint32_t)0x01000000) /*!< Protects Sector 184 from program or erase */ 6019 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT185] Bits */ 6020 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185_OFS (25) /*!< PROT185 Bit Offset */ 6021 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185 ((uint32_t)0x02000000) /*!< Protects Sector 185 from program or erase */ 6022 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT186] Bits */ 6023 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186_OFS (26) /*!< PROT186 Bit Offset */ 6024 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186 ((uint32_t)0x04000000) /*!< Protects Sector 186 from program or erase */ 6025 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT187] Bits */ 6026 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187_OFS (27) /*!< PROT187 Bit Offset */ 6027 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187 ((uint32_t)0x08000000) /*!< Protects Sector 187 from program or erase */ 6028 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT188] Bits */ 6029 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188_OFS (28) /*!< PROT188 Bit Offset */ 6030 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188 ((uint32_t)0x10000000) /*!< Protects Sector 188 from program or erase */ 6031 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT189] Bits */ 6032 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189_OFS (29) /*!< PROT189 Bit Offset */ 6033 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189 ((uint32_t)0x20000000) /*!< Protects Sector 189 from program or erase */ 6034 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT190] Bits */ 6035 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190_OFS (30) /*!< PROT190 Bit Offset */ 6036 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190 ((uint32_t)0x40000000) /*!< Protects Sector 190 from program or erase */ 6037 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT191] Bits */ 6038 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191_OFS (31) /*!< PROT191 Bit Offset */ 6039 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191 ((uint32_t)0x80000000) /*!< Protects Sector 191 from program or erase */ 6040 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT192] Bits */ 6041 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192_OFS ( 0) /*!< PROT192 Bit Offset */ 6042 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192 ((uint32_t)0x00000001) /*!< Protects Sector 192 from program or erase */ 6043 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT193] Bits */ 6044 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193_OFS ( 1) /*!< PROT193 Bit Offset */ 6045 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193 ((uint32_t)0x00000002) /*!< Protects Sector 193 from program or erase */ 6046 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT194] Bits */ 6047 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194_OFS ( 2) /*!< PROT194 Bit Offset */ 6048 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194 ((uint32_t)0x00000004) /*!< Protects Sector 194 from program or erase */ 6049 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT195] Bits */ 6050 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195_OFS ( 3) /*!< PROT195 Bit Offset */ 6051 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195 ((uint32_t)0x00000008) /*!< Protects Sector 195 from program or erase */ 6052 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT196] Bits */ 6053 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196_OFS ( 4) /*!< PROT196 Bit Offset */ 6054 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196 ((uint32_t)0x00000010) /*!< Protects Sector 196 from program or erase */ 6055 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT197] Bits */ 6056 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197_OFS ( 5) /*!< PROT197 Bit Offset */ 6057 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197 ((uint32_t)0x00000020) /*!< Protects Sector 197 from program or erase */ 6058 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT198] Bits */ 6059 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198_OFS ( 6) /*!< PROT198 Bit Offset */ 6060 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198 ((uint32_t)0x00000040) /*!< Protects Sector 198 from program or erase */ 6061 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT199] Bits */ 6062 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199_OFS ( 7) /*!< PROT199 Bit Offset */ 6063 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199 ((uint32_t)0x00000080) /*!< Protects Sector 199 from program or erase */ 6064 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT200] Bits */ 6065 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200_OFS ( 8) /*!< PROT200 Bit Offset */ 6066 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200 ((uint32_t)0x00000100) /*!< Protects Sector 200 from program or erase */ 6067 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT201] Bits */ 6068 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201_OFS ( 9) /*!< PROT201 Bit Offset */ 6069 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201 ((uint32_t)0x00000200) /*!< Protects Sector 201 from program or erase */ 6070 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT202] Bits */ 6071 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202_OFS (10) /*!< PROT202 Bit Offset */ 6072 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202 ((uint32_t)0x00000400) /*!< Protects Sector 202 from program or erase */ 6073 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT203] Bits */ 6074 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203_OFS (11) /*!< PROT203 Bit Offset */ 6075 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203 ((uint32_t)0x00000800) /*!< Protects Sector 203 from program or erase */ 6076 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT204] Bits */ 6077 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204_OFS (12) /*!< PROT204 Bit Offset */ 6078 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204 ((uint32_t)0x00001000) /*!< Protects Sector 204 from program or erase */ 6079 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT205] Bits */ 6080 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205_OFS (13) /*!< PROT205 Bit Offset */ 6081 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205 ((uint32_t)0x00002000) /*!< Protects Sector 205 from program or erase */ 6082 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT206] Bits */ 6083 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206_OFS (14) /*!< PROT206 Bit Offset */ 6084 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206 ((uint32_t)0x00004000) /*!< Protects Sector 206 from program or erase */ 6085 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT207] Bits */ 6086 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207_OFS (15) /*!< PROT207 Bit Offset */ 6087 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207 ((uint32_t)0x00008000) /*!< Protects Sector 207 from program or erase */ 6088 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT208] Bits */ 6089 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208_OFS (16) /*!< PROT208 Bit Offset */ 6090 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208 ((uint32_t)0x00010000) /*!< Protects Sector 208 from program or erase */ 6091 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT209] Bits */ 6092 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209_OFS (17) /*!< PROT209 Bit Offset */ 6093 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209 ((uint32_t)0x00020000) /*!< Protects Sector 209 from program or erase */ 6094 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT210] Bits */ 6095 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210_OFS (18) /*!< PROT210 Bit Offset */ 6096 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210 ((uint32_t)0x00040000) /*!< Protects Sector 210 from program or erase */ 6097 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT211] Bits */ 6098 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211_OFS (19) /*!< PROT211 Bit Offset */ 6099 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211 ((uint32_t)0x00080000) /*!< Protects Sector 211 from program or erase */ 6100 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT212] Bits */ 6101 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212_OFS (20) /*!< PROT212 Bit Offset */ 6102 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212 ((uint32_t)0x00100000) /*!< Protects Sector 212 from program or erase */ 6103 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT213] Bits */ 6104 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213_OFS (21) /*!< PROT213 Bit Offset */ 6105 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213 ((uint32_t)0x00200000) /*!< Protects Sector 213 from program or erase */ 6106 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT214] Bits */ 6107 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214_OFS (22) /*!< PROT214 Bit Offset */ 6108 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214 ((uint32_t)0x00400000) /*!< Protects Sector 214 from program or erase */ 6109 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT215] Bits */ 6110 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215_OFS (23) /*!< PROT215 Bit Offset */ 6111 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215 ((uint32_t)0x00800000) /*!< Protects Sector 215 from program or erase */ 6112 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT216] Bits */ 6113 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216_OFS (24) /*!< PROT216 Bit Offset */ 6114 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216 ((uint32_t)0x01000000) /*!< Protects Sector 216 from program or erase */ 6115 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT217] Bits */ 6116 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217_OFS (25) /*!< PROT217 Bit Offset */ 6117 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217 ((uint32_t)0x02000000) /*!< Protects Sector 217 from program or erase */ 6118 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT218] Bits */ 6119 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218_OFS (26) /*!< PROT218 Bit Offset */ 6120 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218 ((uint32_t)0x04000000) /*!< Protects Sector 218 from program or erase */ 6121 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT219] Bits */ 6122 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219_OFS (27) /*!< PROT219 Bit Offset */ 6123 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219 ((uint32_t)0x08000000) /*!< Protects Sector 219 from program or erase */ 6124 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT220] Bits */ 6125 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220_OFS (28) /*!< PROT220 Bit Offset */ 6126 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220 ((uint32_t)0x10000000) /*!< Protects Sector 220 from program or erase */ 6127 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT221] Bits */ 6128 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221_OFS (29) /*!< PROT221 Bit Offset */ 6129 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221 ((uint32_t)0x20000000) /*!< Protects Sector 221 from program or erase */ 6130 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT222] Bits */ 6131 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222_OFS (30) /*!< PROT222 Bit Offset */ 6132 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222 ((uint32_t)0x40000000) /*!< Protects Sector 222 from program or erase */ 6133 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT223] Bits */ 6134 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223_OFS (31) /*!< PROT223 Bit Offset */ 6135 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223 ((uint32_t)0x80000000) /*!< Protects Sector 223 from program or erase */ 6136 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT224] Bits */ 6137 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224_OFS ( 0) /*!< PROT224 Bit Offset */ 6138 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224 ((uint32_t)0x00000001) /*!< Protects Sector 224 from program or erase */ 6139 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT225] Bits */ 6140 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225_OFS ( 1) /*!< PROT225 Bit Offset */ 6141 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225 ((uint32_t)0x00000002) /*!< Protects Sector 225 from program or erase */ 6142 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT226] Bits */ 6143 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226_OFS ( 2) /*!< PROT226 Bit Offset */ 6144 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226 ((uint32_t)0x00000004) /*!< Protects Sector 226 from program or erase */ 6145 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT227] Bits */ 6146 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227_OFS ( 3) /*!< PROT227 Bit Offset */ 6147 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227 ((uint32_t)0x00000008) /*!< Protects Sector 227 from program or erase */ 6148 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT228] Bits */ 6149 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228_OFS ( 4) /*!< PROT228 Bit Offset */ 6150 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228 ((uint32_t)0x00000010) /*!< Protects Sector 228 from program or erase */ 6151 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT229] Bits */ 6152 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229_OFS ( 5) /*!< PROT229 Bit Offset */ 6153 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229 ((uint32_t)0x00000020) /*!< Protects Sector 229 from program or erase */ 6154 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT230] Bits */ 6155 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230_OFS ( 6) /*!< PROT230 Bit Offset */ 6156 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230 ((uint32_t)0x00000040) /*!< Protects Sector 230 from program or erase */ 6157 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT231] Bits */ 6158 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231_OFS ( 7) /*!< PROT231 Bit Offset */ 6159 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231 ((uint32_t)0x00000080) /*!< Protects Sector 231 from program or erase */ 6160 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT232] Bits */ 6161 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232_OFS ( 8) /*!< PROT232 Bit Offset */ 6162 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232 ((uint32_t)0x00000100) /*!< Protects Sector 232 from program or erase */ 6163 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT233] Bits */ 6164 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233_OFS ( 9) /*!< PROT233 Bit Offset */ 6165 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233 ((uint32_t)0x00000200) /*!< Protects Sector 233 from program or erase */ 6166 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT234] Bits */ 6167 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234_OFS (10) /*!< PROT234 Bit Offset */ 6168 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234 ((uint32_t)0x00000400) /*!< Protects Sector 234 from program or erase */ 6169 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT235] Bits */ 6170 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235_OFS (11) /*!< PROT235 Bit Offset */ 6171 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235 ((uint32_t)0x00000800) /*!< Protects Sector 235 from program or erase */ 6172 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT236] Bits */ 6173 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236_OFS (12) /*!< PROT236 Bit Offset */ 6174 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236 ((uint32_t)0x00001000) /*!< Protects Sector 236 from program or erase */ 6175 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT237] Bits */ 6176 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237_OFS (13) /*!< PROT237 Bit Offset */ 6177 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237 ((uint32_t)0x00002000) /*!< Protects Sector 237 from program or erase */ 6178 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT238] Bits */ 6179 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238_OFS (14) /*!< PROT238 Bit Offset */ 6180 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238 ((uint32_t)0x00004000) /*!< Protects Sector 238 from program or erase */ 6181 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT239] Bits */ 6182 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239_OFS (15) /*!< PROT239 Bit Offset */ 6183 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239 ((uint32_t)0x00008000) /*!< Protects Sector 239 from program or erase */ 6184 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT240] Bits */ 6185 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240_OFS (16) /*!< PROT240 Bit Offset */ 6186 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240 ((uint32_t)0x00010000) /*!< Protects Sector 240 from program or erase */ 6187 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT241] Bits */ 6188 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241_OFS (17) /*!< PROT241 Bit Offset */ 6189 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241 ((uint32_t)0x00020000) /*!< Protects Sector 241 from program or erase */ 6190 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT242] Bits */ 6191 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242_OFS (18) /*!< PROT242 Bit Offset */ 6192 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242 ((uint32_t)0x00040000) /*!< Protects Sector 242 from program or erase */ 6193 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT243] Bits */ 6194 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243_OFS (19) /*!< PROT243 Bit Offset */ 6195 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243 ((uint32_t)0x00080000) /*!< Protects Sector 243 from program or erase */ 6196 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT244] Bits */ 6197 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244_OFS (20) /*!< PROT244 Bit Offset */ 6198 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244 ((uint32_t)0x00100000) /*!< Protects Sector 244 from program or erase */ 6199 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT245] Bits */ 6200 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245_OFS (21) /*!< PROT245 Bit Offset */ 6201 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245 ((uint32_t)0x00200000) /*!< Protects Sector 245 from program or erase */ 6202 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT246] Bits */ 6203 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246_OFS (22) /*!< PROT246 Bit Offset */ 6204 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246 ((uint32_t)0x00400000) /*!< Protects Sector 246 from program or erase */ 6205 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT247] Bits */ 6206 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247_OFS (23) /*!< PROT247 Bit Offset */ 6207 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247 ((uint32_t)0x00800000) /*!< Protects Sector 247 from program or erase */ 6208 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT248] Bits */ 6209 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248_OFS (24) /*!< PROT248 Bit Offset */ 6210 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248 ((uint32_t)0x01000000) /*!< Protects Sector 248 from program or erase */ 6211 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT249] Bits */ 6212 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249_OFS (25) /*!< PROT249 Bit Offset */ 6213 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249 ((uint32_t)0x02000000) /*!< Protects Sector 249 from program or erase */ 6214 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT250] Bits */ 6215 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250_OFS (26) /*!< PROT250 Bit Offset */ 6216 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250 ((uint32_t)0x04000000) /*!< Protects Sector 250 from program or erase */ 6217 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT251] Bits */ 6218 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251_OFS (27) /*!< PROT251 Bit Offset */ 6219 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251 ((uint32_t)0x08000000) /*!< Protects Sector 251 from program or erase */ 6220 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT252] Bits */ 6221 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252_OFS (28) /*!< PROT252 Bit Offset */ 6222 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252 ((uint32_t)0x10000000) /*!< Protects Sector 252 from program or erase */ 6223 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT253] Bits */ 6224 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253_OFS (29) /*!< PROT253 Bit Offset */ 6225 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253 ((uint32_t)0x20000000) /*!< Protects Sector 253 from program or erase */ 6226 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT254] Bits */ 6227 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254_OFS (30) /*!< PROT254 Bit Offset */ 6228 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254 ((uint32_t)0x40000000) /*!< Protects Sector 254 from program or erase */ 6229 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT255] Bits */ 6230 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255_OFS (31) /*!< PROT255 Bit Offset */ 6231 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255 ((uint32_t)0x80000000) /*!< Protects Sector 255 from program or erase */ 6232 6233 /****************************************************************************** 6234 * FL_BOOTOVER_MAILBOX Bits 6235 ******************************************************************************/ 6236 6237 /****************************************************************************** 6238 * FPB Bits 6239 ******************************************************************************/ 6240 6241 6242 /****************************************************************************** 6243 * FPU Bits 6244 ******************************************************************************/ 6245 6246 6247 /****************************************************************************** 6248 * ITM Bits 6249 ******************************************************************************/ 6250 6251 6252 /****************************************************************************** 6253 * LCD_F Bits 6254 ******************************************************************************/ 6255 /* LCD_F_CTL[ON] Bits */ 6256 #define LCD_F_CTL_ON_OFS ( 0) /*!< LCDON Bit Offset */ 6257 #define LCD_F_CTL_ON ((uint32_t)0x00000001) /*!< LCD on */ 6258 /* LCD_F_CTL[LP] Bits */ 6259 #define LCD_F_CTL_LP_OFS ( 1) /*!< LCDLP Bit Offset */ 6260 #define LCD_F_CTL_LP ((uint32_t)0x00000002) /*!< LCD Low-power Waveform */ 6261 /* LCD_F_CTL[SON] Bits */ 6262 #define LCD_F_CTL_SON_OFS ( 2) /*!< LCDSON Bit Offset */ 6263 #define LCD_F_CTL_SON ((uint32_t)0x00000004) /*!< LCD segments on */ 6264 /* LCD_F_CTL[MX] Bits */ 6265 #define LCD_F_CTL_MX_OFS ( 3) /*!< LCDMXx Bit Offset */ 6266 #define LCD_F_CTL_MX_MASK ((uint32_t)0x00000038) /*!< LCDMXx Bit Mask */ 6267 #define LCD_F_CTL_MX0 ((uint32_t)0x00000008) /*!< MX Bit 0 */ 6268 #define LCD_F_CTL_MX1 ((uint32_t)0x00000010) /*!< MX Bit 1 */ 6269 #define LCD_F_CTL_MX2 ((uint32_t)0x00000020) /*!< MX Bit 2 */ 6270 #define LCD_F_CTL_MX_0 ((uint32_t)0x00000000) /*!< Static */ 6271 #define LCD_F_CTL_MX_1 ((uint32_t)0x00000008) /*!< 2-mux */ 6272 #define LCD_F_CTL_MX_2 ((uint32_t)0x00000010) /*!< 3-mux */ 6273 #define LCD_F_CTL_MX_3 ((uint32_t)0x00000018) /*!< 4-mux */ 6274 #define LCD_F_CTL_MX_4 ((uint32_t)0x00000020) /*!< 5-mux */ 6275 #define LCD_F_CTL_MX_5 ((uint32_t)0x00000028) /*!< 6-mux */ 6276 #define LCD_F_CTL_MX_6 ((uint32_t)0x00000030) /*!< 7-mux */ 6277 #define LCD_F_CTL_MX_7 ((uint32_t)0x00000038) /*!< 8-mux */ 6278 /* LCD_F_CTL[PRE] Bits */ 6279 #define LCD_F_CTL_PRE_OFS ( 8) /*!< LCDPREx Bit Offset */ 6280 #define LCD_F_CTL_PRE_MASK ((uint32_t)0x00000700) /*!< LCDPREx Bit Mask */ 6281 #define LCD_F_CTL_PRE0 ((uint32_t)0x00000100) /*!< PRE Bit 0 */ 6282 #define LCD_F_CTL_PRE1 ((uint32_t)0x00000200) /*!< PRE Bit 1 */ 6283 #define LCD_F_CTL_PRE2 ((uint32_t)0x00000400) /*!< PRE Bit 2 */ 6284 #define LCD_F_CTL_PRE_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ 6285 #define LCD_F_CTL_PRE_1 ((uint32_t)0x00000100) /*!< Divide by 2 */ 6286 #define LCD_F_CTL_PRE_2 ((uint32_t)0x00000200) /*!< Divide by 4 */ 6287 #define LCD_F_CTL_PRE_3 ((uint32_t)0x00000300) /*!< Divide by 8 */ 6288 #define LCD_F_CTL_PRE_4 ((uint32_t)0x00000400) /*!< Divide by 16 */ 6289 #define LCD_F_CTL_PRE_5 ((uint32_t)0x00000500) /*!< Divide by 32 */ 6290 #define LCD_F_CTL_PRE_6 ((uint32_t)0x00000600) /*!< Reserved (defaults to divide by 32) */ 6291 #define LCD_F_CTL_PRE_7 ((uint32_t)0x00000700) /*!< Reserved (defaults to divide by 32) */ 6292 /* LCD_F_CTL[DIV] Bits */ 6293 #define LCD_F_CTL_DIV_OFS (11) /*!< LCDDIVx Bit Offset */ 6294 #define LCD_F_CTL_DIV_MASK ((uint32_t)0x0000F800) /*!< LCDDIVx Bit Mask */ 6295 #define LCD_F_CTL_DIV0 ((uint32_t)0x00000800) /*!< DIV Bit 0 */ 6296 #define LCD_F_CTL_DIV1 ((uint32_t)0x00001000) /*!< DIV Bit 1 */ 6297 #define LCD_F_CTL_DIV2 ((uint32_t)0x00002000) /*!< DIV Bit 2 */ 6298 #define LCD_F_CTL_DIV3 ((uint32_t)0x00004000) /*!< DIV Bit 3 */ 6299 #define LCD_F_CTL_DIV4 ((uint32_t)0x00008000) /*!< DIV Bit 4 */ 6300 #define LCD_F_CTL_DIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ 6301 #define LCD_F_CTL_DIV_1 ((uint32_t)0x00000800) /*!< Divide by 2 */ 6302 #define LCD_F_CTL_DIV_2 ((uint32_t)0x00001000) /*!< Divide by 3 */ 6303 #define LCD_F_CTL_DIV_3 ((uint32_t)0x00001800) /*!< Divide by 4 */ 6304 #define LCD_F_CTL_DIV_4 ((uint32_t)0x00002000) /*!< Divide by 5 */ 6305 #define LCD_F_CTL_DIV_5 ((uint32_t)0x00002800) /*!< Divide by 6 */ 6306 #define LCD_F_CTL_DIV_6 ((uint32_t)0x00003000) /*!< Divide by 7 */ 6307 #define LCD_F_CTL_DIV_7 ((uint32_t)0x00003800) /*!< Divide by 8 */ 6308 #define LCD_F_CTL_DIV_8 ((uint32_t)0x00004000) /*!< Divide by 9 */ 6309 #define LCD_F_CTL_DIV_9 ((uint32_t)0x00004800) /*!< Divide by 10 */ 6310 #define LCD_F_CTL_DIV_10 ((uint32_t)0x00005000) /*!< Divide by 11 */ 6311 #define LCD_F_CTL_DIV_11 ((uint32_t)0x00005800) /*!< Divide by 12 */ 6312 #define LCD_F_CTL_DIV_12 ((uint32_t)0x00006000) /*!< Divide by 13 */ 6313 #define LCD_F_CTL_DIV_13 ((uint32_t)0x00006800) /*!< Divide by 14 */ 6314 #define LCD_F_CTL_DIV_14 ((uint32_t)0x00007000) /*!< Divide by 15 */ 6315 #define LCD_F_CTL_DIV_15 ((uint32_t)0x00007800) /*!< Divide by 16 */ 6316 #define LCD_F_CTL_DIV_16 ((uint32_t)0x00008000) /*!< Divide by 17 */ 6317 #define LCD_F_CTL_DIV_17 ((uint32_t)0x00008800) /*!< Divide by 18 */ 6318 #define LCD_F_CTL_DIV_18 ((uint32_t)0x00009000) /*!< Divide by 19 */ 6319 #define LCD_F_CTL_DIV_19 ((uint32_t)0x00009800) /*!< Divide by 20 */ 6320 #define LCD_F_CTL_DIV_20 ((uint32_t)0x0000A000) /*!< Divide by 21 */ 6321 #define LCD_F_CTL_DIV_21 ((uint32_t)0x0000A800) /*!< Divide by 22 */ 6322 #define LCD_F_CTL_DIV_22 ((uint32_t)0x0000B000) /*!< Divide by 23 */ 6323 #define LCD_F_CTL_DIV_23 ((uint32_t)0x0000B800) /*!< Divide by 24 */ 6324 #define LCD_F_CTL_DIV_24 ((uint32_t)0x0000C000) /*!< Divide by 25 */ 6325 #define LCD_F_CTL_DIV_25 ((uint32_t)0x0000C800) /*!< Divide by 26 */ 6326 #define LCD_F_CTL_DIV_26 ((uint32_t)0x0000D000) /*!< Divide by 27 */ 6327 #define LCD_F_CTL_DIV_27 ((uint32_t)0x0000D800) /*!< Divide by 28 */ 6328 #define LCD_F_CTL_DIV_28 ((uint32_t)0x0000E000) /*!< Divide by 29 */ 6329 #define LCD_F_CTL_DIV_29 ((uint32_t)0x0000E800) /*!< Divide by 30 */ 6330 #define LCD_F_CTL_DIV_30 ((uint32_t)0x0000F000) /*!< Divide by 31 */ 6331 #define LCD_F_CTL_DIV_31 ((uint32_t)0x0000F800) /*!< Divide by 32 */ 6332 /* LCD_F_CTL[SSEL] Bits */ 6333 #define LCD_F_CTL_SSEL_OFS (16) /*!< LCDSSEL Bit Offset */ 6334 #define LCD_F_CTL_SSEL_MASK ((uint32_t)0x00030000) /*!< LCDSSEL Bit Mask */ 6335 #define LCD_F_CTL_SSEL0 ((uint32_t)0x00010000) /*!< SSEL Bit 0 */ 6336 #define LCD_F_CTL_SSEL1 ((uint32_t)0x00020000) /*!< SSEL Bit 1 */ 6337 #define LCD_F_CTL_SSEL_0 ((uint32_t)0x00000000) /*!< ACLK */ 6338 #define LCD_F_CTL_SSEL_1 ((uint32_t)0x00010000) /*!< VLOCLK */ 6339 #define LCD_F_CTL_SSEL_2 ((uint32_t)0x00020000) /*!< REFOCLK */ 6340 #define LCD_F_CTL_SSEL_3 ((uint32_t)0x00030000) /*!< LFXTCLK */ 6341 /* LCD_F_BMCTL[BLKMOD] Bits */ 6342 #define LCD_F_BMCTL_BLKMOD_OFS ( 0) /*!< LCDBLKMODx Bit Offset */ 6343 #define LCD_F_BMCTL_BLKMOD_MASK ((uint32_t)0x00000003) /*!< LCDBLKMODx Bit Mask */ 6344 #define LCD_F_BMCTL_BLKMOD0 ((uint32_t)0x00000001) /*!< BLKMOD Bit 0 */ 6345 #define LCD_F_BMCTL_BLKMOD1 ((uint32_t)0x00000002) /*!< BLKMOD Bit 1 */ 6346 #define LCD_F_BMCTL_BLKMOD_0 ((uint32_t)0x00000000) /*!< Blinking disabled */ 6347 #define LCD_F_BMCTL_BLKMOD_1 ((uint32_t)0x00000001) /*!< Blinking of individual segments as enabled in blinking memory register */ 6348 /* LCDBMx. */ 6349 #define LCD_F_BMCTL_BLKMOD_2 ((uint32_t)0x00000002) /*!< Blinking of all segments */ 6350 #define LCD_F_BMCTL_BLKMOD_3 ((uint32_t)0x00000003) /*!< Switching between display contents as stored in LCDMx and LCDBMx memory */ 6351 /* registers. */ 6352 /* LCD_F_BMCTL[BLKPRE] Bits */ 6353 #define LCD_F_BMCTL_BLKPRE_OFS ( 2) /*!< LCDBLKPREx Bit Offset */ 6354 #define LCD_F_BMCTL_BLKPRE_MASK ((uint32_t)0x0000001C) /*!< LCDBLKPREx Bit Mask */ 6355 #define LCD_F_BMCTL_BLKPRE0 ((uint32_t)0x00000004) /*!< BLKPRE Bit 0 */ 6356 #define LCD_F_BMCTL_BLKPRE1 ((uint32_t)0x00000008) /*!< BLKPRE Bit 1 */ 6357 #define LCD_F_BMCTL_BLKPRE2 ((uint32_t)0x00000010) /*!< BLKPRE Bit 2 */ 6358 #define LCD_F_BMCTL_BLKPRE_0 ((uint32_t)0x00000000) /*!< Divide by 512 */ 6359 #define LCD_F_BMCTL_BLKPRE_1 ((uint32_t)0x00000004) /*!< Divide by 1024 */ 6360 #define LCD_F_BMCTL_BLKPRE_2 ((uint32_t)0x00000008) /*!< Divide by 2048 */ 6361 #define LCD_F_BMCTL_BLKPRE_3 ((uint32_t)0x0000000C) /*!< Divide by 4096 */ 6362 #define LCD_F_BMCTL_BLKPRE_4 ((uint32_t)0x00000010) /*!< Divide by 8162 */ 6363 #define LCD_F_BMCTL_BLKPRE_5 ((uint32_t)0x00000014) /*!< Divide by 16384 */ 6364 #define LCD_F_BMCTL_BLKPRE_6 ((uint32_t)0x00000018) /*!< Divide by 32768 */ 6365 #define LCD_F_BMCTL_BLKPRE_7 ((uint32_t)0x0000001C) /*!< Divide by 65536 */ 6366 /* LCD_F_BMCTL[BLKDIV] Bits */ 6367 #define LCD_F_BMCTL_BLKDIV_OFS ( 5) /*!< LCDBLKDIVx Bit Offset */ 6368 #define LCD_F_BMCTL_BLKDIV_MASK ((uint32_t)0x000000E0) /*!< LCDBLKDIVx Bit Mask */ 6369 #define LCD_F_BMCTL_BLKDIV0 ((uint32_t)0x00000020) /*!< BLKDIV Bit 0 */ 6370 #define LCD_F_BMCTL_BLKDIV1 ((uint32_t)0x00000040) /*!< BLKDIV Bit 1 */ 6371 #define LCD_F_BMCTL_BLKDIV2 ((uint32_t)0x00000080) /*!< BLKDIV Bit 2 */ 6372 #define LCD_F_BMCTL_BLKDIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ 6373 #define LCD_F_BMCTL_BLKDIV_1 ((uint32_t)0x00000020) /*!< Divide by 2 */ 6374 #define LCD_F_BMCTL_BLKDIV_2 ((uint32_t)0x00000040) /*!< Divide by 3 */ 6375 #define LCD_F_BMCTL_BLKDIV_3 ((uint32_t)0x00000060) /*!< Divide by 4 */ 6376 #define LCD_F_BMCTL_BLKDIV_4 ((uint32_t)0x00000080) /*!< Divide by 5 */ 6377 #define LCD_F_BMCTL_BLKDIV_5 ((uint32_t)0x000000A0) /*!< Divide by 6 */ 6378 #define LCD_F_BMCTL_BLKDIV_6 ((uint32_t)0x000000C0) /*!< Divide by 7 */ 6379 #define LCD_F_BMCTL_BLKDIV_7 ((uint32_t)0x000000E0) /*!< Divide by 8 */ 6380 /* LCD_F_BMCTL[DISP] Bits */ 6381 #define LCD_F_BMCTL_DISP_OFS (16) /*!< LCDDISP Bit Offset */ 6382 #define LCD_F_BMCTL_DISP ((uint32_t)0x00010000) /*!< Select LCD memory registers for display */ 6383 /* LCD_F_BMCTL[CLRM] Bits */ 6384 #define LCD_F_BMCTL_CLRM_OFS (17) /*!< LCDCLRM Bit Offset */ 6385 #define LCD_F_BMCTL_CLRM ((uint32_t)0x00020000) /*!< Clear LCD memory */ 6386 /* LCD_F_BMCTL[CLRBM] Bits */ 6387 #define LCD_F_BMCTL_CLRBM_OFS (18) /*!< LCDCLRBM Bit Offset */ 6388 #define LCD_F_BMCTL_CLRBM ((uint32_t)0x00040000) /*!< Clear LCD blinking memory */ 6389 /* LCD_F_VCTL[LCD2B] Bits */ 6390 #define LCD_F_VCTL_LCD2B_OFS ( 0) /*!< LCD2B Bit Offset */ 6391 #define LCD_F_VCTL_LCD2B ((uint32_t)0x00000001) /*!< Bias select. */ 6392 /* LCD_F_VCTL[EXTBIAS] Bits */ 6393 #define LCD_F_VCTL_EXTBIAS_OFS ( 5) /*!< LCDEXTBIAS Bit Offset */ 6394 #define LCD_F_VCTL_EXTBIAS ((uint32_t)0x00000020) /*!< V2 to V4 voltage select */ 6395 /* LCD_F_VCTL[R03EXT] Bits */ 6396 #define LCD_F_VCTL_R03EXT_OFS ( 6) /*!< R03EXT Bit Offset */ 6397 #define LCD_F_VCTL_R03EXT ((uint32_t)0x00000040) /*!< V5 voltage select */ 6398 /* LCD_F_VCTL[REXT] Bits */ 6399 #define LCD_F_VCTL_REXT_OFS ( 7) /*!< LCDREXT Bit Offset */ 6400 #define LCD_F_VCTL_REXT ((uint32_t)0x00000080) /*!< V2 to V4 voltage on external Rx3 pins */ 6401 /* LCD_F_PCTL0[S0] Bits */ 6402 #define LCD_F_PCTL0_S0_OFS ( 0) /*!< LCDS0 Bit Offset */ 6403 #define LCD_F_PCTL0_S0 ((uint32_t)0x00000001) /*!< LCD pin 0 enable */ 6404 /* LCD_F_PCTL0[S1] Bits */ 6405 #define LCD_F_PCTL0_S1_OFS ( 1) /*!< LCDS1 Bit Offset */ 6406 #define LCD_F_PCTL0_S1 ((uint32_t)0x00000002) /*!< LCD pin 1 enable */ 6407 /* LCD_F_PCTL0[S2] Bits */ 6408 #define LCD_F_PCTL0_S2_OFS ( 2) /*!< LCDS2 Bit Offset */ 6409 #define LCD_F_PCTL0_S2 ((uint32_t)0x00000004) /*!< LCD pin 2 enable */ 6410 /* LCD_F_PCTL0[S3] Bits */ 6411 #define LCD_F_PCTL0_S3_OFS ( 3) /*!< LCDS3 Bit Offset */ 6412 #define LCD_F_PCTL0_S3 ((uint32_t)0x00000008) /*!< LCD pin 3 enable */ 6413 /* LCD_F_PCTL0[S4] Bits */ 6414 #define LCD_F_PCTL0_S4_OFS ( 4) /*!< LCDS4 Bit Offset */ 6415 #define LCD_F_PCTL0_S4 ((uint32_t)0x00000010) /*!< LCD pin 4 enable */ 6416 /* LCD_F_PCTL0[S5] Bits */ 6417 #define LCD_F_PCTL0_S5_OFS ( 5) /*!< LCDS5 Bit Offset */ 6418 #define LCD_F_PCTL0_S5 ((uint32_t)0x00000020) /*!< LCD pin 5 enable */ 6419 /* LCD_F_PCTL0[S6] Bits */ 6420 #define LCD_F_PCTL0_S6_OFS ( 6) /*!< LCDS6 Bit Offset */ 6421 #define LCD_F_PCTL0_S6 ((uint32_t)0x00000040) /*!< LCD pin 6 enable */ 6422 /* LCD_F_PCTL0[S7] Bits */ 6423 #define LCD_F_PCTL0_S7_OFS ( 7) /*!< LCDS7 Bit Offset */ 6424 #define LCD_F_PCTL0_S7 ((uint32_t)0x00000080) /*!< LCD pin 7 enable */ 6425 /* LCD_F_PCTL0[S8] Bits */ 6426 #define LCD_F_PCTL0_S8_OFS ( 8) /*!< LCDS8 Bit Offset */ 6427 #define LCD_F_PCTL0_S8 ((uint32_t)0x00000100) /*!< LCD pin 8 enable */ 6428 /* LCD_F_PCTL0[S9] Bits */ 6429 #define LCD_F_PCTL0_S9_OFS ( 9) /*!< LCDS9 Bit Offset */ 6430 #define LCD_F_PCTL0_S9 ((uint32_t)0x00000200) /*!< LCD pin 9 enable */ 6431 /* LCD_F_PCTL0[S10] Bits */ 6432 #define LCD_F_PCTL0_S10_OFS (10) /*!< LCDS10 Bit Offset */ 6433 #define LCD_F_PCTL0_S10 ((uint32_t)0x00000400) /*!< LCD pin 10 enable */ 6434 /* LCD_F_PCTL0[S11] Bits */ 6435 #define LCD_F_PCTL0_S11_OFS (11) /*!< LCDS11 Bit Offset */ 6436 #define LCD_F_PCTL0_S11 ((uint32_t)0x00000800) /*!< LCD pin 11 enable */ 6437 /* LCD_F_PCTL0[S12] Bits */ 6438 #define LCD_F_PCTL0_S12_OFS (12) /*!< LCDS12 Bit Offset */ 6439 #define LCD_F_PCTL0_S12 ((uint32_t)0x00001000) /*!< LCD pin 12 enable */ 6440 /* LCD_F_PCTL0[S13] Bits */ 6441 #define LCD_F_PCTL0_S13_OFS (13) /*!< LCDS13 Bit Offset */ 6442 #define LCD_F_PCTL0_S13 ((uint32_t)0x00002000) /*!< LCD pin 13 enable */ 6443 /* LCD_F_PCTL0[S14] Bits */ 6444 #define LCD_F_PCTL0_S14_OFS (14) /*!< LCDS14 Bit Offset */ 6445 #define LCD_F_PCTL0_S14 ((uint32_t)0x00004000) /*!< LCD pin 14 enable */ 6446 /* LCD_F_PCTL0[S15] Bits */ 6447 #define LCD_F_PCTL0_S15_OFS (15) /*!< LCDS15 Bit Offset */ 6448 #define LCD_F_PCTL0_S15 ((uint32_t)0x00008000) /*!< LCD pin 15 enable */ 6449 /* LCD_F_PCTL0[S16] Bits */ 6450 #define LCD_F_PCTL0_S16_OFS (16) /*!< LCDS16 Bit Offset */ 6451 #define LCD_F_PCTL0_S16 ((uint32_t)0x00010000) /*!< LCD pin 16 enable */ 6452 /* LCD_F_PCTL0[S17] Bits */ 6453 #define LCD_F_PCTL0_S17_OFS (17) /*!< LCDS17 Bit Offset */ 6454 #define LCD_F_PCTL0_S17 ((uint32_t)0x00020000) /*!< LCD pin 17 enable */ 6455 /* LCD_F_PCTL0[S18] Bits */ 6456 #define LCD_F_PCTL0_S18_OFS (18) /*!< LCDS18 Bit Offset */ 6457 #define LCD_F_PCTL0_S18 ((uint32_t)0x00040000) /*!< LCD pin 18 enable */ 6458 /* LCD_F_PCTL0[S19] Bits */ 6459 #define LCD_F_PCTL0_S19_OFS (19) /*!< LCDS19 Bit Offset */ 6460 #define LCD_F_PCTL0_S19 ((uint32_t)0x00080000) /*!< LCD pin 19 enable */ 6461 /* LCD_F_PCTL0[S20] Bits */ 6462 #define LCD_F_PCTL0_S20_OFS (20) /*!< LCDS20 Bit Offset */ 6463 #define LCD_F_PCTL0_S20 ((uint32_t)0x00100000) /*!< LCD pin 20 enable */ 6464 /* LCD_F_PCTL0[S21] Bits */ 6465 #define LCD_F_PCTL0_S21_OFS (21) /*!< LCDS21 Bit Offset */ 6466 #define LCD_F_PCTL0_S21 ((uint32_t)0x00200000) /*!< LCD pin 21 enable */ 6467 /* LCD_F_PCTL0[S22] Bits */ 6468 #define LCD_F_PCTL0_S22_OFS (22) /*!< LCDS22 Bit Offset */ 6469 #define LCD_F_PCTL0_S22 ((uint32_t)0x00400000) /*!< LCD pin 22 enable */ 6470 /* LCD_F_PCTL0[S23] Bits */ 6471 #define LCD_F_PCTL0_S23_OFS (23) /*!< LCDS23 Bit Offset */ 6472 #define LCD_F_PCTL0_S23 ((uint32_t)0x00800000) /*!< LCD pin 23 enable */ 6473 /* LCD_F_PCTL0[S24] Bits */ 6474 #define LCD_F_PCTL0_S24_OFS (24) /*!< LCDS24 Bit Offset */ 6475 #define LCD_F_PCTL0_S24 ((uint32_t)0x01000000) /*!< LCD pin 24 enable */ 6476 /* LCD_F_PCTL0[S25] Bits */ 6477 #define LCD_F_PCTL0_S25_OFS (25) /*!< LCDS25 Bit Offset */ 6478 #define LCD_F_PCTL0_S25 ((uint32_t)0x02000000) /*!< LCD pin 25 enable */ 6479 /* LCD_F_PCTL0[S26] Bits */ 6480 #define LCD_F_PCTL0_S26_OFS (26) /*!< LCDS26 Bit Offset */ 6481 #define LCD_F_PCTL0_S26 ((uint32_t)0x04000000) /*!< LCD pin 26 enable */ 6482 /* LCD_F_PCTL0[S27] Bits */ 6483 #define LCD_F_PCTL0_S27_OFS (27) /*!< LCDS27 Bit Offset */ 6484 #define LCD_F_PCTL0_S27 ((uint32_t)0x08000000) /*!< LCD pin 27 enable */ 6485 /* LCD_F_PCTL0[S28] Bits */ 6486 #define LCD_F_PCTL0_S28_OFS (28) /*!< LCDS28 Bit Offset */ 6487 #define LCD_F_PCTL0_S28 ((uint32_t)0x10000000) /*!< LCD pin 28 enable */ 6488 /* LCD_F_PCTL0[S29] Bits */ 6489 #define LCD_F_PCTL0_S29_OFS (29) /*!< LCDS29 Bit Offset */ 6490 #define LCD_F_PCTL0_S29 ((uint32_t)0x20000000) /*!< LCD pin 29 enable */ 6491 /* LCD_F_PCTL0[S30] Bits */ 6492 #define LCD_F_PCTL0_S30_OFS (30) /*!< LCDS30 Bit Offset */ 6493 #define LCD_F_PCTL0_S30 ((uint32_t)0x40000000) /*!< LCD pin 30 enable */ 6494 /* LCD_F_PCTL0[S31] Bits */ 6495 #define LCD_F_PCTL0_S31_OFS (31) /*!< LCDS31 Bit Offset */ 6496 #define LCD_F_PCTL0_S31 ((uint32_t)0x80000000) /*!< LCD pin 31 enable */ 6497 /* LCD_F_PCTL1[S32] Bits */ 6498 #define LCD_F_PCTL1_S32_OFS ( 0) /*!< LCDS32 Bit Offset */ 6499 #define LCD_F_PCTL1_S32 ((uint32_t)0x00000001) /*!< LCD pin 32 enable */ 6500 /* LCD_F_PCTL1[S33] Bits */ 6501 #define LCD_F_PCTL1_S33_OFS ( 1) /*!< LCDS33 Bit Offset */ 6502 #define LCD_F_PCTL1_S33 ((uint32_t)0x00000002) /*!< LCD pin 33 enable */ 6503 /* LCD_F_PCTL1[S34] Bits */ 6504 #define LCD_F_PCTL1_S34_OFS ( 2) /*!< LCDS34 Bit Offset */ 6505 #define LCD_F_PCTL1_S34 ((uint32_t)0x00000004) /*!< LCD pin 34 enable */ 6506 /* LCD_F_PCTL1[S35] Bits */ 6507 #define LCD_F_PCTL1_S35_OFS ( 3) /*!< LCDS35 Bit Offset */ 6508 #define LCD_F_PCTL1_S35 ((uint32_t)0x00000008) /*!< LCD pin 35 enable */ 6509 /* LCD_F_PCTL1[S36] Bits */ 6510 #define LCD_F_PCTL1_S36_OFS ( 4) /*!< LCDS36 Bit Offset */ 6511 #define LCD_F_PCTL1_S36 ((uint32_t)0x00000010) /*!< LCD pin 36 enable */ 6512 /* LCD_F_PCTL1[S37] Bits */ 6513 #define LCD_F_PCTL1_S37_OFS ( 5) /*!< LCDS37 Bit Offset */ 6514 #define LCD_F_PCTL1_S37 ((uint32_t)0x00000020) /*!< LCD pin 37 enable */ 6515 /* LCD_F_PCTL1[S38] Bits */ 6516 #define LCD_F_PCTL1_S38_OFS ( 6) /*!< LCDS38 Bit Offset */ 6517 #define LCD_F_PCTL1_S38 ((uint32_t)0x00000040) /*!< LCD pin 38 enable */ 6518 /* LCD_F_PCTL1[S39] Bits */ 6519 #define LCD_F_PCTL1_S39_OFS ( 7) /*!< LCDS39 Bit Offset */ 6520 #define LCD_F_PCTL1_S39 ((uint32_t)0x00000080) /*!< LCD pin 39 enable */ 6521 /* LCD_F_PCTL1[S40] Bits */ 6522 #define LCD_F_PCTL1_S40_OFS ( 8) /*!< LCDS40 Bit Offset */ 6523 #define LCD_F_PCTL1_S40 ((uint32_t)0x00000100) /*!< LCD pin 40 enable */ 6524 /* LCD_F_PCTL1[S41] Bits */ 6525 #define LCD_F_PCTL1_S41_OFS ( 9) /*!< LCDS41 Bit Offset */ 6526 #define LCD_F_PCTL1_S41 ((uint32_t)0x00000200) /*!< LCD pin 41 enable */ 6527 /* LCD_F_PCTL1[S42] Bits */ 6528 #define LCD_F_PCTL1_S42_OFS (10) /*!< LCDS42 Bit Offset */ 6529 #define LCD_F_PCTL1_S42 ((uint32_t)0x00000400) /*!< LCD pin 42 enable */ 6530 /* LCD_F_PCTL1[S43] Bits */ 6531 #define LCD_F_PCTL1_S43_OFS (11) /*!< LCDS43 Bit Offset */ 6532 #define LCD_F_PCTL1_S43 ((uint32_t)0x00000800) /*!< LCD pin 43 enable */ 6533 /* LCD_F_PCTL1[S44] Bits */ 6534 #define LCD_F_PCTL1_S44_OFS (12) /*!< LCDS44 Bit Offset */ 6535 #define LCD_F_PCTL1_S44 ((uint32_t)0x00001000) /*!< LCD pin 44 enable */ 6536 /* LCD_F_PCTL1[S45] Bits */ 6537 #define LCD_F_PCTL1_S45_OFS (13) /*!< LCDS45 Bit Offset */ 6538 #define LCD_F_PCTL1_S45 ((uint32_t)0x00002000) /*!< LCD pin 45 enable */ 6539 /* LCD_F_PCTL1[S46] Bits */ 6540 #define LCD_F_PCTL1_S46_OFS (14) /*!< LCDS46 Bit Offset */ 6541 #define LCD_F_PCTL1_S46 ((uint32_t)0x00004000) /*!< LCD pin 46 enable */ 6542 /* LCD_F_PCTL1[S47] Bits */ 6543 #define LCD_F_PCTL1_S47_OFS (15) /*!< LCDS47 Bit Offset */ 6544 #define LCD_F_PCTL1_S47 ((uint32_t)0x00008000) /*!< LCD pin 47 enable */ 6545 /* LCD_F_PCTL1[S48] Bits */ 6546 #define LCD_F_PCTL1_S48_OFS (16) /*!< LCDS48 Bit Offset */ 6547 #define LCD_F_PCTL1_S48 ((uint32_t)0x00010000) /*!< LCD pin 48 enable */ 6548 /* LCD_F_PCTL1[S49] Bits */ 6549 #define LCD_F_PCTL1_S49_OFS (17) /*!< LCDS49 Bit Offset */ 6550 #define LCD_F_PCTL1_S49 ((uint32_t)0x00020000) /*!< LCD pin 49 enable */ 6551 /* LCD_F_PCTL1[S50] Bits */ 6552 #define LCD_F_PCTL1_S50_OFS (18) /*!< LCDS50 Bit Offset */ 6553 #define LCD_F_PCTL1_S50 ((uint32_t)0x00040000) /*!< LCD pin 50 enable */ 6554 /* LCD_F_PCTL1[S51] Bits */ 6555 #define LCD_F_PCTL1_S51_OFS (19) /*!< LCDS51 Bit Offset */ 6556 #define LCD_F_PCTL1_S51 ((uint32_t)0x00080000) /*!< LCD pin 51 enable */ 6557 /* LCD_F_PCTL1[S52] Bits */ 6558 #define LCD_F_PCTL1_S52_OFS (20) /*!< LCDS52 Bit Offset */ 6559 #define LCD_F_PCTL1_S52 ((uint32_t)0x00100000) /*!< LCD pin 52 enable */ 6560 /* LCD_F_PCTL1[S53] Bits */ 6561 #define LCD_F_PCTL1_S53_OFS (21) /*!< LCDS53 Bit Offset */ 6562 #define LCD_F_PCTL1_S53 ((uint32_t)0x00200000) /*!< LCD pin 53 enable */ 6563 /* LCD_F_PCTL1[S54] Bits */ 6564 #define LCD_F_PCTL1_S54_OFS (22) /*!< LCDS54 Bit Offset */ 6565 #define LCD_F_PCTL1_S54 ((uint32_t)0x00400000) /*!< LCD pin 54 enable */ 6566 /* LCD_F_PCTL1[S55] Bits */ 6567 #define LCD_F_PCTL1_S55_OFS (23) /*!< LCDS55 Bit Offset */ 6568 #define LCD_F_PCTL1_S55 ((uint32_t)0x00800000) /*!< LCD pin 55 enable */ 6569 /* LCD_F_PCTL1[S56] Bits */ 6570 #define LCD_F_PCTL1_S56_OFS (24) /*!< LCDS56 Bit Offset */ 6571 #define LCD_F_PCTL1_S56 ((uint32_t)0x01000000) /*!< LCD pin 56 enable */ 6572 /* LCD_F_PCTL1[S57] Bits */ 6573 #define LCD_F_PCTL1_S57_OFS (25) /*!< LCDS57 Bit Offset */ 6574 #define LCD_F_PCTL1_S57 ((uint32_t)0x02000000) /*!< LCD pin 57 enable */ 6575 /* LCD_F_PCTL1[S58] Bits */ 6576 #define LCD_F_PCTL1_S58_OFS (26) /*!< LCDS58 Bit Offset */ 6577 #define LCD_F_PCTL1_S58 ((uint32_t)0x04000000) /*!< LCD pin 58 enable */ 6578 /* LCD_F_PCTL1[S59] Bits */ 6579 #define LCD_F_PCTL1_S59_OFS (27) /*!< LCDS59 Bit Offset */ 6580 #define LCD_F_PCTL1_S59 ((uint32_t)0x08000000) /*!< LCD pin 59 enable */ 6581 /* LCD_F_PCTL1[S60] Bits */ 6582 #define LCD_F_PCTL1_S60_OFS (28) /*!< LCDS60 Bit Offset */ 6583 #define LCD_F_PCTL1_S60 ((uint32_t)0x10000000) /*!< LCD pin 60 enable */ 6584 /* LCD_F_PCTL1[S61] Bits */ 6585 #define LCD_F_PCTL1_S61_OFS (29) /*!< LCDS61 Bit Offset */ 6586 #define LCD_F_PCTL1_S61 ((uint32_t)0x20000000) /*!< LCD pin 61 enable */ 6587 /* LCD_F_PCTL1[S62] Bits */ 6588 #define LCD_F_PCTL1_S62_OFS (30) /*!< LCDS62 Bit Offset */ 6589 #define LCD_F_PCTL1_S62 ((uint32_t)0x40000000) /*!< LCD pin 62 enable */ 6590 /* LCD_F_PCTL1[S63] Bits */ 6591 #define LCD_F_PCTL1_S63_OFS (31) /*!< LCDS63 Bit Offset */ 6592 #define LCD_F_PCTL1_S63 ((uint32_t)0x80000000) /*!< LCD pin 63 enable */ 6593 /* LCD_F_CSSEL0[CSS0] Bits */ 6594 #define LCD_F_CSSEL0_CSS0_OFS ( 0) /*!< LCDCSS0 Bit Offset */ 6595 #define LCD_F_CSSEL0_CSS0 ((uint32_t)0x00000001) /*!< L0 Com Seg select */ 6596 /* LCD_F_CSSEL0[CSS1] Bits */ 6597 #define LCD_F_CSSEL0_CSS1_OFS ( 1) /*!< LCDCSS1 Bit Offset */ 6598 #define LCD_F_CSSEL0_CSS1 ((uint32_t)0x00000002) /*!< L1 Com Seg select */ 6599 /* LCD_F_CSSEL0[CSS2] Bits */ 6600 #define LCD_F_CSSEL0_CSS2_OFS ( 2) /*!< LCDCSS2 Bit Offset */ 6601 #define LCD_F_CSSEL0_CSS2 ((uint32_t)0x00000004) /*!< L2 Com Seg select */ 6602 /* LCD_F_CSSEL0[CSS3] Bits */ 6603 #define LCD_F_CSSEL0_CSS3_OFS ( 3) /*!< LCDCSS3 Bit Offset */ 6604 #define LCD_F_CSSEL0_CSS3 ((uint32_t)0x00000008) /*!< L3 Com Seg select */ 6605 /* LCD_F_CSSEL0[CSS4] Bits */ 6606 #define LCD_F_CSSEL0_CSS4_OFS ( 4) /*!< LCDCSS4 Bit Offset */ 6607 #define LCD_F_CSSEL0_CSS4 ((uint32_t)0x00000010) /*!< L4 Com Seg select */ 6608 /* LCD_F_CSSEL0[CSS5] Bits */ 6609 #define LCD_F_CSSEL0_CSS5_OFS ( 5) /*!< LCDCSS5 Bit Offset */ 6610 #define LCD_F_CSSEL0_CSS5 ((uint32_t)0x00000020) /*!< L5 Com Seg select */ 6611 /* LCD_F_CSSEL0[CSS6] Bits */ 6612 #define LCD_F_CSSEL0_CSS6_OFS ( 6) /*!< LCDCSS6 Bit Offset */ 6613 #define LCD_F_CSSEL0_CSS6 ((uint32_t)0x00000040) /*!< L6 Com Seg select */ 6614 /* LCD_F_CSSEL0[CSS7] Bits */ 6615 #define LCD_F_CSSEL0_CSS7_OFS ( 7) /*!< LCDCSS7 Bit Offset */ 6616 #define LCD_F_CSSEL0_CSS7 ((uint32_t)0x00000080) /*!< L7 Com Seg select */ 6617 /* LCD_F_CSSEL0[CSS8] Bits */ 6618 #define LCD_F_CSSEL0_CSS8_OFS ( 8) /*!< LCDCSS8 Bit Offset */ 6619 #define LCD_F_CSSEL0_CSS8 ((uint32_t)0x00000100) /*!< L8 Com Seg select */ 6620 /* LCD_F_CSSEL0[CSS9] Bits */ 6621 #define LCD_F_CSSEL0_CSS9_OFS ( 9) /*!< LCDCSS9 Bit Offset */ 6622 #define LCD_F_CSSEL0_CSS9 ((uint32_t)0x00000200) /*!< L9 Com Seg select */ 6623 /* LCD_F_CSSEL0[CSS10] Bits */ 6624 #define LCD_F_CSSEL0_CSS10_OFS (10) /*!< LCDCSS10 Bit Offset */ 6625 #define LCD_F_CSSEL0_CSS10 ((uint32_t)0x00000400) /*!< L10 Com Seg select */ 6626 /* LCD_F_CSSEL0[CSS11] Bits */ 6627 #define LCD_F_CSSEL0_CSS11_OFS (11) /*!< LCDCSS11 Bit Offset */ 6628 #define LCD_F_CSSEL0_CSS11 ((uint32_t)0x00000800) /*!< L11 Com Seg select */ 6629 /* LCD_F_CSSEL0[CSS12] Bits */ 6630 #define LCD_F_CSSEL0_CSS12_OFS (12) /*!< LCDCSS12 Bit Offset */ 6631 #define LCD_F_CSSEL0_CSS12 ((uint32_t)0x00001000) /*!< L12 Com Seg select */ 6632 /* LCD_F_CSSEL0[CSS13] Bits */ 6633 #define LCD_F_CSSEL0_CSS13_OFS (13) /*!< LCDCSS13 Bit Offset */ 6634 #define LCD_F_CSSEL0_CSS13 ((uint32_t)0x00002000) /*!< L13 Com Seg select */ 6635 /* LCD_F_CSSEL0[CSS14] Bits */ 6636 #define LCD_F_CSSEL0_CSS14_OFS (14) /*!< LCDCSS14 Bit Offset */ 6637 #define LCD_F_CSSEL0_CSS14 ((uint32_t)0x00004000) /*!< L14 Com Seg select */ 6638 /* LCD_F_CSSEL0[CSS15] Bits */ 6639 #define LCD_F_CSSEL0_CSS15_OFS (15) /*!< LCDCSS15 Bit Offset */ 6640 #define LCD_F_CSSEL0_CSS15 ((uint32_t)0x00008000) /*!< L15 Com Seg select */ 6641 /* LCD_F_CSSEL0[CSS16] Bits */ 6642 #define LCD_F_CSSEL0_CSS16_OFS (16) /*!< LCDCSS16 Bit Offset */ 6643 #define LCD_F_CSSEL0_CSS16 ((uint32_t)0x00010000) /*!< L16 Com Seg select */ 6644 /* LCD_F_CSSEL0[CSS17] Bits */ 6645 #define LCD_F_CSSEL0_CSS17_OFS (17) /*!< LCDCSS17 Bit Offset */ 6646 #define LCD_F_CSSEL0_CSS17 ((uint32_t)0x00020000) /*!< L17 Com Seg select */ 6647 /* LCD_F_CSSEL0[CSS18] Bits */ 6648 #define LCD_F_CSSEL0_CSS18_OFS (18) /*!< LCDCSS18 Bit Offset */ 6649 #define LCD_F_CSSEL0_CSS18 ((uint32_t)0x00040000) /*!< L18 Com Seg select */ 6650 /* LCD_F_CSSEL0[CSS19] Bits */ 6651 #define LCD_F_CSSEL0_CSS19_OFS (19) /*!< LCDCSS19 Bit Offset */ 6652 #define LCD_F_CSSEL0_CSS19 ((uint32_t)0x00080000) /*!< L19 Com Seg select */ 6653 /* LCD_F_CSSEL0[CSS20] Bits */ 6654 #define LCD_F_CSSEL0_CSS20_OFS (20) /*!< LCDCSS20 Bit Offset */ 6655 #define LCD_F_CSSEL0_CSS20 ((uint32_t)0x00100000) /*!< L20 Com Seg select */ 6656 /* LCD_F_CSSEL0[CSS21] Bits */ 6657 #define LCD_F_CSSEL0_CSS21_OFS (21) /*!< LCDCSS21 Bit Offset */ 6658 #define LCD_F_CSSEL0_CSS21 ((uint32_t)0x00200000) /*!< L21 Com Seg select */ 6659 /* LCD_F_CSSEL0[CSS22] Bits */ 6660 #define LCD_F_CSSEL0_CSS22_OFS (22) /*!< LCDCSS22 Bit Offset */ 6661 #define LCD_F_CSSEL0_CSS22 ((uint32_t)0x00400000) /*!< L22 Com Seg select */ 6662 /* LCD_F_CSSEL0[CSS23] Bits */ 6663 #define LCD_F_CSSEL0_CSS23_OFS (23) /*!< LCDCSS23 Bit Offset */ 6664 #define LCD_F_CSSEL0_CSS23 ((uint32_t)0x00800000) /*!< L23 Com Seg select */ 6665 /* LCD_F_CSSEL0[CSS24] Bits */ 6666 #define LCD_F_CSSEL0_CSS24_OFS (24) /*!< LCDCSS24 Bit Offset */ 6667 #define LCD_F_CSSEL0_CSS24 ((uint32_t)0x01000000) /*!< L24 Com Seg select */ 6668 /* LCD_F_CSSEL0[CSS25] Bits */ 6669 #define LCD_F_CSSEL0_CSS25_OFS (25) /*!< LCDCSS25 Bit Offset */ 6670 #define LCD_F_CSSEL0_CSS25 ((uint32_t)0x02000000) /*!< L25 Com Seg select */ 6671 /* LCD_F_CSSEL0[CSS26] Bits */ 6672 #define LCD_F_CSSEL0_CSS26_OFS (26) /*!< LCDCSS26 Bit Offset */ 6673 #define LCD_F_CSSEL0_CSS26 ((uint32_t)0x04000000) /*!< L26 Com Seg select */ 6674 /* LCD_F_CSSEL0[CSS27] Bits */ 6675 #define LCD_F_CSSEL0_CSS27_OFS (27) /*!< LCDCSS27 Bit Offset */ 6676 #define LCD_F_CSSEL0_CSS27 ((uint32_t)0x08000000) /*!< L27 Com Seg select */ 6677 /* LCD_F_CSSEL0[CSS28] Bits */ 6678 #define LCD_F_CSSEL0_CSS28_OFS (28) /*!< LCDCSS28 Bit Offset */ 6679 #define LCD_F_CSSEL0_CSS28 ((uint32_t)0x10000000) /*!< L28 Com Seg select */ 6680 /* LCD_F_CSSEL0[CSS29] Bits */ 6681 #define LCD_F_CSSEL0_CSS29_OFS (29) /*!< LCDCSS29 Bit Offset */ 6682 #define LCD_F_CSSEL0_CSS29 ((uint32_t)0x20000000) /*!< L29 Com Seg select */ 6683 /* LCD_F_CSSEL0[CSS30] Bits */ 6684 #define LCD_F_CSSEL0_CSS30_OFS (30) /*!< LCDCSS30 Bit Offset */ 6685 #define LCD_F_CSSEL0_CSS30 ((uint32_t)0x40000000) /*!< L30 Com Seg select */ 6686 /* LCD_F_CSSEL0[CSS31] Bits */ 6687 #define LCD_F_CSSEL0_CSS31_OFS (31) /*!< LCDCSS31 Bit Offset */ 6688 #define LCD_F_CSSEL0_CSS31 ((uint32_t)0x80000000) /*!< L31 Com Seg select */ 6689 /* LCD_F_CSSEL1[CSS32] Bits */ 6690 #define LCD_F_CSSEL1_CSS32_OFS ( 0) /*!< LCDCSS32 Bit Offset */ 6691 #define LCD_F_CSSEL1_CSS32 ((uint32_t)0x00000001) /*!< L32 Com Seg select */ 6692 /* LCD_F_CSSEL1[CSS33] Bits */ 6693 #define LCD_F_CSSEL1_CSS33_OFS ( 1) /*!< LCDCSS33 Bit Offset */ 6694 #define LCD_F_CSSEL1_CSS33 ((uint32_t)0x00000002) /*!< L33 Com Seg select */ 6695 /* LCD_F_CSSEL1[CSS34] Bits */ 6696 #define LCD_F_CSSEL1_CSS34_OFS ( 2) /*!< LCDCSS34 Bit Offset */ 6697 #define LCD_F_CSSEL1_CSS34 ((uint32_t)0x00000004) /*!< L34 Com Seg select */ 6698 /* LCD_F_CSSEL1[CSS35] Bits */ 6699 #define LCD_F_CSSEL1_CSS35_OFS ( 3) /*!< LCDCSS35 Bit Offset */ 6700 #define LCD_F_CSSEL1_CSS35 ((uint32_t)0x00000008) /*!< L35 Com Seg select */ 6701 /* LCD_F_CSSEL1[CSS36] Bits */ 6702 #define LCD_F_CSSEL1_CSS36_OFS ( 4) /*!< LCDCSS36 Bit Offset */ 6703 #define LCD_F_CSSEL1_CSS36 ((uint32_t)0x00000010) /*!< L36 Com Seg select */ 6704 /* LCD_F_CSSEL1[CSS37] Bits */ 6705 #define LCD_F_CSSEL1_CSS37_OFS ( 5) /*!< LCDCSS37 Bit Offset */ 6706 #define LCD_F_CSSEL1_CSS37 ((uint32_t)0x00000020) /*!< L37 Com Seg select */ 6707 /* LCD_F_CSSEL1[CSS38] Bits */ 6708 #define LCD_F_CSSEL1_CSS38_OFS ( 6) /*!< LCDCSS38 Bit Offset */ 6709 #define LCD_F_CSSEL1_CSS38 ((uint32_t)0x00000040) /*!< L38 Com Seg select */ 6710 /* LCD_F_CSSEL1[CSS39] Bits */ 6711 #define LCD_F_CSSEL1_CSS39_OFS ( 7) /*!< LCDCSS39 Bit Offset */ 6712 #define LCD_F_CSSEL1_CSS39 ((uint32_t)0x00000080) /*!< L39 Com Seg select */ 6713 /* LCD_F_CSSEL1[CSS40] Bits */ 6714 #define LCD_F_CSSEL1_CSS40_OFS ( 8) /*!< LCDCSS40 Bit Offset */ 6715 #define LCD_F_CSSEL1_CSS40 ((uint32_t)0x00000100) /*!< L40 Com Seg select */ 6716 /* LCD_F_CSSEL1[CSS41] Bits */ 6717 #define LCD_F_CSSEL1_CSS41_OFS ( 9) /*!< LCDCSS41 Bit Offset */ 6718 #define LCD_F_CSSEL1_CSS41 ((uint32_t)0x00000200) /*!< L41 Com Seg select */ 6719 /* LCD_F_CSSEL1[CSS42] Bits */ 6720 #define LCD_F_CSSEL1_CSS42_OFS (10) /*!< LCDCSS42 Bit Offset */ 6721 #define LCD_F_CSSEL1_CSS42 ((uint32_t)0x00000400) /*!< L42 Com Seg select */ 6722 /* LCD_F_CSSEL1[CSS43] Bits */ 6723 #define LCD_F_CSSEL1_CSS43_OFS (11) /*!< LCDCSS43 Bit Offset */ 6724 #define LCD_F_CSSEL1_CSS43 ((uint32_t)0x00000800) /*!< L43 Com Seg select */ 6725 /* LCD_F_CSSEL1[CSS44] Bits */ 6726 #define LCD_F_CSSEL1_CSS44_OFS (12) /*!< LCDCSS44 Bit Offset */ 6727 #define LCD_F_CSSEL1_CSS44 ((uint32_t)0x00001000) /*!< L44 Com Seg select */ 6728 /* LCD_F_CSSEL1[CSS45] Bits */ 6729 #define LCD_F_CSSEL1_CSS45_OFS (13) /*!< LCDCSS45 Bit Offset */ 6730 #define LCD_F_CSSEL1_CSS45 ((uint32_t)0x00002000) /*!< L45 Com Seg select */ 6731 /* LCD_F_CSSEL1[CSS46] Bits */ 6732 #define LCD_F_CSSEL1_CSS46_OFS (14) /*!< LCDCSS46 Bit Offset */ 6733 #define LCD_F_CSSEL1_CSS46 ((uint32_t)0x00004000) /*!< L46 Com Seg select */ 6734 /* LCD_F_CSSEL1[CSS47] Bits */ 6735 #define LCD_F_CSSEL1_CSS47_OFS (15) /*!< LCDCSS47 Bit Offset */ 6736 #define LCD_F_CSSEL1_CSS47 ((uint32_t)0x00008000) /*!< L47 Com Seg select */ 6737 /* LCD_F_CSSEL1[CSS48] Bits */ 6738 #define LCD_F_CSSEL1_CSS48_OFS (16) /*!< LCDCSS48 Bit Offset */ 6739 #define LCD_F_CSSEL1_CSS48 ((uint32_t)0x00010000) /*!< L48 Com Seg select */ 6740 /* LCD_F_CSSEL1[CSS49] Bits */ 6741 #define LCD_F_CSSEL1_CSS49_OFS (17) /*!< LCDCSS49 Bit Offset */ 6742 #define LCD_F_CSSEL1_CSS49 ((uint32_t)0x00020000) /*!< L49 Com Seg select */ 6743 /* LCD_F_CSSEL1[CSS50] Bits */ 6744 #define LCD_F_CSSEL1_CSS50_OFS (18) /*!< LCDCSS50 Bit Offset */ 6745 #define LCD_F_CSSEL1_CSS50 ((uint32_t)0x00040000) /*!< L50 Com Seg select */ 6746 /* LCD_F_CSSEL1[CSS51] Bits */ 6747 #define LCD_F_CSSEL1_CSS51_OFS (19) /*!< LCDCSS51 Bit Offset */ 6748 #define LCD_F_CSSEL1_CSS51 ((uint32_t)0x00080000) /*!< L51 Com Seg select */ 6749 /* LCD_F_CSSEL1[CSS52] Bits */ 6750 #define LCD_F_CSSEL1_CSS52_OFS (20) /*!< LCDCSS52 Bit Offset */ 6751 #define LCD_F_CSSEL1_CSS52 ((uint32_t)0x00100000) /*!< L52 Com Seg select */ 6752 /* LCD_F_CSSEL1[CSS53] Bits */ 6753 #define LCD_F_CSSEL1_CSS53_OFS (21) /*!< LCDCSS53 Bit Offset */ 6754 #define LCD_F_CSSEL1_CSS53 ((uint32_t)0x00200000) /*!< L53 Com Seg select */ 6755 /* LCD_F_CSSEL1[CSS54] Bits */ 6756 #define LCD_F_CSSEL1_CSS54_OFS (22) /*!< LCDCSS54 Bit Offset */ 6757 #define LCD_F_CSSEL1_CSS54 ((uint32_t)0x00400000) /*!< L54 Com Seg select */ 6758 /* LCD_F_CSSEL1[CSS55] Bits */ 6759 #define LCD_F_CSSEL1_CSS55_OFS (23) /*!< LCDCSS55 Bit Offset */ 6760 #define LCD_F_CSSEL1_CSS55 ((uint32_t)0x00800000) /*!< L55 Com Seg select */ 6761 /* LCD_F_CSSEL1[CSS56] Bits */ 6762 #define LCD_F_CSSEL1_CSS56_OFS (24) /*!< LCDCSS56 Bit Offset */ 6763 #define LCD_F_CSSEL1_CSS56 ((uint32_t)0x01000000) /*!< L56 Com Seg select */ 6764 /* LCD_F_CSSEL1[CSS57] Bits */ 6765 #define LCD_F_CSSEL1_CSS57_OFS (25) /*!< LCDCSS57 Bit Offset */ 6766 #define LCD_F_CSSEL1_CSS57 ((uint32_t)0x02000000) /*!< L57 Com Seg select */ 6767 /* LCD_F_CSSEL1[CSS58] Bits */ 6768 #define LCD_F_CSSEL1_CSS58_OFS (26) /*!< LCDCSS58 Bit Offset */ 6769 #define LCD_F_CSSEL1_CSS58 ((uint32_t)0x04000000) /*!< L58 Com Seg select */ 6770 /* LCD_F_CSSEL1[CSS59] Bits */ 6771 #define LCD_F_CSSEL1_CSS59_OFS (27) /*!< LCDCSS59 Bit Offset */ 6772 #define LCD_F_CSSEL1_CSS59 ((uint32_t)0x08000000) /*!< L59 Com Seg select */ 6773 /* LCD_F_CSSEL1[CSS60] Bits */ 6774 #define LCD_F_CSSEL1_CSS60_OFS (28) /*!< LCDCSS60 Bit Offset */ 6775 #define LCD_F_CSSEL1_CSS60 ((uint32_t)0x10000000) /*!< L60 Com Seg select */ 6776 /* LCD_F_CSSEL1[CSS61] Bits */ 6777 #define LCD_F_CSSEL1_CSS61_OFS (29) /*!< LCDCSS61 Bit Offset */ 6778 #define LCD_F_CSSEL1_CSS61 ((uint32_t)0x20000000) /*!< L61 Com Seg select */ 6779 /* LCD_F_CSSEL1[CSS62] Bits */ 6780 #define LCD_F_CSSEL1_CSS62_OFS (30) /*!< LCDCSS62 Bit Offset */ 6781 #define LCD_F_CSSEL1_CSS62 ((uint32_t)0x40000000) /*!< L62 Com Seg select */ 6782 /* LCD_F_CSSEL1[CSS63] Bits */ 6783 #define LCD_F_CSSEL1_CSS63_OFS (31) /*!< LCDCSS63 Bit Offset */ 6784 #define LCD_F_CSSEL1_CSS63 ((uint32_t)0x80000000) /*!< L63 Com Seg select */ 6785 /* LCD_F_ANMCTL[ANMEN] Bits */ 6786 #define LCD_F_ANMCTL_ANMEN_OFS ( 0) /*!< LCDANMEN Bit Offset */ 6787 #define LCD_F_ANMCTL_ANMEN ((uint32_t)0x00000001) /*!< Enable Animation */ 6788 /* LCD_F_ANMCTL[ANMSTP] Bits */ 6789 #define LCD_F_ANMCTL_ANMSTP_OFS ( 1) /*!< LCDANMSTP Bit Offset */ 6790 #define LCD_F_ANMCTL_ANMSTP_MASK ((uint32_t)0x0000000E) /*!< LCDANMSTP Bit Mask */ 6791 #define LCD_F_ANMCTL_ANMSTP0 ((uint32_t)0x00000002) /*!< ANMSTP Bit 0 */ 6792 #define LCD_F_ANMCTL_ANMSTP1 ((uint32_t)0x00000004) /*!< ANMSTP Bit 1 */ 6793 #define LCD_F_ANMCTL_ANMSTP2 ((uint32_t)0x00000008) /*!< ANMSTP Bit 2 */ 6794 #define LCD_F_ANMCTL_ANMSTP_0 ((uint32_t)0x00000000) /*!< T0 */ 6795 #define LCD_F_ANMCTL_ANMSTP_1 ((uint32_t)0x00000002) /*!< T0 to T1 */ 6796 #define LCD_F_ANMCTL_ANMSTP_2 ((uint32_t)0x00000004) /*!< T0 to T2 */ 6797 #define LCD_F_ANMCTL_ANMSTP_3 ((uint32_t)0x00000006) /*!< T0 to T3 */ 6798 #define LCD_F_ANMCTL_ANMSTP_4 ((uint32_t)0x00000008) /*!< T0 to T4 */ 6799 #define LCD_F_ANMCTL_ANMSTP_5 ((uint32_t)0x0000000A) /*!< T0 to T5 */ 6800 #define LCD_F_ANMCTL_ANMSTP_6 ((uint32_t)0x0000000C) /*!< T0 to T6 */ 6801 #define LCD_F_ANMCTL_ANMSTP_7 ((uint32_t)0x0000000E) /*!< T0 to T7 */ 6802 /* LCD_F_ANMCTL[ANMCLR] Bits */ 6803 #define LCD_F_ANMCTL_ANMCLR_OFS ( 7) /*!< LCDANMCLR Bit Offset */ 6804 #define LCD_F_ANMCTL_ANMCLR ((uint32_t)0x00000080) /*!< Clear Animation Memory */ 6805 /* LCD_F_ANMCTL[ANMPRE] Bits */ 6806 #define LCD_F_ANMCTL_ANMPRE_OFS (16) /*!< LCDANMPREx Bit Offset */ 6807 #define LCD_F_ANMCTL_ANMPRE_MASK ((uint32_t)0x00070000) /*!< LCDANMPREx Bit Mask */ 6808 #define LCD_F_ANMCTL_ANMPRE0 ((uint32_t)0x00010000) /*!< ANMPRE Bit 0 */ 6809 #define LCD_F_ANMCTL_ANMPRE1 ((uint32_t)0x00020000) /*!< ANMPRE Bit 1 */ 6810 #define LCD_F_ANMCTL_ANMPRE2 ((uint32_t)0x00040000) /*!< ANMPRE Bit 2 */ 6811 #define LCD_F_ANMCTL_ANMPRE_0 ((uint32_t)0x00000000) /*!< Divide by 512 */ 6812 #define LCD_F_ANMCTL_ANMPRE_1 ((uint32_t)0x00010000) /*!< Divide by 1024 */ 6813 #define LCD_F_ANMCTL_ANMPRE_2 ((uint32_t)0x00020000) /*!< Divide by 2048 */ 6814 #define LCD_F_ANMCTL_ANMPRE_3 ((uint32_t)0x00030000) /*!< Divide by 4096 */ 6815 #define LCD_F_ANMCTL_ANMPRE_4 ((uint32_t)0x00040000) /*!< Divide by 8162 */ 6816 #define LCD_F_ANMCTL_ANMPRE_5 ((uint32_t)0x00050000) /*!< Divide by 16384 */ 6817 #define LCD_F_ANMCTL_ANMPRE_6 ((uint32_t)0x00060000) /*!< Divide by 32768 */ 6818 #define LCD_F_ANMCTL_ANMPRE_7 ((uint32_t)0x00070000) /*!< Divide by 65536 */ 6819 /* LCD_F_ANMCTL[ANMDIV] Bits */ 6820 #define LCD_F_ANMCTL_ANMDIV_OFS (19) /*!< LCDANMDIVx Bit Offset */ 6821 #define LCD_F_ANMCTL_ANMDIV_MASK ((uint32_t)0x00380000) /*!< LCDANMDIVx Bit Mask */ 6822 #define LCD_F_ANMCTL_ANMDIV0 ((uint32_t)0x00080000) /*!< ANMDIV Bit 0 */ 6823 #define LCD_F_ANMCTL_ANMDIV1 ((uint32_t)0x00100000) /*!< ANMDIV Bit 1 */ 6824 #define LCD_F_ANMCTL_ANMDIV2 ((uint32_t)0x00200000) /*!< ANMDIV Bit 2 */ 6825 #define LCD_F_ANMCTL_ANMDIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ 6826 #define LCD_F_ANMCTL_ANMDIV_1 ((uint32_t)0x00080000) /*!< Divide by 2 */ 6827 #define LCD_F_ANMCTL_ANMDIV_2 ((uint32_t)0x00100000) /*!< Divide by 3 */ 6828 #define LCD_F_ANMCTL_ANMDIV_3 ((uint32_t)0x00180000) /*!< Divide by 4 */ 6829 #define LCD_F_ANMCTL_ANMDIV_4 ((uint32_t)0x00200000) /*!< Divide by 5 */ 6830 #define LCD_F_ANMCTL_ANMDIV_5 ((uint32_t)0x00280000) /*!< Divide by 6 */ 6831 #define LCD_F_ANMCTL_ANMDIV_6 ((uint32_t)0x00300000) /*!< Divide by 7 */ 6832 #define LCD_F_ANMCTL_ANMDIV_7 ((uint32_t)0x00380000) /*!< Divide by 8 */ 6833 /* LCD_F_IE[BLKOFFIE] Bits */ 6834 #define LCD_F_IE_BLKOFFIE_OFS ( 1) /*!< LCDBLKOFFIE Bit Offset */ 6835 #define LCD_F_IE_BLKOFFIE ((uint32_t)0x00000002) /*!< LCD Blink, segments off interrupt enable */ 6836 /* LCD_F_IE[BLKONIE] Bits */ 6837 #define LCD_F_IE_BLKONIE_OFS ( 2) /*!< LCDBLKONIE Bit Offset */ 6838 #define LCD_F_IE_BLKONIE ((uint32_t)0x00000004) /*!< LCD Blink, segments on interrupt enable */ 6839 /* LCD_F_IE[FRMIE] Bits */ 6840 #define LCD_F_IE_FRMIE_OFS ( 3) /*!< LCDFRMIE Bit Offset */ 6841 #define LCD_F_IE_FRMIE ((uint32_t)0x00000008) /*!< LCD Frame interrupt enable */ 6842 /* LCD_F_IE[ANMSTPIE] Bits */ 6843 #define LCD_F_IE_ANMSTPIE_OFS ( 8) /*!< LCDANMSTPIE Bit Offset */ 6844 #define LCD_F_IE_ANMSTPIE ((uint32_t)0x00000100) /*!< LCD Animation step interrupt enable */ 6845 /* LCD_F_IE[ANMLOOPIE] Bits */ 6846 #define LCD_F_IE_ANMLOOPIE_OFS ( 9) /*!< LCDANMLOOPIE Bit Offset */ 6847 #define LCD_F_IE_ANMLOOPIE ((uint32_t)0x00000200) /*!< LCD Animation loop interrupt enable */ 6848 /* LCD_F_IFG[BLKOFFIFG] Bits */ 6849 #define LCD_F_IFG_BLKOFFIFG_OFS ( 1) /*!< LCDBLKOFFIFG Bit Offset */ 6850 #define LCD_F_IFG_BLKOFFIFG ((uint32_t)0x00000002) /*!< LCD Blink, segments off interrupt flag */ 6851 /* LCD_F_IFG[BLKONIFG] Bits */ 6852 #define LCD_F_IFG_BLKONIFG_OFS ( 2) /*!< LCDBLKONIFG Bit Offset */ 6853 #define LCD_F_IFG_BLKONIFG ((uint32_t)0x00000004) /*!< LCD Blink, segments on interrupt flag */ 6854 /* LCD_F_IFG[FRMIFG] Bits */ 6855 #define LCD_F_IFG_FRMIFG_OFS ( 3) /*!< LCDFRMIFG Bit Offset */ 6856 #define LCD_F_IFG_FRMIFG ((uint32_t)0x00000008) /*!< LCD Frame interrupt flag */ 6857 /* LCD_F_IFG[ANMSTPIFG] Bits */ 6858 #define LCD_F_IFG_ANMSTPIFG_OFS ( 8) /*!< LCDANMSTPIFG Bit Offset */ 6859 #define LCD_F_IFG_ANMSTPIFG ((uint32_t)0x00000100) /*!< LCD Animation step interrupt flag */ 6860 /* LCD_F_IFG[ANMLOOPIFG] Bits */ 6861 #define LCD_F_IFG_ANMLOOPIFG_OFS ( 9) /*!< LCDANMLOOPIFG Bit Offset */ 6862 #define LCD_F_IFG_ANMLOOPIFG ((uint32_t)0x00000200) /*!< LCD Animation loop interrupt flag */ 6863 /* LCD_F_SETIFG[SETLCDBLKOFFIFG] Bits */ 6864 #define LCD_F_SETIFG_SETLCDBLKOFFIFG_OFS ( 1) /*!< SETLCDBLKOFFIFG Bit Offset */ 6865 #define LCD_F_SETIFG_SETLCDBLKOFFIFG ((uint32_t)0x00000002) /*!< Sets LCDBLKOFFIFG */ 6866 /* LCD_F_SETIFG[SETLCDBLKONIFG] Bits */ 6867 #define LCD_F_SETIFG_SETLCDBLKONIFG_OFS ( 2) /*!< SETLCDBLKONIFG Bit Offset */ 6868 #define LCD_F_SETIFG_SETLCDBLKONIFG ((uint32_t)0x00000004) /*!< Sets LCDBLKONIFG */ 6869 /* LCD_F_SETIFG[SETLCDFRMIFG] Bits */ 6870 #define LCD_F_SETIFG_SETLCDFRMIFG_OFS ( 3) /*!< SETLCDFRMIFG Bit Offset */ 6871 #define LCD_F_SETIFG_SETLCDFRMIFG ((uint32_t)0x00000008) /*!< Sets LCDFRMIFG */ 6872 /* LCD_F_SETIFG[SETLCDANMSTPIFG] Bits */ 6873 #define LCD_F_SETIFG_SETLCDANMSTPIFG_OFS ( 8) /*!< SETLCDANMSTPIFG Bit Offset */ 6874 #define LCD_F_SETIFG_SETLCDANMSTPIFG ((uint32_t)0x00000100) /*!< Sets LCDANMSTPIFG */ 6875 /* LCD_F_SETIFG[SETLCDANMLOOPIFG] Bits */ 6876 #define LCD_F_SETIFG_SETLCDANMLOOPIFG_OFS ( 9) /*!< SETLCDANMLOOPIFG Bit Offset */ 6877 #define LCD_F_SETIFG_SETLCDANMLOOPIFG ((uint32_t)0x00000200) /*!< Sets LCDANMLOOPIFG */ 6878 /* LCD_F_CLRIFG[CLRLCDBLKOFFIFG] Bits */ 6879 #define LCD_F_CLRIFG_CLRLCDBLKOFFIFG_OFS ( 1) /*!< CLRLCDBLKOFFIFG Bit Offset */ 6880 #define LCD_F_CLRIFG_CLRLCDBLKOFFIFG ((uint32_t)0x00000002) /*!< Clears LCDBLKOFFIFG */ 6881 /* LCD_F_CLRIFG[CLRLCDBLKONIFG] Bits */ 6882 #define LCD_F_CLRIFG_CLRLCDBLKONIFG_OFS ( 2) /*!< CLRLCDBLKONIFG Bit Offset */ 6883 #define LCD_F_CLRIFG_CLRLCDBLKONIFG ((uint32_t)0x00000004) /*!< Clears LCDBLKONIFG */ 6884 /* LCD_F_CLRIFG[CLRLCDFRMIFG] Bits */ 6885 #define LCD_F_CLRIFG_CLRLCDFRMIFG_OFS ( 3) /*!< CLRLCDFRMIFG Bit Offset */ 6886 #define LCD_F_CLRIFG_CLRLCDFRMIFG ((uint32_t)0x00000008) /*!< Clears LCDFRMIFG */ 6887 /* LCD_F_CLRIFG[CLRLCDANMSTPIFG] Bits */ 6888 #define LCD_F_CLRIFG_CLRLCDANMSTPIFG_OFS ( 8) /*!< CLRLCDANMSTPIFG Bit Offset */ 6889 #define LCD_F_CLRIFG_CLRLCDANMSTPIFG ((uint32_t)0x00000100) /*!< Clears LCDANMSTPIFG */ 6890 /* LCD_F_CLRIFG[CLRLCDANMLOOPIFG] Bits */ 6891 #define LCD_F_CLRIFG_CLRLCDANMLOOPIFG_OFS ( 9) /*!< CLRLCDANMLOOPIFG Bit Offset */ 6892 #define LCD_F_CLRIFG_CLRLCDANMLOOPIFG ((uint32_t)0x00000200) /*!< Clears LCDANMLOOPIFG */ 6893 6894 /****************************************************************************** 6895 * MPU Bits 6896 ******************************************************************************/ 6897 6898 /* Pre-defined bitfield values */ 6899 6900 /* MPU_RASR_SIZE Bitfield Bits */ 6901 #define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /*!< 32B */ 6902 #define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /*!< 64B */ 6903 #define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /*!< 128B */ 6904 #define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /*!< 256B */ 6905 #define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /*!< 512B */ 6906 #define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /*!< 1KB */ 6907 #define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /*!< 2KB */ 6908 #define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /*!< 4KB */ 6909 #define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /*!< 8KB */ 6910 #define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /*!< 16KB */ 6911 #define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /*!< 32KB */ 6912 #define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /*!< 64KB */ 6913 #define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /*!< 128KB */ 6914 #define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /*!< 256KB */ 6915 #define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /*!< 512KB */ 6916 #define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /*!< 1MB */ 6917 #define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /*!< 2MB */ 6918 #define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /*!< 4MB */ 6919 #define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /*!< 8MB */ 6920 #define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /*!< 16MB */ 6921 #define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /*!< 32MB */ 6922 #define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /*!< 64MB */ 6923 #define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /*!< 128MB */ 6924 #define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /*!< 256MB */ 6925 #define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /*!< 512MB */ 6926 #define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /*!< 1GB */ 6927 #define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /*!< 2GB */ 6928 #define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /*!< 4GB */ 6929 6930 /* MPU_RASR_AP Bitfield Bits */ 6931 #define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /*!< Privileged permissions: No access. User permissions: No access. */ 6932 #define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /*!< Privileged permissions: Read-write. User permissions: No access. */ 6933 #define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /*!< Privileged permissions: Read-write. User permissions: Read-only. */ 6934 #define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /*!< Privileged permissions: Read-write. User permissions: Read-write. */ 6935 #define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /*!< Privileged permissions: Read-only. User permissions: No access. */ 6936 #define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /*!< Privileged permissions: Read-only. User permissions: Read-only. */ 6937 6938 /* MPU_RASR_XN Bitfield Bits */ 6939 #define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /*!< Instruction access enabled */ 6940 #define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /*!< Instruction access disabled */ 6941 6942 6943 /****************************************************************************** 6944 * NVIC Bits 6945 ******************************************************************************/ 6946 6947 /* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */ 6948 #define NVIC_IPR0_PRI_0_OFS ( 0) /*!< PRI_0 Offset */ 6949 #define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */ 6950 /* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */ 6951 #define NVIC_IPR0_PRI_1_OFS ( 8) /*!< PRI_1 Offset */ 6952 #define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */ 6953 /* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */ 6954 #define NVIC_IPR0_PRI_2_OFS (16) /*!< PRI_2 Offset */ 6955 #define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */ 6956 /* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */ 6957 #define NVIC_IPR0_PRI_3_OFS (24) /*!< PRI_3 Offset */ 6958 #define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */ 6959 /* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */ 6960 #define NVIC_IPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ 6961 #define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ 6962 /* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */ 6963 #define NVIC_IPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ 6964 #define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ 6965 /* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */ 6966 #define NVIC_IPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ 6967 #define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ 6968 /* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */ 6969 #define NVIC_IPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ 6970 #define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */ 6971 /* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */ 6972 #define NVIC_IPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ 6973 #define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ 6974 /* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */ 6975 #define NVIC_IPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ 6976 #define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ 6977 /* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */ 6978 #define NVIC_IPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ 6979 #define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ 6980 /* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */ 6981 #define NVIC_IPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ 6982 #define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */ 6983 /* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */ 6984 #define NVIC_IPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ 6985 #define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ 6986 /* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */ 6987 #define NVIC_IPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ 6988 #define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ 6989 /* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */ 6990 #define NVIC_IPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ 6991 #define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ 6992 /* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */ 6993 #define NVIC_IPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ 6994 #define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */ 6995 /* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */ 6996 #define NVIC_IPR4_PRI_16_OFS ( 0) /*!< PRI_16 Offset */ 6997 #define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */ 6998 /* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */ 6999 #define NVIC_IPR4_PRI_17_OFS ( 8) /*!< PRI_17 Offset */ 7000 #define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */ 7001 /* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */ 7002 #define NVIC_IPR4_PRI_18_OFS (16) /*!< PRI_18 Offset */ 7003 #define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */ 7004 /* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */ 7005 #define NVIC_IPR4_PRI_19_OFS (24) /*!< PRI_19 Offset */ 7006 #define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */ 7007 /* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */ 7008 #define NVIC_IPR5_PRI_20_OFS ( 0) /*!< PRI_20 Offset */ 7009 #define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */ 7010 /* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */ 7011 #define NVIC_IPR5_PRI_21_OFS ( 8) /*!< PRI_21 Offset */ 7012 #define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */ 7013 /* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */ 7014 #define NVIC_IPR5_PRI_22_OFS (16) /*!< PRI_22 Offset */ 7015 #define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */ 7016 /* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */ 7017 #define NVIC_IPR5_PRI_23_OFS (24) /*!< PRI_23 Offset */ 7018 #define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */ 7019 /* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */ 7020 #define NVIC_IPR6_PRI_24_OFS ( 0) /*!< PRI_24 Offset */ 7021 #define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */ 7022 /* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */ 7023 #define NVIC_IPR6_PRI_25_OFS ( 8) /*!< PRI_25 Offset */ 7024 #define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */ 7025 /* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */ 7026 #define NVIC_IPR6_PRI_26_OFS (16) /*!< PRI_26 Offset */ 7027 #define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */ 7028 /* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */ 7029 #define NVIC_IPR6_PRI_27_OFS (24) /*!< PRI_27 Offset */ 7030 #define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */ 7031 /* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */ 7032 #define NVIC_IPR7_PRI_28_OFS ( 0) /*!< PRI_28 Offset */ 7033 #define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */ 7034 /* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */ 7035 #define NVIC_IPR7_PRI_29_OFS ( 8) /*!< PRI_29 Offset */ 7036 #define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */ 7037 /* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */ 7038 #define NVIC_IPR7_PRI_30_OFS (16) /*!< PRI_30 Offset */ 7039 #define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */ 7040 /* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */ 7041 #define NVIC_IPR7_PRI_31_OFS (24) /*!< PRI_31 Offset */ 7042 #define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */ 7043 /* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */ 7044 #define NVIC_IPR8_PRI_32_OFS ( 0) /*!< PRI_32 Offset */ 7045 #define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */ 7046 /* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */ 7047 #define NVIC_IPR8_PRI_33_OFS ( 8) /*!< PRI_33 Offset */ 7048 #define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */ 7049 /* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */ 7050 #define NVIC_IPR8_PRI_34_OFS (16) /*!< PRI_34 Offset */ 7051 #define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */ 7052 /* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */ 7053 #define NVIC_IPR8_PRI_35_OFS (24) /*!< PRI_35 Offset */ 7054 #define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */ 7055 /* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */ 7056 #define NVIC_IPR9_PRI_36_OFS ( 0) /*!< PRI_36 Offset */ 7057 #define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */ 7058 /* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */ 7059 #define NVIC_IPR9_PRI_37_OFS ( 8) /*!< PRI_37 Offset */ 7060 #define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */ 7061 /* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */ 7062 #define NVIC_IPR9_PRI_38_OFS (16) /*!< PRI_38 Offset */ 7063 #define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */ 7064 /* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */ 7065 #define NVIC_IPR9_PRI_39_OFS (24) /*!< PRI_39 Offset */ 7066 #define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */ 7067 /* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */ 7068 #define NVIC_IPR10_PRI_40_OFS ( 0) /*!< PRI_40 Offset */ 7069 #define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */ 7070 /* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */ 7071 #define NVIC_IPR10_PRI_41_OFS ( 8) /*!< PRI_41 Offset */ 7072 #define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */ 7073 /* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */ 7074 #define NVIC_IPR10_PRI_42_OFS (16) /*!< PRI_42 Offset */ 7075 #define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */ 7076 /* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */ 7077 #define NVIC_IPR10_PRI_43_OFS (24) /*!< PRI_43 Offset */ 7078 #define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */ 7079 /* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */ 7080 #define NVIC_IPR11_PRI_44_OFS ( 0) /*!< PRI_44 Offset */ 7081 #define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */ 7082 /* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */ 7083 #define NVIC_IPR11_PRI_45_OFS ( 8) /*!< PRI_45 Offset */ 7084 #define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */ 7085 /* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */ 7086 #define NVIC_IPR11_PRI_46_OFS (16) /*!< PRI_46 Offset */ 7087 #define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */ 7088 /* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */ 7089 #define NVIC_IPR11_PRI_47_OFS (24) /*!< PRI_47 Offset */ 7090 #define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */ 7091 /* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */ 7092 #define NVIC_IPR12_PRI_48_OFS ( 0) /*!< PRI_48 Offset */ 7093 #define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */ 7094 /* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */ 7095 #define NVIC_IPR12_PRI_49_OFS ( 8) /*!< PRI_49 Offset */ 7096 #define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */ 7097 /* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */ 7098 #define NVIC_IPR12_PRI_50_OFS (16) /*!< PRI_50 Offset */ 7099 #define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */ 7100 /* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */ 7101 #define NVIC_IPR12_PRI_51_OFS (24) /*!< PRI_51 Offset */ 7102 #define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */ 7103 /* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */ 7104 #define NVIC_IPR13_PRI_52_OFS ( 0) /*!< PRI_52 Offset */ 7105 #define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */ 7106 /* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */ 7107 #define NVIC_IPR13_PRI_53_OFS ( 8) /*!< PRI_53 Offset */ 7108 #define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */ 7109 /* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */ 7110 #define NVIC_IPR13_PRI_54_OFS (16) /*!< PRI_54 Offset */ 7111 #define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */ 7112 /* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */ 7113 #define NVIC_IPR13_PRI_55_OFS (24) /*!< PRI_55 Offset */ 7114 #define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */ 7115 /* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */ 7116 #define NVIC_IPR14_PRI_56_OFS ( 0) /*!< PRI_56 Offset */ 7117 #define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */ 7118 /* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */ 7119 #define NVIC_IPR14_PRI_57_OFS ( 8) /*!< PRI_57 Offset */ 7120 #define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */ 7121 /* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */ 7122 #define NVIC_IPR14_PRI_58_OFS (16) /*!< PRI_58 Offset */ 7123 #define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */ 7124 /* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */ 7125 #define NVIC_IPR14_PRI_59_OFS (24) /*!< PRI_59 Offset */ 7126 #define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */ 7127 /* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */ 7128 #define NVIC_IPR15_PRI_60_OFS ( 0) /*!< PRI_60 Offset */ 7129 #define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */ 7130 /* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */ 7131 #define NVIC_IPR15_PRI_61_OFS ( 8) /*!< PRI_61 Offset */ 7132 #define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */ 7133 /* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */ 7134 #define NVIC_IPR15_PRI_62_OFS (16) /*!< PRI_62 Offset */ 7135 #define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */ 7136 /* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */ 7137 #define NVIC_IPR15_PRI_63_OFS (24) /*!< PRI_63 Offset */ 7138 #define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */ 7139 7140 7141 /****************************************************************************** 7142 * PCM Bits 7143 ******************************************************************************/ 7144 /* PCM_CTL0[AMR] Bits */ 7145 #define PCM_CTL0_AMR_OFS ( 0) /*!< AMR Bit Offset */ 7146 #define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /*!< AMR Bit Mask */ 7147 #define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /*!< AMR Bit 0 */ 7148 #define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /*!< AMR Bit 1 */ 7149 #define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /*!< AMR Bit 2 */ 7150 #define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /*!< AMR Bit 3 */ 7151 #define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 7152 #define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ 7153 #define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 7154 #define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 7155 #define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 7156 #define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 7157 #define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 7158 #define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ 7159 #define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 7160 #define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 7161 #define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 7162 #define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 7163 /* PCM_CTL0[LPMR] Bits */ 7164 #define PCM_CTL0_LPMR_OFS ( 4) /*!< LPMR Bit Offset */ 7165 #define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /*!< LPMR Bit Mask */ 7166 #define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /*!< LPMR Bit 0 */ 7167 #define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /*!< LPMR Bit 1 */ 7168 #define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /*!< LPMR Bit 2 */ 7169 #define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /*!< LPMR Bit 3 */ 7170 #define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ 7171 /* entered. */ 7172 #define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ 7173 #define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /*!< LPM4.5 */ 7174 #define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ 7175 /* entered. */ 7176 #define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ 7177 #define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /*!< LPM4.5 */ 7178 /* PCM_CTL0[CPM] Bits */ 7179 #define PCM_CTL0_CPM_OFS ( 8) /*!< CPM Bit Offset */ 7180 #define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /*!< CPM Bit Mask */ 7181 #define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /*!< CPM Bit 0 */ 7182 #define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /*!< CPM Bit 1 */ 7183 #define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /*!< CPM Bit 2 */ 7184 #define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /*!< CPM Bit 3 */ 7185 #define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /*!< CPM Bit 4 */ 7186 #define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /*!< CPM Bit 5 */ 7187 #define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 7188 #define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ 7189 #define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 7190 #define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 7191 #define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 7192 #define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 7193 #define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ 7194 #define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ 7195 #define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ 7196 #define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ 7197 #define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ 7198 #define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ 7199 #define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /*!< LPM3 */ 7200 #define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 7201 #define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ 7202 #define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 7203 #define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 7204 #define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 7205 #define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 7206 #define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ 7207 #define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ 7208 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ 7209 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ 7210 #define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ 7211 #define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ 7212 #define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /*!< LPM3 */ 7213 /* PCM_CTL0[KEY] Bits */ 7214 #define PCM_CTL0_KEY_OFS (16) /*!< PCMKEY Bit Offset */ 7215 #define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ 7216 /* PCM_CTL1[LOCKLPM5] Bits */ 7217 #define PCM_CTL1_LOCKLPM5_OFS ( 0) /*!< LOCKLPM5 Bit Offset */ 7218 #define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /*!< Lock LPM5 */ 7219 /* PCM_CTL1[LOCKBKUP] Bits */ 7220 #define PCM_CTL1_LOCKBKUP_OFS ( 1) /*!< LOCKBKUP Bit Offset */ 7221 #define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /*!< Lock Backup */ 7222 /* PCM_CTL1[FORCE_LPM_ENTRY] Bits */ 7223 #define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /*!< FORCE_LPM_ENTRY Bit Offset */ 7224 #define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /*!< Force LPM entry */ 7225 /* PCM_CTL1[PMR_BUSY] Bits */ 7226 #define PCM_CTL1_PMR_BUSY_OFS ( 8) /*!< PMR_BUSY Bit Offset */ 7227 #define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /*!< Power mode request busy flag */ 7228 /* PCM_CTL1[KEY] Bits */ 7229 #define PCM_CTL1_KEY_OFS (16) /*!< PCMKEY Bit Offset */ 7230 #define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ 7231 /* PCM_IE[LPM_INVALID_TR_IE] Bits */ 7232 #define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /*!< LPM_INVALID_TR_IE Bit Offset */ 7233 #define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /*!< LPM invalid transition interrupt enable */ 7234 /* PCM_IE[LPM_INVALID_CLK_IE] Bits */ 7235 #define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /*!< LPM_INVALID_CLK_IE Bit Offset */ 7236 #define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /*!< LPM invalid clock interrupt enable */ 7237 /* PCM_IE[AM_INVALID_TR_IE] Bits */ 7238 #define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /*!< AM_INVALID_TR_IE Bit Offset */ 7239 #define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /*!< Active mode invalid transition interrupt enable */ 7240 /* PCM_IE[DCDC_ERROR_IE] Bits */ 7241 #define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /*!< DCDC_ERROR_IE Bit Offset */ 7242 #define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /*!< DC-DC error interrupt enable */ 7243 /* PCM_IFG[LPM_INVALID_TR_IFG] Bits */ 7244 #define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /*!< LPM_INVALID_TR_IFG Bit Offset */ 7245 #define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< LPM invalid transition flag */ 7246 /* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */ 7247 #define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< LPM_INVALID_CLK_IFG Bit Offset */ 7248 #define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< LPM invalid clock flag */ 7249 /* PCM_IFG[AM_INVALID_TR_IFG] Bits */ 7250 #define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /*!< AM_INVALID_TR_IFG Bit Offset */ 7251 #define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Active mode invalid transition flag */ 7252 /* PCM_IFG[DCDC_ERROR_IFG] Bits */ 7253 #define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /*!< DCDC_ERROR_IFG Bit Offset */ 7254 #define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< DC-DC error flag */ 7255 /* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */ 7256 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */ 7257 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< Clear LPM invalid transition flag */ 7258 /* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */ 7259 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */ 7260 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< Clear LPM invalid clock flag */ 7261 /* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */ 7262 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /*!< CLR_AM_INVALID_TR_IFG Bit Offset */ 7263 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Clear active mode invalid transition flag */ 7264 /* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */ 7265 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /*!< CLR_DCDC_ERROR_IFG Bit Offset */ 7266 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< Clear DC-DC error flag */ 7267 /* Pre-defined bitfield values */ 7268 #define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ 7269 #define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ 7270 7271 7272 /****************************************************************************** 7273 * PMAP Bits 7274 ******************************************************************************/ 7275 /* PMAP_CTL[LOCKED] Bits */ 7276 #define PMAP_CTL_LOCKED_OFS ( 0) /*!< PMAPLOCKED Bit Offset */ 7277 #define PMAP_CTL_LOCKED ((uint16_t)0x0001) /*!< Port mapping lock bit */ 7278 /* PMAP_CTL[PRECFG] Bits */ 7279 #define PMAP_CTL_PRECFG_OFS ( 1) /*!< PMAPRECFG Bit Offset */ 7280 #define PMAP_CTL_PRECFG ((uint16_t)0x0002) /*!< Port mapping reconfiguration control bit */ 7281 /* Pre-defined bitfield values */ 7282 #define PMAP_NONE 0 7283 #define PMAP_UCA0CLK 1 7284 #define PMAP_UCA0RXD 2 7285 #define PMAP_UCA0SOMI 2 7286 #define PMAP_UCA0TXD 3 7287 #define PMAP_UCA0SIMO 3 7288 #define PMAP_UCB0CLK 4 7289 #define PMAP_UCB0SDA 5 7290 #define PMAP_UCB0SIMO 5 7291 #define PMAP_UCB0SCL 6 7292 #define PMAP_UCB0SOMI 6 7293 #define PMAP_UCA1STE 7 7294 #define PMAP_UCA1CLK 8 7295 #define PMAP_UCA1RXD 9 7296 #define PMAP_UCA1SOMI 9 7297 #define PMAP_UCA1TXD 10 7298 #define PMAP_UCA1SIMO 10 7299 #define PMAP_UCA2STE 11 7300 #define PMAP_UCA2CLK 12 7301 #define PMAP_UCA2RXD 13 7302 #define PMAP_UCA2SOMI 13 7303 #define PMAP_UCA2TXD 14 7304 #define PMAP_UCA2SIMO 14 7305 #define PMAP_UCB2STE 15 7306 #define PMAP_UCB2CLK 16 7307 #define PMAP_UCB2SDA 17 7308 #define PMAP_UCB2SIMO 17 7309 #define PMAP_UCB2SCL 18 7310 #define PMAP_UCB2SOMI 18 7311 #define PMAP_TA0CCR0A 19 7312 #define PMAP_TA0CCR1A 20 7313 #define PMAP_TA0CCR2A 21 7314 #define PMAP_TA0CCR3A 22 7315 #define PMAP_TA0CCR4A 23 7316 #define PMAP_TA1CCR1A 24 7317 #define PMAP_TA1CCR2A 25 7318 #define PMAP_TA1CCR3A 26 7319 #define PMAP_TA1CCR4A 27 7320 #define PMAP_TA0CLK 28 7321 #define PMAP_CE0OUT 28 7322 #define PMAP_TA1CLK 29 7323 #define PMAP_CE1OUT 29 7324 #define PMAP_DMAE0 30 7325 #define PMAP_SMCLK 30 7326 #define PMAP_ANALOG 31 7327 7328 #define PMAP_KEYID_VAL ((uint16_t)0x2D52) /*!< Port Mapping Key */ 7329 7330 7331 /****************************************************************************** 7332 * PSS Bits 7333 ******************************************************************************/ 7334 /* PSS_KEY[KEY] Bits */ 7335 #define PSS_KEY_KEY_OFS ( 0) /*!< PSSKEY Bit Offset */ 7336 #define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< PSSKEY Bit Mask */ 7337 /* PSS_CTL0[SVSMHOFF] Bits */ 7338 #define PSS_CTL0_SVSMHOFF_OFS ( 0) /*!< SVSMHOFF Bit Offset */ 7339 #define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /*!< SVSM high-side off */ 7340 /* PSS_CTL0[SVSMHLP] Bits */ 7341 #define PSS_CTL0_SVSMHLP_OFS ( 1) /*!< SVSMHLP Bit Offset */ 7342 #define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /*!< SVSM high-side low power normal performance mode */ 7343 /* PSS_CTL0[SVSMHS] Bits */ 7344 #define PSS_CTL0_SVSMHS_OFS ( 2) /*!< SVSMHS Bit Offset */ 7345 #define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /*!< Supply supervisor or monitor selection for the high-side */ 7346 /* PSS_CTL0[SVSMHTH] Bits */ 7347 #define PSS_CTL0_SVSMHTH_OFS ( 3) /*!< SVSMHTH Bit Offset */ 7348 #define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /*!< SVSMHTH Bit Mask */ 7349 /* PSS_CTL0[SVMHOE] Bits */ 7350 #define PSS_CTL0_SVMHOE_OFS ( 6) /*!< SVMHOE Bit Offset */ 7351 #define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /*!< SVSM high-side output enable */ 7352 /* PSS_CTL0[SVMHOUTPOLAL] Bits */ 7353 #define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /*!< SVMHOUTPOLAL Bit Offset */ 7354 #define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /*!< SVMHOUT pin polarity active low */ 7355 /* PSS_CTL0[DCDC_FORCE] Bits */ 7356 #define PSS_CTL0_DCDC_FORCE_OFS (10) /*!< DCDC_FORCE Bit Offset */ 7357 #define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /*!< Force DC-DC regulator operation */ 7358 /* PSS_CTL0[VCORETRAN] Bits */ 7359 #define PSS_CTL0_VCORETRAN_OFS (12) /*!< VCORETRAN Bit Offset */ 7360 #define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /*!< VCORETRAN Bit Mask */ 7361 #define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /*!< VCORETRAN Bit 0 */ 7362 #define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /*!< VCORETRAN Bit 1 */ 7363 #define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ 7364 #define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ 7365 #define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ 7366 #define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ 7367 #define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ 7368 #define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ 7369 #define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ 7370 #define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ 7371 /* PSS_IE[SVSMHIE] Bits */ 7372 #define PSS_IE_SVSMHIE_OFS ( 1) /*!< SVSMHIE Bit Offset */ 7373 #define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /*!< High-side SVSM interrupt enable */ 7374 /* PSS_IFG[SVSMHIFG] Bits */ 7375 #define PSS_IFG_SVSMHIFG_OFS ( 1) /*!< SVSMHIFG Bit Offset */ 7376 #define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /*!< High-side SVSM interrupt flag */ 7377 /* PSS_CLRIFG[CLRSVSMHIFG] Bits */ 7378 #define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /*!< CLRSVSMHIFG Bit Offset */ 7379 #define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /*!< SVSMH clear interrupt flag */ 7380 /* Pre-defined bitfield values */ 7381 #define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /*!< PSS control key value */ 7382 7383 7384 /****************************************************************************** 7385 * REF_A Bits 7386 ******************************************************************************/ 7387 /* REF_A_CTL0[ON] Bits */ 7388 #define REF_A_CTL0_ON_OFS ( 0) /*!< REFON Bit Offset */ 7389 #define REF_A_CTL0_ON ((uint16_t)0x0001) /*!< Reference enable */ 7390 /* REF_A_CTL0[OUT] Bits */ 7391 #define REF_A_CTL0_OUT_OFS ( 1) /*!< REFOUT Bit Offset */ 7392 #define REF_A_CTL0_OUT ((uint16_t)0x0002) /*!< Reference output buffer */ 7393 /* REF_A_CTL0[TCOFF] Bits */ 7394 #define REF_A_CTL0_TCOFF_OFS ( 3) /*!< REFTCOFF Bit Offset */ 7395 #define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /*!< Temperature sensor disabled */ 7396 /* REF_A_CTL0[VSEL] Bits */ 7397 #define REF_A_CTL0_VSEL_OFS ( 4) /*!< REFVSEL Bit Offset */ 7398 #define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /*!< REFVSEL Bit Mask */ 7399 #define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /*!< VSEL Bit 0 */ 7400 #define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /*!< VSEL Bit 1 */ 7401 #define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /*!< 1.2 V available when reference requested or REFON = 1 */ 7402 #define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /*!< 1.45 V available when reference requested or REFON = 1 */ 7403 #define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /*!< 2.5 V available when reference requested or REFON = 1 */ 7404 /* REF_A_CTL0[GENOT] Bits */ 7405 #define REF_A_CTL0_GENOT_OFS ( 6) /*!< REFGENOT Bit Offset */ 7406 #define REF_A_CTL0_GENOT ((uint16_t)0x0040) /*!< Reference generator one-time trigger */ 7407 /* REF_A_CTL0[BGOT] Bits */ 7408 #define REF_A_CTL0_BGOT_OFS ( 7) /*!< REFBGOT Bit Offset */ 7409 #define REF_A_CTL0_BGOT ((uint16_t)0x0080) /*!< Bandgap and bandgap buffer one-time trigger */ 7410 /* REF_A_CTL0[GENACT] Bits */ 7411 #define REF_A_CTL0_GENACT_OFS ( 8) /*!< REFGENACT Bit Offset */ 7412 #define REF_A_CTL0_GENACT ((uint16_t)0x0100) /*!< Reference generator active */ 7413 /* REF_A_CTL0[BGACT] Bits */ 7414 #define REF_A_CTL0_BGACT_OFS ( 9) /*!< REFBGACT Bit Offset */ 7415 #define REF_A_CTL0_BGACT ((uint16_t)0x0200) /*!< Reference bandgap active */ 7416 /* REF_A_CTL0[GENBUSY] Bits */ 7417 #define REF_A_CTL0_GENBUSY_OFS (10) /*!< REFGENBUSY Bit Offset */ 7418 #define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /*!< Reference generator busy */ 7419 /* REF_A_CTL0[BGMODE] Bits */ 7420 #define REF_A_CTL0_BGMODE_OFS (11) /*!< BGMODE Bit Offset */ 7421 #define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /*!< Bandgap mode */ 7422 /* REF_A_CTL0[GENRDY] Bits */ 7423 #define REF_A_CTL0_GENRDY_OFS (12) /*!< REFGENRDY Bit Offset */ 7424 #define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /*!< Variable reference voltage ready status */ 7425 /* REF_A_CTL0[BGRDY] Bits */ 7426 #define REF_A_CTL0_BGRDY_OFS (13) /*!< REFBGRDY Bit Offset */ 7427 #define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /*!< Buffered bandgap voltage ready status */ 7428 7429 /****************************************************************************** 7430 * RSTCTL Bits 7431 ******************************************************************************/ 7432 /* RSTCTL_RESET_REQ[SOFT_REQ] Bits */ 7433 #define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /*!< SOFT_REQ Bit Offset */ 7434 #define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /*!< Soft Reset request */ 7435 /* RSTCTL_RESET_REQ[HARD_REQ] Bits */ 7436 #define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /*!< HARD_REQ Bit Offset */ 7437 #define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /*!< Hard Reset request */ 7438 /* RSTCTL_RESET_REQ[RSTKEY] Bits */ 7439 #define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /*!< RSTKEY Bit Offset */ 7440 #define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /*!< RSTKEY Bit Mask */ 7441 /* RSTCTL_HARDRESET_STAT[SRC0] Bits */ 7442 #define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 7443 #define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< Indicates that SRC0 was the source of the Hard Reset */ 7444 /* RSTCTL_HARDRESET_STAT[SRC1] Bits */ 7445 #define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 7446 #define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< Indicates that SRC1 was the source of the Hard Reset */ 7447 /* RSTCTL_HARDRESET_STAT[SRC2] Bits */ 7448 #define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 7449 #define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< Indicates that SRC2 was the source of the Hard Reset */ 7450 /* RSTCTL_HARDRESET_STAT[SRC3] Bits */ 7451 #define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 7452 #define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< Indicates that SRC3 was the source of the Hard Reset */ 7453 /* RSTCTL_HARDRESET_STAT[SRC4] Bits */ 7454 #define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 7455 #define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< Indicates that SRC4 was the source of the Hard Reset */ 7456 /* RSTCTL_HARDRESET_STAT[SRC5] Bits */ 7457 #define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 7458 #define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< Indicates that SRC5 was the source of the Hard Reset */ 7459 /* RSTCTL_HARDRESET_STAT[SRC6] Bits */ 7460 #define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 7461 #define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< Indicates that SRC6 was the source of the Hard Reset */ 7462 /* RSTCTL_HARDRESET_STAT[SRC7] Bits */ 7463 #define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 7464 #define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< Indicates that SRC7 was the source of the Hard Reset */ 7465 /* RSTCTL_HARDRESET_STAT[SRC8] Bits */ 7466 #define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 7467 #define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< Indicates that SRC8 was the source of the Hard Reset */ 7468 /* RSTCTL_HARDRESET_STAT[SRC9] Bits */ 7469 #define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 7470 #define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< Indicates that SRC9 was the source of the Hard Reset */ 7471 /* RSTCTL_HARDRESET_STAT[SRC10] Bits */ 7472 #define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 7473 #define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< Indicates that SRC10 was the source of the Hard Reset */ 7474 /* RSTCTL_HARDRESET_STAT[SRC11] Bits */ 7475 #define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 7476 #define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< Indicates that SRC11 was the source of the Hard Reset */ 7477 /* RSTCTL_HARDRESET_STAT[SRC12] Bits */ 7478 #define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 7479 #define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< Indicates that SRC12 was the source of the Hard Reset */ 7480 /* RSTCTL_HARDRESET_STAT[SRC13] Bits */ 7481 #define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 7482 #define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< Indicates that SRC13 was the source of the Hard Reset */ 7483 /* RSTCTL_HARDRESET_STAT[SRC14] Bits */ 7484 #define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 7485 #define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< Indicates that SRC14 was the source of the Hard Reset */ 7486 /* RSTCTL_HARDRESET_STAT[SRC15] Bits */ 7487 #define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 7488 #define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< Indicates that SRC15 was the source of the Hard Reset */ 7489 /* RSTCTL_HARDRESET_CLR[SRC0] Bits */ 7490 #define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 7491 #define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7492 /* RSTCTL_HARDRESET_CLR[SRC1] Bits */ 7493 #define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 7494 #define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7495 /* RSTCTL_HARDRESET_CLR[SRC2] Bits */ 7496 #define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 7497 #define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7498 /* RSTCTL_HARDRESET_CLR[SRC3] Bits */ 7499 #define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 7500 #define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7501 /* RSTCTL_HARDRESET_CLR[SRC4] Bits */ 7502 #define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 7503 #define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7504 /* RSTCTL_HARDRESET_CLR[SRC5] Bits */ 7505 #define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 7506 #define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7507 /* RSTCTL_HARDRESET_CLR[SRC6] Bits */ 7508 #define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 7509 #define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7510 /* RSTCTL_HARDRESET_CLR[SRC7] Bits */ 7511 #define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 7512 #define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7513 /* RSTCTL_HARDRESET_CLR[SRC8] Bits */ 7514 #define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 7515 #define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7516 /* RSTCTL_HARDRESET_CLR[SRC9] Bits */ 7517 #define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 7518 #define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7519 /* RSTCTL_HARDRESET_CLR[SRC10] Bits */ 7520 #define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 7521 #define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7522 /* RSTCTL_HARDRESET_CLR[SRC11] Bits */ 7523 #define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 7524 #define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7525 /* RSTCTL_HARDRESET_CLR[SRC12] Bits */ 7526 #define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 7527 #define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7528 /* RSTCTL_HARDRESET_CLR[SRC13] Bits */ 7529 #define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 7530 #define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7531 /* RSTCTL_HARDRESET_CLR[SRC14] Bits */ 7532 #define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 7533 #define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 7534 /* RSTCTL_HARDRESET_CLR[SRC15] Bits */ 7535 #define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 7536 #define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */ 7537 /* RSTCTL_HARDRESET_SET[SRC0] Bits */ 7538 #define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 7539 #define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7540 /* initiates a Hard Reset) */ 7541 /* RSTCTL_HARDRESET_SET[SRC1] Bits */ 7542 #define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 7543 #define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7544 /* initiates a Hard Reset) */ 7545 /* RSTCTL_HARDRESET_SET[SRC2] Bits */ 7546 #define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 7547 #define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7548 /* initiates a Hard Reset) */ 7549 /* RSTCTL_HARDRESET_SET[SRC3] Bits */ 7550 #define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 7551 #define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7552 /* initiates a Hard Reset) */ 7553 /* RSTCTL_HARDRESET_SET[SRC4] Bits */ 7554 #define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 7555 #define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7556 /* initiates a Hard Reset) */ 7557 /* RSTCTL_HARDRESET_SET[SRC5] Bits */ 7558 #define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 7559 #define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7560 /* initiates a Hard Reset) */ 7561 /* RSTCTL_HARDRESET_SET[SRC6] Bits */ 7562 #define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 7563 #define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7564 /* initiates a Hard Reset) */ 7565 /* RSTCTL_HARDRESET_SET[SRC7] Bits */ 7566 #define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 7567 #define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7568 /* initiates a Hard Reset) */ 7569 /* RSTCTL_HARDRESET_SET[SRC8] Bits */ 7570 #define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 7571 #define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7572 /* initiates a Hard Reset) */ 7573 /* RSTCTL_HARDRESET_SET[SRC9] Bits */ 7574 #define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 7575 #define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7576 /* initiates a Hard Reset) */ 7577 /* RSTCTL_HARDRESET_SET[SRC10] Bits */ 7578 #define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 7579 #define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7580 /* initiates a Hard Reset) */ 7581 /* RSTCTL_HARDRESET_SET[SRC11] Bits */ 7582 #define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 7583 #define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7584 /* initiates a Hard Reset) */ 7585 /* RSTCTL_HARDRESET_SET[SRC12] Bits */ 7586 #define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 7587 #define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7588 /* initiates a Hard Reset) */ 7589 /* RSTCTL_HARDRESET_SET[SRC13] Bits */ 7590 #define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 7591 #define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7592 /* initiates a Hard Reset) */ 7593 /* RSTCTL_HARDRESET_SET[SRC14] Bits */ 7594 #define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 7595 #define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7596 /* initiates a Hard Reset) */ 7597 /* RSTCTL_HARDRESET_SET[SRC15] Bits */ 7598 #define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 7599 #define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 7600 /* initiates a Hard Reset) */ 7601 /* RSTCTL_SOFTRESET_STAT[SRC0] Bits */ 7602 #define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 7603 #define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< If 1, indicates that SRC0 was the source of the Soft Reset */ 7604 /* RSTCTL_SOFTRESET_STAT[SRC1] Bits */ 7605 #define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 7606 #define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */ 7607 /* RSTCTL_SOFTRESET_STAT[SRC2] Bits */ 7608 #define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 7609 #define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< If 1, indicates that SRC2 was the source of the Soft Reset */ 7610 /* RSTCTL_SOFTRESET_STAT[SRC3] Bits */ 7611 #define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 7612 #define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< If 1, indicates that SRC3 was the source of the Soft Reset */ 7613 /* RSTCTL_SOFTRESET_STAT[SRC4] Bits */ 7614 #define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 7615 #define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< If 1, indicates that SRC4 was the source of the Soft Reset */ 7616 /* RSTCTL_SOFTRESET_STAT[SRC5] Bits */ 7617 #define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 7618 #define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< If 1, indicates that SRC5 was the source of the Soft Reset */ 7619 /* RSTCTL_SOFTRESET_STAT[SRC6] Bits */ 7620 #define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 7621 #define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< If 1, indicates that SRC6 was the source of the Soft Reset */ 7622 /* RSTCTL_SOFTRESET_STAT[SRC7] Bits */ 7623 #define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 7624 #define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< If 1, indicates that SRC7 was the source of the Soft Reset */ 7625 /* RSTCTL_SOFTRESET_STAT[SRC8] Bits */ 7626 #define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 7627 #define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< If 1, indicates that SRC8 was the source of the Soft Reset */ 7628 /* RSTCTL_SOFTRESET_STAT[SRC9] Bits */ 7629 #define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 7630 #define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< If 1, indicates that SRC9 was the source of the Soft Reset */ 7631 /* RSTCTL_SOFTRESET_STAT[SRC10] Bits */ 7632 #define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 7633 #define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< If 1, indicates that SRC10 was the source of the Soft Reset */ 7634 /* RSTCTL_SOFTRESET_STAT[SRC11] Bits */ 7635 #define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 7636 #define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< If 1, indicates that SRC11 was the source of the Soft Reset */ 7637 /* RSTCTL_SOFTRESET_STAT[SRC12] Bits */ 7638 #define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 7639 #define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< If 1, indicates that SRC12 was the source of the Soft Reset */ 7640 /* RSTCTL_SOFTRESET_STAT[SRC13] Bits */ 7641 #define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 7642 #define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< If 1, indicates that SRC13 was the source of the Soft Reset */ 7643 /* RSTCTL_SOFTRESET_STAT[SRC14] Bits */ 7644 #define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 7645 #define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< If 1, indicates that SRC14 was the source of the Soft Reset */ 7646 /* RSTCTL_SOFTRESET_STAT[SRC15] Bits */ 7647 #define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 7648 #define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< If 1, indicates that SRC15 was the source of the Soft Reset */ 7649 /* RSTCTL_SOFTRESET_CLR[SRC0] Bits */ 7650 #define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 7651 #define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7652 /* RSTCTL_SOFTRESET_CLR[SRC1] Bits */ 7653 #define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 7654 #define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7655 /* RSTCTL_SOFTRESET_CLR[SRC2] Bits */ 7656 #define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 7657 #define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7658 /* RSTCTL_SOFTRESET_CLR[SRC3] Bits */ 7659 #define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 7660 #define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7661 /* RSTCTL_SOFTRESET_CLR[SRC4] Bits */ 7662 #define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 7663 #define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7664 /* RSTCTL_SOFTRESET_CLR[SRC5] Bits */ 7665 #define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 7666 #define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7667 /* RSTCTL_SOFTRESET_CLR[SRC6] Bits */ 7668 #define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 7669 #define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7670 /* RSTCTL_SOFTRESET_CLR[SRC7] Bits */ 7671 #define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 7672 #define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7673 /* RSTCTL_SOFTRESET_CLR[SRC8] Bits */ 7674 #define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 7675 #define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7676 /* RSTCTL_SOFTRESET_CLR[SRC9] Bits */ 7677 #define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 7678 #define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7679 /* RSTCTL_SOFTRESET_CLR[SRC10] Bits */ 7680 #define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 7681 #define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7682 /* RSTCTL_SOFTRESET_CLR[SRC11] Bits */ 7683 #define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 7684 #define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7685 /* RSTCTL_SOFTRESET_CLR[SRC12] Bits */ 7686 #define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 7687 #define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7688 /* RSTCTL_SOFTRESET_CLR[SRC13] Bits */ 7689 #define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 7690 #define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7691 /* RSTCTL_SOFTRESET_CLR[SRC14] Bits */ 7692 #define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 7693 #define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7694 /* RSTCTL_SOFTRESET_CLR[SRC15] Bits */ 7695 #define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 7696 #define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 7697 /* RSTCTL_SOFTRESET_SET[SRC0] Bits */ 7698 #define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 7699 #define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7700 /* initiates a Soft Reset) */ 7701 /* RSTCTL_SOFTRESET_SET[SRC1] Bits */ 7702 #define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 7703 #define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7704 /* initiates a Soft Reset) */ 7705 /* RSTCTL_SOFTRESET_SET[SRC2] Bits */ 7706 #define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 7707 #define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7708 /* initiates a Soft Reset) */ 7709 /* RSTCTL_SOFTRESET_SET[SRC3] Bits */ 7710 #define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 7711 #define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7712 /* initiates a Soft Reset) */ 7713 /* RSTCTL_SOFTRESET_SET[SRC4] Bits */ 7714 #define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 7715 #define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7716 /* initiates a Soft Reset) */ 7717 /* RSTCTL_SOFTRESET_SET[SRC5] Bits */ 7718 #define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 7719 #define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7720 /* initiates a Soft Reset) */ 7721 /* RSTCTL_SOFTRESET_SET[SRC6] Bits */ 7722 #define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 7723 #define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7724 /* initiates a Soft Reset) */ 7725 /* RSTCTL_SOFTRESET_SET[SRC7] Bits */ 7726 #define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 7727 #define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7728 /* initiates a Soft Reset) */ 7729 /* RSTCTL_SOFTRESET_SET[SRC8] Bits */ 7730 #define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 7731 #define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7732 /* initiates a Soft Reset) */ 7733 /* RSTCTL_SOFTRESET_SET[SRC9] Bits */ 7734 #define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 7735 #define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7736 /* initiates a Soft Reset) */ 7737 /* RSTCTL_SOFTRESET_SET[SRC10] Bits */ 7738 #define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 7739 #define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7740 /* initiates a Soft Reset) */ 7741 /* RSTCTL_SOFTRESET_SET[SRC11] Bits */ 7742 #define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 7743 #define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7744 /* initiates a Soft Reset) */ 7745 /* RSTCTL_SOFTRESET_SET[SRC12] Bits */ 7746 #define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 7747 #define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7748 /* initiates a Soft Reset) */ 7749 /* RSTCTL_SOFTRESET_SET[SRC13] Bits */ 7750 #define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 7751 #define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7752 /* initiates a Soft Reset) */ 7753 /* RSTCTL_SOFTRESET_SET[SRC14] Bits */ 7754 #define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 7755 #define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7756 /* initiates a Soft Reset) */ 7757 /* RSTCTL_SOFTRESET_SET[SRC15] Bits */ 7758 #define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 7759 #define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 7760 /* initiates a Soft Reset) */ 7761 /* RSTCTL_PSSRESET_STAT[SVSMH] Bits */ 7762 #define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /*!< SVSMH Bit Offset */ 7763 #define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */ 7764 /* RSTCTL_PSSRESET_STAT[BGREF] Bits */ 7765 #define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /*!< BGREF Bit Offset */ 7766 #define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */ 7767 /* RSTCTL_PSSRESET_STAT[VCCDET] Bits */ 7768 #define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /*!< VCCDET Bit Offset */ 7769 #define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */ 7770 /* RSTCTL_PSSRESET_CLR[CLR] Bits */ 7771 #define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 7772 #define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */ 7773 /* RSTCTL_PCMRESET_STAT[LPM35] Bits */ 7774 #define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /*!< LPM35 Bit Offset */ 7775 #define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */ 7776 /* RSTCTL_PCMRESET_STAT[LPM45] Bits */ 7777 #define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /*!< LPM45 Bit Offset */ 7778 #define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */ 7779 /* RSTCTL_PCMRESET_CLR[CLR] Bits */ 7780 #define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 7781 #define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */ 7782 /* RSTCTL_PINRESET_STAT[RSTNMI] Bits */ 7783 #define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /*!< RSTNMI Bit Offset */ 7784 #define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /*!< POR was caused by RSTn/NMI pin based reset event */ 7785 /* RSTCTL_PINRESET_CLR[CLR] Bits */ 7786 #define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 7787 #define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */ 7788 /* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */ 7789 #define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ 7790 #define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /*!< Indicates if Reboot reset was caused by the SYSCTL module. */ 7791 /* RSTCTL_REBOOTRESET_CLR[CLR] Bits */ 7792 #define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 7793 #define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */ 7794 /* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */ 7795 #define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /*!< DCOR_SHT Bit Offset */ 7796 #define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /*!< Indicates if POR was caused by DCO short circuit fault in the external */ 7797 /* resistor mode */ 7798 /* RSTCTL_CSRESET_CLR[CLR] Bits */ 7799 #define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 7800 #define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as */ 7801 /* DCOR_SHTIFG flag in CSIFG register of clock system */ 7802 /* Pre-defined bitfield values */ 7803 #define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bits 1-0 */ 7804 7805 7806 /****************************************************************************** 7807 * RTC_C Bits 7808 ******************************************************************************/ 7809 /* RTC_C_CTL0[RDYIFG] Bits */ 7810 #define RTC_C_CTL0_RDYIFG_OFS ( 0) /*!< RTCRDYIFG Bit Offset */ 7811 #define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /*!< Real-time clock ready interrupt flag */ 7812 /* RTC_C_CTL0[AIFG] Bits */ 7813 #define RTC_C_CTL0_AIFG_OFS ( 1) /*!< RTCAIFG Bit Offset */ 7814 #define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /*!< Real-time clock alarm interrupt flag */ 7815 /* RTC_C_CTL0[TEVIFG] Bits */ 7816 #define RTC_C_CTL0_TEVIFG_OFS ( 2) /*!< RTCTEVIFG Bit Offset */ 7817 #define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /*!< Real-time clock time event interrupt flag */ 7818 /* RTC_C_CTL0[OFIFG] Bits */ 7819 #define RTC_C_CTL0_OFIFG_OFS ( 3) /*!< RTCOFIFG Bit Offset */ 7820 #define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /*!< 32-kHz crystal oscillator fault interrupt flag */ 7821 /* RTC_C_CTL0[RDYIE] Bits */ 7822 #define RTC_C_CTL0_RDYIE_OFS ( 4) /*!< RTCRDYIE Bit Offset */ 7823 #define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /*!< Real-time clock ready interrupt enable */ 7824 /* RTC_C_CTL0[AIE] Bits */ 7825 #define RTC_C_CTL0_AIE_OFS ( 5) /*!< RTCAIE Bit Offset */ 7826 #define RTC_C_CTL0_AIE ((uint16_t)0x0020) /*!< Real-time clock alarm interrupt enable */ 7827 /* RTC_C_CTL0[TEVIE] Bits */ 7828 #define RTC_C_CTL0_TEVIE_OFS ( 6) /*!< RTCTEVIE Bit Offset */ 7829 #define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /*!< Real-time clock time event interrupt enable */ 7830 /* RTC_C_CTL0[OFIE] Bits */ 7831 #define RTC_C_CTL0_OFIE_OFS ( 7) /*!< RTCOFIE Bit Offset */ 7832 #define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /*!< 32-kHz crystal oscillator fault interrupt enable */ 7833 /* RTC_C_CTL0[KEY] Bits */ 7834 #define RTC_C_CTL0_KEY_OFS ( 8) /*!< RTCKEY Bit Offset */ 7835 #define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /*!< RTCKEY Bit Mask */ 7836 /* RTC_C_CTL13[TEV] Bits */ 7837 #define RTC_C_CTL13_TEV_OFS ( 0) /*!< RTCTEV Bit Offset */ 7838 #define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /*!< RTCTEV Bit Mask */ 7839 #define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /*!< TEV Bit 0 */ 7840 #define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /*!< TEV Bit 1 */ 7841 #define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /*!< Minute changed */ 7842 #define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /*!< Hour changed */ 7843 #define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /*!< Every day at midnight (00:00) */ 7844 #define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /*!< Every day at noon (12:00) */ 7845 /* RTC_C_CTL13[SSEL] Bits */ 7846 #define RTC_C_CTL13_SSEL_OFS ( 2) /*!< RTCSSEL Bit Offset */ 7847 #define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /*!< RTCSSEL Bit Mask */ 7848 #define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /*!< SSEL Bit 0 */ 7849 #define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /*!< SSEL Bit 1 */ 7850 #define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /*!< BCLK */ 7851 #define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /*!< BCLK */ 7852 /* RTC_C_CTL13[RDY] Bits */ 7853 #define RTC_C_CTL13_RDY_OFS ( 4) /*!< RTCRDY Bit Offset */ 7854 #define RTC_C_CTL13_RDY ((uint16_t)0x0010) /*!< Real-time clock ready */ 7855 /* RTC_C_CTL13[MODE] Bits */ 7856 #define RTC_C_CTL13_MODE_OFS ( 5) /*!< RTCMODE Bit Offset */ 7857 #define RTC_C_CTL13_MODE ((uint16_t)0x0020) 7858 /* RTC_C_CTL13[HOLD] Bits */ 7859 #define RTC_C_CTL13_HOLD_OFS ( 6) /*!< RTCHOLD Bit Offset */ 7860 #define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /*!< Real-time clock hold */ 7861 /* RTC_C_CTL13[BCD] Bits */ 7862 #define RTC_C_CTL13_BCD_OFS ( 7) /*!< RTCBCD Bit Offset */ 7863 #define RTC_C_CTL13_BCD ((uint16_t)0x0080) /*!< Real-time clock BCD select */ 7864 /* RTC_C_CTL13[CALF] Bits */ 7865 #define RTC_C_CTL13_CALF_OFS ( 8) /*!< RTCCALF Bit Offset */ 7866 #define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /*!< RTCCALF Bit Mask */ 7867 #define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /*!< CALF Bit 0 */ 7868 #define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /*!< CALF Bit 1 */ 7869 #define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ 7870 #define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /*!< 512 Hz */ 7871 #define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /*!< 256 Hz */ 7872 #define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /*!< 1 Hz */ 7873 #define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ 7874 #define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /*!< 512 Hz */ 7875 #define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /*!< 256 Hz */ 7876 #define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /*!< 1 Hz */ 7877 /* RTC_C_OCAL[OCAL] Bits */ 7878 #define RTC_C_OCAL_OCAL_OFS ( 0) /*!< RTCOCAL Bit Offset */ 7879 #define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /*!< RTCOCAL Bit Mask */ 7880 /* RTC_C_OCAL[OCALS] Bits */ 7881 #define RTC_C_OCAL_OCALS_OFS (15) /*!< RTCOCALS Bit Offset */ 7882 #define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /*!< Real-time clock offset error calibration sign */ 7883 /* RTC_C_TCMP[TCMPx] Bits */ 7884 #define RTC_C_TCMP_TCMPX_OFS ( 0) /*!< RTCTCMP Bit Offset */ 7885 #define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /*!< RTCTCMP Bit Mask */ 7886 /* RTC_C_TCMP[TCOK] Bits */ 7887 #define RTC_C_TCMP_TCOK_OFS (13) /*!< RTCTCOK Bit Offset */ 7888 #define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /*!< Real-time clock temperature compensation write OK */ 7889 /* RTC_C_TCMP[TCRDY] Bits */ 7890 #define RTC_C_TCMP_TCRDY_OFS (14) /*!< RTCTCRDY Bit Offset */ 7891 #define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /*!< Real-time clock temperature compensation ready */ 7892 /* RTC_C_TCMP[TCMPS] Bits */ 7893 #define RTC_C_TCMP_TCMPS_OFS (15) /*!< RTCTCMPS Bit Offset */ 7894 #define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /*!< Real-time clock temperature compensation sign */ 7895 /* RTC_C_PS0CTL[RT0PSIFG] Bits */ 7896 #define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /*!< RT0PSIFG Bit Offset */ 7897 #define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /*!< Prescale timer 0 interrupt flag */ 7898 /* RTC_C_PS0CTL[RT0PSIE] Bits */ 7899 #define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /*!< RT0PSIE Bit Offset */ 7900 #define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /*!< Prescale timer 0 interrupt enable */ 7901 /* RTC_C_PS0CTL[RT0IP] Bits */ 7902 #define RTC_C_PS0CTL_RT0IP_OFS ( 2) /*!< RT0IP Bit Offset */ 7903 #define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /*!< RT0IP Bit Mask */ 7904 #define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /*!< RT0IP Bit 0 */ 7905 #define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /*!< RT0IP Bit 1 */ 7906 #define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /*!< RT0IP Bit 2 */ 7907 #define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ 7908 #define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ 7909 #define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ 7910 #define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ 7911 #define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ 7912 #define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ 7913 #define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ 7914 #define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ 7915 #define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ 7916 #define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ 7917 #define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ 7918 #define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ 7919 #define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ 7920 #define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ 7921 #define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ 7922 #define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ 7923 /* RTC_C_PS1CTL[RT1PSIFG] Bits */ 7924 #define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /*!< RT1PSIFG Bit Offset */ 7925 #define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /*!< Prescale timer 1 interrupt flag */ 7926 /* RTC_C_PS1CTL[RT1PSIE] Bits */ 7927 #define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /*!< RT1PSIE Bit Offset */ 7928 #define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /*!< Prescale timer 1 interrupt enable */ 7929 /* RTC_C_PS1CTL[RT1IP] Bits */ 7930 #define RTC_C_PS1CTL_RT1IP_OFS ( 2) /*!< RT1IP Bit Offset */ 7931 #define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /*!< RT1IP Bit Mask */ 7932 #define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /*!< RT1IP Bit 0 */ 7933 #define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /*!< RT1IP Bit 1 */ 7934 #define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /*!< RT1IP Bit 2 */ 7935 #define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ 7936 #define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ 7937 #define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ 7938 #define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ 7939 #define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ 7940 #define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ 7941 #define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ 7942 #define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ 7943 #define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ 7944 #define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ 7945 #define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ 7946 #define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ 7947 #define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ 7948 #define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ 7949 #define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ 7950 #define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ 7951 /* RTC_C_PS[RT0PS] Bits */ 7952 #define RTC_C_PS_RT0PS_OFS ( 0) /*!< RT0PS Bit Offset */ 7953 #define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /*!< RT0PS Bit Mask */ 7954 /* RTC_C_PS[RT1PS] Bits */ 7955 #define RTC_C_PS_RT1PS_OFS ( 8) /*!< RT1PS Bit Offset */ 7956 #define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /*!< RT1PS Bit Mask */ 7957 /* RTC_C_TIM0[SEC] Bits */ 7958 #define RTC_C_TIM0_SEC_OFS ( 0) /*!< Seconds Bit Offset */ 7959 #define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /*!< Seconds Bit Mask */ 7960 /* RTC_C_TIM0[MIN] Bits */ 7961 #define RTC_C_TIM0_MIN_OFS ( 8) /*!< Minutes Bit Offset */ 7962 #define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /*!< Minutes Bit Mask */ 7963 /* RTC_C_TIM0[SEC_LD] Bits */ 7964 #define RTC_C_TIM0_SEC_LD_OFS ( 0) /*!< SecondsLowDigit Bit Offset */ 7965 #define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /*!< SecondsLowDigit Bit Mask */ 7966 /* RTC_C_TIM0[SEC_HD] Bits */ 7967 #define RTC_C_TIM0_SEC_HD_OFS ( 4) /*!< SecondsHighDigit Bit Offset */ 7968 #define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /*!< SecondsHighDigit Bit Mask */ 7969 /* RTC_C_TIM0[MIN_LD] Bits */ 7970 #define RTC_C_TIM0_MIN_LD_OFS ( 8) /*!< MinutesLowDigit Bit Offset */ 7971 #define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /*!< MinutesLowDigit Bit Mask */ 7972 /* RTC_C_TIM0[MIN_HD] Bits */ 7973 #define RTC_C_TIM0_MIN_HD_OFS (12) /*!< MinutesHighDigit Bit Offset */ 7974 #define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /*!< MinutesHighDigit Bit Mask */ 7975 /* RTC_C_TIM1[HOUR] Bits */ 7976 #define RTC_C_TIM1_HOUR_OFS ( 0) /*!< Hours Bit Offset */ 7977 #define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /*!< Hours Bit Mask */ 7978 /* RTC_C_TIM1[DOW] Bits */ 7979 #define RTC_C_TIM1_DOW_OFS ( 8) /*!< DayofWeek Bit Offset */ 7980 #define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /*!< DayofWeek Bit Mask */ 7981 /* RTC_C_TIM1[HOUR_LD] Bits */ 7982 #define RTC_C_TIM1_HOUR_LD_OFS ( 0) /*!< HoursLowDigit Bit Offset */ 7983 #define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /*!< HoursLowDigit Bit Mask */ 7984 /* RTC_C_TIM1[HOUR_HD] Bits */ 7985 #define RTC_C_TIM1_HOUR_HD_OFS ( 4) /*!< HoursHighDigit Bit Offset */ 7986 #define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /*!< HoursHighDigit Bit Mask */ 7987 /* RTC_C_DATE[DAY] Bits */ 7988 #define RTC_C_DATE_DAY_OFS ( 0) /*!< Day Bit Offset */ 7989 #define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /*!< Day Bit Mask */ 7990 /* RTC_C_DATE[MON] Bits */ 7991 #define RTC_C_DATE_MON_OFS ( 8) /*!< Month Bit Offset */ 7992 #define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /*!< Month Bit Mask */ 7993 /* RTC_C_DATE[DAY_LD] Bits */ 7994 #define RTC_C_DATE_DAY_LD_OFS ( 0) /*!< DayLowDigit Bit Offset */ 7995 #define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /*!< DayLowDigit Bit Mask */ 7996 /* RTC_C_DATE[DAY_HD] Bits */ 7997 #define RTC_C_DATE_DAY_HD_OFS ( 4) /*!< DayHighDigit Bit Offset */ 7998 #define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /*!< DayHighDigit Bit Mask */ 7999 /* RTC_C_DATE[MON_LD] Bits */ 8000 #define RTC_C_DATE_MON_LD_OFS ( 8) /*!< MonthLowDigit Bit Offset */ 8001 #define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /*!< MonthLowDigit Bit Mask */ 8002 /* RTC_C_DATE[MON_HD] Bits */ 8003 #define RTC_C_DATE_MON_HD_OFS (12) /*!< MonthHighDigit Bit Offset */ 8004 #define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /*!< Month high digit (0 or 1) */ 8005 /* RTC_C_YEAR[YEAR_LB] Bits */ 8006 #define RTC_C_YEAR_YEAR_LB_OFS ( 0) /*!< YearLowByte Bit Offset */ 8007 #define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /*!< YearLowByte Bit Mask */ 8008 /* RTC_C_YEAR[YEAR_HB] Bits */ 8009 #define RTC_C_YEAR_YEAR_HB_OFS ( 8) /*!< YearHighByte Bit Offset */ 8010 #define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /*!< YearHighByte Bit Mask */ 8011 /* RTC_C_YEAR[YEAR] Bits */ 8012 #define RTC_C_YEAR_YEAR_OFS ( 0) /*!< Year Bit Offset */ 8013 #define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /*!< Year Bit Mask */ 8014 /* RTC_C_YEAR[DEC] Bits */ 8015 #define RTC_C_YEAR_DEC_OFS ( 4) /*!< Decade Bit Offset */ 8016 #define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /*!< Decade Bit Mask */ 8017 /* RTC_C_YEAR[CENT_LD] Bits */ 8018 #define RTC_C_YEAR_CENT_LD_OFS ( 8) /*!< CenturyLowDigit Bit Offset */ 8019 #define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /*!< CenturyLowDigit Bit Mask */ 8020 /* RTC_C_YEAR[CENT_HD] Bits */ 8021 #define RTC_C_YEAR_CENT_HD_OFS (12) /*!< CenturyHighDigit Bit Offset */ 8022 #define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /*!< CenturyHighDigit Bit Mask */ 8023 /* RTC_C_AMINHR[MIN] Bits */ 8024 #define RTC_C_AMINHR_MIN_OFS ( 0) /*!< Minutes Bit Offset */ 8025 #define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /*!< Minutes Bit Mask */ 8026 /* RTC_C_AMINHR[MINAE] Bits */ 8027 #define RTC_C_AMINHR_MINAE_OFS ( 7) /*!< MINAE Bit Offset */ 8028 #define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /*!< Alarm enable */ 8029 /* RTC_C_AMINHR[HOUR] Bits */ 8030 #define RTC_C_AMINHR_HOUR_OFS ( 8) /*!< Hours Bit Offset */ 8031 #define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /*!< Hours Bit Mask */ 8032 /* RTC_C_AMINHR[HOURAE] Bits */ 8033 #define RTC_C_AMINHR_HOURAE_OFS (15) /*!< HOURAE Bit Offset */ 8034 #define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /*!< Alarm enable */ 8035 /* RTC_C_AMINHR[MIN_LD] Bits */ 8036 #define RTC_C_AMINHR_MIN_LD_OFS ( 0) /*!< MinutesLowDigit Bit Offset */ 8037 #define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /*!< MinutesLowDigit Bit Mask */ 8038 /* RTC_C_AMINHR[MIN_HD] Bits */ 8039 #define RTC_C_AMINHR_MIN_HD_OFS ( 4) /*!< MinutesHighDigit Bit Offset */ 8040 #define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /*!< MinutesHighDigit Bit Mask */ 8041 /* RTC_C_AMINHR[HOUR_LD] Bits */ 8042 #define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /*!< HoursLowDigit Bit Offset */ 8043 #define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /*!< HoursLowDigit Bit Mask */ 8044 /* RTC_C_AMINHR[HOUR_HD] Bits */ 8045 #define RTC_C_AMINHR_HOUR_HD_OFS (12) /*!< HoursHighDigit Bit Offset */ 8046 #define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /*!< HoursHighDigit Bit Mask */ 8047 /* RTC_C_ADOWDAY[DOW] Bits */ 8048 #define RTC_C_ADOWDAY_DOW_OFS ( 0) /*!< DayofWeek Bit Offset */ 8049 #define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /*!< DayofWeek Bit Mask */ 8050 /* RTC_C_ADOWDAY[DOWAE] Bits */ 8051 #define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /*!< DOWAE Bit Offset */ 8052 #define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /*!< Alarm enable */ 8053 /* RTC_C_ADOWDAY[DAY] Bits */ 8054 #define RTC_C_ADOWDAY_DAY_OFS ( 8) /*!< DayofMonth Bit Offset */ 8055 #define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /*!< DayofMonth Bit Mask */ 8056 /* RTC_C_ADOWDAY[DAYAE] Bits */ 8057 #define RTC_C_ADOWDAY_DAYAE_OFS (15) /*!< DAYAE Bit Offset */ 8058 #define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /*!< Alarm enable */ 8059 /* RTC_C_ADOWDAY[DAY_LD] Bits */ 8060 #define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /*!< DayLowDigit Bit Offset */ 8061 #define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /*!< DayLowDigit Bit Mask */ 8062 /* RTC_C_ADOWDAY[DAY_HD] Bits */ 8063 #define RTC_C_ADOWDAY_DAY_HD_OFS (12) /*!< DayHighDigit Bit Offset */ 8064 #define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /*!< DayHighDigit Bit Mask */ 8065 /* Pre-defined bitfield values */ 8066 #define RTC_C_KEY ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ 8067 #define RTC_C_KEY_H ((uint16_t)0x00A5) /*!< RTC_C Key Value for RTC_C write access */ 8068 #define RTC_C_KEY_VAL ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ 8069 8070 8071 /****************************************************************************** 8072 * SCB Bits 8073 ******************************************************************************/ 8074 /* SCB_PFR0[STATE0] Bits */ 8075 #define SCB_PFR0_STATE0_OFS ( 0) /*!< STATE0 Bit Offset */ 8076 #define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /*!< STATE0 Bit Mask */ 8077 #define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /*!< STATE0 Bit 0 */ 8078 #define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /*!< STATE0 Bit 1 */ 8079 #define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /*!< STATE0 Bit 2 */ 8080 #define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /*!< STATE0 Bit 3 */ 8081 #define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /*!< no ARM encoding */ 8082 #define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /*!< N/A */ 8083 /* SCB_PFR0[STATE1] Bits */ 8084 #define SCB_PFR0_STATE1_OFS ( 4) /*!< STATE1 Bit Offset */ 8085 #define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /*!< STATE1 Bit Mask */ 8086 #define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /*!< STATE1 Bit 0 */ 8087 #define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /*!< STATE1 Bit 1 */ 8088 #define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /*!< STATE1 Bit 2 */ 8089 #define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /*!< STATE1 Bit 3 */ 8090 #define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /*!< N/A */ 8091 #define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /*!< N/A */ 8092 #define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL */ 8093 /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */ 8094 /* can be added using the appropriate instruction attribute, but other 32-bit */ 8095 /* basic instructions cannot.) */ 8096 #define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /*!< Thumb-2 encoding with all Thumb-2 basic instructions */ 8097 /* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */ 8098 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */ 8099 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */ 8100 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */ 8101 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */ 8102 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */ 8103 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */ 8104 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ 8105 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /*!< two-stack support */ 8106 /* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */ 8107 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */ 8108 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */ 8109 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */ 8110 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */ 8111 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */ 8112 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */ 8113 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ 8114 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */ 8115 /* SCB_MMFR0[PMSA_SUPPORT] Bits */ 8116 #define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /*!< PMSA_SUPPORT Bit Offset */ 8117 #define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /*!< PMSA_SUPPORT Bit Mask */ 8118 #define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /*!< PMSA_SUPPORT Bit 0 */ 8119 #define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /*!< PMSA_SUPPORT Bit 1 */ 8120 #define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /*!< PMSA_SUPPORT Bit 2 */ 8121 #define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /*!< PMSA_SUPPORT Bit 3 */ 8122 #define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ 8123 #define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /*!< IMPLEMENTATION DEFINED (N/A) */ 8124 #define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /*!< PMSA base (features as defined for ARMv6) (N/A) */ 8125 #define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /*!< PMSAv7 (base plus subregion support) */ 8126 /* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */ 8127 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /*!< CACHE_COHERENCE_SUPPORT Bit Offset */ 8128 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /*!< CACHE_COHERENCE_SUPPORT Bit Mask */ 8129 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /*!< CACHE_COHERENCE_SUPPORT Bit 0 */ 8130 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /*!< CACHE_COHERENCE_SUPPORT Bit 1 */ 8131 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /*!< CACHE_COHERENCE_SUPPORT Bit 2 */ 8132 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /*!< CACHE_COHERENCE_SUPPORT Bit 3 */ 8133 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /*!< no shared support */ 8134 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /*!< partial-inner-shared coherency (coherency amongst some - but not all - of */ 8135 /* the entities within an inner-coherent domain) */ 8136 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /*!< full-inner-shared coherency (coherency amongst all of the entities within an */ 8137 /* inner-coherent domain) */ 8138 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /*!< full coherency (coherency amongst all of the entities) */ 8139 /* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */ 8140 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */ 8141 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */ 8142 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */ 8143 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */ 8144 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */ 8145 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */ 8146 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /*!< Outer non-sharable not supported */ 8147 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /*!< Outer sharable supported */ 8148 /* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */ 8149 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */ 8150 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */ 8151 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */ 8152 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */ 8153 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */ 8154 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */ 8155 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ 8156 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /*!< Auxiliary control register */ 8157 /* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */ 8158 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */ 8159 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */ 8160 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */ 8161 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */ 8162 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */ 8163 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */ 8164 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /*!< not supported */ 8165 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /*!< wait for interrupt supported */ 8166 /* SCB_ISAR0[BITCOUNT_INSTRS] Bits */ 8167 #define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /*!< BITCOUNT_INSTRS Bit Offset */ 8168 #define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< BITCOUNT_INSTRS Bit Mask */ 8169 #define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /*!< BITCOUNT_INSTRS Bit 0 */ 8170 #define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /*!< BITCOUNT_INSTRS Bit 1 */ 8171 #define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /*!< BITCOUNT_INSTRS Bit 2 */ 8172 #define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /*!< BITCOUNT_INSTRS Bit 3 */ 8173 #define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /*!< no bit-counting instructions present */ 8174 #define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds CLZ */ 8175 /* SCB_ISAR0[BITFIELD_INSTRS] Bits */ 8176 #define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /*!< BITFIELD_INSTRS Bit Offset */ 8177 #define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /*!< BITFIELD_INSTRS Bit Mask */ 8178 #define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /*!< BITFIELD_INSTRS Bit 0 */ 8179 #define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /*!< BITFIELD_INSTRS Bit 1 */ 8180 #define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /*!< BITFIELD_INSTRS Bit 2 */ 8181 #define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /*!< BITFIELD_INSTRS Bit 3 */ 8182 #define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /*!< no bitfield instructions present */ 8183 #define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /*!< adds BFC, BFI, SBFX, UBFX */ 8184 /* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */ 8185 #define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /*!< CMPBRANCH_INSTRS Bit Offset */ 8186 #define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /*!< CMPBRANCH_INSTRS Bit Mask */ 8187 #define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /*!< CMPBRANCH_INSTRS Bit 0 */ 8188 #define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /*!< CMPBRANCH_INSTRS Bit 1 */ 8189 #define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /*!< CMPBRANCH_INSTRS Bit 2 */ 8190 #define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /*!< CMPBRANCH_INSTRS Bit 3 */ 8191 #define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no combined compare-and-branch instructions present */ 8192 #define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /*!< adds CB{N}Z */ 8193 /* SCB_ISAR0[COPROC_INSTRS] Bits */ 8194 #define SCB_ISAR0_COPROC_INSTRS_OFS (16) /*!< COPROC_INSTRS Bit Offset */ 8195 #define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /*!< COPROC_INSTRS Bit Mask */ 8196 #define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /*!< COPROC_INSTRS Bit 0 */ 8197 #define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /*!< COPROC_INSTRS Bit 1 */ 8198 #define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /*!< COPROC_INSTRS Bit 2 */ 8199 #define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /*!< COPROC_INSTRS Bit 3 */ 8200 #define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /*!< no coprocessor support, other than for separately attributed architectures */ 8201 /* such as CP15 or VFP */ 8202 #define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /*!< adds generic CDP, LDC, MCR, MRC, STC */ 8203 #define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */ 8204 #define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /*!< adds generic MCRR, MRRC */ 8205 #define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /*!< adds generic MCRR2, MRRC2 */ 8206 /* SCB_ISAR0[DEBUG_INSTRS] Bits */ 8207 #define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /*!< DEBUG_INSTRS Bit Offset */ 8208 #define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /*!< DEBUG_INSTRS Bit Mask */ 8209 #define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /*!< DEBUG_INSTRS Bit 0 */ 8210 #define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /*!< DEBUG_INSTRS Bit 1 */ 8211 #define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /*!< DEBUG_INSTRS Bit 2 */ 8212 #define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /*!< DEBUG_INSTRS Bit 3 */ 8213 #define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /*!< no debug instructions present */ 8214 #define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /*!< adds BKPT */ 8215 /* SCB_ISAR0[DIVIDE_INSTRS] Bits */ 8216 #define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /*!< DIVIDE_INSTRS Bit Offset */ 8217 #define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /*!< DIVIDE_INSTRS Bit Mask */ 8218 #define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /*!< DIVIDE_INSTRS Bit 0 */ 8219 #define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /*!< DIVIDE_INSTRS Bit 1 */ 8220 #define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /*!< DIVIDE_INSTRS Bit 2 */ 8221 #define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /*!< DIVIDE_INSTRS Bit 3 */ 8222 #define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /*!< no divide instructions present */ 8223 #define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /*!< adds SDIV, UDIV (v1 quotient only result) */ 8224 /* SCB_ISAR1[ETEND_INSRS] Bits */ 8225 #define SCB_ISAR1_ETEND_INSRS_OFS (12) /*!< EXTEND_INSRS Bit Offset */ 8226 #define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /*!< EXTEND_INSRS Bit Mask */ 8227 #define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /*!< ETEND_INSRS Bit 0 */ 8228 #define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /*!< ETEND_INSRS Bit 1 */ 8229 #define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /*!< ETEND_INSRS Bit 2 */ 8230 #define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /*!< ETEND_INSRS Bit 3 */ 8231 #define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */ 8232 #define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /*!< adds SXTB, SXTH, UXTB, UXTH */ 8233 #define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /*!< N/A */ 8234 /* SCB_ISAR1[IFTHEN_INSTRS] Bits */ 8235 #define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /*!< IFTHEN_INSTRS Bit Offset */ 8236 #define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /*!< IFTHEN_INSTRS Bit Mask */ 8237 #define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /*!< IFTHEN_INSTRS Bit 0 */ 8238 #define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /*!< IFTHEN_INSTRS Bit 1 */ 8239 #define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /*!< IFTHEN_INSTRS Bit 2 */ 8240 #define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /*!< IFTHEN_INSTRS Bit 3 */ 8241 #define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /*!< IT instructions not present */ 8242 #define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /*!< adds IT instructions (and IT bits in PSRs) */ 8243 /* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */ 8244 #define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /*!< IMMEDIATE_INSTRS Bit Offset */ 8245 #define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /*!< IMMEDIATE_INSTRS Bit Mask */ 8246 #define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /*!< IMMEDIATE_INSTRS Bit 0 */ 8247 #define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /*!< IMMEDIATE_INSTRS Bit 1 */ 8248 #define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /*!< IMMEDIATE_INSTRS Bit 2 */ 8249 #define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /*!< IMMEDIATE_INSTRS Bit 3 */ 8250 #define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no special immediate-generating instructions present */ 8251 #define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /*!< adds ADDW, MOVW, MOVT, SUBW */ 8252 /* SCB_ISAR1[INTERWORK_INSTRS] Bits */ 8253 #define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /*!< INTERWORK_INSTRS Bit Offset */ 8254 #define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /*!< INTERWORK_INSTRS Bit Mask */ 8255 #define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /*!< INTERWORK_INSTRS Bit 0 */ 8256 #define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /*!< INTERWORK_INSTRS Bit 1 */ 8257 #define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /*!< INTERWORK_INSTRS Bit 2 */ 8258 #define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /*!< INTERWORK_INSTRS Bit 3 */ 8259 #define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /*!< no interworking instructions supported */ 8260 #define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /*!< adds BX (and T bit in PSRs) */ 8261 #define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /*!< adds BLX, and PC loads have BX-like behavior */ 8262 #define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /*!< N/A */ 8263 /* SCB_ISAR2[LOADSTORE_INSTRS] Bits */ 8264 #define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /*!< LOADSTORE_INSTRS Bit Offset */ 8265 #define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< LOADSTORE_INSTRS Bit Mask */ 8266 #define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /*!< LOADSTORE_INSTRS Bit 0 */ 8267 #define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /*!< LOADSTORE_INSTRS Bit 1 */ 8268 #define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /*!< LOADSTORE_INSTRS Bit 2 */ 8269 #define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /*!< LOADSTORE_INSTRS Bit 3 */ 8270 #define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /*!< no additional normal load/store instructions present */ 8271 #define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRD/STRD */ 8272 /* SCB_ISAR2[MEMHINT_INSTRS] Bits */ 8273 #define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /*!< MEMHINT_INSTRS Bit Offset */ 8274 #define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< MEMHINT_INSTRS Bit Mask */ 8275 #define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /*!< MEMHINT_INSTRS Bit 0 */ 8276 #define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /*!< MEMHINT_INSTRS Bit 1 */ 8277 #define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /*!< MEMHINT_INSTRS Bit 2 */ 8278 #define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /*!< MEMHINT_INSTRS Bit 3 */ 8279 #define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /*!< no memory hint instructions presen */ 8280 #define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds PLD */ 8281 #define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /*!< adds PLD (ie a repeat on value 1) */ 8282 #define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /*!< adds PLI */ 8283 /* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */ 8284 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /*!< MULTIACCESSINT_INSTRS Bit Offset */ 8285 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /*!< MULTIACCESSINT_INSTRS Bit Mask */ 8286 #define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /*!< MULTIACCESSINT_INSTRS Bit 0 */ 8287 #define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /*!< MULTIACCESSINT_INSTRS Bit 1 */ 8288 #define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /*!< MULTIACCESSINT_INSTRS Bit 2 */ 8289 #define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /*!< MULTIACCESSINT_INSTRS Bit 3 */ 8290 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /*!< the (LDM/STM) instructions are non-interruptible */ 8291 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /*!< the (LDM/STM) instructions are restartable */ 8292 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /*!< the (LDM/STM) instructions are continuable */ 8293 /* SCB_ISAR2[MULT_INSTRS] Bits */ 8294 #define SCB_ISAR2_MULT_INSTRS_OFS (12) /*!< MULT_INSTRS Bit Offset */ 8295 #define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /*!< MULT_INSTRS Bit Mask */ 8296 #define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /*!< MULT_INSTRS Bit 0 */ 8297 #define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /*!< MULT_INSTRS Bit 1 */ 8298 #define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /*!< MULT_INSTRS Bit 2 */ 8299 #define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /*!< MULT_INSTRS Bit 3 */ 8300 #define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /*!< only MUL present */ 8301 #define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /*!< adds MLA */ 8302 #define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /*!< adds MLS */ 8303 /* SCB_ISAR2[MULTS_INSTRS] Bits */ 8304 #define SCB_ISAR2_MULTS_INSTRS_OFS (16) /*!< MULTS_INSTRS Bit Offset */ 8305 #define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /*!< MULTS_INSTRS Bit Mask */ 8306 #define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /*!< MULTS_INSTRS Bit 0 */ 8307 #define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /*!< MULTS_INSTRS Bit 1 */ 8308 #define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /*!< MULTS_INSTRS Bit 2 */ 8309 #define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /*!< MULTS_INSTRS Bit 3 */ 8310 #define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /*!< no signed multiply instructions present */ 8311 #define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /*!< adds SMULL, SMLAL */ 8312 #define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /*!< N/A */ 8313 #define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /*!< N/A */ 8314 /* SCB_ISAR2[MULTU_INSTRS] Bits */ 8315 #define SCB_ISAR2_MULTU_INSTRS_OFS (20) /*!< MULTU_INSTRS Bit Offset */ 8316 #define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /*!< MULTU_INSTRS Bit Mask */ 8317 #define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /*!< MULTU_INSTRS Bit 0 */ 8318 #define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /*!< MULTU_INSTRS Bit 1 */ 8319 #define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /*!< MULTU_INSTRS Bit 2 */ 8320 #define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /*!< MULTU_INSTRS Bit 3 */ 8321 #define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /*!< no unsigned multiply instructions present */ 8322 #define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /*!< adds UMULL, UMLAL */ 8323 #define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /*!< N/A */ 8324 /* SCB_ISAR2[REVERSAL_INSTRS] Bits */ 8325 #define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /*!< REVERSAL_INSTRS Bit Offset */ 8326 #define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /*!< REVERSAL_INSTRS Bit Mask */ 8327 #define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /*!< REVERSAL_INSTRS Bit 0 */ 8328 #define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /*!< REVERSAL_INSTRS Bit 1 */ 8329 #define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /*!< REVERSAL_INSTRS Bit 2 */ 8330 #define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /*!< REVERSAL_INSTRS Bit 3 */ 8331 #define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /*!< no reversal instructions present */ 8332 #define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /*!< adds REV, REV16, REVSH */ 8333 #define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /*!< adds RBIT */ 8334 /* SCB_ISAR3[SATRUATE_INSTRS] Bits */ 8335 #define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /*!< SATRUATE_INSTRS Bit Offset */ 8336 #define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< SATRUATE_INSTRS Bit Mask */ 8337 #define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /*!< SATRUATE_INSTRS Bit 0 */ 8338 #define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /*!< SATRUATE_INSTRS Bit 1 */ 8339 #define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /*!< SATRUATE_INSTRS Bit 2 */ 8340 #define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /*!< SATRUATE_INSTRS Bit 3 */ 8341 #define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no non-SIMD saturate instructions present */ 8342 #define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /*!< N/A */ 8343 /* SCB_ISAR3[SIMD_INSTRS] Bits */ 8344 #define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /*!< SIMD_INSTRS Bit Offset */ 8345 #define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /*!< SIMD_INSTRS Bit Mask */ 8346 #define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /*!< SIMD_INSTRS Bit 0 */ 8347 #define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /*!< SIMD_INSTRS Bit 1 */ 8348 #define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /*!< SIMD_INSTRS Bit 2 */ 8349 #define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /*!< SIMD_INSTRS Bit 3 */ 8350 #define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /*!< no SIMD instructions present */ 8351 #define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /*!< adds SSAT, USAT (and the Q flag in the PSRs) */ 8352 #define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /*!< N/A */ 8353 /* SCB_ISAR3[SVC_INSTRS] Bits */ 8354 #define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /*!< SVC_INSTRS Bit Offset */ 8355 #define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /*!< SVC_INSTRS Bit Mask */ 8356 #define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /*!< SVC_INSTRS Bit 0 */ 8357 #define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /*!< SVC_INSTRS Bit 1 */ 8358 #define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /*!< SVC_INSTRS Bit 2 */ 8359 #define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /*!< SVC_INSTRS Bit 3 */ 8360 #define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /*!< no SVC (SWI) instructions present */ 8361 #define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /*!< adds SVC (SWI) */ 8362 /* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */ 8363 #define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /*!< SYNCPRIM_INSTRS Bit Offset */ 8364 #define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /*!< SYNCPRIM_INSTRS Bit Mask */ 8365 #define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /*!< SYNCPRIM_INSTRS Bit 0 */ 8366 #define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /*!< SYNCPRIM_INSTRS Bit 1 */ 8367 #define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /*!< SYNCPRIM_INSTRS Bit 2 */ 8368 #define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /*!< SYNCPRIM_INSTRS Bit 3 */ 8369 #define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /*!< no synchronization primitives present */ 8370 #define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /*!< adds LDREX, STREX */ 8371 #define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */ 8372 /* SCB_ISAR3[TABBRANCH_INSTRS] Bits */ 8373 #define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /*!< TABBRANCH_INSTRS Bit Offset */ 8374 #define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /*!< TABBRANCH_INSTRS Bit Mask */ 8375 #define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /*!< TABBRANCH_INSTRS Bit 0 */ 8376 #define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /*!< TABBRANCH_INSTRS Bit 1 */ 8377 #define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /*!< TABBRANCH_INSTRS Bit 2 */ 8378 #define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /*!< TABBRANCH_INSTRS Bit 3 */ 8379 #define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no table-branch instructions present */ 8380 #define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /*!< adds TBB, TBH */ 8381 /* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */ 8382 #define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /*!< THUMBCOPY_INSTRS Bit Offset */ 8383 #define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /*!< THUMBCOPY_INSTRS Bit Mask */ 8384 #define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /*!< THUMBCOPY_INSTRS Bit 0 */ 8385 #define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /*!< THUMBCOPY_INSTRS Bit 1 */ 8386 #define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /*!< THUMBCOPY_INSTRS Bit 2 */ 8387 #define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /*!< THUMBCOPY_INSTRS Bit 3 */ 8388 #define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */ 8389 #define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */ 8390 /* SCB_ISAR3[TRUENOP_INSTRS] Bits */ 8391 #define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /*!< TRUENOP_INSTRS Bit Offset */ 8392 #define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /*!< TRUENOP_INSTRS Bit Mask */ 8393 #define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /*!< TRUENOP_INSTRS Bit 0 */ 8394 #define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /*!< TRUENOP_INSTRS Bit 1 */ 8395 #define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /*!< TRUENOP_INSTRS Bit 2 */ 8396 #define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /*!< TRUENOP_INSTRS Bit 3 */ 8397 #define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /*!< true NOP instructions not present - that is, NOP instructions with no */ 8398 /* register dependencies */ 8399 #define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */ 8400 /* SCB_ISAR4[UNPRIV_INSTRS] Bits */ 8401 #define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /*!< UNPRIV_INSTRS Bit Offset */ 8402 #define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /*!< UNPRIV_INSTRS Bit Mask */ 8403 #define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /*!< UNPRIV_INSTRS Bit 0 */ 8404 #define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /*!< UNPRIV_INSTRS Bit 1 */ 8405 #define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /*!< UNPRIV_INSTRS Bit 2 */ 8406 #define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /*!< UNPRIV_INSTRS Bit 3 */ 8407 #define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /*!< no "T variant" instructions exist */ 8408 #define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRBT, LDRT, STRBT, STRT */ 8409 #define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */ 8410 /* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */ 8411 #define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /*!< WITHSHIFTS_INSTRS Bit Offset */ 8412 #define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /*!< WITHSHIFTS_INSTRS Bit Mask */ 8413 #define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /*!< WITHSHIFTS_INSTRS Bit 0 */ 8414 #define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /*!< WITHSHIFTS_INSTRS Bit 1 */ 8415 #define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /*!< WITHSHIFTS_INSTRS Bit 2 */ 8416 #define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /*!< WITHSHIFTS_INSTRS Bit 3 */ 8417 #define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /*!< non-zero shifts only support MOV and shift instructions (see notes) */ 8418 #define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /*!< shifts of loads/stores over the range LSL 0-3 */ 8419 #define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /*!< adds other constant shift options. */ 8420 #define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /*!< adds register-controlled shift options. */ 8421 /* SCB_ISAR4[WRITEBACK_INSTRS] Bits */ 8422 #define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /*!< WRITEBACK_INSTRS Bit Offset */ 8423 #define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /*!< WRITEBACK_INSTRS Bit Mask */ 8424 #define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /*!< WRITEBACK_INSTRS Bit 0 */ 8425 #define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /*!< WRITEBACK_INSTRS Bit 1 */ 8426 #define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /*!< WRITEBACK_INSTRS Bit 2 */ 8427 #define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /*!< WRITEBACK_INSTRS Bit 3 */ 8428 #define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /*!< only non-writeback addressing modes present, except that */ 8429 /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */ 8430 #define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */ 8431 /* SCB_ISAR4[BARRIER_INSTRS] Bits */ 8432 #define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /*!< BARRIER_INSTRS Bit Offset */ 8433 #define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /*!< BARRIER_INSTRS Bit Mask */ 8434 #define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /*!< BARRIER_INSTRS Bit 0 */ 8435 #define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /*!< BARRIER_INSTRS Bit 1 */ 8436 #define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /*!< BARRIER_INSTRS Bit 2 */ 8437 #define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /*!< BARRIER_INSTRS Bit 3 */ 8438 #define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /*!< no barrier instructions supported */ 8439 #define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /*!< adds DMB, DSB, ISB barrier instructions */ 8440 /* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */ 8441 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */ 8442 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */ 8443 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */ 8444 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */ 8445 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */ 8446 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */ 8447 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /*!< no additional support */ 8448 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */ 8449 /* SCB_ISAR4[PSR_M_INSTRS] Bits */ 8450 #define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /*!< PSR_M_INSTRS Bit Offset */ 8451 #define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /*!< PSR_M_INSTRS Bit Mask */ 8452 #define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /*!< PSR_M_INSTRS Bit 0 */ 8453 #define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /*!< PSR_M_INSTRS Bit 1 */ 8454 #define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /*!< PSR_M_INSTRS Bit 2 */ 8455 #define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /*!< PSR_M_INSTRS Bit 3 */ 8456 #define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /*!< instructions not present */ 8457 #define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */ 8458 /* SCB_CPACR[CP11] Bits */ 8459 #define SCB_CPACR_CP11_OFS (22) /*!< CP11 Bit Offset */ 8460 #define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /*!< CP11 Bit Mask */ 8461 /* SCB_CPACR[CP10] Bits */ 8462 #define SCB_CPACR_CP10_OFS (20) /*!< CP10 Bit Offset */ 8463 #define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /*!< CP10 Bit Mask */ 8464 /* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */ 8465 #define SCB_SHPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ 8466 #define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ 8467 /* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */ 8468 #define SCB_SHPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ 8469 #define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ 8470 /* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */ 8471 #define SCB_SHPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ 8472 #define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ 8473 /* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */ 8474 #define SCB_SHPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ 8475 #define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */ 8476 /* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */ 8477 #define SCB_SHPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ 8478 #define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ 8479 /* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */ 8480 #define SCB_SHPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ 8481 #define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ 8482 /* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */ 8483 #define SCB_SHPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ 8484 #define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ 8485 /* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */ 8486 #define SCB_SHPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ 8487 #define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */ 8488 /* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */ 8489 #define SCB_SHPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ 8490 #define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ 8491 /* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */ 8492 #define SCB_SHPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ 8493 #define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ 8494 /* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */ 8495 #define SCB_SHPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ 8496 #define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ 8497 /* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */ 8498 #define SCB_SHPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ 8499 #define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */ 8500 8501 /* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */ 8502 #define SCB_CFSR_IACCVIOL_OFS ( 0) /*!< IACCVIOL Offset */ 8503 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */ 8504 /* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */ 8505 #define SCB_CFSR_DACCVIOL_OFS ( 1) /*!< DACCVIOL Offset */ 8506 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */ 8507 /* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */ 8508 #define SCB_CFSR_MUNSTKERR_OFS ( 3) /*!< MUNSTKERR Offset */ 8509 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */ 8510 /* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */ 8511 #define SCB_CFSR_MSTKERR_OFS ( 4) /*!< MSTKERR Offset */ 8512 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */ 8513 /* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */ 8514 #define SCB_CFSR_MMARVALID_OFS ( 7) /*!< MMARVALID Offset */ 8515 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */ 8516 /* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */ 8517 #define SCB_CFSR_IBUSERR_OFS ( 8) /*!< IBUSERR Offset */ 8518 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */ 8519 /* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */ 8520 #define SCB_CFSR_PRECISERR_OFS ( 9) /*!< PRECISERR Offset */ 8521 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */ 8522 /* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */ 8523 #define SCB_CFSR_IMPRECISERR_OFS (10) /*!< IMPRECISERR Offset */ 8524 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */ 8525 /* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */ 8526 #define SCB_CFSR_UNSTKERR_OFS (11) /*!< UNSTKERR Offset */ 8527 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */ 8528 /* SCB_CFSR[SCB_CFSR_STKERR] Bits */ 8529 #define SCB_CFSR_STKERR_OFS (12) /*!< STKERR Offset */ 8530 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */ 8531 /* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */ 8532 #define SCB_CFSR_BFARVALID_OFS (15) /*!< BFARVALID Offset */ 8533 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */ 8534 /* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */ 8535 #define SCB_CFSR_UNDEFINSTR_OFS (16) /*!< UNDEFINSTR Offset */ 8536 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */ 8537 /* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */ 8538 #define SCB_CFSR_INVSTATE_OFS (17) /*!< INVSTATE Offset */ 8539 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */ 8540 /* SCB_CFSR[SCB_CFSR_INVPC] Bits */ 8541 #define SCB_CFSR_INVPC_OFS (18) /*!< INVPC Offset */ 8542 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */ 8543 /* SCB_CFSR[SCB_CFSR_NOCP] Bits */ 8544 #define SCB_CFSR_NOCP_OFS (19) /*!< NOCP Offset */ 8545 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */ 8546 /* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */ 8547 #define SCB_CFSR_UNALIGNED_OFS (24) /*!< UNALIGNED Offset */ 8548 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */ 8549 /* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */ 8550 #define SCB_CFSR_DIVBYZERO_OFS (25) /*!< DIVBYZERO Offset */ 8551 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */ 8552 /* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */ 8553 #define SCB_CFSR_MLSPERR_OFS ( 5) /*!< MLSPERR Offset */ 8554 #define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */ 8555 /* SCB_CFSR[SCB_CFSR_LSPERR] Bits */ 8556 #define SCB_CFSR_LSPERR_OFS (13) /*!< LSPERR Offset */ 8557 #define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */ 8558 8559 8560 /****************************************************************************** 8561 * SCNSCB Bits 8562 ******************************************************************************/ 8563 8564 8565 /****************************************************************************** 8566 * SYSCTL_A Bits 8567 ******************************************************************************/ 8568 /* SYSCTL_A_REBOOT_CTL[REBOOT] Bits */ 8569 #define SYSCTL_A_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ 8570 #define SYSCTL_A_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ 8571 /* SYSCTL_A_REBOOT_CTL[WKEY] Bits */ 8572 #define SYSCTL_A_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ 8573 #define SYSCTL_A_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ 8574 /* SYSCTL_A_NMI_CTLSTAT[CS_SRC] Bits */ 8575 #define SYSCTL_A_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ 8576 #define SYSCTL_A_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ 8577 /* SYSCTL_A_NMI_CTLSTAT[PSS_SRC] Bits */ 8578 #define SYSCTL_A_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ 8579 #define SYSCTL_A_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ 8580 /* SYSCTL_A_NMI_CTLSTAT[PCM_SRC] Bits */ 8581 #define SYSCTL_A_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ 8582 #define SYSCTL_A_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ 8583 /* SYSCTL_A_NMI_CTLSTAT[PIN_SRC] Bits */ 8584 #define SYSCTL_A_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ 8585 #define SYSCTL_A_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) 8586 /* SYSCTL_A_NMI_CTLSTAT[CS_FLG] Bits */ 8587 #define SYSCTL_A_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ 8588 #define SYSCTL_A_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ 8589 /* SYSCTL_A_NMI_CTLSTAT[PSS_FLG] Bits */ 8590 #define SYSCTL_A_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ 8591 #define SYSCTL_A_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ 8592 /* SYSCTL_A_NMI_CTLSTAT[PCM_FLG] Bits */ 8593 #define SYSCTL_A_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ 8594 #define SYSCTL_A_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ 8595 /* SYSCTL_A_NMI_CTLSTAT[PIN_FLG] Bits */ 8596 #define SYSCTL_A_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ 8597 #define SYSCTL_A_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ 8598 /* SYSCTL_A_WDTRESET_CTL[TIMEOUT] Bits */ 8599 #define SYSCTL_A_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ 8600 #define SYSCTL_A_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ 8601 /* SYSCTL_A_WDTRESET_CTL[VIOLATION] Bits */ 8602 #define SYSCTL_A_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ 8603 #define SYSCTL_A_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ 8604 /* SYSCTL_A_PERIHALT_CTL[HALT_T16_0] Bits */ 8605 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ 8606 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ 8607 /* SYSCTL_A_PERIHALT_CTL[HALT_T16_1] Bits */ 8608 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ 8609 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ 8610 /* SYSCTL_A_PERIHALT_CTL[HALT_T16_2] Bits */ 8611 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ 8612 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ 8613 /* SYSCTL_A_PERIHALT_CTL[HALT_T16_3] Bits */ 8614 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ 8615 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ 8616 /* SYSCTL_A_PERIHALT_CTL[HALT_T32_0] Bits */ 8617 #define SYSCTL_A_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ 8618 #define SYSCTL_A_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ 8619 /* SYSCTL_A_PERIHALT_CTL[HALT_eUA0] Bits */ 8620 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ 8621 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ 8622 /* SYSCTL_A_PERIHALT_CTL[HALT_eUA1] Bits */ 8623 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ 8624 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ 8625 /* SYSCTL_A_PERIHALT_CTL[HALT_eUA2] Bits */ 8626 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ 8627 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ 8628 /* SYSCTL_A_PERIHALT_CTL[HALT_eUA3] Bits */ 8629 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ 8630 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ 8631 /* SYSCTL_A_PERIHALT_CTL[HALT_eUB0] Bits */ 8632 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ 8633 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ 8634 /* SYSCTL_A_PERIHALT_CTL[HALT_eUB1] Bits */ 8635 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ 8636 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ 8637 /* SYSCTL_A_PERIHALT_CTL[HALT_eUB2] Bits */ 8638 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ 8639 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ 8640 /* SYSCTL_A_PERIHALT_CTL[HALT_eUB3] Bits */ 8641 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ 8642 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ 8643 /* SYSCTL_A_PERIHALT_CTL[HALT_ADC] Bits */ 8644 #define SYSCTL_A_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ 8645 #define SYSCTL_A_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ 8646 /* SYSCTL_A_PERIHALT_CTL[HALT_WDT] Bits */ 8647 #define SYSCTL_A_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ 8648 #define SYSCTL_A_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ 8649 /* SYSCTL_A_PERIHALT_CTL[HALT_DMA] Bits */ 8650 #define SYSCTL_A_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ 8651 #define SYSCTL_A_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ 8652 /* SYSCTL_A_PERIHALT_CTL[HALT_LCD] Bits */ 8653 #define SYSCTL_A_PERIHALT_CTL_HALT_LCD_OFS (16) /*!< HALT_LCD Bit Offset */ 8654 #define SYSCTL_A_PERIHALT_CTL_HALT_LCD ((uint32_t)0x00010000) /*!< Freezes IP operation when CPU is halted */ 8655 /* SYSCTL_A_DIO_GLTFLT_CTL[GLTCH_EN] Bits */ 8656 #define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ 8657 #define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ 8658 /* SYSCTL_A_SECDATA_UNLOCK[UNLKEY] Bits */ 8659 #define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ 8660 #define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ 8661 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK0_EN] Bits */ 8662 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ 8663 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank0 of the SRAM */ 8664 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK1_EN] Bits */ 8665 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ 8666 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank1 of the SRAM */ 8667 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK2_EN] Bits */ 8668 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ 8669 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank2 of the SRAM */ 8670 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK3_EN] Bits */ 8671 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ 8672 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank3 of the SRAM */ 8673 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK4_EN] Bits */ 8674 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ 8675 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank4 of the SRAM */ 8676 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK5_EN] Bits */ 8677 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ 8678 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank5 of the SRAM */ 8679 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK6_EN] Bits */ 8680 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ 8681 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank6 of the SRAM */ 8682 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK7_EN] Bits */ 8683 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ 8684 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank7 of the SRAM */ 8685 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK8_EN] Bits */ 8686 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN_OFS ( 8) /*!< BNK8_EN Bit Offset */ 8687 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank8 of the SRAM */ 8688 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK9_EN] Bits */ 8689 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN_OFS ( 9) /*!< BNK9_EN Bit Offset */ 8690 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank9 of the SRAM */ 8691 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK10_EN] Bits */ 8692 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN_OFS (10) /*!< BNK10_EN Bit Offset */ 8693 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank10 of the SRAM */ 8694 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK11_EN] Bits */ 8695 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN_OFS (11) /*!< BNK11_EN Bit Offset */ 8696 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank11 of the SRAM */ 8697 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK12_EN] Bits */ 8698 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN_OFS (12) /*!< BNK12_EN Bit Offset */ 8699 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank12 of the SRAM */ 8700 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK13_EN] Bits */ 8701 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN_OFS (13) /*!< BNK13_EN Bit Offset */ 8702 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank13 of the SRAM */ 8703 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK14_EN] Bits */ 8704 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN_OFS (14) /*!< BNK14_EN Bit Offset */ 8705 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank14 of the SRAM */ 8706 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK15_EN] Bits */ 8707 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN_OFS (15) /*!< BNK15_EN Bit Offset */ 8708 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank15 of the SRAM */ 8709 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK16_EN] Bits */ 8710 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN_OFS (16) /*!< BNK16_EN Bit Offset */ 8711 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank16 of the SRAM */ 8712 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK17_EN] Bits */ 8713 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN_OFS (17) /*!< BNK17_EN Bit Offset */ 8714 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank17 of the SRAM */ 8715 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK18_EN] Bits */ 8716 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN_OFS (18) /*!< BNK18_EN Bit Offset */ 8717 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank18 of the SRAM */ 8718 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK19_EN] Bits */ 8719 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN_OFS (19) /*!< BNK19_EN Bit Offset */ 8720 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank19 of the SRAM */ 8721 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK20_EN] Bits */ 8722 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN_OFS (20) /*!< BNK20_EN Bit Offset */ 8723 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank20 of the SRAM */ 8724 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK21_EN] Bits */ 8725 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN_OFS (21) /*!< BNK21_EN Bit Offset */ 8726 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank21 of the SRAM */ 8727 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK22_EN] Bits */ 8728 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN_OFS (22) /*!< BNK22_EN Bit Offset */ 8729 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank22 of the SRAM */ 8730 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK23_EN] Bits */ 8731 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN_OFS (23) /*!< BNK23_EN Bit Offset */ 8732 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank23 of the SRAM */ 8733 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK24_EN] Bits */ 8734 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN_OFS (24) /*!< BNK24_EN Bit Offset */ 8735 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank24 of the SRAM */ 8736 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK25_EN] Bits */ 8737 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN_OFS (25) /*!< BNK25_EN Bit Offset */ 8738 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank25 of the SRAM */ 8739 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK26_EN] Bits */ 8740 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN_OFS (26) /*!< BNK26_EN Bit Offset */ 8741 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank26 of the SRAM */ 8742 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK27_EN] Bits */ 8743 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN_OFS (27) /*!< BNK27_EN Bit Offset */ 8744 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank27 of the SRAM */ 8745 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK28_EN] Bits */ 8746 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN_OFS (28) /*!< BNK28_EN Bit Offset */ 8747 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank28 of the SRAM */ 8748 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK29_EN] Bits */ 8749 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN_OFS (29) /*!< BNK29_EN Bit Offset */ 8750 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank29 of the SRAM */ 8751 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK30_EN] Bits */ 8752 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN_OFS (30) /*!< BNK30_EN Bit Offset */ 8753 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank30 of the SRAM */ 8754 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK31_EN] Bits */ 8755 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN_OFS (31) /*!< BNK31_EN Bit Offset */ 8756 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank31 of the SRAM */ 8757 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK32_EN] Bits */ 8758 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN_OFS ( 0) /*!< BNK32_EN Bit Offset */ 8759 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank32 of the SRAM */ 8760 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK33_EN] Bits */ 8761 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN_OFS ( 1) /*!< BNK33_EN Bit Offset */ 8762 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank33 of the SRAM */ 8763 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK34_EN] Bits */ 8764 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN_OFS ( 2) /*!< BNK34_EN Bit Offset */ 8765 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank34 of the SRAM */ 8766 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK35_EN] Bits */ 8767 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN_OFS ( 3) /*!< BNK35_EN Bit Offset */ 8768 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank35 of the SRAM */ 8769 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK36_EN] Bits */ 8770 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN_OFS ( 4) /*!< BNK36_EN Bit Offset */ 8771 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank36 of the SRAM */ 8772 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK37_EN] Bits */ 8773 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN_OFS ( 5) /*!< BNK37_EN Bit Offset */ 8774 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank37 of the SRAM */ 8775 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK38_EN] Bits */ 8776 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN_OFS ( 6) /*!< BNK38_EN Bit Offset */ 8777 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank38 of the SRAM */ 8778 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK39_EN] Bits */ 8779 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN_OFS ( 7) /*!< BNK39_EN Bit Offset */ 8780 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank39 of the SRAM */ 8781 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK40_EN] Bits */ 8782 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN_OFS ( 8) /*!< BNK40_EN Bit Offset */ 8783 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank40 of the SRAM */ 8784 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK41_EN] Bits */ 8785 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN_OFS ( 9) /*!< BNK41_EN Bit Offset */ 8786 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank41 of the SRAM */ 8787 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK42_EN] Bits */ 8788 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN_OFS (10) /*!< BNK42_EN Bit Offset */ 8789 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank42 of the SRAM */ 8790 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK43_EN] Bits */ 8791 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN_OFS (11) /*!< BNK43_EN Bit Offset */ 8792 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank43 of the SRAM */ 8793 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK44_EN] Bits */ 8794 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN_OFS (12) /*!< BNK44_EN Bit Offset */ 8795 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank44 of the SRAM */ 8796 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK45_EN] Bits */ 8797 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN_OFS (13) /*!< BNK45_EN Bit Offset */ 8798 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank45 of the SRAM */ 8799 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK46_EN] Bits */ 8800 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN_OFS (14) /*!< BNK46_EN Bit Offset */ 8801 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank46 of the SRAM */ 8802 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK47_EN] Bits */ 8803 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN_OFS (15) /*!< BNK47_EN Bit Offset */ 8804 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank47 of the SRAM */ 8805 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK48_EN] Bits */ 8806 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN_OFS (16) /*!< BNK48_EN Bit Offset */ 8807 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank48 of the SRAM */ 8808 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK49_EN] Bits */ 8809 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN_OFS (17) /*!< BNK49_EN Bit Offset */ 8810 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank49 of the SRAM */ 8811 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK50_EN] Bits */ 8812 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN_OFS (18) /*!< BNK50_EN Bit Offset */ 8813 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank50 of the SRAM */ 8814 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK51_EN] Bits */ 8815 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN_OFS (19) /*!< BNK51_EN Bit Offset */ 8816 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank51 of the SRAM */ 8817 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK52_EN] Bits */ 8818 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN_OFS (20) /*!< BNK52_EN Bit Offset */ 8819 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank52 of the SRAM */ 8820 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK53_EN] Bits */ 8821 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN_OFS (21) /*!< BNK53_EN Bit Offset */ 8822 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank53 of the SRAM */ 8823 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK54_EN] Bits */ 8824 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN_OFS (22) /*!< BNK54_EN Bit Offset */ 8825 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank54 of the SRAM */ 8826 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK55_EN] Bits */ 8827 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN_OFS (23) /*!< BNK55_EN Bit Offset */ 8828 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank55 of the SRAM */ 8829 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK56_EN] Bits */ 8830 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN_OFS (24) /*!< BNK56_EN Bit Offset */ 8831 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank56 of the SRAM */ 8832 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK57_EN] Bits */ 8833 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN_OFS (25) /*!< BNK57_EN Bit Offset */ 8834 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank57 of the SRAM */ 8835 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK58_EN] Bits */ 8836 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN_OFS (26) /*!< BNK58_EN Bit Offset */ 8837 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank58 of the SRAM */ 8838 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK59_EN] Bits */ 8839 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN_OFS (27) /*!< BNK59_EN Bit Offset */ 8840 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank59 of the SRAM */ 8841 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK60_EN] Bits */ 8842 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN_OFS (28) /*!< BNK60_EN Bit Offset */ 8843 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank60 of the SRAM */ 8844 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK61_EN] Bits */ 8845 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN_OFS (29) /*!< BNK61_EN Bit Offset */ 8846 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank61 of the SRAM */ 8847 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK62_EN] Bits */ 8848 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN_OFS (30) /*!< BNK62_EN Bit Offset */ 8849 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank62 of the SRAM */ 8850 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK63_EN] Bits */ 8851 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN_OFS (31) /*!< BNK63_EN Bit Offset */ 8852 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank63 of the SRAM */ 8853 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK64_EN] Bits */ 8854 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN_OFS ( 0) /*!< BNK64_EN Bit Offset */ 8855 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank64 of the SRAM */ 8856 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK65_EN] Bits */ 8857 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN_OFS ( 1) /*!< BNK65_EN Bit Offset */ 8858 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank65 of the SRAM */ 8859 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK66_EN] Bits */ 8860 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN_OFS ( 2) /*!< BNK66_EN Bit Offset */ 8861 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank66 of the SRAM */ 8862 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK67_EN] Bits */ 8863 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN_OFS ( 3) /*!< BNK67_EN Bit Offset */ 8864 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank67 of the SRAM */ 8865 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK68_EN] Bits */ 8866 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN_OFS ( 4) /*!< BNK68_EN Bit Offset */ 8867 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank68 of the SRAM */ 8868 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK69_EN] Bits */ 8869 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN_OFS ( 5) /*!< BNK69_EN Bit Offset */ 8870 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank69 of the SRAM */ 8871 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK70_EN] Bits */ 8872 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN_OFS ( 6) /*!< BNK70_EN Bit Offset */ 8873 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank70 of the SRAM */ 8874 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK71_EN] Bits */ 8875 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN_OFS ( 7) /*!< BNK71_EN Bit Offset */ 8876 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank71 of the SRAM */ 8877 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK72_EN] Bits */ 8878 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN_OFS ( 8) /*!< BNK72_EN Bit Offset */ 8879 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank72 of the SRAM */ 8880 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK73_EN] Bits */ 8881 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN_OFS ( 9) /*!< BNK73_EN Bit Offset */ 8882 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank73 of the SRAM */ 8883 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK74_EN] Bits */ 8884 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN_OFS (10) /*!< BNK74_EN Bit Offset */ 8885 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank74 of the SRAM */ 8886 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK75_EN] Bits */ 8887 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN_OFS (11) /*!< BNK75_EN Bit Offset */ 8888 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank75 of the SRAM */ 8889 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK76_EN] Bits */ 8890 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN_OFS (12) /*!< BNK76_EN Bit Offset */ 8891 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank76 of the SRAM */ 8892 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK77_EN] Bits */ 8893 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN_OFS (13) /*!< BNK77_EN Bit Offset */ 8894 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank77 of the SRAM */ 8895 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK78_EN] Bits */ 8896 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN_OFS (14) /*!< BNK78_EN Bit Offset */ 8897 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank78 of the SRAM */ 8898 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK79_EN] Bits */ 8899 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN_OFS (15) /*!< BNK79_EN Bit Offset */ 8900 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank79 of the SRAM */ 8901 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK80_EN] Bits */ 8902 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN_OFS (16) /*!< BNK80_EN Bit Offset */ 8903 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank80 of the SRAM */ 8904 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK81_EN] Bits */ 8905 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN_OFS (17) /*!< BNK81_EN Bit Offset */ 8906 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank81 of the SRAM */ 8907 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK82_EN] Bits */ 8908 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN_OFS (18) /*!< BNK82_EN Bit Offset */ 8909 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank82 of the SRAM */ 8910 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK83_EN] Bits */ 8911 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN_OFS (19) /*!< BNK83_EN Bit Offset */ 8912 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank83 of the SRAM */ 8913 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK84_EN] Bits */ 8914 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN_OFS (20) /*!< BNK84_EN Bit Offset */ 8915 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank84 of the SRAM */ 8916 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK85_EN] Bits */ 8917 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN_OFS (21) /*!< BNK85_EN Bit Offset */ 8918 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank85 of the SRAM */ 8919 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK86_EN] Bits */ 8920 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN_OFS (22) /*!< BNK86_EN Bit Offset */ 8921 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank86 of the SRAM */ 8922 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK87_EN] Bits */ 8923 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN_OFS (23) /*!< BNK87_EN Bit Offset */ 8924 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank87 of the SRAM */ 8925 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK88_EN] Bits */ 8926 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN_OFS (24) /*!< BNK88_EN Bit Offset */ 8927 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank88 of the SRAM */ 8928 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK89_EN] Bits */ 8929 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN_OFS (25) /*!< BNK89_EN Bit Offset */ 8930 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank89 of the SRAM */ 8931 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK90_EN] Bits */ 8932 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN_OFS (26) /*!< BNK90_EN Bit Offset */ 8933 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank90 of the SRAM */ 8934 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK91_EN] Bits */ 8935 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN_OFS (27) /*!< BNK91_EN Bit Offset */ 8936 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank91 of the SRAM */ 8937 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK92_EN] Bits */ 8938 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN_OFS (28) /*!< BNK92_EN Bit Offset */ 8939 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank92 of the SRAM */ 8940 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK93_EN] Bits */ 8941 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN_OFS (29) /*!< BNK93_EN Bit Offset */ 8942 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank93 of the SRAM */ 8943 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK94_EN] Bits */ 8944 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN_OFS (30) /*!< BNK94_EN Bit Offset */ 8945 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank94 of the SRAM */ 8946 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK95_EN] Bits */ 8947 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN_OFS (31) /*!< BNK95_EN Bit Offset */ 8948 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank95 of the SRAM */ 8949 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK96_EN] Bits */ 8950 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN_OFS ( 0) /*!< BNK96_EN Bit Offset */ 8951 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank96 of the SRAM */ 8952 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK97_EN] Bits */ 8953 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN_OFS ( 1) /*!< BNK97_EN Bit Offset */ 8954 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank97 of the SRAM */ 8955 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK98_EN] Bits */ 8956 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN_OFS ( 2) /*!< BNK98_EN Bit Offset */ 8957 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank98 of the SRAM */ 8958 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK99_EN] Bits */ 8959 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN_OFS ( 3) /*!< BNK99_EN Bit Offset */ 8960 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank99 of the SRAM */ 8961 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK100_EN] Bits */ 8962 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN_OFS ( 4) /*!< BNK100_EN Bit Offset */ 8963 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank100 of the SRAM */ 8964 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK101_EN] Bits */ 8965 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN_OFS ( 5) /*!< BNK101_EN Bit Offset */ 8966 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank101 of the SRAM */ 8967 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK102_EN] Bits */ 8968 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN_OFS ( 6) /*!< BNK102_EN Bit Offset */ 8969 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank102 of the SRAM */ 8970 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK103_EN] Bits */ 8971 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN_OFS ( 7) /*!< BNK103_EN Bit Offset */ 8972 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank103 of the SRAM */ 8973 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK104_EN] Bits */ 8974 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN_OFS ( 8) /*!< BNK104_EN Bit Offset */ 8975 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank104 of the SRAM */ 8976 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK105_EN] Bits */ 8977 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN_OFS ( 9) /*!< BNK105_EN Bit Offset */ 8978 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank105 of the SRAM */ 8979 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK106_EN] Bits */ 8980 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN_OFS (10) /*!< BNK106_EN Bit Offset */ 8981 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank106 of the SRAM */ 8982 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK107_EN] Bits */ 8983 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN_OFS (11) /*!< BNK107_EN Bit Offset */ 8984 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank107 of the SRAM */ 8985 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK108_EN] Bits */ 8986 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN_OFS (12) /*!< BNK108_EN Bit Offset */ 8987 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank108 of the SRAM */ 8988 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK109_EN] Bits */ 8989 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN_OFS (13) /*!< BNK109_EN Bit Offset */ 8990 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank109 of the SRAM */ 8991 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK110_EN] Bits */ 8992 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN_OFS (14) /*!< BNK110_EN Bit Offset */ 8993 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank110 of the SRAM */ 8994 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK111_EN] Bits */ 8995 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN_OFS (15) /*!< BNK111_EN Bit Offset */ 8996 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank111 of the SRAM */ 8997 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK112_EN] Bits */ 8998 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN_OFS (16) /*!< BNK112_EN Bit Offset */ 8999 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank112 of the SRAM */ 9000 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK113_EN] Bits */ 9001 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN_OFS (17) /*!< BNK113_EN Bit Offset */ 9002 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank113 of the SRAM */ 9003 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK114_EN] Bits */ 9004 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN_OFS (18) /*!< BNK114_EN Bit Offset */ 9005 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank114 of the SRAM */ 9006 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK115_EN] Bits */ 9007 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN_OFS (19) /*!< BNK115_EN Bit Offset */ 9008 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank115 of the SRAM */ 9009 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK116_EN] Bits */ 9010 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN_OFS (20) /*!< BNK116_EN Bit Offset */ 9011 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank116 of the SRAM */ 9012 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK117_EN] Bits */ 9013 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN_OFS (21) /*!< BNK117_EN Bit Offset */ 9014 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank117 of the SRAM */ 9015 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK118_EN] Bits */ 9016 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN_OFS (22) /*!< BNK118_EN Bit Offset */ 9017 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank118 of the SRAM */ 9018 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK119_EN] Bits */ 9019 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN_OFS (23) /*!< BNK119_EN Bit Offset */ 9020 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank119 of the SRAM */ 9021 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK120_EN] Bits */ 9022 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN_OFS (24) /*!< BNK120_EN Bit Offset */ 9023 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank120 of the SRAM */ 9024 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK121_EN] Bits */ 9025 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN_OFS (25) /*!< BNK121_EN Bit Offset */ 9026 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank121 of the SRAM */ 9027 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK122_EN] Bits */ 9028 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN_OFS (26) /*!< BNK122_EN Bit Offset */ 9029 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank122 of the SRAM */ 9030 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK123_EN] Bits */ 9031 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN_OFS (27) /*!< BNK123_EN Bit Offset */ 9032 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank123 of the SRAM */ 9033 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK124_EN] Bits */ 9034 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN_OFS (28) /*!< BNK124_EN Bit Offset */ 9035 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank124 of the SRAM */ 9036 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK125_EN] Bits */ 9037 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN_OFS (29) /*!< BNK125_EN Bit Offset */ 9038 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank125 of the SRAM */ 9039 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK126_EN] Bits */ 9040 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN_OFS (30) /*!< BNK126_EN Bit Offset */ 9041 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank126 of the SRAM */ 9042 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK127_EN] Bits */ 9043 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN_OFS (31) /*!< BNK127_EN Bit Offset */ 9044 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank127 of the SRAM */ 9045 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK0_EN] Bits */ 9046 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN_OFS ( 0) /*!< BLK0_EN Bit Offset */ 9047 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN ((uint32_t)0x00000001) /*!< Block0 is always retained in LPM3, LPM4 and LPM3.5 modes of operation */ 9048 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK1_EN] Bits */ 9049 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN_OFS ( 1) /*!< BLK1_EN Bit Offset */ 9050 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN ((uint32_t)0x00000002) /*!< When 1, Block1 of the SRAM is retained in LPM3 and LPM4 */ 9051 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK2_EN] Bits */ 9052 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN_OFS ( 2) /*!< BLK2_EN Bit Offset */ 9053 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN ((uint32_t)0x00000004) /*!< When 1, Block2 of the SRAM is retained in LPM3 and LPM4 */ 9054 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK3_EN] Bits */ 9055 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN_OFS ( 3) /*!< BLK3_EN Bit Offset */ 9056 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN ((uint32_t)0x00000008) /*!< When 1, Block3 of the SRAM is retained in LPM3 and LPM4 */ 9057 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK4_EN] Bits */ 9058 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN_OFS ( 4) /*!< BLK4_EN Bit Offset */ 9059 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN ((uint32_t)0x00000010) /*!< When 1, Block4 of the SRAM is retained in LPM3 and LPM4 */ 9060 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK5_EN] Bits */ 9061 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN_OFS ( 5) /*!< BLK5_EN Bit Offset */ 9062 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN ((uint32_t)0x00000020) /*!< When 1, Block5 of the SRAM is retained in LPM3 and LPM4 */ 9063 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK6_EN] Bits */ 9064 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN_OFS ( 6) /*!< BLK6_EN Bit Offset */ 9065 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN ((uint32_t)0x00000040) /*!< When 1, Block6 of the SRAM is retained in LPM3 and LPM4 */ 9066 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK7_EN] Bits */ 9067 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN_OFS ( 7) /*!< BLK7_EN Bit Offset */ 9068 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN ((uint32_t)0x00000080) /*!< When 1, Block7 of the SRAM is retained in LPM3 and LPM4 */ 9069 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK8_EN] Bits */ 9070 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN_OFS ( 8) /*!< BLK8_EN Bit Offset */ 9071 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN ((uint32_t)0x00000100) /*!< When 1, Block8 of the SRAM is retained in LPM3 and LPM4 */ 9072 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK9_EN] Bits */ 9073 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN_OFS ( 9) /*!< BLK9_EN Bit Offset */ 9074 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN ((uint32_t)0x00000200) /*!< When 1, Block9 of the SRAM is retained in LPM3 and LPM4 */ 9075 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK10_EN] Bits */ 9076 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN_OFS (10) /*!< BLK10_EN Bit Offset */ 9077 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN ((uint32_t)0x00000400) /*!< When 1, Block10 of the SRAM is retained in LPM3 and LPM4 */ 9078 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK11_EN] Bits */ 9079 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN_OFS (11) /*!< BLK11_EN Bit Offset */ 9080 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN ((uint32_t)0x00000800) /*!< When 1, Block11 of the SRAM is retained in LPM3 and LPM4 */ 9081 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK12_EN] Bits */ 9082 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN_OFS (12) /*!< BLK12_EN Bit Offset */ 9083 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN ((uint32_t)0x00001000) /*!< When 1, Block12 of the SRAM is retained in LPM3 and LPM4 */ 9084 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK13_EN] Bits */ 9085 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN_OFS (13) /*!< BLK13_EN Bit Offset */ 9086 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN ((uint32_t)0x00002000) /*!< When 1, Block13 of the SRAM is retained in LPM3 and LPM4 */ 9087 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK14_EN] Bits */ 9088 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN_OFS (14) /*!< BLK14_EN Bit Offset */ 9089 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN ((uint32_t)0x00004000) /*!< When 1, Block14 of the SRAM is retained in LPM3 and LPM4 */ 9090 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK15_EN] Bits */ 9091 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN_OFS (15) /*!< BLK15_EN Bit Offset */ 9092 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN ((uint32_t)0x00008000) /*!< When 1, Block15 of the SRAM is retained in LPM3 and LPM4 */ 9093 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK16_EN] Bits */ 9094 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN_OFS (16) /*!< BLK16_EN Bit Offset */ 9095 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN ((uint32_t)0x00010000) /*!< When 1, Block16 of the SRAM is retained in LPM3 and LPM4 */ 9096 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK17_EN] Bits */ 9097 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN_OFS (17) /*!< BLK17_EN Bit Offset */ 9098 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN ((uint32_t)0x00020000) /*!< When 1, Block17 of the SRAM is retained in LPM3 and LPM4 */ 9099 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK18_EN] Bits */ 9100 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN_OFS (18) /*!< BLK18_EN Bit Offset */ 9101 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN ((uint32_t)0x00040000) /*!< When 1, Block18 of the SRAM is retained in LPM3 and LPM4 */ 9102 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK19_EN] Bits */ 9103 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN_OFS (19) /*!< BLK19_EN Bit Offset */ 9104 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN ((uint32_t)0x00080000) /*!< When 1, Block19 of the SRAM is retained in LPM3 and LPM4 */ 9105 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK20_EN] Bits */ 9106 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN_OFS (20) /*!< BLK20_EN Bit Offset */ 9107 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN ((uint32_t)0x00100000) /*!< When 1, Block20 of the SRAM is retained in LPM3 and LPM4 */ 9108 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK21_EN] Bits */ 9109 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN_OFS (21) /*!< BLK21_EN Bit Offset */ 9110 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN ((uint32_t)0x00200000) /*!< When 1, Block21 of the SRAM is retained in LPM3 and LPM4 */ 9111 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK22_EN] Bits */ 9112 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN_OFS (22) /*!< BLK22_EN Bit Offset */ 9113 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN ((uint32_t)0x00400000) /*!< When 1, Block22 of the SRAM is retained in LPM3 and LPM4 */ 9114 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK23_EN] Bits */ 9115 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN_OFS (23) /*!< BLK23_EN Bit Offset */ 9116 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN ((uint32_t)0x00800000) /*!< When 1, Block23 of the SRAM is retained in LPM3 and LPM4 */ 9117 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK24_EN] Bits */ 9118 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN_OFS (24) /*!< BLK24_EN Bit Offset */ 9119 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN ((uint32_t)0x01000000) /*!< When 1, Block24 of the SRAM is retained in LPM3 and LPM4 */ 9120 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK25_EN] Bits */ 9121 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN_OFS (25) /*!< BLK25_EN Bit Offset */ 9122 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN ((uint32_t)0x02000000) /*!< When 1, Block25 of the SRAM is retained in LPM3 and LPM4 */ 9123 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK26_EN] Bits */ 9124 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN_OFS (26) /*!< BLK26_EN Bit Offset */ 9125 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN ((uint32_t)0x04000000) /*!< When 1, Block26 of the SRAM is retained in LPM3 and LPM4 */ 9126 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK27_EN] Bits */ 9127 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN_OFS (27) /*!< BLK27_EN Bit Offset */ 9128 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN ((uint32_t)0x08000000) /*!< When 1, Block27 of the SRAM is retained in LPM3 and LPM4 */ 9129 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK28_EN] Bits */ 9130 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN_OFS (28) /*!< BLK28_EN Bit Offset */ 9131 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN ((uint32_t)0x10000000) /*!< When 1, Block28 of the SRAM is retained in LPM3 and LPM4 */ 9132 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK29_EN] Bits */ 9133 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN_OFS (29) /*!< BLK29_EN Bit Offset */ 9134 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN ((uint32_t)0x20000000) /*!< When 1, Block29 of the SRAM is retained in LPM3 and LPM4 */ 9135 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK30_EN] Bits */ 9136 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN_OFS (30) /*!< BLK30_EN Bit Offset */ 9137 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN ((uint32_t)0x40000000) /*!< When 1, Block30 of the SRAM is retained in LPM3 and LPM4 */ 9138 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK31_EN] Bits */ 9139 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN_OFS (31) /*!< BLK31_EN Bit Offset */ 9140 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN ((uint32_t)0x80000000) /*!< When 1, Block31 of the SRAM is retained in LPM3 and LPM4 */ 9141 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK32_EN] Bits */ 9142 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN_OFS ( 0) /*!< BLK32_EN Bit Offset */ 9143 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN ((uint32_t)0x00000001) /*!< When 1, Block32 of the SRAM is retained in LPM3 and LPM4 */ 9144 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK33_EN] Bits */ 9145 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN_OFS ( 1) /*!< BLK33_EN Bit Offset */ 9146 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN ((uint32_t)0x00000002) /*!< When 1, Block33 of the SRAM is retained in LPM3 and LPM4 */ 9147 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK34_EN] Bits */ 9148 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN_OFS ( 2) /*!< BLK34_EN Bit Offset */ 9149 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN ((uint32_t)0x00000004) /*!< When 1, Block34 of the SRAM is retained in LPM3 and LPM4 */ 9150 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK35_EN] Bits */ 9151 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN_OFS ( 3) /*!< BLK35_EN Bit Offset */ 9152 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN ((uint32_t)0x00000008) /*!< When 1, Block35 of the SRAM is retained in LPM3 and LPM4 */ 9153 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK36_EN] Bits */ 9154 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN_OFS ( 4) /*!< BLK36_EN Bit Offset */ 9155 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN ((uint32_t)0x00000010) /*!< When 1, Block36 of the SRAM is retained in LPM3 and LPM4 */ 9156 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK37_EN] Bits */ 9157 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN_OFS ( 5) /*!< BLK37_EN Bit Offset */ 9158 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN ((uint32_t)0x00000020) /*!< When 1, Block37 of the SRAM is retained in LPM3 and LPM4 */ 9159 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK38_EN] Bits */ 9160 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN_OFS ( 6) /*!< BLK38_EN Bit Offset */ 9161 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN ((uint32_t)0x00000040) /*!< When 1, Block38 of the SRAM is retained in LPM3 and LPM4 */ 9162 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK39_EN] Bits */ 9163 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN_OFS ( 7) /*!< BLK39_EN Bit Offset */ 9164 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN ((uint32_t)0x00000080) /*!< When 1, Block39 of the SRAM is retained in LPM3 and LPM4 */ 9165 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK40_EN] Bits */ 9166 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN_OFS ( 8) /*!< BLK40_EN Bit Offset */ 9167 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN ((uint32_t)0x00000100) /*!< When 1, Block40 of the SRAM is retained in LPM3 and LPM4 */ 9168 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK41_EN] Bits */ 9169 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN_OFS ( 9) /*!< BLK41_EN Bit Offset */ 9170 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN ((uint32_t)0x00000200) /*!< When 1, Block41 of the SRAM is retained in LPM3 and LPM4 */ 9171 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK42_EN] Bits */ 9172 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN_OFS (10) /*!< BLK42_EN Bit Offset */ 9173 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN ((uint32_t)0x00000400) /*!< When 1, Block42 of the SRAM is retained in LPM3 and LPM4 */ 9174 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK43_EN] Bits */ 9175 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN_OFS (11) /*!< BLK43_EN Bit Offset */ 9176 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN ((uint32_t)0x00000800) /*!< When 1, Block43 of the SRAM is retained in LPM3 and LPM4 */ 9177 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK44_EN] Bits */ 9178 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN_OFS (12) /*!< BLK44_EN Bit Offset */ 9179 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN ((uint32_t)0x00001000) /*!< When 1, Block44 of the SRAM is retained in LPM3 and LPM4 */ 9180 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK45_EN] Bits */ 9181 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN_OFS (13) /*!< BLK45_EN Bit Offset */ 9182 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN ((uint32_t)0x00002000) /*!< When 1, Block45 of the SRAM is retained in LPM3 and LPM4 */ 9183 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK46_EN] Bits */ 9184 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN_OFS (14) /*!< BLK46_EN Bit Offset */ 9185 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN ((uint32_t)0x00004000) /*!< When 1, Block46 of the SRAM is retained in LPM3 and LPM4 */ 9186 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK47_EN] Bits */ 9187 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN_OFS (15) /*!< BLK47_EN Bit Offset */ 9188 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN ((uint32_t)0x00008000) /*!< When 1, Block47 of the SRAM is retained in LPM3 and LPM4 */ 9189 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK48_EN] Bits */ 9190 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN_OFS (16) /*!< BLK48_EN Bit Offset */ 9191 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN ((uint32_t)0x00010000) /*!< When 1, Block48 of the SRAM is retained in LPM3 and LPM4 */ 9192 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK49_EN] Bits */ 9193 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN_OFS (17) /*!< BLK49_EN Bit Offset */ 9194 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN ((uint32_t)0x00020000) /*!< When 1, Block49 of the SRAM is retained in LPM3 and LPM4 */ 9195 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK50_EN] Bits */ 9196 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN_OFS (18) /*!< BLK50_EN Bit Offset */ 9197 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN ((uint32_t)0x00040000) /*!< When 1, Block50 of the SRAM is retained in LPM3 and LPM4 */ 9198 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK51_EN] Bits */ 9199 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN_OFS (19) /*!< BLK51_EN Bit Offset */ 9200 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN ((uint32_t)0x00080000) /*!< When 1, Block51 of the SRAM is retained in LPM3 and LPM4 */ 9201 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK52_EN] Bits */ 9202 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN_OFS (20) /*!< BLK52_EN Bit Offset */ 9203 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN ((uint32_t)0x00100000) /*!< When 1, Block52 of the SRAM is retained in LPM3 and LPM4 */ 9204 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK53_EN] Bits */ 9205 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN_OFS (21) /*!< BLK53_EN Bit Offset */ 9206 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN ((uint32_t)0x00200000) /*!< When 1, Block53 of the SRAM is retained in LPM3 and LPM4 */ 9207 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK54_EN] Bits */ 9208 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN_OFS (22) /*!< BLK54_EN Bit Offset */ 9209 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN ((uint32_t)0x00400000) /*!< When 1, Block54 of the SRAM is retained in LPM3 and LPM4 */ 9210 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK55_EN] Bits */ 9211 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN_OFS (23) /*!< BLK55_EN Bit Offset */ 9212 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN ((uint32_t)0x00800000) /*!< When 1, Block55 of the SRAM is retained in LPM3 and LPM4 */ 9213 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK56_EN] Bits */ 9214 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN_OFS (24) /*!< BLK56_EN Bit Offset */ 9215 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN ((uint32_t)0x01000000) /*!< When 1, Block56 of the SRAM is retained in LPM3 and LPM4 */ 9216 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK57_EN] Bits */ 9217 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN_OFS (25) /*!< BLK57_EN Bit Offset */ 9218 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN ((uint32_t)0x02000000) /*!< When 1, Block57 of the SRAM is retained in LPM3 and LPM4 */ 9219 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK58_EN] Bits */ 9220 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN_OFS (26) /*!< BLK58_EN Bit Offset */ 9221 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN ((uint32_t)0x04000000) /*!< When 1, Block58 of the SRAM is retained in LPM3 and LPM4 */ 9222 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK59_EN] Bits */ 9223 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN_OFS (27) /*!< BLK59_EN Bit Offset */ 9224 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN ((uint32_t)0x08000000) /*!< When 1, Block59 of the SRAM is retained in LPM3 and LPM4 */ 9225 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK60_EN] Bits */ 9226 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN_OFS (28) /*!< BLK60_EN Bit Offset */ 9227 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN ((uint32_t)0x10000000) /*!< When 1, Block60 of the SRAM is retained in LPM3 and LPM4 */ 9228 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK61_EN] Bits */ 9229 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN_OFS (29) /*!< BLK61_EN Bit Offset */ 9230 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN ((uint32_t)0x20000000) /*!< When 1, Block61 of the SRAM is retained in LPM3 and LPM4 */ 9231 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK62_EN] Bits */ 9232 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN_OFS (30) /*!< BLK62_EN Bit Offset */ 9233 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN ((uint32_t)0x40000000) /*!< When 1, Block62 of the SRAM is retained in LPM3 and LPM4 */ 9234 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK63_EN] Bits */ 9235 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN_OFS (31) /*!< BLK63_EN Bit Offset */ 9236 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN ((uint32_t)0x80000000) /*!< When 1, Block63 of the SRAM is retained in LPM3 and LPM4 */ 9237 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK64_EN] Bits */ 9238 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN_OFS ( 0) /*!< BLK64_EN Bit Offset */ 9239 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN ((uint32_t)0x00000001) /*!< When 1, Block64 of the SRAM is retained in LPM3 and LPM4 */ 9240 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK65_EN] Bits */ 9241 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN_OFS ( 1) /*!< BLK65_EN Bit Offset */ 9242 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN ((uint32_t)0x00000002) /*!< When 1, Block65 of the SRAM is retained in LPM3 and LPM4 */ 9243 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK66_EN] Bits */ 9244 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN_OFS ( 2) /*!< BLK66_EN Bit Offset */ 9245 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN ((uint32_t)0x00000004) /*!< When 1, Block66 of the SRAM is retained in LPM3 and LPM4 */ 9246 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK67_EN] Bits */ 9247 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN_OFS ( 3) /*!< BLK67_EN Bit Offset */ 9248 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN ((uint32_t)0x00000008) /*!< When 1, Block67 of the SRAM is retained in LPM3 and LPM4 */ 9249 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK68_EN] Bits */ 9250 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN_OFS ( 4) /*!< BLK68_EN Bit Offset */ 9251 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN ((uint32_t)0x00000010) /*!< When 1, Block68 of the SRAM is retained in LPM3 and LPM4 */ 9252 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK69_EN] Bits */ 9253 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN_OFS ( 5) /*!< BLK69_EN Bit Offset */ 9254 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN ((uint32_t)0x00000020) /*!< When 1, Block69 of the SRAM is retained in LPM3 and LPM4 */ 9255 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK70_EN] Bits */ 9256 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN_OFS ( 6) /*!< BLK70_EN Bit Offset */ 9257 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN ((uint32_t)0x00000040) /*!< When 1, Block70 of the SRAM is retained in LPM3 and LPM4 */ 9258 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK71_EN] Bits */ 9259 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN_OFS ( 7) /*!< BLK71_EN Bit Offset */ 9260 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN ((uint32_t)0x00000080) /*!< When 1, Block71 of the SRAM is retained in LPM3 and LPM4 */ 9261 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK72_EN] Bits */ 9262 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN_OFS ( 8) /*!< BLK72_EN Bit Offset */ 9263 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN ((uint32_t)0x00000100) /*!< When 1, Block72 of the SRAM is retained in LPM3 and LPM4 */ 9264 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK73_EN] Bits */ 9265 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN_OFS ( 9) /*!< BLK73_EN Bit Offset */ 9266 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN ((uint32_t)0x00000200) /*!< When 1, Block73 of the SRAM is retained in LPM3 and LPM4 */ 9267 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK74_EN] Bits */ 9268 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN_OFS (10) /*!< BLK74_EN Bit Offset */ 9269 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN ((uint32_t)0x00000400) /*!< When 1, Block74 of the SRAM is retained in LPM3 and LPM4 */ 9270 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK75_EN] Bits */ 9271 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN_OFS (11) /*!< BLK75_EN Bit Offset */ 9272 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN ((uint32_t)0x00000800) /*!< When 1, Block75 of the SRAM is retained in LPM3 and LPM4 */ 9273 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK76_EN] Bits */ 9274 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN_OFS (12) /*!< BLK76_EN Bit Offset */ 9275 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN ((uint32_t)0x00001000) /*!< When 1, Block76 of the SRAM is retained in LPM3 and LPM4 */ 9276 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK77_EN] Bits */ 9277 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN_OFS (13) /*!< BLK77_EN Bit Offset */ 9278 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN ((uint32_t)0x00002000) /*!< When 1, Block77 of the SRAM is retained in LPM3 and LPM4 */ 9279 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK78_EN] Bits */ 9280 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN_OFS (14) /*!< BLK78_EN Bit Offset */ 9281 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN ((uint32_t)0x00004000) /*!< When 1, Block78 of the SRAM is retained in LPM3 and LPM4 */ 9282 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK79_EN] Bits */ 9283 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN_OFS (15) /*!< BLK79_EN Bit Offset */ 9284 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN ((uint32_t)0x00008000) /*!< When 1, Block79 of the SRAM is retained in LPM3 and LPM4 */ 9285 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK80_EN] Bits */ 9286 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN_OFS (16) /*!< BLK80_EN Bit Offset */ 9287 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN ((uint32_t)0x00010000) /*!< When 1, Block80 of the SRAM is retained in LPM3 and LPM4 */ 9288 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK81_EN] Bits */ 9289 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN_OFS (17) /*!< BLK81_EN Bit Offset */ 9290 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN ((uint32_t)0x00020000) /*!< When 1, Block81 of the SRAM is retained in LPM3 and LPM4 */ 9291 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK82_EN] Bits */ 9292 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN_OFS (18) /*!< BLK82_EN Bit Offset */ 9293 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN ((uint32_t)0x00040000) /*!< When 1, Block82 of the SRAM is retained in LPM3 and LPM4 */ 9294 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK83_EN] Bits */ 9295 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN_OFS (19) /*!< BLK83_EN Bit Offset */ 9296 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN ((uint32_t)0x00080000) /*!< When 1, Block83 of the SRAM is retained in LPM3 and LPM4 */ 9297 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK84_EN] Bits */ 9298 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN_OFS (20) /*!< BLK84_EN Bit Offset */ 9299 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN ((uint32_t)0x00100000) /*!< When 1, Block84 of the SRAM is retained in LPM3 and LPM4 */ 9300 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK85_EN] Bits */ 9301 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN_OFS (21) /*!< BLK85_EN Bit Offset */ 9302 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN ((uint32_t)0x00200000) /*!< When 1, Block85 of the SRAM is retained in LPM3 and LPM4 */ 9303 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK86_EN] Bits */ 9304 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN_OFS (22) /*!< BLK86_EN Bit Offset */ 9305 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN ((uint32_t)0x00400000) /*!< When 1, Block86 of the SRAM is retained in LPM3 and LPM4 */ 9306 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK87_EN] Bits */ 9307 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN_OFS (23) /*!< BLK87_EN Bit Offset */ 9308 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN ((uint32_t)0x00800000) /*!< When 1, Block87 of the SRAM is retained in LPM3 and LPM4 */ 9309 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK88_EN] Bits */ 9310 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN_OFS (24) /*!< BLK88_EN Bit Offset */ 9311 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN ((uint32_t)0x01000000) /*!< When 1, Block88 of the SRAM is retained in LPM3 and LPM4 */ 9312 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK89_EN] Bits */ 9313 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN_OFS (25) /*!< BLK89_EN Bit Offset */ 9314 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN ((uint32_t)0x02000000) /*!< When 1, Block89 of the SRAM is retained in LPM3 and LPM4 */ 9315 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK90_EN] Bits */ 9316 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN_OFS (26) /*!< BLK90_EN Bit Offset */ 9317 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN ((uint32_t)0x04000000) /*!< When 1, Block90 of the SRAM is retained in LPM3 and LPM4 */ 9318 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK91_EN] Bits */ 9319 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN_OFS (27) /*!< BLK91_EN Bit Offset */ 9320 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN ((uint32_t)0x08000000) /*!< When 1, Block91 of the SRAM is retained in LPM3 and LPM4 */ 9321 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK92_EN] Bits */ 9322 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN_OFS (28) /*!< BLK92_EN Bit Offset */ 9323 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN ((uint32_t)0x10000000) /*!< When 1, Block92 of the SRAM is retained in LPM3 and LPM4 */ 9324 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK93_EN] Bits */ 9325 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN_OFS (29) /*!< BLK93_EN Bit Offset */ 9326 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN ((uint32_t)0x20000000) /*!< When 1, Block93 of the SRAM is retained in LPM3 and LPM4 */ 9327 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK94_EN] Bits */ 9328 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN_OFS (30) /*!< BLK94_EN Bit Offset */ 9329 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN ((uint32_t)0x40000000) /*!< When 1, Block94 of the SRAM is retained in LPM3 and LPM4 */ 9330 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK95_EN] Bits */ 9331 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN_OFS (31) /*!< BLK95_EN Bit Offset */ 9332 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN ((uint32_t)0x80000000) /*!< When 1, Block95 of the SRAM is retained in LPM3 and LPM4 */ 9333 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK96_EN] Bits */ 9334 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN_OFS ( 0) /*!< BLK96_EN Bit Offset */ 9335 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN ((uint32_t)0x00000001) /*!< When 1, Block96 of the SRAM is retained in LPM3 and LPM4 */ 9336 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK97_EN] Bits */ 9337 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN_OFS ( 1) /*!< BLK97_EN Bit Offset */ 9338 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN ((uint32_t)0x00000002) /*!< When 1, Block97 of the SRAM is retained in LPM3 and LPM4 */ 9339 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK98_EN] Bits */ 9340 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN_OFS ( 2) /*!< BLK98_EN Bit Offset */ 9341 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN ((uint32_t)0x00000004) /*!< When 1, Block98 of the SRAM is retained in LPM3 and LPM4 */ 9342 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK99_EN] Bits */ 9343 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN_OFS ( 3) /*!< BLK99_EN Bit Offset */ 9344 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN ((uint32_t)0x00000008) /*!< When 1, Block99 of the SRAM is retained in LPM3 and LPM4 */ 9345 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK100_EN] Bits */ 9346 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN_OFS ( 4) /*!< BLK100_EN Bit Offset */ 9347 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN ((uint32_t)0x00000010) /*!< When 1, Block100 of the SRAM is retained in LPM3 and LPM4 */ 9348 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK101_EN] Bits */ 9349 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN_OFS ( 5) /*!< BLK101_EN Bit Offset */ 9350 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN ((uint32_t)0x00000020) /*!< When 1, Block101 of the SRAM is retained in LPM3 and LPM4 */ 9351 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK102_EN] Bits */ 9352 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN_OFS ( 6) /*!< BLK102_EN Bit Offset */ 9353 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN ((uint32_t)0x00000040) /*!< When 1, Block102 of the SRAM is retained in LPM3 and LPM4 */ 9354 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK103_EN] Bits */ 9355 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN_OFS ( 7) /*!< BLK103_EN Bit Offset */ 9356 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN ((uint32_t)0x00000080) /*!< When 1, Block103 of the SRAM is retained in LPM3 and LPM4 */ 9357 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK104_EN] Bits */ 9358 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN_OFS ( 8) /*!< BLK104_EN Bit Offset */ 9359 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN ((uint32_t)0x00000100) /*!< When 1, Block104 of the SRAM is retained in LPM3 and LPM4 */ 9360 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK105_EN] Bits */ 9361 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN_OFS ( 9) /*!< BLK105_EN Bit Offset */ 9362 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN ((uint32_t)0x00000200) /*!< When 1, Block105 of the SRAM is retained in LPM3 and LPM4 */ 9363 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK106_EN] Bits */ 9364 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN_OFS (10) /*!< BLK106_EN Bit Offset */ 9365 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN ((uint32_t)0x00000400) /*!< When 1, Block106 of the SRAM is retained in LPM3 and LPM4 */ 9366 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK107_EN] Bits */ 9367 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN_OFS (11) /*!< BLK107_EN Bit Offset */ 9368 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN ((uint32_t)0x00000800) /*!< When 1, Block107 of the SRAM is retained in LPM3 and LPM4 */ 9369 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK108_EN] Bits */ 9370 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN_OFS (12) /*!< BLK108_EN Bit Offset */ 9371 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN ((uint32_t)0x00001000) /*!< When 1, Block108 of the SRAM is retained in LPM3 and LPM4 */ 9372 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK109_EN] Bits */ 9373 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN_OFS (13) /*!< BLK109_EN Bit Offset */ 9374 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN ((uint32_t)0x00002000) /*!< When 1, Block109 of the SRAM is retained in LPM3 and LPM4 */ 9375 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK110_EN] Bits */ 9376 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN_OFS (14) /*!< BLK110_EN Bit Offset */ 9377 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN ((uint32_t)0x00004000) /*!< When 1, Block110 of the SRAM is retained in LPM3 and LPM4 */ 9378 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK111_EN] Bits */ 9379 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN_OFS (15) /*!< BLK111_EN Bit Offset */ 9380 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN ((uint32_t)0x00008000) /*!< When 1, Block111 of the SRAM is retained in LPM3 and LPM4 */ 9381 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK112_EN] Bits */ 9382 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN_OFS (16) /*!< BLK112_EN Bit Offset */ 9383 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN ((uint32_t)0x00010000) /*!< When 1, Block112 of the SRAM is retained in LPM3 and LPM4 */ 9384 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK113_EN] Bits */ 9385 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN_OFS (17) /*!< BLK113_EN Bit Offset */ 9386 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN ((uint32_t)0x00020000) /*!< When 1, Block113 of the SRAM is retained in LPM3 and LPM4 */ 9387 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK114_EN] Bits */ 9388 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN_OFS (18) /*!< BLK114_EN Bit Offset */ 9389 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN ((uint32_t)0x00040000) /*!< When 1, Block114 of the SRAM is retained in LPM3 and LPM4 */ 9390 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK115_EN] Bits */ 9391 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN_OFS (19) /*!< BLK115_EN Bit Offset */ 9392 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN ((uint32_t)0x00080000) /*!< When 1, Block115 of the SRAM is retained in LPM3 and LPM4 */ 9393 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK116_EN] Bits */ 9394 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN_OFS (20) /*!< BLK116_EN Bit Offset */ 9395 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN ((uint32_t)0x00100000) /*!< When 1, Block116 of the SRAM is retained in LPM3 and LPM4 */ 9396 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK117_EN] Bits */ 9397 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN_OFS (21) /*!< BLK117_EN Bit Offset */ 9398 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN ((uint32_t)0x00200000) /*!< When 1, Block117 of the SRAM is retained in LPM3 and LPM4 */ 9399 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK118_EN] Bits */ 9400 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN_OFS (22) /*!< BLK118_EN Bit Offset */ 9401 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN ((uint32_t)0x00400000) /*!< When 1, Block118 of the SRAM is retained in LPM3 and LPM4 */ 9402 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK119_EN] Bits */ 9403 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN_OFS (23) /*!< BLK119_EN Bit Offset */ 9404 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN ((uint32_t)0x00800000) /*!< When 1, Block119 of the SRAM is retained in LPM3 and LPM4 */ 9405 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK120_EN] Bits */ 9406 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN_OFS (24) /*!< BLK120_EN Bit Offset */ 9407 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN ((uint32_t)0x01000000) /*!< When 1, Block120 of the SRAM is retained in LPM3 and LPM4 */ 9408 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK121_EN] Bits */ 9409 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN_OFS (25) /*!< BLK121_EN Bit Offset */ 9410 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN ((uint32_t)0x02000000) /*!< When 1, Block121 of the SRAM is retained in LPM3 and LPM4 */ 9411 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK122_EN] Bits */ 9412 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN_OFS (26) /*!< BLK122_EN Bit Offset */ 9413 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN ((uint32_t)0x04000000) /*!< When 1, Block122 of the SRAM is retained in LPM3 and LPM4 */ 9414 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK123_EN] Bits */ 9415 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN_OFS (27) /*!< BLK123_EN Bit Offset */ 9416 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN ((uint32_t)0x08000000) /*!< When 1, Block123 of the SRAM is retained in LPM3 and LPM4 */ 9417 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK124_EN] Bits */ 9418 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN_OFS (28) /*!< BLK124_EN Bit Offset */ 9419 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN ((uint32_t)0x10000000) /*!< When 1, Block124 of the SRAM is retained in LPM3 and LPM4 */ 9420 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK125_EN] Bits */ 9421 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN_OFS (29) /*!< BLK125_EN Bit Offset */ 9422 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN ((uint32_t)0x20000000) /*!< When 1, Block125 of the SRAM is retained in LPM3 and LPM4 */ 9423 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK126_EN] Bits */ 9424 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN_OFS (30) /*!< BLK126_EN Bit Offset */ 9425 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN ((uint32_t)0x40000000) /*!< When 1, Block126 of the SRAM is retained in LPM3 and LPM4 */ 9426 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK127_EN] Bits */ 9427 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN_OFS (31) /*!< BLK127_EN Bit Offset */ 9428 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN ((uint32_t)0x80000000) /*!< When 1, Block127 of the SRAM is retained in LPM3 and LPM4 */ 9429 /* SYSCTL_A_SRAM_STAT[BNKEN_RDY] Bits */ 9430 #define SYSCTL_A_SRAM_STAT_BNKEN_RDY_OFS ( 0) /*!< BNKEN_RDY Bit Offset */ 9431 #define SYSCTL_A_SRAM_STAT_BNKEN_RDY ((uint32_t)0x00000001) /*!< When 1, indicates SRAM is ready for access and banks can be */ 9432 /* enabled/disabled. */ 9433 /* SYSCTL_A_SRAM_STAT[BLKRET_RDY] Bits */ 9434 #define SYSCTL_A_SRAM_STAT_BLKRET_RDY_OFS ( 1) /*!< BLKRET_RDY Bit Offset */ 9435 #define SYSCTL_A_SRAM_STAT_BLKRET_RDY ((uint32_t)0x00000002) /*!< When 1, indicates SRAM is ready for access and blocks can be */ 9436 /* enabled/disabled for retention. */ 9437 /* SYSCTL_A_MASTER_UNLOCK[UNLKEY] Bits */ 9438 #define SYSCTL_A_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ 9439 #define SYSCTL_A_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ 9440 /* SYSCTL_A_RESET_REQ[POR] Bits */ 9441 #define SYSCTL_A_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ 9442 #define SYSCTL_A_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ 9443 /* SYSCTL_A_RESET_REQ[REBOOT] Bits */ 9444 #define SYSCTL_A_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ 9445 #define SYSCTL_A_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ 9446 /* SYSCTL_A_RESET_REQ[WKEY] Bits */ 9447 #define SYSCTL_A_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ 9448 #define SYSCTL_A_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ 9449 /* SYSCTL_A_RESET_STATOVER[SOFT] Bits */ 9450 #define SYSCTL_A_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ 9451 #define SYSCTL_A_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ 9452 /* SYSCTL_A_RESET_STATOVER[HARD] Bits */ 9453 #define SYSCTL_A_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ 9454 #define SYSCTL_A_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ 9455 /* SYSCTL_A_RESET_STATOVER[REBOOT] Bits */ 9456 #define SYSCTL_A_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ 9457 #define SYSCTL_A_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ 9458 /* SYSCTL_A_RESET_STATOVER[SOFT_OVER] Bits */ 9459 #define SYSCTL_A_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ 9460 #define SYSCTL_A_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ 9461 /* SYSCTL_A_RESET_STATOVER[HARD_OVER] Bits */ 9462 #define SYSCTL_A_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ 9463 #define SYSCTL_A_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ 9464 /* SYSCTL_A_RESET_STATOVER[RBT_OVER] Bits */ 9465 #define SYSCTL_A_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ 9466 #define SYSCTL_A_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ 9467 /* Pre-defined bitfield values */ 9468 #define SYSCTL_A_CSYS_MASTER_UNLOCK_UNLKEY_VAL ((uint32_t)0x0000695A) /*!< Unlock key value which when written, determines if accesses to other CPU_SYS register */ 9469 #define SYSCTL_A_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ 9470 #define SYSCTL_A_BOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ 9471 #define SYSCTL_A_ETW_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ 9472 #define SYSCTL_A_SECDATA_UNLOCK_KEY_VAL ((uint32_t)0x0000695A) /*!< Unlock Key value, which requests for secure data region to be unlocked for data access */ 9473 9474 9475 /****************************************************************************** 9476 * SYSTICK Bits 9477 ******************************************************************************/ 9478 9479 /****************************************************************************** 9480 * Timer32 Bits 9481 ******************************************************************************/ 9482 /* TIMER32_CONTROL[ONESHOT] Bits */ 9483 #define TIMER32_CONTROL_ONESHOT_OFS ( 0) /*!< ONESHOT Bit Offset */ 9484 #define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /*!< Selects one-shot or wrapping counter mode */ 9485 /* TIMER32_CONTROL[SIZE] Bits */ 9486 #define TIMER32_CONTROL_SIZE_OFS ( 1) /*!< SIZE Bit Offset */ 9487 #define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /*!< Selects 16 or 32 bit counter operation */ 9488 /* TIMER32_CONTROL[PRESCALE] Bits */ 9489 #define TIMER32_CONTROL_PRESCALE_OFS ( 2) /*!< PRESCALE Bit Offset */ 9490 #define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /*!< PRESCALE Bit Mask */ 9491 #define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /*!< PRESCALE Bit 0 */ 9492 #define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /*!< PRESCALE Bit 1 */ 9493 #define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /*!< 0 stages of prescale, clock is divided by 1 */ 9494 #define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /*!< 4 stages of prescale, clock is divided by 16 */ 9495 #define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /*!< 8 stages of prescale, clock is divided by 256 */ 9496 /* TIMER32_CONTROL[IE] Bits */ 9497 #define TIMER32_CONTROL_IE_OFS ( 5) /*!< IE Bit Offset */ 9498 #define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /*!< Interrupt enable bit */ 9499 /* TIMER32_CONTROL[MODE] Bits */ 9500 #define TIMER32_CONTROL_MODE_OFS ( 6) /*!< MODE Bit Offset */ 9501 #define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /*!< Mode bit */ 9502 /* TIMER32_CONTROL[ENABLE] Bits */ 9503 #define TIMER32_CONTROL_ENABLE_OFS ( 7) /*!< ENABLE Bit Offset */ 9504 #define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080) 9505 /* TIMER32_RIS[RAW_IFG] Bits */ 9506 #define TIMER32_RIS_RAW_IFG_OFS ( 0) /*!< RAW_IFG Bit Offset */ 9507 #define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /*!< Raw interrupt status */ 9508 /* TIMER32_MIS[IFG] Bits */ 9509 #define TIMER32_MIS_IFG_OFS ( 0) /*!< IFG Bit Offset */ 9510 #define TIMER32_MIS_IFG ((uint32_t)0x00000001) /*!< Enabled interrupt status */ 9511 9512 9513 9514 /****************************************************************************** 9515 * TIMER_A Bits 9516 ******************************************************************************/ 9517 /* TIMER_A_CTL[IFG] Bits */ 9518 #define TIMER_A_CTL_IFG_OFS ( 0) /*!< TAIFG Bit Offset */ 9519 #define TIMER_A_CTL_IFG ((uint16_t)0x0001) /*!< TimerA interrupt flag */ 9520 /* TIMER_A_CTL[IE] Bits */ 9521 #define TIMER_A_CTL_IE_OFS ( 1) /*!< TAIE Bit Offset */ 9522 #define TIMER_A_CTL_IE ((uint16_t)0x0002) /*!< TimerA interrupt enable */ 9523 /* TIMER_A_CTL[CLR] Bits */ 9524 #define TIMER_A_CTL_CLR_OFS ( 2) /*!< TACLR Bit Offset */ 9525 #define TIMER_A_CTL_CLR ((uint16_t)0x0004) /*!< TimerA clear */ 9526 /* TIMER_A_CTL[MC] Bits */ 9527 #define TIMER_A_CTL_MC_OFS ( 4) /*!< MC Bit Offset */ 9528 #define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /*!< MC Bit Mask */ 9529 #define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /*!< MC Bit 0 */ 9530 #define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /*!< MC Bit 1 */ 9531 #define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ 9532 #define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ 9533 #define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ 9534 #define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ 9535 #define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ 9536 #define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ 9537 #define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ 9538 #define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ 9539 /* TIMER_A_CTL[ID] Bits */ 9540 #define TIMER_A_CTL_ID_OFS ( 6) /*!< ID Bit Offset */ 9541 #define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /*!< ID Bit Mask */ 9542 #define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /*!< ID Bit 0 */ 9543 #define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /*!< ID Bit 1 */ 9544 #define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /*!< /1 */ 9545 #define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /*!< /2 */ 9546 #define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /*!< /4 */ 9547 #define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /*!< /8 */ 9548 #define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /*!< /1 */ 9549 #define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /*!< /2 */ 9550 #define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /*!< /4 */ 9551 #define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /*!< /8 */ 9552 /* TIMER_A_CTL[SSEL] Bits */ 9553 #define TIMER_A_CTL_SSEL_OFS ( 8) /*!< TASSEL Bit Offset */ 9554 #define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /*!< TASSEL Bit Mask */ 9555 #define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /*!< SSEL Bit 0 */ 9556 #define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /*!< SSEL Bit 1 */ 9557 #define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /*!< TAxCLK */ 9558 #define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /*!< ACLK */ 9559 #define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /*!< SMCLK */ 9560 #define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /*!< INCLK */ 9561 #define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /*!< TAxCLK */ 9562 #define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /*!< ACLK */ 9563 #define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /*!< SMCLK */ 9564 #define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /*!< INCLK */ 9565 /* TIMER_A_CCTLN[CCIFG] Bits */ 9566 #define TIMER_A_CCTLN_CCIFG_OFS ( 0) /*!< CCIFG Bit Offset */ 9567 #define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /*!< Capture/compare interrupt flag */ 9568 /* TIMER_A_CCTLN[COV] Bits */ 9569 #define TIMER_A_CCTLN_COV_OFS ( 1) /*!< COV Bit Offset */ 9570 #define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /*!< Capture overflow */ 9571 /* TIMER_A_CCTLN[OUT] Bits */ 9572 #define TIMER_A_CCTLN_OUT_OFS ( 2) /*!< OUT Bit Offset */ 9573 #define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /*!< Output */ 9574 /* TIMER_A_CCTLN[CCI] Bits */ 9575 #define TIMER_A_CCTLN_CCI_OFS ( 3) /*!< CCI Bit Offset */ 9576 #define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /*!< Capture/compare input */ 9577 /* TIMER_A_CCTLN[CCIE] Bits */ 9578 #define TIMER_A_CCTLN_CCIE_OFS ( 4) /*!< CCIE Bit Offset */ 9579 #define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /*!< Capture/compare interrupt enable */ 9580 /* TIMER_A_CCTLN[OUTMOD] Bits */ 9581 #define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /*!< OUTMOD Bit Offset */ 9582 #define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /*!< OUTMOD Bit Mask */ 9583 #define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /*!< OUTMOD Bit 0 */ 9584 #define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /*!< OUTMOD Bit 1 */ 9585 #define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /*!< OUTMOD Bit 2 */ 9586 #define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /*!< OUT bit value */ 9587 #define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /*!< Set */ 9588 #define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /*!< Toggle/reset */ 9589 #define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /*!< Set/reset */ 9590 #define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /*!< Toggle */ 9591 #define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /*!< Reset */ 9592 #define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /*!< Toggle/set */ 9593 #define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /*!< Reset/set */ 9594 /* TIMER_A_CCTLN[CAP] Bits */ 9595 #define TIMER_A_CCTLN_CAP_OFS ( 8) /*!< CAP Bit Offset */ 9596 #define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /*!< Capture mode */ 9597 /* TIMER_A_CCTLN[SCCI] Bits */ 9598 #define TIMER_A_CCTLN_SCCI_OFS (10) /*!< SCCI Bit Offset */ 9599 #define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /*!< Synchronized capture/compare input */ 9600 /* TIMER_A_CCTLN[SCS] Bits */ 9601 #define TIMER_A_CCTLN_SCS_OFS (11) /*!< SCS Bit Offset */ 9602 #define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /*!< Synchronize capture source */ 9603 /* TIMER_A_CCTLN[CCIS] Bits */ 9604 #define TIMER_A_CCTLN_CCIS_OFS (12) /*!< CCIS Bit Offset */ 9605 #define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /*!< CCIS Bit Mask */ 9606 #define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /*!< CCIS Bit 0 */ 9607 #define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /*!< CCIS Bit 1 */ 9608 #define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /*!< CCIxA */ 9609 #define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /*!< CCIxB */ 9610 #define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /*!< GND */ 9611 #define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /*!< VCC */ 9612 #define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /*!< CCIxA */ 9613 #define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /*!< CCIxB */ 9614 #define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /*!< GND */ 9615 #define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /*!< VCC */ 9616 /* TIMER_A_CCTLN[CM] Bits */ 9617 #define TIMER_A_CCTLN_CM_OFS (14) /*!< CM Bit Offset */ 9618 #define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /*!< CM Bit Mask */ 9619 #define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /*!< CM Bit 0 */ 9620 #define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /*!< CM Bit 1 */ 9621 #define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /*!< No capture */ 9622 #define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /*!< Capture on rising edge */ 9623 #define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /*!< Capture on falling edge */ 9624 #define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ 9625 #define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /*!< No capture */ 9626 #define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /*!< Capture on rising edge */ 9627 #define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /*!< Capture on falling edge */ 9628 #define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ 9629 /* TIMER_A_EX0[IDEX] Bits */ 9630 #define TIMER_A_EX0_IDEX_OFS ( 0) /*!< TAIDEX Bit Offset */ 9631 #define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /*!< TAIDEX Bit Mask */ 9632 #define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /*!< IDEX Bit 0 */ 9633 #define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /*!< IDEX Bit 1 */ 9634 #define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /*!< IDEX Bit 2 */ 9635 #define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /*!< Divide by 1 */ 9636 #define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /*!< Divide by 2 */ 9637 #define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /*!< Divide by 3 */ 9638 #define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /*!< Divide by 4 */ 9639 #define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /*!< Divide by 5 */ 9640 #define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /*!< Divide by 6 */ 9641 #define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /*!< Divide by 7 */ 9642 #define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /*!< Divide by 8 */ 9643 #define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /*!< Divide by 1 */ 9644 #define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /*!< Divide by 2 */ 9645 #define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /*!< Divide by 3 */ 9646 #define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /*!< Divide by 4 */ 9647 #define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /*!< Divide by 5 */ 9648 #define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /*!< Divide by 6 */ 9649 #define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /*!< Divide by 7 */ 9650 #define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /*!< Divide by 8 */ 9651 9652 /****************************************************************************** 9653 * TLV Bits 9654 ******************************************************************************/ 9655 /****************************************************************************** 9656 * TLV table start and TLV tags * 9657 ******************************************************************************/ 9658 #define TLV_START_ADDR (TLV_BASE + 0x0004) /*!< Start Address of the TLV structure */ 9659 9660 #define TLV_TAG_RESERVED1 1 9661 #define TLV_TAG_RESERVED2 2 9662 #define TLV_TAG_CS 3 9663 #define TLV_TAG_FLASHCTL 4 9664 #define TLV_TAG_ADC14 5 9665 #define TLV_TAG_RESERVED6 6 9666 #define TLV_TAG_RESERVED7 7 9667 #define TLV_TAG_REF 8 9668 #define TLV_TAG_RESERVED9 9 9669 #define TLV_TAG_RESERVED10 10 9670 #define TLV_TAG_DEVINFO 11 9671 #define TLV_TAG_DIEREC 12 9672 #define TLV_TAG_RANDNUM 13 9673 #define TLV_TAG_RESERVED14 14 9674 #define TLV_TAG_BSL 15 9675 #define TLV_TAG_END (0x0BD0E11D) 9676 9677 9678 /****************************************************************************** 9679 * TPIU Bits 9680 ******************************************************************************/ 9681 9682 9683 /****************************************************************************** 9684 * WDT_A Bits 9685 ******************************************************************************/ 9686 /* WDT_A_CTL[IS] Bits */ 9687 #define WDT_A_CTL_IS_OFS ( 0) /*!< WDTIS Bit Offset */ 9688 #define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /*!< WDTIS Bit Mask */ 9689 #define WDT_A_CTL_IS0 ((uint16_t)0x0001) /*!< IS Bit 0 */ 9690 #define WDT_A_CTL_IS1 ((uint16_t)0x0002) /*!< IS Bit 1 */ 9691 #define WDT_A_CTL_IS2 ((uint16_t)0x0004) /*!< IS Bit 2 */ 9692 #define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ 9693 #define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ 9694 #define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ 9695 #define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ 9696 #define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ 9697 #define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ 9698 #define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ 9699 #define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ 9700 /* WDT_A_CTL[CNTCL] Bits */ 9701 #define WDT_A_CTL_CNTCL_OFS ( 3) /*!< WDTCNTCL Bit Offset */ 9702 #define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /*!< Watchdog timer counter clear */ 9703 /* WDT_A_CTL[TMSEL] Bits */ 9704 #define WDT_A_CTL_TMSEL_OFS ( 4) /*!< WDTTMSEL Bit Offset */ 9705 #define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /*!< Watchdog timer mode select */ 9706 /* WDT_A_CTL[SSEL] Bits */ 9707 #define WDT_A_CTL_SSEL_OFS ( 5) /*!< WDTSSEL Bit Offset */ 9708 #define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /*!< WDTSSEL Bit Mask */ 9709 #define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /*!< SSEL Bit 0 */ 9710 #define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /*!< SSEL Bit 1 */ 9711 #define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /*!< SMCLK */ 9712 #define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /*!< ACLK */ 9713 #define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /*!< VLOCLK */ 9714 #define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /*!< BCLK */ 9715 #define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /*!< SMCLK */ 9716 #define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /*!< ACLK */ 9717 #define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /*!< VLOCLK */ 9718 #define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /*!< BCLK */ 9719 /* WDT_A_CTL[HOLD] Bits */ 9720 #define WDT_A_CTL_HOLD_OFS ( 7) /*!< WDTHOLD Bit Offset */ 9721 #define WDT_A_CTL_HOLD ((uint16_t)0x0080) /*!< Watchdog timer hold */ 9722 /* WDT_A_CTL[PW] Bits */ 9723 #define WDT_A_CTL_PW_OFS ( 8) /*!< WDTPW Bit Offset */ 9724 #define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /*!< WDTPW Bit Mask */ 9725 /* Pre-defined bitfield values */ 9726 #define WDT_A_CTL_PW ((uint16_t)0x5A00) /*!< WDT Key Value for WDT write access */ 9727 9728 9729 /****************************************************************************** 9730 * BSL * 9731 ******************************************************************************/ 9732 #define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF) /*!< I2C slave address = 0x48, Interface selection = Auto */ 9733 #define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) /*!< Address of BSL API table */ 9734 #define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) 9735 9736 #define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000) /*!< Auto detect interface */ 9737 #define BSL_UART_INTERFACE ((uint32_t)0x0000C0000) /*!< UART interface */ 9738 #define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000) /*!< SPI interface */ 9739 #define BSL_I2C_INTERFACE ((uint32_t)0x000080000) /*!< I2C interface */ 9740 9741 #define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */ 9742 9743 9744 /****************************************************************************** 9745 * Mailbox struct legacy definition * 9746 ******************************************************************************/ 9747 #define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type 9748 9749 /****************************************************************************** 9750 * Device Unlock Support * 9751 ******************************************************************************/ 9752 /* unlock the device by: 9753 * Load SYSCTL_SECDATA_UNLOCK register address into R0 9754 * Load SYSCTL_SECDATA_UNLOCK unlock key into R1 9755 * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register 9756 */ 9757 #define UNLOCK_DEVICE\ 9758 __asm(" MOVW.W R0, #0x3040");\ 9759 __asm(" MOVT.W R0, #0xE004");\ 9760 __asm(" MOVW.W R1, #0x695A");\ 9761 __asm(" MOVT.W R1, #0x0000");\ 9762 __asm(" STR R1, [R0]"); 9763 9764 /****************************************************************************** 9765 * 9766 * The following are values that can be used to choose the command that will be 9767 * run by the boot code. Perform a logical OR of these settings to create your 9768 * general parameter command. 9769 * 9770 ******************************************************************************/ 9771 #define COMMAND_FACTORY_RESET ((uint32_t)0x00010000) 9772 #define COMMAND_BSL_CONFIG ((uint32_t)0x00020000) 9773 #define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000) 9774 #define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000) 9775 #define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000) 9776 #define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000) 9777 #define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000) 9778 #define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000) 9779 #define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000) 9780 #define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000) 9781 #define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000) 9782 #define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000) 9783 #define COMMAND_NONE ((uint32_t)0xFFFFFFFF) 9784 9785 /****************************************************************************** 9786 * 9787 * The following are values that can be used to configure the BSL. Perform a 9788 * logical OR of these settings to create your BSL parameter. 9789 * 9790 ******************************************************************************/ 9791 #define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000) 9792 9793 #define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000) 9794 #define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001) 9795 #define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002) 9796 9797 #define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000) 9798 #define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010) 9799 #define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020) 9800 #define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030) 9801 #define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040) 9802 #define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050) 9803 #define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060) 9804 #define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070) 9805 9806 #define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000) 9807 #define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000) 9808 9809 #define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000) 9810 #define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000) 9811 #define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000) 9812 #define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000) 9813 9814 #define BSL_CONFIG_I2C_ADD_OFFSET (16) 9815 9816 9817 /****************************************************************************** 9818 * ULP Advisor * 9819 ******************************************************************************/ 9820 #ifdef __TI_ARM__ 9821 #pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8}) 9822 #pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8}) 9823 #pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8}) 9824 #pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8}) 9825 #pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8}) 9826 #pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8}) 9827 #pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8}) 9828 #pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8}) 9829 #pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8}) 9830 #pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8}) 9831 #endif 9832 9833 9834 #ifdef __cplusplus 9835 } 9836 #endif 9837 9838 #endif /* __MSP432P4111_H__ */ 9839 9840
