1 /****************************************************************************** 2 * 3 * Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the 15 * distribution. 16 * 17 * Neither the name of Texas Instruments Incorporated nor the names of 18 * its contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * MSP432P401R Register Definitions 34 * 35 * This file includes CMSIS compliant component and register definitions 36 * 37 * For legacy components the definitions that are compatible with MSP430 code, 38 * are included with msp432p401r_classic.h 39 * 40 * With CMSIS definitions, the register defines have been reformatted: 41 * ModuleName[ModuleInstance]->RegisterName 42 * 43 * Writing to CMSIS bit fields can be done through register level 44 * or via bitband area access: 45 * - ADC14->CTL0 |= ADC14_CTL0_ENC; 46 * - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1; 47 * 48 * File creation date: 2017-08-03 49 * 50 ******************************************************************************/ 51 52 #ifndef __MSP432P401R_H__ 53 #define __MSP432P401R_H__ 54 55 /* Use standard integer types with explicit width */ 56 #include <stdint.h> 57 58 #ifdef __cplusplus 59 extern "C" { 60 #endif 61 62 #define __MSP432_HEADER_VERSION__ 3202 63 64 /* Remap MSP432 intrinsics to ARM equivalents */ 65 #include "msp_compatibility.h" 66 67 /****************************************************************************** 68 * include MSP430 legacy definitions to make porting of code from MSP430 * 69 * code base easier * 70 * With fully CMSIS compliant code, NO_MSP_CLASSIC_DEFINES may be defined in * 71 * your project to omit including the classic defines * 72 ******************************************************************************/ 73 #ifndef NO_MSP_CLASSIC_DEFINES 74 #include "msp432p401r_classic.h" 75 #endif 76 77 78 #ifndef __CMSIS_CONFIG__ 79 #define __CMSIS_CONFIG__ 80 81 /** @addtogroup MSP432P401R_Definitions MSP432P401R Definitions 82 This file defines all structures and symbols for MSP432P401R: 83 - components and registers 84 - peripheral base address 85 - peripheral ID 86 - Peripheral definitions 87 @{ 88 */ 89 90 /****************************************************************************** 91 * Processor and Core Peripherals * 92 ******************************************************************************/ 93 /** @addtogroup MSP432P401R_CMSIS Device CMSIS Definitions 94 Configuration of the Cortex-M4 Processor and Core Peripherals 95 @{ 96 */ 97 98 /****************************************************************************** 99 * CMSIS-compatible Interrupt Number Definition * 100 ******************************************************************************/ 101 typedef enum IRQn 102 { 103 /* Cortex-M4 Processor Exceptions Numbers */ 104 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ 105 HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ 106 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ 107 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ 108 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ 109 SVCall_IRQn = -5, /* 11 SV Call Interrupt */ 110 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ 111 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ 112 SysTick_IRQn = -1, /* 15 System Tick Interrupt */ 113 /* Peripheral Exceptions Numbers */ 114 PSS_IRQn = 0, /* 16 PSS Interrupt */ 115 CS_IRQn = 1, /* 17 CS Interrupt */ 116 PCM_IRQn = 2, /* 18 PCM Interrupt */ 117 WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */ 118 FPU_IRQn = 4, /* 20 FPU Interrupt */ 119 FLCTL_IRQn = 5, /* 21 Flash Controller Interrupt*/ 120 COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */ 121 COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */ 122 TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ 123 TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ 124 TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ 125 TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ 126 TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ 127 TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ 128 TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ 129 TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ 130 EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */ 131 EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */ 132 EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */ 133 EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */ 134 EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */ 135 EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */ 136 EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */ 137 EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */ 138 ADC14_IRQn = 24, /* 40 ADC14 Interrupt */ 139 T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */ 140 T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */ 141 T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */ 142 AES256_IRQn = 28, /* 44 AES256 Interrupt */ 143 RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */ 144 DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */ 145 DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */ 146 DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */ 147 DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */ 148 DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */ 149 PORT1_IRQn = 35, /* 51 Port1 Interrupt */ 150 PORT2_IRQn = 36, /* 52 Port2 Interrupt */ 151 PORT3_IRQn = 37, /* 53 Port3 Interrupt */ 152 PORT4_IRQn = 38, /* 54 Port4 Interrupt */ 153 PORT5_IRQn = 39, /* 55 Port5 Interrupt */ 154 PORT6_IRQn = 40 /* 56 Port6 Interrupt */ 155 } IRQn_Type; 156 157 /****************************************************************************** 158 * Processor and Core Peripheral Section * 159 ******************************************************************************/ 160 #define __CM4_REV 0x0001 /* Core revision r0p1 */ 161 #define __MPU_PRESENT 1 /* MPU present or not */ 162 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */ 163 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ 164 #define __FPU_PRESENT 1 /* FPU present or not */ 165 166 /****************************************************************************** 167 * Available Peripherals * 168 ******************************************************************************/ 169 #define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */ 170 #define __MCU_HAS_AES256__ /*!< Module AES256 is available */ 171 #define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */ 172 #define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */ 173 #define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */ 174 #define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */ 175 #define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */ 176 #define __MCU_HAS_CS__ /*!< Module CS is available */ 177 #define __MCU_HAS_DIO__ /*!< Module DIO is available */ 178 #define __MCU_HAS_DMA__ /*!< Module DMA is available */ 179 #define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */ 180 #define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */ 181 #define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */ 182 #define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */ 183 #define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */ 184 #define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */ 185 #define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */ 186 #define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */ 187 #define __MCU_HAS_FLCTL__ /*!< Module FLCTL is available */ 188 #define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */ 189 #define __MCU_HAS_PCM__ /*!< Module PCM is available */ 190 #define __MCU_HAS_PMAP__ /*!< Module PMAP is available */ 191 #define __MCU_HAS_PSS__ /*!< Module PSS is available */ 192 #define __MCU_HAS_REF_A__ /*!< Module REF_A is available */ 193 #define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */ 194 #define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */ 195 #define __MCU_HAS_SYSCTL__ /*!< Module SYSCTL is available */ 196 #define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */ 197 #define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */ 198 #define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */ 199 #define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */ 200 #define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */ 201 #define __MCU_HAS_TLV__ /*!< Module TLV is available */ 202 #define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */ 203 204 /* Definitions to show that specific ports are available */ 205 206 #define __MSP432_HAS_PORTA_R__ 207 #define __MSP432_HAS_PORTB_R__ 208 #define __MSP432_HAS_PORTC_R__ 209 #define __MSP432_HAS_PORTD_R__ 210 #define __MSP432_HAS_PORTE_R__ 211 #define __MSP432_HAS_PORTJ_R__ 212 213 #define __MSP432_HAS_PORT1_R__ 214 #define __MSP432_HAS_PORT2_R__ 215 #define __MSP432_HAS_PORT3_R__ 216 #define __MSP432_HAS_PORT4_R__ 217 #define __MSP432_HAS_PORT5_R__ 218 #define __MSP432_HAS_PORT6_R__ 219 #define __MSP432_HAS_PORT7_R__ 220 #define __MSP432_HAS_PORT8_R__ 221 #define __MSP432_HAS_PORT9_R__ 222 #define __MSP432_HAS_PORT10_R__ 223 224 225 /*@}*/ /* end of group MSP432P401R_CMSIS */ 226 227 /* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */ 228 #ifdef __TI_ARM__ 229 /* disable the TI ULP advisor check for the core header file definitions */ 230 #pragma diag_push 231 #pragma CHECK_ULP("none") 232 #include "core_cm4.h" 233 #pragma diag_pop 234 #else 235 #include "core_cm4.h" 236 #endif 237 238 /* System Header */ 239 #include "system_msp432p401r.h" 240 241 /****************************************************************************** 242 * Definition of standard bits * 243 ******************************************************************************/ 244 #define BIT0 (uint16_t)(0x0001) 245 #define BIT1 (uint16_t)(0x0002) 246 #define BIT2 (uint16_t)(0x0004) 247 #define BIT3 (uint16_t)(0x0008) 248 #define BIT4 (uint16_t)(0x0010) 249 #define BIT5 (uint16_t)(0x0020) 250 #define BIT6 (uint16_t)(0x0040) 251 #define BIT7 (uint16_t)(0x0080) 252 #define BIT8 (uint16_t)(0x0100) 253 #define BIT9 (uint16_t)(0x0200) 254 #define BITA (uint16_t)(0x0400) 255 #define BITB (uint16_t)(0x0800) 256 #define BITC (uint16_t)(0x1000) 257 #define BITD (uint16_t)(0x2000) 258 #define BITE (uint16_t)(0x4000) 259 #define BITF (uint16_t)(0x8000) 260 261 /****************************************************************************** 262 * Device and peripheral memory map * 263 ******************************************************************************/ 264 /** @addtogroup MSP432P401R_MemoryMap MSP432P401R Memory Mapping 265 @{ 266 */ 267 268 #define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */ 269 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */ 270 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */ 271 #define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */ 272 273 #define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */ 274 #define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */ 275 #define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */ 276 #define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */ 277 #define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */ 278 #define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */ 279 #define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */ 280 #define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */ 281 #define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */ 282 #define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */ 283 #define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ 284 #define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ 285 #define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ 286 #define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ 287 #define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ 288 #define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ 289 #define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ 290 #define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ 291 #define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ 292 #define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ 293 #define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ 294 #define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ 295 #define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ 296 #define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ 297 #define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ 298 #define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ 299 #define FLCTL_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL registers */ 300 #define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */ 301 #define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */ 302 #define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */ 303 #define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */ 304 #define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */ 305 #define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */ 306 #define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ 307 #define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ 308 #define SYSCTL_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL registers */ 309 #define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */ 310 #define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */ 311 #define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */ 312 #define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */ 313 #define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */ 314 #define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */ 315 #define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */ 316 317 318 /*@}*/ /* end of group MSP432P401R_MemoryMap */ 319 320 /****************************************************************************** 321 * Definitions for bit band access * 322 ******************************************************************************/ 323 #define BITBAND_SRAM_BASE ((uint32_t)(0x22000000)) 324 #define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) 325 326 /* SRAM allows 32 bit bit band access */ 327 #define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4))) 328 /* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */ 329 #define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) 330 331 /****************************************************************************** 332 * Peripheral register definitions * 333 ******************************************************************************/ 334 /** @addtogroup MSP432P401R_Peripherals MSP432P401R Peripherals 335 MSP432P401R Device Specific Peripheral registers structures 336 @{ 337 */ 338 339 #if defined ( __CC_ARM ) 340 #pragma anon_unions 341 #endif 342 343 344 /****************************************************************************** 345 * ADC14 Registers 346 ******************************************************************************/ 347 /** @addtogroup ADC14 MSP432P401R (ADC14) 348 @{ 349 */ 350 typedef struct { 351 __IO uint32_t CTL0; /*!< Control 0 Register */ 352 __IO uint32_t CTL1; /*!< Control 1 Register */ 353 __IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */ 354 __IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */ 355 __IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */ 356 __IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */ 357 __IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */ 358 __IO uint32_t MEM[32]; /*!< Conversion Memory Register */ 359 uint32_t RESERVED0[9]; 360 __IO uint32_t IER0; /*!< Interrupt Enable 0 Register */ 361 __IO uint32_t IER1; /*!< Interrupt Enable 1 Register */ 362 __I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */ 363 __I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */ 364 __O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */ 365 __IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */ 366 __IO uint32_t IV; /*!< Interrupt Vector Register */ 367 } ADC14_Type; 368 369 /*@}*/ /* end of group ADC14 */ 370 371 372 /****************************************************************************** 373 * AES256 Registers 374 ******************************************************************************/ 375 /** @addtogroup AES256 MSP432P401R (AES256) 376 @{ 377 */ 378 typedef struct { 379 __IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */ 380 __IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */ 381 __IO uint16_t STAT; /*!< AES Accelerator Status Register */ 382 __O uint16_t KEY; /*!< AES Accelerator Key Register */ 383 __O uint16_t DIN; /*!< AES Accelerator Data In Register */ 384 __O uint16_t DOUT; /*!< AES Accelerator Data Out Register */ 385 __O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */ 386 __O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */ 387 } AES256_Type; 388 389 /*@}*/ /* end of group AES256 */ 390 391 392 /****************************************************************************** 393 * CAPTIO Registers 394 ******************************************************************************/ 395 /** @addtogroup CAPTIO MSP432P401R (CAPTIO) 396 @{ 397 */ 398 typedef struct { 399 uint16_t RESERVED0[7]; 400 __IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */ 401 } CAPTIO_Type; 402 403 /*@}*/ /* end of group CAPTIO */ 404 405 406 /****************************************************************************** 407 * COMP_E Registers 408 ******************************************************************************/ 409 /** @addtogroup COMP_E MSP432P401R (COMP_E) 410 @{ 411 */ 412 typedef struct { 413 __IO uint16_t CTL0; /*!< Comparator Control Register 0 */ 414 __IO uint16_t CTL1; /*!< Comparator Control Register 1 */ 415 __IO uint16_t CTL2; /*!< Comparator Control Register 2 */ 416 __IO uint16_t CTL3; /*!< Comparator Control Register 3 */ 417 uint16_t RESERVED0[2]; 418 __IO uint16_t INT; /*!< Comparator Interrupt Control Register */ 419 __I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */ 420 } COMP_E_Type; 421 422 /*@}*/ /* end of group COMP_E */ 423 424 425 /****************************************************************************** 426 * CRC32 Registers 427 ******************************************************************************/ 428 /** @addtogroup CRC32 MSP432P401R (CRC32) 429 @{ 430 */ 431 typedef struct { 432 __IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */ 433 uint16_t RESERVED0; 434 __IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */ 435 uint16_t RESERVED1; 436 __IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */ 437 __IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */ 438 __IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */ 439 __IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */ 440 __IO uint16_t DI16; /*!< Data Input for CRC16 computation */ 441 uint16_t RESERVED2; 442 __IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */ 443 uint16_t RESERVED3; 444 __IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */ 445 uint16_t RESERVED4[2]; 446 __IO uint16_t RESR16; /*!< CRC16 Result Reverse */ 447 } CRC32_Type; 448 449 /*@}*/ /* end of group CRC32 */ 450 451 452 /****************************************************************************** 453 * CS Registers 454 ******************************************************************************/ 455 /** @addtogroup CS MSP432P401R (CS) 456 @{ 457 */ 458 typedef struct { 459 __IO uint32_t KEY; /*!< Key Register */ 460 __IO uint32_t CTL0; /*!< Control 0 Register */ 461 __IO uint32_t CTL1; /*!< Control 1 Register */ 462 __IO uint32_t CTL2; /*!< Control 2 Register */ 463 __IO uint32_t CTL3; /*!< Control 3 Register */ 464 uint32_t RESERVED0[7]; 465 __IO uint32_t CLKEN; /*!< Clock Enable Register */ 466 __I uint32_t STAT; /*!< Status Register */ 467 uint32_t RESERVED1[2]; 468 __IO uint32_t IE; /*!< Interrupt Enable Register */ 469 uint32_t RESERVED2; 470 __I uint32_t IFG; /*!< Interrupt Flag Register */ 471 uint32_t RESERVED3; 472 __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 473 uint32_t RESERVED4; 474 __O uint32_t SETIFG; /*!< Set Interrupt Flag Register */ 475 uint32_t RESERVED5; 476 __IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */ 477 __IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */ 478 } CS_Type; 479 480 /*@}*/ /* end of group CS */ 481 482 483 /****************************************************************************** 484 * DIO Registers 485 ******************************************************************************/ 486 /** @addtogroup DIO MSP432P401R (DIO) 487 @{ 488 */ 489 typedef struct { 490 union { 491 __I uint16_t IN; /*!< Port Pair Input */ 492 struct { 493 __I uint8_t IN_L; /*!< Low Port Input */ 494 __I uint8_t IN_H; /*!< High Port Input */ 495 }; 496 }; 497 union { 498 __IO uint16_t OUT; /*!< Port Pair Output */ 499 struct { 500 __IO uint8_t OUT_L; /*!< Low Port Output */ 501 __IO uint8_t OUT_H; /*!< High Port Output */ 502 }; 503 }; 504 union { 505 __IO uint16_t DIR; /*!< Port Pair Direction */ 506 struct { 507 __IO uint8_t DIR_L; /*!< Low Port Direction */ 508 __IO uint8_t DIR_H; /*!< High Port Direction */ 509 }; 510 }; 511 union { 512 __IO uint16_t REN; /*!< Port Pair Resistor Enable */ 513 struct { 514 __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ 515 __IO uint8_t REN_H; /*!< High Port Resistor Enable */ 516 }; 517 }; 518 union { 519 __IO uint16_t DS; /*!< Port Pair Drive Strength */ 520 struct { 521 __IO uint8_t DS_L; /*!< Low Port Drive Strength */ 522 __IO uint8_t DS_H; /*!< High Port Drive Strength */ 523 }; 524 }; 525 union { 526 __IO uint16_t SEL0; /*!< Port Pair Select 0 */ 527 struct { 528 __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ 529 __IO uint8_t SEL0_H; /*!< High Port Select 0 */ 530 }; 531 }; 532 union { 533 __IO uint16_t SEL1; /*!< Port Pair Select 1 */ 534 struct { 535 __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ 536 __IO uint8_t SEL1_H; /*!< High Port Select 1 */ 537 }; 538 }; 539 __I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */ 540 uint16_t RESERVED0[3]; 541 union { 542 __IO uint16_t SELC; /*!< Port Pair Complement Select */ 543 struct { 544 __IO uint8_t SELC_L; /*!< Low Port Complement Select */ 545 __IO uint8_t SELC_H; /*!< High Port Complement Select */ 546 }; 547 }; 548 union { 549 __IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */ 550 struct { 551 __IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */ 552 __IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */ 553 }; 554 }; 555 union { 556 __IO uint16_t IE; /*!< Port Pair Interrupt Enable */ 557 struct { 558 __IO uint8_t IE_L; /*!< Low Port Interrupt Enable */ 559 __IO uint8_t IE_H; /*!< High Port Interrupt Enable */ 560 }; 561 }; 562 union { 563 __IO uint16_t IFG; /*!< Port Pair Interrupt Flag */ 564 struct { 565 __IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */ 566 __IO uint8_t IFG_H; /*!< High Port Interrupt Flag */ 567 }; 568 }; 569 __I uint16_t IV_H; /*!< High Port Interrupt Vector Value */ 570 } DIO_PORT_Interruptable_Type; 571 572 typedef struct { 573 union { 574 __I uint16_t IN; /*!< Port Pair Input */ 575 struct { 576 __I uint8_t IN_L; /*!< Low Port Input */ 577 __I uint8_t IN_H; /*!< High Port Input */ 578 }; 579 }; 580 union { 581 __IO uint16_t OUT; /*!< Port Pair Output */ 582 struct { 583 __IO uint8_t OUT_L; /*!< Low Port Output */ 584 __IO uint8_t OUT_H; /*!< High Port Output */ 585 }; 586 }; 587 union { 588 __IO uint16_t DIR; /*!< Port Pair Direction */ 589 struct { 590 __IO uint8_t DIR_L; /*!< Low Port Direction */ 591 __IO uint8_t DIR_H; /*!< High Port Direction */ 592 }; 593 }; 594 union { 595 __IO uint16_t REN; /*!< Port Pair Resistor Enable */ 596 struct { 597 __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ 598 __IO uint8_t REN_H; /*!< High Port Resistor Enable */ 599 }; 600 }; 601 union { 602 __IO uint16_t DS; /*!< Port Pair Drive Strength */ 603 struct { 604 __IO uint8_t DS_L; /*!< Low Port Drive Strength */ 605 __IO uint8_t DS_H; /*!< High Port Drive Strength */ 606 }; 607 }; 608 union { 609 __IO uint16_t SEL0; /*!< Port Pair Select 0 */ 610 struct { 611 __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ 612 __IO uint8_t SEL0_H; /*!< High Port Select 0 */ 613 }; 614 }; 615 union { 616 __IO uint16_t SEL1; /*!< Port Pair Select 1 */ 617 struct { 618 __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ 619 __IO uint8_t SEL1_H; /*!< High Port Select 1 */ 620 }; 621 }; 622 uint16_t RESERVED0[4]; 623 union { 624 __IO uint16_t SELC; /*!< Port Pair Complement Select */ 625 struct { 626 __IO uint8_t SELC_L; /*!< Low Port Complement Select */ 627 __IO uint8_t SELC_H; /*!< High Port Complement Select */ 628 }; 629 }; 630 } DIO_PORT_Not_Interruptable_Type; 631 632 633 typedef struct { 634 __I uint8_t IN; /*!< Port Input */ 635 uint8_t RESERVED0; 636 __IO uint8_t OUT; /*!< Port Output */ 637 uint8_t RESERVED1; 638 __IO uint8_t DIR; /*!< Port Direction */ 639 uint8_t RESERVED2; 640 __IO uint8_t REN; /*!< Port Resistor Enable */ 641 uint8_t RESERVED3; 642 __IO uint8_t DS; /*!< Port Drive Strength */ 643 uint8_t RESERVED4; 644 __IO uint8_t SEL0; /*!< Port Select 0 */ 645 uint8_t RESERVED5; 646 __IO uint8_t SEL1; /*!< Port Select 1 */ 647 uint8_t RESERVED6; 648 __I uint16_t IV; /*!< Port Interrupt Vector Value */ 649 uint8_t RESERVED7[6]; 650 __IO uint8_t SELC; /*!< Port Complement Select */ 651 uint8_t RESERVED8; 652 __IO uint8_t IES; /*!< Port Interrupt Edge Select */ 653 uint8_t RESERVED9; 654 __IO uint8_t IE; /*!< Port Interrupt Enable */ 655 uint8_t RESERVED10; 656 __IO uint8_t IFG; /*!< Port Interrupt Flag */ 657 } DIO_PORT_Odd_Interruptable_Type; 658 659 typedef struct { 660 uint8_t RESERVED0; 661 __I uint8_t IN; /*!< Port Input */ 662 uint8_t RESERVED1; 663 __IO uint8_t OUT; /*!< Port Output */ 664 uint8_t RESERVED2; 665 __IO uint8_t DIR; /*!< Port Direction */ 666 uint8_t RESERVED3; 667 __IO uint8_t REN; /*!< Port Resistor Enable */ 668 uint8_t RESERVED4; 669 __IO uint8_t DS; /*!< Port Drive Strength */ 670 uint8_t RESERVED5; 671 __IO uint8_t SEL0; /*!< Port Select 0 */ 672 uint8_t RESERVED6; 673 __IO uint8_t SEL1; /*!< Port Select 1 */ 674 uint8_t RESERVED7[9]; 675 __IO uint8_t SELC; /*!< Port Complement Select */ 676 uint8_t RESERVED8; 677 __IO uint8_t IES; /*!< Port Interrupt Edge Select */ 678 uint8_t RESERVED9; 679 __IO uint8_t IE; /*!< Port Interrupt Enable */ 680 uint8_t RESERVED10; 681 __IO uint8_t IFG; /*!< Port Interrupt Flag */ 682 __I uint16_t IV; /*!< Port Interrupt Vector Value */ 683 } DIO_PORT_Even_Interruptable_Type; 684 685 /*@}*/ /* end of group MSP432P401R_DIO */ 686 687 688 /****************************************************************************** 689 * DMA Registers 690 ******************************************************************************/ 691 /** @addtogroup DMA MSP432P401R (DMA) 692 @{ 693 */ 694 typedef struct { 695 __I uint32_t DEVICE_CFG; /*!< Device Configuration Status */ 696 __IO uint32_t SW_CHTRIG; /*!< Software Channel Trigger Register */ 697 uint32_t RESERVED0[2]; 698 __IO uint32_t CH_SRCCFG[32]; /*!< Channel n Source Configuration Register */ 699 uint32_t RESERVED1[28]; 700 __IO uint32_t INT1_SRCCFG; /*!< Interrupt 1 Source Channel Configuration */ 701 __IO uint32_t INT2_SRCCFG; /*!< Interrupt 2 Source Channel Configuration Register */ 702 __IO uint32_t INT3_SRCCFG; /*!< Interrupt 3 Source Channel Configuration Register */ 703 uint32_t RESERVED2; 704 __I uint32_t INT0_SRCFLG; /*!< Interrupt 0 Source Channel Flag Register */ 705 __O uint32_t INT0_CLRFLG; /*!< Interrupt 0 Source Channel Clear Flag Register */ 706 } DMA_Channel_Type; 707 708 typedef struct { 709 __I uint32_t STAT; /*!< Status Register */ 710 __O uint32_t CFG; /*!< Configuration Register */ 711 __IO uint32_t CTLBASE; /*!< Channel Control Data Base Pointer Register */ 712 __I uint32_t ALTBASE; /*!< Channel Alternate Control Data Base Pointer Register */ 713 __I uint32_t WAITSTAT; /*!< Channel Wait on Request Status Register */ 714 __O uint32_t SWREQ; /*!< Channel Software Request Register */ 715 __IO uint32_t USEBURSTSET; /*!< Channel Useburst Set Register */ 716 __O uint32_t USEBURSTCLR; /*!< Channel Useburst Clear Register */ 717 __IO uint32_t REQMASKSET; /*!< Channel Request Mask Set Register */ 718 __O uint32_t REQMASKCLR; /*!< Channel Request Mask Clear Register */ 719 __IO uint32_t ENASET; /*!< Channel Enable Set Register */ 720 __O uint32_t ENACLR; /*!< Channel Enable Clear Register */ 721 __IO uint32_t ALTSET; /*!< Channel Primary-Alternate Set Register */ 722 __O uint32_t ALTCLR; /*!< Channel Primary-Alternate Clear Register */ 723 __IO uint32_t PRIOSET; /*!< Channel Priority Set Register */ 724 __O uint32_t PRIOCLR; /*!< Channel Priority Clear Register */ 725 uint32_t RESERVED4[3]; 726 __IO uint32_t ERRCLR; /*!< Bus Error Clear Register */ 727 } DMA_Control_Type; 728 729 /*@}*/ /* end of group DMA */ 730 731 732 /****************************************************************************** 733 * EUSCI_A Registers 734 ******************************************************************************/ 735 /** @addtogroup EUSCI_A MSP432P401R (EUSCI_A) 736 @{ 737 */ 738 typedef struct { 739 __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ 740 __IO uint16_t CTLW1; /*!< eUSCI_Ax Control Word Register 1 */ 741 uint16_t RESERVED0; 742 __IO uint16_t BRW; /*!< eUSCI_Ax Baud Rate Control Word Register */ 743 __IO uint16_t MCTLW; /*!< eUSCI_Ax Modulation Control Word Register */ 744 __IO uint16_t STATW; /*!< eUSCI_Ax Status Register */ 745 __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ 746 __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ 747 __IO uint16_t ABCTL; /*!< eUSCI_Ax Auto Baud Rate Control Register */ 748 __IO uint16_t IRCTL; /*!< eUSCI_Ax IrDA Control Word Register */ 749 uint16_t RESERVED1[3]; 750 __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ 751 __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ 752 __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ 753 } EUSCI_A_Type; 754 755 /*@}*/ /* end of group EUSCI_A */ 756 757 /** @addtogroup EUSCI_A_SPI MSP432P401R (EUSCI_A_SPI) 758 @{ 759 */ 760 typedef struct { 761 __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ 762 uint16_t RESERVED0[2]; 763 __IO uint16_t BRW; /*!< eUSCI_Ax Bit Rate Control Register 1 */ 764 uint16_t RESERVED1; 765 __IO uint16_t STATW; 766 __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ 767 __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ 768 uint16_t RESERVED2[5]; 769 __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ 770 __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ 771 __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ 772 } EUSCI_A_SPI_Type; 773 774 /*@}*/ /* end of group EUSCI_A_SPI */ 775 776 777 /****************************************************************************** 778 * EUSCI_B Registers 779 ******************************************************************************/ 780 /** @addtogroup EUSCI_B MSP432P401R (EUSCI_B) 781 @{ 782 */ 783 typedef struct { 784 __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ 785 __IO uint16_t CTLW1; /*!< eUSCI_Bx Control Word Register 1 */ 786 uint16_t RESERVED0; 787 __IO uint16_t BRW; /*!< eUSCI_Bx Baud Rate Control Word Register */ 788 __IO uint16_t STATW; /*!< eUSCI_Bx Status Register */ 789 __IO uint16_t TBCNT; /*!< eUSCI_Bx Byte Counter Threshold Register */ 790 __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ 791 __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ 792 uint16_t RESERVED1[2]; 793 __IO uint16_t I2COA0; /*!< eUSCI_Bx I2C Own Address 0 Register */ 794 __IO uint16_t I2COA1; /*!< eUSCI_Bx I2C Own Address 1 Register */ 795 __IO uint16_t I2COA2; /*!< eUSCI_Bx I2C Own Address 2 Register */ 796 __IO uint16_t I2COA3; /*!< eUSCI_Bx I2C Own Address 3 Register */ 797 __I uint16_t ADDRX; /*!< eUSCI_Bx I2C Received Address Register */ 798 __IO uint16_t ADDMASK; /*!< eUSCI_Bx I2C Address Mask Register */ 799 __IO uint16_t I2CSA; /*!< eUSCI_Bx I2C Slave Address Register */ 800 uint16_t RESERVED2[4]; 801 __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ 802 __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ 803 __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ 804 } EUSCI_B_Type; 805 806 /*@}*/ /* end of group EUSCI_B */ 807 808 /** @addtogroup EUSCI_B_SPI MSP432P401R (EUSCI_B_SPI) 809 @{ 810 */ 811 typedef struct { 812 __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ 813 uint16_t RESERVED0[2]; 814 __IO uint16_t BRW; /*!< eUSCI_Bx Bit Rate Control Register 1 */ 815 __IO uint16_t STATW; 816 uint16_t RESERVED1; 817 __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ 818 __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ 819 uint16_t RESERVED2[13]; 820 __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ 821 __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ 822 __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ 823 } EUSCI_B_SPI_Type; 824 825 /*@}*/ /* end of group EUSCI_B_SPI */ 826 827 828 /****************************************************************************** 829 * FLCTL Registers 830 ******************************************************************************/ 831 /** @addtogroup FLCTL MSP432P401R (FLCTL) 832 @{ 833 */ 834 typedef struct { 835 __I uint32_t POWER_STAT; /*!< Power Status Register */ 836 uint32_t RESERVED0[3]; 837 __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ 838 __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ 839 uint32_t RESERVED1[2]; 840 __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ 841 __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ 842 __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ 843 uint32_t RESERVED2[4]; 844 __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ 845 __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ 846 uint32_t RESERVED3[3]; 847 __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ 848 __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ 849 __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ 850 uint32_t RESERVED4; 851 __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ 852 __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ 853 __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ 854 __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ 855 __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ 856 __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ 857 __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ 858 __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ 859 __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ 860 __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ 861 __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ 862 __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ 863 __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ 864 __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ 865 __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ 866 __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ 867 __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ 868 __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ 869 uint32_t RESERVED5[2]; 870 __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ 871 __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ 872 uint32_t RESERVED6[2]; 873 __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ 874 __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ 875 uint32_t RESERVED7[2]; 876 __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ 877 __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ 878 __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ 879 __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ 880 uint32_t RESERVED8[4]; 881 __IO uint32_t IFG; /*!< Interrupt Flag Register */ 882 __IO uint32_t IE; /*!< Interrupt Enable Register */ 883 __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 884 __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ 885 __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ 886 __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ 887 __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ 888 __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ 889 __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ 890 __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ 891 __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ 892 __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ 893 __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ 894 } FLCTL_Type; 895 896 /*@}*/ /* end of group FLCTL */ 897 898 899 /****************************************************************************** 900 * FL_BOOTOVER_MAILBOX Registers 901 ******************************************************************************/ 902 /** @addtogroup SEC_ZONE_PARAMS MSP432P401R (FL_BOOTOVER_MAILBOX) 903 @{ 904 */ 905 typedef struct { 906 __IO uint32_t SEC_ZONE_SECEN; /*!< IP Protection Secure Zone Enable. */ 907 __IO uint32_t SEC_ZONE_START_ADDR; /*!< Start address of IP protected secure zone. */ 908 __IO uint32_t SEC_ZONE_LENGTH; /*!< Length of IP protected secure zone in number of bytes. */ 909 __IO uint32_t SEC_ZONE_AESINIT_VECT[4]; /*!< IP protected secure zone 0 AES initialization vector */ 910 __IO uint32_t SEC_ZONE_SECKEYS[8]; /*!< AES-CBC security keys. */ 911 __IO uint32_t SEC_ZONE_UNENC_PWD[4]; /*!< Unencrypted password for authentication. */ 912 __IO uint32_t SEC_ZONE_ENCUPDATE_EN; /*!< IP Protected Secure Zone Encrypted In-field Update Enable */ 913 __IO uint32_t SEC_ZONE_DATA_EN; /*!< IP Protected Secure Zone Data Access Enable */ 914 __IO uint32_t SEC_ZONE_ACK; /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */ 915 uint32_t RESERVED0[2]; 916 } SEC_ZONE_PARAMS_Type; 917 918 /*@}*/ /* end of group SEC_ZONE_PARAMS */ 919 920 /** @addtogroup SEC_ZONE_UPDATE MSP432P401R (FL_BOOTOVER_MAILBOX) 921 @{ 922 */ 923 typedef struct { 924 __IO uint32_t SEC_ZONE_PAYLOADADDR; /*!< Start address where the payload is loaded in the device. */ 925 __IO uint32_t SEC_ZONE_PAYLOADLEN; /*!< Length of the payload in bytes. */ 926 __IO uint32_t SEC_ZONE_UPDATE_ACK; /*!< Acknowledgment for the IP Protected Secure Zone Update Command */ 927 uint32_t RESERVED0; 928 } SEC_ZONE_UPDATE_Type; 929 930 /*@}*/ /* end of group SEC_ZONE_UPDATE */ 931 932 /** @addtogroup FL_BOOTOVER_MAILBOX MSP432P401R (FL_BOOTOVER_MAILBOX) 933 @{ 934 */ 935 typedef struct { 936 __IO uint32_t MB_START; /*!< Flash MailBox start: 0x0115ACF6 */ 937 __IO uint32_t CMD; /*!< Command for Boot override operations. */ 938 uint32_t RESERVED0[2]; 939 __IO uint32_t JTAG_SWD_LOCK_SECEN; /*!< JTAG and SWD Lock Enable */ 940 __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4]; /*!< JTAG and SWD lock AES initialization vector for AES-CBC */ 941 __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8]; /*!< JTAG and SWD lock AES CBC security Keys 0-7. */ 942 __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4]; /*!< JTAG and SWD lock unencrypted password */ 943 __IO uint32_t JTAG_SWD_LOCK_ACK; /*!< Acknowledgment for JTAG and SWD Lock command */ 944 uint32_t RESERVED1[2]; 945 SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4]; 946 __IO uint32_t BSL_ENABLE; /*!< BSL Enable. */ 947 __IO uint32_t BSL_START_ADDRESS; /*!< Contains the pointer to the BSL function. */ 948 __IO uint32_t BSL_PARAMETERS; /*!< BSL hardware invoke conifguration field. */ 949 uint32_t RESERVED2[2]; 950 __IO uint32_t BSL_ACK; /*!< Acknowledgment for the BSL Configuration Command */ 951 __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD; /*!< Start address where the payload is loaded in the device. */ 952 __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN; /*!< Length of the encrypted payload in bytes */ 953 __IO uint32_t JTAG_SWD_LOCK_DST_ADDR; /*!< Destination address where the final data needs to be stored into the device. */ 954 __IO uint32_t ENC_UPDATE_ACK; /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */ 955 uint32_t RESERVED3; 956 SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4]; 957 uint32_t RESERVED4; 958 __IO uint32_t FACTORY_RESET_ENABLE; /*!< Enable/Disable Factory Reset */ 959 __IO uint32_t FACTORY_RESET_PWDEN; /*!< Factory reset password enable */ 960 __IO uint32_t FACTORY_RESET_PWD[4]; /*!< 128-bit Password for factory reset to be saved into the device. */ 961 __IO uint32_t FACTORY_RESET_PARAMS_ACK; /*!< Acknowledgment for the Factory Reset Params Command */ 962 uint32_t RESERVED5; 963 __IO uint32_t FACTORY_RESET_PASSWORD[4]; /*!< 128-bit Password for factory reset. */ 964 __IO uint32_t FACTORY_RESET_ACK; /*!< Acknowledgment for the Factory Reset Command */ 965 uint32_t RESERVED6[2]; 966 __IO uint32_t MB_END; /*!< Mailbox end */ 967 } FL_BOOTOVER_MAILBOX_Type; 968 969 /*@}*/ /* end of group FL_BOOTOVER_MAILBOX */ 970 971 972 /****************************************************************************** 973 * PCM Registers 974 ******************************************************************************/ 975 /** @addtogroup PCM MSP432P401R (PCM) 976 @{ 977 */ 978 typedef struct { 979 __IO uint32_t CTL0; /*!< Control 0 Register */ 980 __IO uint32_t CTL1; /*!< Control 1 Register */ 981 __IO uint32_t IE; /*!< Interrupt Enable Register */ 982 __I uint32_t IFG; /*!< Interrupt Flag Register */ 983 __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 984 } PCM_Type; 985 986 /*@}*/ /* end of group PCM */ 987 988 989 /****************************************************************************** 990 * PMAP Registers 991 ******************************************************************************/ 992 /** @addtogroup PMAP MSP432P401R (PMAP) 993 @{ 994 */ 995 typedef struct { 996 __IO uint16_t KEYID; 997 __IO uint16_t CTL; 998 } PMAP_COMMON_Type; 999 1000 typedef struct { 1001 union { 1002 __IO uint16_t PMAP_REGISTER[4]; 1003 struct { 1004 __IO uint8_t PMAP_REGISTER0; 1005 __IO uint8_t PMAP_REGISTER1; 1006 __IO uint8_t PMAP_REGISTER2; 1007 __IO uint8_t PMAP_REGISTER3; 1008 __IO uint8_t PMAP_REGISTER4; 1009 __IO uint8_t PMAP_REGISTER5; 1010 __IO uint8_t PMAP_REGISTER6; 1011 __IO uint8_t PMAP_REGISTER7; 1012 }; 1013 }; 1014 } PMAP_REGISTER_Type; 1015 1016 /*@}*/ /* end of group PMAP */ 1017 1018 1019 /****************************************************************************** 1020 * PSS Registers 1021 ******************************************************************************/ 1022 /** @addtogroup PSS MSP432P401R (PSS) 1023 @{ 1024 */ 1025 typedef struct { 1026 __IO uint32_t KEY; /*!< Key Register */ 1027 __IO uint32_t CTL0; /*!< Control 0 Register */ 1028 uint32_t RESERVED0[11]; 1029 __IO uint32_t IE; /*!< Interrupt Enable Register */ 1030 __I uint32_t IFG; /*!< Interrupt Flag Register */ 1031 __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 1032 } PSS_Type; 1033 1034 /*@}*/ /* end of group PSS */ 1035 1036 1037 /****************************************************************************** 1038 * REF_A Registers 1039 ******************************************************************************/ 1040 /** @addtogroup REF_A MSP432P401R (REF_A) 1041 @{ 1042 */ 1043 typedef struct { 1044 __IO uint16_t CTL0; /*!< REF Control Register 0 */ 1045 } REF_A_Type; 1046 1047 /*@}*/ /* end of group REF_A */ 1048 1049 1050 /****************************************************************************** 1051 * RSTCTL Registers 1052 ******************************************************************************/ 1053 /** @addtogroup RSTCTL MSP432P401R (RSTCTL) 1054 @{ 1055 */ 1056 typedef struct { 1057 __IO uint32_t RESET_REQ; /*!< Reset Request Register */ 1058 __I uint32_t HARDRESET_STAT; /*!< Hard Reset Status Register */ 1059 __IO uint32_t HARDRESET_CLR; /*!< Hard Reset Status Clear Register */ 1060 __IO uint32_t HARDRESET_SET; /*!< Hard Reset Status Set Register */ 1061 __I uint32_t SOFTRESET_STAT; /*!< Soft Reset Status Register */ 1062 __IO uint32_t SOFTRESET_CLR; /*!< Soft Reset Status Clear Register */ 1063 __IO uint32_t SOFTRESET_SET; /*!< Soft Reset Status Set Register */ 1064 uint32_t RESERVED0[57]; 1065 __I uint32_t PSSRESET_STAT; /*!< PSS Reset Status Register */ 1066 __IO uint32_t PSSRESET_CLR; /*!< PSS Reset Status Clear Register */ 1067 __I uint32_t PCMRESET_STAT; /*!< PCM Reset Status Register */ 1068 __IO uint32_t PCMRESET_CLR; /*!< PCM Reset Status Clear Register */ 1069 __I uint32_t PINRESET_STAT; /*!< Pin Reset Status Register */ 1070 __IO uint32_t PINRESET_CLR; /*!< Pin Reset Status Clear Register */ 1071 __I uint32_t REBOOTRESET_STAT; /*!< Reboot Reset Status Register */ 1072 __IO uint32_t REBOOTRESET_CLR; /*!< Reboot Reset Status Clear Register */ 1073 __I uint32_t CSRESET_STAT; /*!< CS Reset Status Register */ 1074 __IO uint32_t CSRESET_CLR; /*!< CS Reset Status Clear Register */ 1075 } RSTCTL_Type; 1076 1077 /*@}*/ /* end of group RSTCTL */ 1078 1079 1080 /****************************************************************************** 1081 * RTC_C Registers 1082 ******************************************************************************/ 1083 /** @addtogroup RTC_C MSP432P401R (RTC_C) 1084 @{ 1085 */ 1086 typedef struct { 1087 __IO uint16_t CTL0; /*!< RTCCTL0 Register */ 1088 __IO uint16_t CTL13; /*!< RTCCTL13 Register */ 1089 __IO uint16_t OCAL; /*!< RTCOCAL Register */ 1090 __IO uint16_t TCMP; /*!< RTCTCMP Register */ 1091 __IO uint16_t PS0CTL; /*!< Real-Time Clock Prescale Timer 0 Control Register */ 1092 __IO uint16_t PS1CTL; /*!< Real-Time Clock Prescale Timer 1 Control Register */ 1093 __IO uint16_t PS; /*!< Real-Time Clock Prescale Timer Counter Register */ 1094 __I uint16_t IV; /*!< Real-Time Clock Interrupt Vector Register */ 1095 __IO uint16_t TIM0; /*!< RTCTIM0 Register Hexadecimal Format */ 1096 __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week */ 1097 __IO uint16_t DATE; /*!< RTCDATE - Hexadecimal Format */ 1098 __IO uint16_t YEAR; /*!< RTCYEAR Register Hexadecimal Format */ 1099 __IO uint16_t AMINHR; /*!< RTCMINHR - Hexadecimal Format */ 1100 __IO uint16_t ADOWDAY; /*!< RTCADOWDAY - Hexadecimal Format */ 1101 __IO uint16_t BIN2BCD; /*!< Binary-to-BCD Conversion Register */ 1102 __IO uint16_t BCD2BIN; /*!< BCD-to-Binary Conversion Register */ 1103 } RTC_C_Type; 1104 1105 /*@}*/ /* end of group RTC_C */ 1106 1107 /** @addtogroup RTC_C_BCD MSP432P401R (RTC_C_BCD) 1108 @{ 1109 */ 1110 typedef struct { 1111 uint16_t RESERVED0[8]; 1112 __IO uint16_t TIM0; /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */ 1113 __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week - BCD Format */ 1114 __IO uint16_t DATE; /*!< Real-Time Clock Date - BCD Format */ 1115 __IO uint16_t YEAR; /*!< Real-Time Clock Year Register - BCD Format */ 1116 __IO uint16_t AMINHR; /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */ 1117 __IO uint16_t ADOWDAY; /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */ 1118 } RTC_C_BCD_Type; 1119 1120 /*@}*/ /* end of group RTC_C_BCD */ 1121 1122 1123 /****************************************************************************** 1124 * SYSCTL Registers 1125 ******************************************************************************/ 1126 /** @addtogroup SYSCTL MSP432P401R (SYSCTL) 1127 @{ 1128 */ 1129 typedef struct { 1130 __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ 1131 __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ 1132 __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ 1133 __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ 1134 __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ 1135 __IO uint32_t SRAM_BANKEN; /*!< SRAM Bank Enable Register */ 1136 __IO uint32_t SRAM_BANKRET; /*!< SRAM Bank Retention Control Register */ 1137 uint32_t RESERVED0; 1138 __I uint32_t FLASH_SIZE; /*!< Flash Size Register */ 1139 uint32_t RESERVED1[3]; 1140 __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ 1141 uint32_t RESERVED2[3]; 1142 __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ 1143 } SYSCTL_Type; 1144 1145 typedef struct { 1146 __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ 1147 __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ 1148 __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ 1149 __IO uint32_t RESET_REQ; /*!< Reset Request Register */ 1150 __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ 1151 uint32_t RESERVED7[2]; 1152 __I uint32_t SYSTEM_STAT; /*!< System Status Register */ 1153 } SYSCTL_Boot_Type; 1154 1155 /*@}*/ /* end of group SYSCTL */ 1156 1157 1158 /****************************************************************************** 1159 * Timer32 Registers 1160 ******************************************************************************/ 1161 /** @addtogroup Timer32 MSP432P401R (Timer32) 1162 @{ 1163 */ 1164 typedef struct { 1165 __IO uint32_t LOAD; /*!< Timer Load Register */ 1166 __I uint32_t VALUE; /*!< Timer Current Value Register */ 1167 __IO uint32_t CONTROL; /*!< Timer Control Register */ 1168 __O uint32_t INTCLR; /*!< Timer Interrupt Clear Register */ 1169 __I uint32_t RIS; /*!< Timer Raw Interrupt Status Register */ 1170 __I uint32_t MIS; /*!< Timer Interrupt Status Register */ 1171 __IO uint32_t BGLOAD; /*!< Timer Background Load Register */ 1172 } Timer32_Type; 1173 1174 /*@}*/ /* end of group Timer32 */ 1175 1176 1177 /****************************************************************************** 1178 * Timer_A Registers 1179 ******************************************************************************/ 1180 /** @addtogroup Timer_A MSP432P401R (Timer_A) 1181 @{ 1182 */ 1183 typedef struct { 1184 __IO uint16_t CTL; /*!< TimerAx Control Register */ 1185 __IO uint16_t CCTL[5]; /*!< Timer_A Capture/Compare Control Register */ 1186 uint16_t RESERVED0[2]; 1187 __IO uint16_t R; /*!< TimerA register */ 1188 __IO uint16_t CCR[5]; /*!< Timer_A Capture/Compare Register */ 1189 uint16_t RESERVED1[2]; 1190 __IO uint16_t EX0; /*!< TimerAx Expansion 0 Register */ 1191 uint16_t RESERVED2[6]; 1192 __I uint16_t IV; /*!< TimerAx Interrupt Vector Register */ 1193 } Timer_A_Type; 1194 1195 /*@}*/ /* end of group Timer_A */ 1196 1197 1198 /****************************************************************************** 1199 * TLV Registers 1200 ******************************************************************************/ 1201 /** @addtogroup TLV MSP432P401R (TLV) 1202 @{ 1203 */ 1204 typedef struct { 1205 __I uint32_t TLV_CHECKSUM; /*!< TLV Checksum */ 1206 __I uint32_t DEVICE_INFO_TAG; /*!< Device Info Tag */ 1207 __I uint32_t DEVICE_INFO_LEN; /*!< Device Info Length */ 1208 __I uint32_t DEVICE_ID; /*!< Device ID */ 1209 __I uint32_t HWREV; /*!< HW Revision */ 1210 __I uint32_t BCREV; /*!< Boot Code Revision */ 1211 __I uint32_t ROM_DRVLIB_REV; /*!< ROM Driver Library Revision */ 1212 __I uint32_t DIE_REC_TAG; /*!< Die Record Tag */ 1213 __I uint32_t DIE_REC_LEN; /*!< Die Record Length */ 1214 __I uint32_t DIE_XPOS; /*!< Die X-Position */ 1215 __I uint32_t DIE_YPOS; /*!< Die Y-Position */ 1216 __I uint32_t WAFER_ID; /*!< Wafer ID */ 1217 __I uint32_t LOT_ID; /*!< Lot ID */ 1218 __I uint32_t RESERVED0; /*!< Reserved */ 1219 __I uint32_t RESERVED1; /*!< Reserved */ 1220 __I uint32_t RESERVED2; /*!< Reserved */ 1221 __I uint32_t TEST_RESULTS; /*!< Test Results */ 1222 __I uint32_t CS_CAL_TAG; /*!< Clock System Calibration Tag */ 1223 __I uint32_t CS_CAL_LEN; /*!< Clock System Calibration Length */ 1224 __I uint32_t DCOIR_FCAL_RSEL04; /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */ 1225 __I uint32_t DCOIR_FCAL_RSEL5; /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */ 1226 __I uint32_t RESERVED3; /*!< Reserved */ 1227 __I uint32_t RESERVED4; /*!< Reserved */ 1228 __I uint32_t RESERVED5; /*!< Reserved */ 1229 __I uint32_t RESERVED6; /*!< Reserved */ 1230 __I uint32_t DCOIR_CONSTK_RSEL04; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */ 1231 __I uint32_t DCOIR_CONSTK_RSEL5; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */ 1232 __I uint32_t DCOER_FCAL_RSEL04; /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */ 1233 __I uint32_t DCOER_FCAL_RSEL5; /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */ 1234 __I uint32_t RESERVED7; /*!< Reserved */ 1235 __I uint32_t RESERVED8; /*!< Reserved */ 1236 __I uint32_t RESERVED9; /*!< Reserved */ 1237 __I uint32_t RESERVED10; /*!< Reserved */ 1238 __I uint32_t DCOER_CONSTK_RSEL04; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */ 1239 __I uint32_t DCOER_CONSTK_RSEL5; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */ 1240 __I uint32_t ADC14_CAL_TAG; /*!< ADC14 Calibration Tag */ 1241 __I uint32_t ADC14_CAL_LEN; /*!< ADC14 Calibration Length */ 1242 __I uint32_t ADC_GAIN_FACTOR; /*!< ADC Gain Factor */ 1243 __I uint32_t ADC_OFFSET; /*!< ADC Offset */ 1244 __I uint32_t RESERVED11; /*!< Reserved */ 1245 __I uint32_t RESERVED12; /*!< Reserved */ 1246 __I uint32_t RESERVED13; /*!< Reserved */ 1247 __I uint32_t RESERVED14; /*!< Reserved */ 1248 __I uint32_t RESERVED15; /*!< Reserved */ 1249 __I uint32_t RESERVED16; /*!< Reserved */ 1250 __I uint32_t RESERVED17; /*!< Reserved */ 1251 __I uint32_t RESERVED18; /*!< Reserved */ 1252 __I uint32_t RESERVED19; /*!< Reserved */ 1253 __I uint32_t RESERVED20; /*!< Reserved */ 1254 __I uint32_t RESERVED21; /*!< Reserved */ 1255 __I uint32_t RESERVED22; /*!< Reserved */ 1256 __I uint32_t RESERVED23; /*!< Reserved */ 1257 __I uint32_t RESERVED24; /*!< Reserved */ 1258 __I uint32_t RESERVED25; /*!< Reserved */ 1259 __I uint32_t RESERVED26; /*!< Reserved */ 1260 __I uint32_t ADC14_REF1P2V_TS30C; /*!< ADC14 1.2V Reference Temp. Sensor 30C */ 1261 __I uint32_t ADC14_REF1P2V_TS85C; /*!< ADC14 1.2V Reference Temp. Sensor 85C */ 1262 __I uint32_t ADC14_REF1P45V_TS30C; /*!< ADC14 1.45V Reference Temp. Sensor 30C */ 1263 __I uint32_t ADC14_REF1P45V_TS85C; /*!< ADC14 1.45V Reference Temp. Sensor 85C */ 1264 __I uint32_t ADC14_REF2P5V_TS30C; /*!< ADC14 2.5V Reference Temp. Sensor 30C */ 1265 __I uint32_t ADC14_REF2P5V_TS85C; /*!< ADC14 2.5V Reference Temp. Sensor 85C */ 1266 __I uint32_t REF_CAL_TAG; /*!< REF Calibration Tag */ 1267 __I uint32_t REF_CAL_LEN; /*!< REF Calibration Length */ 1268 __I uint32_t REF_1P2V; /*!< REF 1.2V Reference */ 1269 __I uint32_t REF_1P45V; /*!< REF 1.45V Reference */ 1270 __I uint32_t REF_2P5V; /*!< REF 2.5V Reference */ 1271 __I uint32_t FLASH_INFO_TAG; /*!< Flash Info Tag */ 1272 __I uint32_t FLASH_INFO_LEN; /*!< Flash Info Length */ 1273 __I uint32_t FLASH_MAX_PROG_PULSES; /*!< Flash Maximum Programming Pulses */ 1274 __I uint32_t FLASH_MAX_ERASE_PULSES; /*!< Flash Maximum Erase Pulses */ 1275 __I uint32_t RANDOM_NUM_TAG; /*!< 128-bit Random Number Tag */ 1276 __I uint32_t RANDOM_NUM_LEN; /*!< 128-bit Random Number Length */ 1277 __I uint32_t RANDOM_NUM_1; /*!< 32-bit Random Number 1 */ 1278 __I uint32_t RANDOM_NUM_2; /*!< 32-bit Random Number 2 */ 1279 __I uint32_t RANDOM_NUM_3; /*!< 32-bit Random Number 3 */ 1280 __I uint32_t RANDOM_NUM_4; /*!< 32-bit Random Number 4 */ 1281 __I uint32_t BSL_CFG_TAG; /*!< BSL Configuration Tag */ 1282 __I uint32_t BSL_CFG_LEN; /*!< BSL Configuration Length */ 1283 __I uint32_t BSL_PERIPHIF_SEL; /*!< BSL Peripheral Interface Selection */ 1284 __I uint32_t BSL_PORTIF_CFG_UART; /*!< BSL Port Interface Configuration for UART */ 1285 __I uint32_t BSL_PORTIF_CFG_SPI; /*!< BSL Port Interface Configuration for SPI */ 1286 __I uint32_t BSL_PORTIF_CFG_I2C; /*!< BSL Port Interface Configuration for I2C */ 1287 __I uint32_t TLV_END; /*!< TLV End Word */ 1288 } TLV_Type; 1289 1290 /*@}*/ /* end of group TLV */ 1291 1292 1293 /****************************************************************************** 1294 * WDT_A Registers 1295 ******************************************************************************/ 1296 /** @addtogroup WDT_A MSP432P401R (WDT_A) 1297 @{ 1298 */ 1299 typedef struct { 1300 uint16_t RESERVED0[6]; 1301 __IO uint16_t CTL; /*!< Watchdog Timer Control Register */ 1302 } WDT_A_Type; 1303 1304 /*@}*/ /* end of group WDT_A */ 1305 1306 1307 #if defined ( __CC_ARM ) 1308 #pragma no_anon_unions 1309 #endif 1310 1311 /*@}*/ /* end of group MSP432P401R_Peripherals */ 1312 1313 /****************************************************************************** 1314 * Peripheral declaration * 1315 ******************************************************************************/ 1316 /** @addtogroup MSP432P401R_PeripheralDecl MSP432P401R Peripheral Declaration 1317 @{ 1318 */ 1319 1320 #define ADC14 ((ADC14_Type *) ADC14_BASE) 1321 #define AES256 ((AES256_Type *) AES256_BASE) 1322 #define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE) 1323 #define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE) 1324 #define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE) 1325 #define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE) 1326 #define CRC32 ((CRC32_Type *) CRC32_BASE) 1327 #define CS ((CS_Type *) CS_BASE) 1328 #define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000)) 1329 #define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020)) 1330 #define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040)) 1331 #define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060)) 1332 #define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080)) 1333 #define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120)) 1334 #define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000)) 1335 #define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000)) 1336 #define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020)) 1337 #define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020)) 1338 #define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040)) 1339 #define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040)) 1340 #define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060)) 1341 #define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060)) 1342 #define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080)) 1343 #define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080)) 1344 #define DMA_Channel ((DMA_Channel_Type *) DMA_BASE) 1345 #define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000)) 1346 #define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE) 1347 #define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE) 1348 #define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE) 1349 #define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE) 1350 #define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE) 1351 #define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE) 1352 #define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE) 1353 #define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE) 1354 #define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE) 1355 #define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE) 1356 #define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE) 1357 #define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE) 1358 #define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE) 1359 #define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE) 1360 #define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE) 1361 #define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE) 1362 #define FLCTL ((FLCTL_Type *) FLCTL_BASE) 1363 #define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE) 1364 #define PCM ((PCM_Type *) PCM_BASE) 1365 #define PMAP ((PMAP_COMMON_Type*) PMAP_BASE) 1366 #define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008)) 1367 #define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010)) 1368 #define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018)) 1369 #define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020)) 1370 #define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028)) 1371 #define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030)) 1372 #define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038)) 1373 #define PSS ((PSS_Type *) PSS_BASE) 1374 #define REF_A ((REF_A_Type *) REF_A_BASE) 1375 #define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) 1376 #define RTC_C ((RTC_C_Type *) RTC_C_BASE) 1377 #define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE) 1378 #define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE) 1379 #define SYSCTL_Boot ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000)) 1380 #define TIMER32_1 ((Timer32_Type *) TIMER32_BASE) 1381 #define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020)) 1382 #define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE) 1383 #define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE) 1384 #define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE) 1385 #define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE) 1386 #define TLV ((TLV_Type *) TLV_BASE) 1387 #define WDT_A ((WDT_A_Type *) WDT_A_BASE) 1388 1389 1390 /*@}*/ /* end of group MSP432P401R_PeripheralDecl */ 1391 1392 /*@}*/ /* end of group MSP432P401R_Definitions */ 1393 1394 #endif /* __CMSIS_CONFIG__ */ 1395 1396 /****************************************************************************** 1397 * Peripheral register control bits * 1398 ******************************************************************************/ 1399 1400 /****************************************************************************** 1401 * ADC14 Bits 1402 ******************************************************************************/ 1403 /* ADC14_CTL0[SC] Bits */ 1404 #define ADC14_CTL0_SC_OFS ( 0) /*!< ADC14SC Bit Offset */ 1405 #define ADC14_CTL0_SC ((uint32_t)0x00000001) /*!< ADC14 start conversion */ 1406 /* ADC14_CTL0[ENC] Bits */ 1407 #define ADC14_CTL0_ENC_OFS ( 1) /*!< ADC14ENC Bit Offset */ 1408 #define ADC14_CTL0_ENC ((uint32_t)0x00000002) /*!< ADC14 enable conversion */ 1409 /* ADC14_CTL0[ON] Bits */ 1410 #define ADC14_CTL0_ON_OFS ( 4) /*!< ADC14ON Bit Offset */ 1411 #define ADC14_CTL0_ON ((uint32_t)0x00000010) /*!< ADC14 on */ 1412 /* ADC14_CTL0[MSC] Bits */ 1413 #define ADC14_CTL0_MSC_OFS ( 7) /*!< ADC14MSC Bit Offset */ 1414 #define ADC14_CTL0_MSC ((uint32_t)0x00000080) /*!< ADC14 multiple sample and conversion */ 1415 /* ADC14_CTL0[SHT0] Bits */ 1416 #define ADC14_CTL0_SHT0_OFS ( 8) /*!< ADC14SHT0 Bit Offset */ 1417 #define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /*!< ADC14SHT0 Bit Mask */ 1418 #define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /*!< SHT0 Bit 0 */ 1419 #define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /*!< SHT0 Bit 1 */ 1420 #define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /*!< SHT0 Bit 2 */ 1421 #define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /*!< SHT0 Bit 3 */ 1422 #define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /*!< 4 */ 1423 #define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /*!< 8 */ 1424 #define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /*!< 16 */ 1425 #define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /*!< 32 */ 1426 #define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /*!< 64 */ 1427 #define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /*!< 96 */ 1428 #define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /*!< 128 */ 1429 #define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /*!< 192 */ 1430 #define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /*!< 4 */ 1431 #define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /*!< 8 */ 1432 #define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /*!< 16 */ 1433 #define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /*!< 32 */ 1434 #define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /*!< 64 */ 1435 #define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /*!< 96 */ 1436 #define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /*!< 128 */ 1437 #define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /*!< 192 */ 1438 /* ADC14_CTL0[SHT1] Bits */ 1439 #define ADC14_CTL0_SHT1_OFS (12) /*!< ADC14SHT1 Bit Offset */ 1440 #define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /*!< ADC14SHT1 Bit Mask */ 1441 #define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /*!< SHT1 Bit 0 */ 1442 #define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /*!< SHT1 Bit 1 */ 1443 #define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /*!< SHT1 Bit 2 */ 1444 #define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /*!< SHT1 Bit 3 */ 1445 #define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /*!< 4 */ 1446 #define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /*!< 8 */ 1447 #define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /*!< 16 */ 1448 #define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /*!< 32 */ 1449 #define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /*!< 64 */ 1450 #define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /*!< 96 */ 1451 #define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /*!< 128 */ 1452 #define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /*!< 192 */ 1453 #define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /*!< 4 */ 1454 #define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /*!< 8 */ 1455 #define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /*!< 16 */ 1456 #define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /*!< 32 */ 1457 #define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /*!< 64 */ 1458 #define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /*!< 96 */ 1459 #define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /*!< 128 */ 1460 #define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /*!< 192 */ 1461 /* ADC14_CTL0[BUSY] Bits */ 1462 #define ADC14_CTL0_BUSY_OFS (16) /*!< ADC14BUSY Bit Offset */ 1463 #define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /*!< ADC14 busy */ 1464 /* ADC14_CTL0[CONSEQ] Bits */ 1465 #define ADC14_CTL0_CONSEQ_OFS (17) /*!< ADC14CONSEQ Bit Offset */ 1466 #define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /*!< ADC14CONSEQ Bit Mask */ 1467 #define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /*!< CONSEQ Bit 0 */ 1468 #define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /*!< CONSEQ Bit 1 */ 1469 #define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /*!< Single-channel, single-conversion */ 1470 #define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /*!< Sequence-of-channels */ 1471 #define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /*!< Repeat-single-channel */ 1472 #define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /*!< Repeat-sequence-of-channels */ 1473 /* ADC14_CTL0[SSEL] Bits */ 1474 #define ADC14_CTL0_SSEL_OFS (19) /*!< ADC14SSEL Bit Offset */ 1475 #define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /*!< ADC14SSEL Bit Mask */ 1476 #define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /*!< SSEL Bit 0 */ 1477 #define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /*!< SSEL Bit 1 */ 1478 #define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /*!< SSEL Bit 2 */ 1479 #define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /*!< MODCLK */ 1480 #define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /*!< SYSCLK */ 1481 #define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /*!< ACLK */ 1482 #define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /*!< MCLK */ 1483 #define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /*!< SMCLK */ 1484 #define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /*!< HSMCLK */ 1485 #define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /*!< MODCLK */ 1486 #define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /*!< SYSCLK */ 1487 #define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /*!< ACLK */ 1488 #define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /*!< MCLK */ 1489 #define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /*!< SMCLK */ 1490 #define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /*!< HSMCLK */ 1491 /* ADC14_CTL0[DIV] Bits */ 1492 #define ADC14_CTL0_DIV_OFS (22) /*!< ADC14DIV Bit Offset */ 1493 #define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /*!< ADC14DIV Bit Mask */ 1494 #define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /*!< DIV Bit 0 */ 1495 #define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /*!< DIV Bit 1 */ 1496 #define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /*!< DIV Bit 2 */ 1497 #define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /*!< /1 */ 1498 #define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /*!< /2 */ 1499 #define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /*!< /3 */ 1500 #define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /*!< /4 */ 1501 #define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /*!< /5 */ 1502 #define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /*!< /6 */ 1503 #define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /*!< /7 */ 1504 #define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /*!< /8 */ 1505 #define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /*!< /1 */ 1506 #define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /*!< /2 */ 1507 #define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /*!< /3 */ 1508 #define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /*!< /4 */ 1509 #define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /*!< /5 */ 1510 #define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /*!< /6 */ 1511 #define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /*!< /7 */ 1512 #define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /*!< /8 */ 1513 /* ADC14_CTL0[ISSH] Bits */ 1514 #define ADC14_CTL0_ISSH_OFS (25) /*!< ADC14ISSH Bit Offset */ 1515 #define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /*!< ADC14 invert signal sample-and-hold */ 1516 /* ADC14_CTL0[SHP] Bits */ 1517 #define ADC14_CTL0_SHP_OFS (26) /*!< ADC14SHP Bit Offset */ 1518 #define ADC14_CTL0_SHP ((uint32_t)0x04000000) /*!< ADC14 sample-and-hold pulse-mode select */ 1519 /* ADC14_CTL0[SHS] Bits */ 1520 #define ADC14_CTL0_SHS_OFS (27) /*!< ADC14SHS Bit Offset */ 1521 #define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /*!< ADC14SHS Bit Mask */ 1522 #define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /*!< SHS Bit 0 */ 1523 #define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /*!< SHS Bit 1 */ 1524 #define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /*!< SHS Bit 2 */ 1525 #define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /*!< ADC14SC bit */ 1526 #define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /*!< See device-specific data sheet for source */ 1527 #define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /*!< See device-specific data sheet for source */ 1528 #define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /*!< See device-specific data sheet for source */ 1529 #define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /*!< See device-specific data sheet for source */ 1530 #define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /*!< See device-specific data sheet for source */ 1531 #define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /*!< See device-specific data sheet for source */ 1532 #define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /*!< See device-specific data sheet for source */ 1533 /* ADC14_CTL0[PDIV] Bits */ 1534 #define ADC14_CTL0_PDIV_OFS (30) /*!< ADC14PDIV Bit Offset */ 1535 #define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /*!< ADC14PDIV Bit Mask */ 1536 #define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /*!< PDIV Bit 0 */ 1537 #define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /*!< PDIV Bit 1 */ 1538 #define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /*!< Predivide by 1 */ 1539 #define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /*!< Predivide by 4 */ 1540 #define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /*!< Predivide by 32 */ 1541 #define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ 1542 #define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /*!< Predivide by 1 */ 1543 #define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /*!< Predivide by 4 */ 1544 #define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /*!< Predivide by 32 */ 1545 #define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ 1546 /* ADC14_CTL1[PWRMD] Bits */ 1547 #define ADC14_CTL1_PWRMD_OFS ( 0) /*!< ADC14PWRMD Bit Offset */ 1548 #define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /*!< ADC14PWRMD Bit Mask */ 1549 #define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /*!< PWRMD Bit 0 */ 1550 #define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /*!< PWRMD Bit 1 */ 1551 #define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /*!< Regular power mode for use with any resolution setting. Sample rate can be */ 1552 /* up to 1 Msps. */ 1553 #define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample */ 1554 /* rate must not exceed 200 ksps. */ 1555 /* ADC14_CTL1[REFBURST] Bits */ 1556 #define ADC14_CTL1_REFBURST_OFS ( 2) /*!< ADC14REFBURST Bit Offset */ 1557 #define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /*!< ADC14 reference buffer burst */ 1558 /* ADC14_CTL1[DF] Bits */ 1559 #define ADC14_CTL1_DF_OFS ( 3) /*!< ADC14DF Bit Offset */ 1560 #define ADC14_CTL1_DF ((uint32_t)0x00000008) /*!< ADC14 data read-back format */ 1561 /* ADC14_CTL1[RES] Bits */ 1562 #define ADC14_CTL1_RES_OFS ( 4) /*!< ADC14RES Bit Offset */ 1563 #define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /*!< ADC14RES Bit Mask */ 1564 #define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /*!< RES Bit 0 */ 1565 #define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /*!< RES Bit 1 */ 1566 #define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ 1567 #define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ 1568 #define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ 1569 #define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ 1570 #define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ 1571 #define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ 1572 #define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ 1573 #define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ 1574 /* ADC14_CTL1[CSTARTADD] Bits */ 1575 #define ADC14_CTL1_CSTARTADD_OFS (16) /*!< ADC14CSTARTADD Bit Offset */ 1576 #define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /*!< ADC14CSTARTADD Bit Mask */ 1577 /* ADC14_CTL1[BATMAP] Bits */ 1578 #define ADC14_CTL1_BATMAP_OFS (22) /*!< ADC14BATMAP Bit Offset */ 1579 #define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /*!< Controls 1/2 AVCC ADC input channel selection */ 1580 /* ADC14_CTL1[TCMAP] Bits */ 1581 #define ADC14_CTL1_TCMAP_OFS (23) /*!< ADC14TCMAP Bit Offset */ 1582 #define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /*!< Controls temperature sensor ADC input channel selection */ 1583 /* ADC14_CTL1[CH0MAP] Bits */ 1584 #define ADC14_CTL1_CH0MAP_OFS (24) /*!< ADC14CH0MAP Bit Offset */ 1585 #define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */ 1586 /* ADC14_CTL1[CH1MAP] Bits */ 1587 #define ADC14_CTL1_CH1MAP_OFS (25) /*!< ADC14CH1MAP Bit Offset */ 1588 #define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */ 1589 /* ADC14_CTL1[CH2MAP] Bits */ 1590 #define ADC14_CTL1_CH2MAP_OFS (26) /*!< ADC14CH2MAP Bit Offset */ 1591 #define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */ 1592 /* ADC14_CTL1[CH3MAP] Bits */ 1593 #define ADC14_CTL1_CH3MAP_OFS (27) /*!< ADC14CH3MAP Bit Offset */ 1594 #define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */ 1595 /* ADC14_LO0[LO0] Bits */ 1596 #define ADC14_LO0_LO0_OFS ( 0) /*!< ADC14LO0 Bit Offset */ 1597 #define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO0 Bit Mask */ 1598 /* ADC14_HI0[HI0] Bits */ 1599 #define ADC14_HI0_HI0_OFS ( 0) /*!< ADC14HI0 Bit Offset */ 1600 #define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI0 Bit Mask */ 1601 /* ADC14_LO1[LO1] Bits */ 1602 #define ADC14_LO1_LO1_OFS ( 0) /*!< ADC14LO1 Bit Offset */ 1603 #define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO1 Bit Mask */ 1604 /* ADC14_HI1[HI1] Bits */ 1605 #define ADC14_HI1_HI1_OFS ( 0) /*!< ADC14HI1 Bit Offset */ 1606 #define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI1 Bit Mask */ 1607 /* ADC14_MCTLN[INCH] Bits */ 1608 #define ADC14_MCTLN_INCH_OFS ( 0) /*!< ADC14INCH Bit Offset */ 1609 #define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /*!< ADC14INCH Bit Mask */ 1610 #define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /*!< INCH Bit 0 */ 1611 #define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /*!< INCH Bit 1 */ 1612 #define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /*!< INCH Bit 2 */ 1613 #define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /*!< INCH Bit 3 */ 1614 #define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /*!< INCH Bit 4 */ 1615 #define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ 1616 #define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ 1617 #define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ 1618 #define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ 1619 #define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ 1620 #define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ 1621 #define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ 1622 #define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ 1623 #define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ 1624 #define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ 1625 #define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ 1626 #define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ 1627 #define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ 1628 #define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ 1629 #define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ 1630 #define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ 1631 #define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ 1632 #define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ 1633 #define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ 1634 #define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ 1635 #define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ 1636 #define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ 1637 #define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ 1638 #define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ 1639 #define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ 1640 #define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ 1641 #define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ 1642 #define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ 1643 #define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ 1644 #define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ 1645 #define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ 1646 #define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ 1647 /* ADC14_MCTLN[EOS] Bits */ 1648 #define ADC14_MCTLN_EOS_OFS ( 7) /*!< ADC14EOS Bit Offset */ 1649 #define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /*!< End of sequence */ 1650 /* ADC14_MCTLN[VRSEL] Bits */ 1651 #define ADC14_MCTLN_VRSEL_OFS ( 8) /*!< ADC14VRSEL Bit Offset */ 1652 #define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /*!< ADC14VRSEL Bit Mask */ 1653 #define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /*!< VRSEL Bit 0 */ 1654 #define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /*!< VRSEL Bit 1 */ 1655 #define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /*!< VRSEL Bit 2 */ 1656 #define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /*!< VRSEL Bit 3 */ 1657 #define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /*!< V(R+) = AVCC, V(R-) = AVSS */ 1658 #define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /*!< V(R+) = VREF buffered, V(R-) = AVSS */ 1659 #define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /*!< V(R+) = VeREF+, V(R-) = VeREF- */ 1660 #define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */ 1661 /* ADC14_MCTLN[DIF] Bits */ 1662 #define ADC14_MCTLN_DIF_OFS (13) /*!< ADC14DIF Bit Offset */ 1663 #define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /*!< Differential mode */ 1664 /* ADC14_MCTLN[WINC] Bits */ 1665 #define ADC14_MCTLN_WINC_OFS (14) /*!< ADC14WINC Bit Offset */ 1666 #define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /*!< Comparator window enable */ 1667 /* ADC14_MCTLN[WINCTH] Bits */ 1668 #define ADC14_MCTLN_WINCTH_OFS (15) /*!< ADC14WINCTH Bit Offset */ 1669 #define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /*!< Window comparator threshold register selection */ 1670 /* ADC14_MEMN[CONVRES] Bits */ 1671 #define ADC14_MEMN_CONVRES_OFS ( 0) /*!< Conversion_Results Bit Offset */ 1672 #define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /*!< Conversion_Results Bit Mask */ 1673 /* ADC14_IER0[IE0] Bits */ 1674 #define ADC14_IER0_IE0_OFS ( 0) /*!< ADC14IE0 Bit Offset */ 1675 #define ADC14_IER0_IE0 ((uint32_t)0x00000001) /*!< Interrupt enable */ 1676 /* ADC14_IER0[IE1] Bits */ 1677 #define ADC14_IER0_IE1_OFS ( 1) /*!< ADC14IE1 Bit Offset */ 1678 #define ADC14_IER0_IE1 ((uint32_t)0x00000002) /*!< Interrupt enable */ 1679 /* ADC14_IER0[IE2] Bits */ 1680 #define ADC14_IER0_IE2_OFS ( 2) /*!< ADC14IE2 Bit Offset */ 1681 #define ADC14_IER0_IE2 ((uint32_t)0x00000004) /*!< Interrupt enable */ 1682 /* ADC14_IER0[IE3] Bits */ 1683 #define ADC14_IER0_IE3_OFS ( 3) /*!< ADC14IE3 Bit Offset */ 1684 #define ADC14_IER0_IE3 ((uint32_t)0x00000008) /*!< Interrupt enable */ 1685 /* ADC14_IER0[IE4] Bits */ 1686 #define ADC14_IER0_IE4_OFS ( 4) /*!< ADC14IE4 Bit Offset */ 1687 #define ADC14_IER0_IE4 ((uint32_t)0x00000010) /*!< Interrupt enable */ 1688 /* ADC14_IER0[IE5] Bits */ 1689 #define ADC14_IER0_IE5_OFS ( 5) /*!< ADC14IE5 Bit Offset */ 1690 #define ADC14_IER0_IE5 ((uint32_t)0x00000020) /*!< Interrupt enable */ 1691 /* ADC14_IER0[IE6] Bits */ 1692 #define ADC14_IER0_IE6_OFS ( 6) /*!< ADC14IE6 Bit Offset */ 1693 #define ADC14_IER0_IE6 ((uint32_t)0x00000040) /*!< Interrupt enable */ 1694 /* ADC14_IER0[IE7] Bits */ 1695 #define ADC14_IER0_IE7_OFS ( 7) /*!< ADC14IE7 Bit Offset */ 1696 #define ADC14_IER0_IE7 ((uint32_t)0x00000080) /*!< Interrupt enable */ 1697 /* ADC14_IER0[IE8] Bits */ 1698 #define ADC14_IER0_IE8_OFS ( 8) /*!< ADC14IE8 Bit Offset */ 1699 #define ADC14_IER0_IE8 ((uint32_t)0x00000100) /*!< Interrupt enable */ 1700 /* ADC14_IER0[IE9] Bits */ 1701 #define ADC14_IER0_IE9_OFS ( 9) /*!< ADC14IE9 Bit Offset */ 1702 #define ADC14_IER0_IE9 ((uint32_t)0x00000200) /*!< Interrupt enable */ 1703 /* ADC14_IER0[IE10] Bits */ 1704 #define ADC14_IER0_IE10_OFS (10) /*!< ADC14IE10 Bit Offset */ 1705 #define ADC14_IER0_IE10 ((uint32_t)0x00000400) /*!< Interrupt enable */ 1706 /* ADC14_IER0[IE11] Bits */ 1707 #define ADC14_IER0_IE11_OFS (11) /*!< ADC14IE11 Bit Offset */ 1708 #define ADC14_IER0_IE11 ((uint32_t)0x00000800) /*!< Interrupt enable */ 1709 /* ADC14_IER0[IE12] Bits */ 1710 #define ADC14_IER0_IE12_OFS (12) /*!< ADC14IE12 Bit Offset */ 1711 #define ADC14_IER0_IE12 ((uint32_t)0x00001000) /*!< Interrupt enable */ 1712 /* ADC14_IER0[IE13] Bits */ 1713 #define ADC14_IER0_IE13_OFS (13) /*!< ADC14IE13 Bit Offset */ 1714 #define ADC14_IER0_IE13 ((uint32_t)0x00002000) /*!< Interrupt enable */ 1715 /* ADC14_IER0[IE14] Bits */ 1716 #define ADC14_IER0_IE14_OFS (14) /*!< ADC14IE14 Bit Offset */ 1717 #define ADC14_IER0_IE14 ((uint32_t)0x00004000) /*!< Interrupt enable */ 1718 /* ADC14_IER0[IE15] Bits */ 1719 #define ADC14_IER0_IE15_OFS (15) /*!< ADC14IE15 Bit Offset */ 1720 #define ADC14_IER0_IE15 ((uint32_t)0x00008000) /*!< Interrupt enable */ 1721 /* ADC14_IER0[IE16] Bits */ 1722 #define ADC14_IER0_IE16_OFS (16) /*!< ADC14IE16 Bit Offset */ 1723 #define ADC14_IER0_IE16 ((uint32_t)0x00010000) /*!< Interrupt enable */ 1724 /* ADC14_IER0[IE17] Bits */ 1725 #define ADC14_IER0_IE17_OFS (17) /*!< ADC14IE17 Bit Offset */ 1726 #define ADC14_IER0_IE17 ((uint32_t)0x00020000) /*!< Interrupt enable */ 1727 /* ADC14_IER0[IE19] Bits */ 1728 #define ADC14_IER0_IE19_OFS (19) /*!< ADC14IE19 Bit Offset */ 1729 #define ADC14_IER0_IE19 ((uint32_t)0x00080000) /*!< Interrupt enable */ 1730 /* ADC14_IER0[IE18] Bits */ 1731 #define ADC14_IER0_IE18_OFS (18) /*!< ADC14IE18 Bit Offset */ 1732 #define ADC14_IER0_IE18 ((uint32_t)0x00040000) /*!< Interrupt enable */ 1733 /* ADC14_IER0[IE20] Bits */ 1734 #define ADC14_IER0_IE20_OFS (20) /*!< ADC14IE20 Bit Offset */ 1735 #define ADC14_IER0_IE20 ((uint32_t)0x00100000) /*!< Interrupt enable */ 1736 /* ADC14_IER0[IE21] Bits */ 1737 #define ADC14_IER0_IE21_OFS (21) /*!< ADC14IE21 Bit Offset */ 1738 #define ADC14_IER0_IE21 ((uint32_t)0x00200000) /*!< Interrupt enable */ 1739 /* ADC14_IER0[IE22] Bits */ 1740 #define ADC14_IER0_IE22_OFS (22) /*!< ADC14IE22 Bit Offset */ 1741 #define ADC14_IER0_IE22 ((uint32_t)0x00400000) /*!< Interrupt enable */ 1742 /* ADC14_IER0[IE23] Bits */ 1743 #define ADC14_IER0_IE23_OFS (23) /*!< ADC14IE23 Bit Offset */ 1744 #define ADC14_IER0_IE23 ((uint32_t)0x00800000) /*!< Interrupt enable */ 1745 /* ADC14_IER0[IE24] Bits */ 1746 #define ADC14_IER0_IE24_OFS (24) /*!< ADC14IE24 Bit Offset */ 1747 #define ADC14_IER0_IE24 ((uint32_t)0x01000000) /*!< Interrupt enable */ 1748 /* ADC14_IER0[IE25] Bits */ 1749 #define ADC14_IER0_IE25_OFS (25) /*!< ADC14IE25 Bit Offset */ 1750 #define ADC14_IER0_IE25 ((uint32_t)0x02000000) /*!< Interrupt enable */ 1751 /* ADC14_IER0[IE26] Bits */ 1752 #define ADC14_IER0_IE26_OFS (26) /*!< ADC14IE26 Bit Offset */ 1753 #define ADC14_IER0_IE26 ((uint32_t)0x04000000) /*!< Interrupt enable */ 1754 /* ADC14_IER0[IE27] Bits */ 1755 #define ADC14_IER0_IE27_OFS (27) /*!< ADC14IE27 Bit Offset */ 1756 #define ADC14_IER0_IE27 ((uint32_t)0x08000000) /*!< Interrupt enable */ 1757 /* ADC14_IER0[IE28] Bits */ 1758 #define ADC14_IER0_IE28_OFS (28) /*!< ADC14IE28 Bit Offset */ 1759 #define ADC14_IER0_IE28 ((uint32_t)0x10000000) /*!< Interrupt enable */ 1760 /* ADC14_IER0[IE29] Bits */ 1761 #define ADC14_IER0_IE29_OFS (29) /*!< ADC14IE29 Bit Offset */ 1762 #define ADC14_IER0_IE29 ((uint32_t)0x20000000) /*!< Interrupt enable */ 1763 /* ADC14_IER0[IE30] Bits */ 1764 #define ADC14_IER0_IE30_OFS (30) /*!< ADC14IE30 Bit Offset */ 1765 #define ADC14_IER0_IE30 ((uint32_t)0x40000000) /*!< Interrupt enable */ 1766 /* ADC14_IER0[IE31] Bits */ 1767 #define ADC14_IER0_IE31_OFS (31) /*!< ADC14IE31 Bit Offset */ 1768 #define ADC14_IER0_IE31 ((uint32_t)0x80000000) /*!< Interrupt enable */ 1769 /* ADC14_IER1[INIE] Bits */ 1770 #define ADC14_IER1_INIE_OFS ( 1) /*!< ADC14INIE Bit Offset */ 1771 #define ADC14_IER1_INIE ((uint32_t)0x00000002) /*!< Interrupt enable for ADC14MEMx within comparator window */ 1772 /* ADC14_IER1[LOIE] Bits */ 1773 #define ADC14_IER1_LOIE_OFS ( 2) /*!< ADC14LOIE Bit Offset */ 1774 #define ADC14_IER1_LOIE ((uint32_t)0x00000004) /*!< Interrupt enable for ADC14MEMx below comparator window */ 1775 /* ADC14_IER1[HIIE] Bits */ 1776 #define ADC14_IER1_HIIE_OFS ( 3) /*!< ADC14HIIE Bit Offset */ 1777 #define ADC14_IER1_HIIE ((uint32_t)0x00000008) /*!< Interrupt enable for ADC14MEMx above comparator window */ 1778 /* ADC14_IER1[OVIE] Bits */ 1779 #define ADC14_IER1_OVIE_OFS ( 4) /*!< ADC14OVIE Bit Offset */ 1780 #define ADC14_IER1_OVIE ((uint32_t)0x00000010) /*!< ADC14MEMx overflow-interrupt enable */ 1781 /* ADC14_IER1[TOVIE] Bits */ 1782 #define ADC14_IER1_TOVIE_OFS ( 5) /*!< ADC14TOVIE Bit Offset */ 1783 #define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /*!< ADC14 conversion-time-overflow interrupt enable */ 1784 /* ADC14_IER1[RDYIE] Bits */ 1785 #define ADC14_IER1_RDYIE_OFS ( 6) /*!< ADC14RDYIE Bit Offset */ 1786 #define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt enable */ 1787 /* ADC14_IFGR0[IFG0] Bits */ 1788 #define ADC14_IFGR0_IFG0_OFS ( 0) /*!< ADC14IFG0 Bit Offset */ 1789 #define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /*!< ADC14MEM0 interrupt flag */ 1790 /* ADC14_IFGR0[IFG1] Bits */ 1791 #define ADC14_IFGR0_IFG1_OFS ( 1) /*!< ADC14IFG1 Bit Offset */ 1792 #define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /*!< ADC14MEM1 interrupt flag */ 1793 /* ADC14_IFGR0[IFG2] Bits */ 1794 #define ADC14_IFGR0_IFG2_OFS ( 2) /*!< ADC14IFG2 Bit Offset */ 1795 #define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /*!< ADC14MEM2 interrupt flag */ 1796 /* ADC14_IFGR0[IFG3] Bits */ 1797 #define ADC14_IFGR0_IFG3_OFS ( 3) /*!< ADC14IFG3 Bit Offset */ 1798 #define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /*!< ADC14MEM3 interrupt flag */ 1799 /* ADC14_IFGR0[IFG4] Bits */ 1800 #define ADC14_IFGR0_IFG4_OFS ( 4) /*!< ADC14IFG4 Bit Offset */ 1801 #define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /*!< ADC14MEM4 interrupt flag */ 1802 /* ADC14_IFGR0[IFG5] Bits */ 1803 #define ADC14_IFGR0_IFG5_OFS ( 5) /*!< ADC14IFG5 Bit Offset */ 1804 #define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /*!< ADC14MEM5 interrupt flag */ 1805 /* ADC14_IFGR0[IFG6] Bits */ 1806 #define ADC14_IFGR0_IFG6_OFS ( 6) /*!< ADC14IFG6 Bit Offset */ 1807 #define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /*!< ADC14MEM6 interrupt flag */ 1808 /* ADC14_IFGR0[IFG7] Bits */ 1809 #define ADC14_IFGR0_IFG7_OFS ( 7) /*!< ADC14IFG7 Bit Offset */ 1810 #define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /*!< ADC14MEM7 interrupt flag */ 1811 /* ADC14_IFGR0[IFG8] Bits */ 1812 #define ADC14_IFGR0_IFG8_OFS ( 8) /*!< ADC14IFG8 Bit Offset */ 1813 #define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /*!< ADC14MEM8 interrupt flag */ 1814 /* ADC14_IFGR0[IFG9] Bits */ 1815 #define ADC14_IFGR0_IFG9_OFS ( 9) /*!< ADC14IFG9 Bit Offset */ 1816 #define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /*!< ADC14MEM9 interrupt flag */ 1817 /* ADC14_IFGR0[IFG10] Bits */ 1818 #define ADC14_IFGR0_IFG10_OFS (10) /*!< ADC14IFG10 Bit Offset */ 1819 #define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /*!< ADC14MEM10 interrupt flag */ 1820 /* ADC14_IFGR0[IFG11] Bits */ 1821 #define ADC14_IFGR0_IFG11_OFS (11) /*!< ADC14IFG11 Bit Offset */ 1822 #define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /*!< ADC14MEM11 interrupt flag */ 1823 /* ADC14_IFGR0[IFG12] Bits */ 1824 #define ADC14_IFGR0_IFG12_OFS (12) /*!< ADC14IFG12 Bit Offset */ 1825 #define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /*!< ADC14MEM12 interrupt flag */ 1826 /* ADC14_IFGR0[IFG13] Bits */ 1827 #define ADC14_IFGR0_IFG13_OFS (13) /*!< ADC14IFG13 Bit Offset */ 1828 #define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /*!< ADC14MEM13 interrupt flag */ 1829 /* ADC14_IFGR0[IFG14] Bits */ 1830 #define ADC14_IFGR0_IFG14_OFS (14) /*!< ADC14IFG14 Bit Offset */ 1831 #define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /*!< ADC14MEM14 interrupt flag */ 1832 /* ADC14_IFGR0[IFG15] Bits */ 1833 #define ADC14_IFGR0_IFG15_OFS (15) /*!< ADC14IFG15 Bit Offset */ 1834 #define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /*!< ADC14MEM15 interrupt flag */ 1835 /* ADC14_IFGR0[IFG16] Bits */ 1836 #define ADC14_IFGR0_IFG16_OFS (16) /*!< ADC14IFG16 Bit Offset */ 1837 #define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /*!< ADC14MEM16 interrupt flag */ 1838 /* ADC14_IFGR0[IFG17] Bits */ 1839 #define ADC14_IFGR0_IFG17_OFS (17) /*!< ADC14IFG17 Bit Offset */ 1840 #define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /*!< ADC14MEM17 interrupt flag */ 1841 /* ADC14_IFGR0[IFG18] Bits */ 1842 #define ADC14_IFGR0_IFG18_OFS (18) /*!< ADC14IFG18 Bit Offset */ 1843 #define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /*!< ADC14MEM18 interrupt flag */ 1844 /* ADC14_IFGR0[IFG19] Bits */ 1845 #define ADC14_IFGR0_IFG19_OFS (19) /*!< ADC14IFG19 Bit Offset */ 1846 #define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /*!< ADC14MEM19 interrupt flag */ 1847 /* ADC14_IFGR0[IFG20] Bits */ 1848 #define ADC14_IFGR0_IFG20_OFS (20) /*!< ADC14IFG20 Bit Offset */ 1849 #define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /*!< ADC14MEM20 interrupt flag */ 1850 /* ADC14_IFGR0[IFG21] Bits */ 1851 #define ADC14_IFGR0_IFG21_OFS (21) /*!< ADC14IFG21 Bit Offset */ 1852 #define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /*!< ADC14MEM21 interrupt flag */ 1853 /* ADC14_IFGR0[IFG22] Bits */ 1854 #define ADC14_IFGR0_IFG22_OFS (22) /*!< ADC14IFG22 Bit Offset */ 1855 #define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /*!< ADC14MEM22 interrupt flag */ 1856 /* ADC14_IFGR0[IFG23] Bits */ 1857 #define ADC14_IFGR0_IFG23_OFS (23) /*!< ADC14IFG23 Bit Offset */ 1858 #define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /*!< ADC14MEM23 interrupt flag */ 1859 /* ADC14_IFGR0[IFG24] Bits */ 1860 #define ADC14_IFGR0_IFG24_OFS (24) /*!< ADC14IFG24 Bit Offset */ 1861 #define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /*!< ADC14MEM24 interrupt flag */ 1862 /* ADC14_IFGR0[IFG25] Bits */ 1863 #define ADC14_IFGR0_IFG25_OFS (25) /*!< ADC14IFG25 Bit Offset */ 1864 #define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /*!< ADC14MEM25 interrupt flag */ 1865 /* ADC14_IFGR0[IFG26] Bits */ 1866 #define ADC14_IFGR0_IFG26_OFS (26) /*!< ADC14IFG26 Bit Offset */ 1867 #define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /*!< ADC14MEM26 interrupt flag */ 1868 /* ADC14_IFGR0[IFG27] Bits */ 1869 #define ADC14_IFGR0_IFG27_OFS (27) /*!< ADC14IFG27 Bit Offset */ 1870 #define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /*!< ADC14MEM27 interrupt flag */ 1871 /* ADC14_IFGR0[IFG28] Bits */ 1872 #define ADC14_IFGR0_IFG28_OFS (28) /*!< ADC14IFG28 Bit Offset */ 1873 #define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /*!< ADC14MEM28 interrupt flag */ 1874 /* ADC14_IFGR0[IFG29] Bits */ 1875 #define ADC14_IFGR0_IFG29_OFS (29) /*!< ADC14IFG29 Bit Offset */ 1876 #define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /*!< ADC14MEM29 interrupt flag */ 1877 /* ADC14_IFGR0[IFG30] Bits */ 1878 #define ADC14_IFGR0_IFG30_OFS (30) /*!< ADC14IFG30 Bit Offset */ 1879 #define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /*!< ADC14MEM30 interrupt flag */ 1880 /* ADC14_IFGR0[IFG31] Bits */ 1881 #define ADC14_IFGR0_IFG31_OFS (31) /*!< ADC14IFG31 Bit Offset */ 1882 #define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /*!< ADC14MEM31 interrupt flag */ 1883 /* ADC14_IFGR1[INIFG] Bits */ 1884 #define ADC14_IFGR1_INIFG_OFS ( 1) /*!< ADC14INIFG Bit Offset */ 1885 #define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /*!< Interrupt flag for ADC14MEMx within comparator window */ 1886 /* ADC14_IFGR1[LOIFG] Bits */ 1887 #define ADC14_IFGR1_LOIFG_OFS ( 2) /*!< ADC14LOIFG Bit Offset */ 1888 #define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /*!< Interrupt flag for ADC14MEMx below comparator window */ 1889 /* ADC14_IFGR1[HIIFG] Bits */ 1890 #define ADC14_IFGR1_HIIFG_OFS ( 3) /*!< ADC14HIIFG Bit Offset */ 1891 #define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /*!< Interrupt flag for ADC14MEMx above comparator window */ 1892 /* ADC14_IFGR1[OVIFG] Bits */ 1893 #define ADC14_IFGR1_OVIFG_OFS ( 4) /*!< ADC14OVIFG Bit Offset */ 1894 #define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /*!< ADC14MEMx overflow interrupt flag */ 1895 /* ADC14_IFGR1[TOVIFG] Bits */ 1896 #define ADC14_IFGR1_TOVIFG_OFS ( 5) /*!< ADC14TOVIFG Bit Offset */ 1897 #define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /*!< ADC14 conversion time overflow interrupt flag */ 1898 /* ADC14_IFGR1[RDYIFG] Bits */ 1899 #define ADC14_IFGR1_RDYIFG_OFS ( 6) /*!< ADC14RDYIFG Bit Offset */ 1900 #define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt flag */ 1901 /* ADC14_CLRIFGR0[CLRIFG0] Bits */ 1902 #define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /*!< CLRADC14IFG0 Bit Offset */ 1903 #define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /*!< clear ADC14IFG0 */ 1904 /* ADC14_CLRIFGR0[CLRIFG1] Bits */ 1905 #define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /*!< CLRADC14IFG1 Bit Offset */ 1906 #define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /*!< clear ADC14IFG1 */ 1907 /* ADC14_CLRIFGR0[CLRIFG2] Bits */ 1908 #define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /*!< CLRADC14IFG2 Bit Offset */ 1909 #define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /*!< clear ADC14IFG2 */ 1910 /* ADC14_CLRIFGR0[CLRIFG3] Bits */ 1911 #define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /*!< CLRADC14IFG3 Bit Offset */ 1912 #define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /*!< clear ADC14IFG3 */ 1913 /* ADC14_CLRIFGR0[CLRIFG4] Bits */ 1914 #define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /*!< CLRADC14IFG4 Bit Offset */ 1915 #define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /*!< clear ADC14IFG4 */ 1916 /* ADC14_CLRIFGR0[CLRIFG5] Bits */ 1917 #define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /*!< CLRADC14IFG5 Bit Offset */ 1918 #define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /*!< clear ADC14IFG5 */ 1919 /* ADC14_CLRIFGR0[CLRIFG6] Bits */ 1920 #define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /*!< CLRADC14IFG6 Bit Offset */ 1921 #define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /*!< clear ADC14IFG6 */ 1922 /* ADC14_CLRIFGR0[CLRIFG7] Bits */ 1923 #define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /*!< CLRADC14IFG7 Bit Offset */ 1924 #define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /*!< clear ADC14IFG7 */ 1925 /* ADC14_CLRIFGR0[CLRIFG8] Bits */ 1926 #define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /*!< CLRADC14IFG8 Bit Offset */ 1927 #define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /*!< clear ADC14IFG8 */ 1928 /* ADC14_CLRIFGR0[CLRIFG9] Bits */ 1929 #define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /*!< CLRADC14IFG9 Bit Offset */ 1930 #define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /*!< clear ADC14IFG9 */ 1931 /* ADC14_CLRIFGR0[CLRIFG10] Bits */ 1932 #define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /*!< CLRADC14IFG10 Bit Offset */ 1933 #define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /*!< clear ADC14IFG10 */ 1934 /* ADC14_CLRIFGR0[CLRIFG11] Bits */ 1935 #define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /*!< CLRADC14IFG11 Bit Offset */ 1936 #define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /*!< clear ADC14IFG11 */ 1937 /* ADC14_CLRIFGR0[CLRIFG12] Bits */ 1938 #define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /*!< CLRADC14IFG12 Bit Offset */ 1939 #define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /*!< clear ADC14IFG12 */ 1940 /* ADC14_CLRIFGR0[CLRIFG13] Bits */ 1941 #define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /*!< CLRADC14IFG13 Bit Offset */ 1942 #define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /*!< clear ADC14IFG13 */ 1943 /* ADC14_CLRIFGR0[CLRIFG14] Bits */ 1944 #define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /*!< CLRADC14IFG14 Bit Offset */ 1945 #define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /*!< clear ADC14IFG14 */ 1946 /* ADC14_CLRIFGR0[CLRIFG15] Bits */ 1947 #define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /*!< CLRADC14IFG15 Bit Offset */ 1948 #define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /*!< clear ADC14IFG15 */ 1949 /* ADC14_CLRIFGR0[CLRIFG16] Bits */ 1950 #define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /*!< CLRADC14IFG16 Bit Offset */ 1951 #define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /*!< clear ADC14IFG16 */ 1952 /* ADC14_CLRIFGR0[CLRIFG17] Bits */ 1953 #define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /*!< CLRADC14IFG17 Bit Offset */ 1954 #define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /*!< clear ADC14IFG17 */ 1955 /* ADC14_CLRIFGR0[CLRIFG18] Bits */ 1956 #define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /*!< CLRADC14IFG18 Bit Offset */ 1957 #define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /*!< clear ADC14IFG18 */ 1958 /* ADC14_CLRIFGR0[CLRIFG19] Bits */ 1959 #define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /*!< CLRADC14IFG19 Bit Offset */ 1960 #define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /*!< clear ADC14IFG19 */ 1961 /* ADC14_CLRIFGR0[CLRIFG20] Bits */ 1962 #define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /*!< CLRADC14IFG20 Bit Offset */ 1963 #define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /*!< clear ADC14IFG20 */ 1964 /* ADC14_CLRIFGR0[CLRIFG21] Bits */ 1965 #define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /*!< CLRADC14IFG21 Bit Offset */ 1966 #define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /*!< clear ADC14IFG21 */ 1967 /* ADC14_CLRIFGR0[CLRIFG22] Bits */ 1968 #define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /*!< CLRADC14IFG22 Bit Offset */ 1969 #define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /*!< clear ADC14IFG22 */ 1970 /* ADC14_CLRIFGR0[CLRIFG23] Bits */ 1971 #define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /*!< CLRADC14IFG23 Bit Offset */ 1972 #define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /*!< clear ADC14IFG23 */ 1973 /* ADC14_CLRIFGR0[CLRIFG24] Bits */ 1974 #define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /*!< CLRADC14IFG24 Bit Offset */ 1975 #define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /*!< clear ADC14IFG24 */ 1976 /* ADC14_CLRIFGR0[CLRIFG25] Bits */ 1977 #define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /*!< CLRADC14IFG25 Bit Offset */ 1978 #define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /*!< clear ADC14IFG25 */ 1979 /* ADC14_CLRIFGR0[CLRIFG26] Bits */ 1980 #define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /*!< CLRADC14IFG26 Bit Offset */ 1981 #define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /*!< clear ADC14IFG26 */ 1982 /* ADC14_CLRIFGR0[CLRIFG27] Bits */ 1983 #define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /*!< CLRADC14IFG27 Bit Offset */ 1984 #define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /*!< clear ADC14IFG27 */ 1985 /* ADC14_CLRIFGR0[CLRIFG28] Bits */ 1986 #define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /*!< CLRADC14IFG28 Bit Offset */ 1987 #define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /*!< clear ADC14IFG28 */ 1988 /* ADC14_CLRIFGR0[CLRIFG29] Bits */ 1989 #define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /*!< CLRADC14IFG29 Bit Offset */ 1990 #define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /*!< clear ADC14IFG29 */ 1991 /* ADC14_CLRIFGR0[CLRIFG30] Bits */ 1992 #define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /*!< CLRADC14IFG30 Bit Offset */ 1993 #define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /*!< clear ADC14IFG30 */ 1994 /* ADC14_CLRIFGR0[CLRIFG31] Bits */ 1995 #define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /*!< CLRADC14IFG31 Bit Offset */ 1996 #define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /*!< clear ADC14IFG31 */ 1997 /* ADC14_CLRIFGR1[CLRINIFG] Bits */ 1998 #define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /*!< CLRADC14INIFG Bit Offset */ 1999 #define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /*!< clear ADC14INIFG */ 2000 /* ADC14_CLRIFGR1[CLRLOIFG] Bits */ 2001 #define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /*!< CLRADC14LOIFG Bit Offset */ 2002 #define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /*!< clear ADC14LOIFG */ 2003 /* ADC14_CLRIFGR1[CLRHIIFG] Bits */ 2004 #define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /*!< CLRADC14HIIFG Bit Offset */ 2005 #define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /*!< clear ADC14HIIFG */ 2006 /* ADC14_CLRIFGR1[CLROVIFG] Bits */ 2007 #define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /*!< CLRADC14OVIFG Bit Offset */ 2008 #define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /*!< clear ADC14OVIFG */ 2009 /* ADC14_CLRIFGR1[CLRTOVIFG] Bits */ 2010 #define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /*!< CLRADC14TOVIFG Bit Offset */ 2011 #define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /*!< clear ADC14TOVIFG */ 2012 /* ADC14_CLRIFGR1[CLRRDYIFG] Bits */ 2013 #define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /*!< CLRADC14RDYIFG Bit Offset */ 2014 #define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /*!< clear ADC14RDYIFG */ 2015 2016 /****************************************************************************** 2017 * AES256 Bits 2018 ******************************************************************************/ 2019 /* AES256_CTL0[OP] Bits */ 2020 #define AES256_CTL0_OP_OFS ( 0) /*!< AESOPx Bit Offset */ 2021 #define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /*!< AESOPx Bit Mask */ 2022 #define AES256_CTL0_OP0 ((uint16_t)0x0001) /*!< OP Bit 0 */ 2023 #define AES256_CTL0_OP1 ((uint16_t)0x0002) /*!< OP Bit 1 */ 2024 #define AES256_CTL0_OP_0 ((uint16_t)0x0000) /*!< Encryption */ 2025 #define AES256_CTL0_OP_1 ((uint16_t)0x0001) /*!< Decryption. The provided key is the same key used for encryption */ 2026 #define AES256_CTL0_OP_2 ((uint16_t)0x0002) /*!< Generate first round key required for decryption */ 2027 #define AES256_CTL0_OP_3 ((uint16_t)0x0003) /*!< Decryption. The provided key is the first round key required for decryption */ 2028 /* AES256_CTL0[KL] Bits */ 2029 #define AES256_CTL0_KL_OFS ( 2) /*!< AESKLx Bit Offset */ 2030 #define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /*!< AESKLx Bit Mask */ 2031 #define AES256_CTL0_KL0 ((uint16_t)0x0004) /*!< KL Bit 0 */ 2032 #define AES256_CTL0_KL1 ((uint16_t)0x0008) /*!< KL Bit 1 */ 2033 #define AES256_CTL0_KL_0 ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ 2034 #define AES256_CTL0_KL_1 ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ 2035 #define AES256_CTL0_KL_2 ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ 2036 #define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ 2037 #define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ 2038 #define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ 2039 /* AES256_CTL0[CM] Bits */ 2040 #define AES256_CTL0_CM_OFS ( 5) /*!< AESCMx Bit Offset */ 2041 #define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /*!< AESCMx Bit Mask */ 2042 #define AES256_CTL0_CM0 ((uint16_t)0x0020) /*!< CM Bit 0 */ 2043 #define AES256_CTL0_CM1 ((uint16_t)0x0040) /*!< CM Bit 1 */ 2044 #define AES256_CTL0_CM_0 ((uint16_t)0x0000) /*!< ECB */ 2045 #define AES256_CTL0_CM_1 ((uint16_t)0x0020) /*!< CBC */ 2046 #define AES256_CTL0_CM_2 ((uint16_t)0x0040) /*!< OFB */ 2047 #define AES256_CTL0_CM_3 ((uint16_t)0x0060) /*!< CFB */ 2048 #define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /*!< ECB */ 2049 #define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /*!< CBC */ 2050 #define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /*!< OFB */ 2051 #define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /*!< CFB */ 2052 /* AES256_CTL0[SWRST] Bits */ 2053 #define AES256_CTL0_SWRST_OFS ( 7) /*!< AESSWRST Bit Offset */ 2054 #define AES256_CTL0_SWRST ((uint16_t)0x0080) /*!< AES software reset */ 2055 /* AES256_CTL0[RDYIFG] Bits */ 2056 #define AES256_CTL0_RDYIFG_OFS ( 8) /*!< AESRDYIFG Bit Offset */ 2057 #define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /*!< AES ready interrupt flag */ 2058 /* AES256_CTL0[ERRFG] Bits */ 2059 #define AES256_CTL0_ERRFG_OFS (11) /*!< AESERRFG Bit Offset */ 2060 #define AES256_CTL0_ERRFG ((uint16_t)0x0800) /*!< AES error flag */ 2061 /* AES256_CTL0[RDYIE] Bits */ 2062 #define AES256_CTL0_RDYIE_OFS (12) /*!< AESRDYIE Bit Offset */ 2063 #define AES256_CTL0_RDYIE ((uint16_t)0x1000) /*!< AES ready interrupt enable */ 2064 /* AES256_CTL0[CMEN] Bits */ 2065 #define AES256_CTL0_CMEN_OFS (15) /*!< AESCMEN Bit Offset */ 2066 #define AES256_CTL0_CMEN ((uint16_t)0x8000) /*!< AES cipher mode enable */ 2067 /* AES256_CTL1[BLKCNT] Bits */ 2068 #define AES256_CTL1_BLKCNT_OFS ( 0) /*!< AESBLKCNTx Bit Offset */ 2069 #define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /*!< AESBLKCNTx Bit Mask */ 2070 #define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /*!< BLKCNT Bit 0 */ 2071 #define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /*!< BLKCNT Bit 1 */ 2072 #define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /*!< BLKCNT Bit 2 */ 2073 #define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /*!< BLKCNT Bit 3 */ 2074 #define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /*!< BLKCNT Bit 4 */ 2075 #define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /*!< BLKCNT Bit 5 */ 2076 #define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /*!< BLKCNT Bit 6 */ 2077 #define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /*!< BLKCNT Bit 7 */ 2078 /* AES256_STAT[BUSY] Bits */ 2079 #define AES256_STAT_BUSY_OFS ( 0) /*!< AESBUSY Bit Offset */ 2080 #define AES256_STAT_BUSY ((uint16_t)0x0001) /*!< AES accelerator module busy */ 2081 /* AES256_STAT[KEYWR] Bits */ 2082 #define AES256_STAT_KEYWR_OFS ( 1) /*!< AESKEYWR Bit Offset */ 2083 #define AES256_STAT_KEYWR ((uint16_t)0x0002) /*!< All 16 bytes written to AESAKEY */ 2084 /* AES256_STAT[DINWR] Bits */ 2085 #define AES256_STAT_DINWR_OFS ( 2) /*!< AESDINWR Bit Offset */ 2086 #define AES256_STAT_DINWR ((uint16_t)0x0004) /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ 2087 /* AES256_STAT[DOUTRD] Bits */ 2088 #define AES256_STAT_DOUTRD_OFS ( 3) /*!< AESDOUTRD Bit Offset */ 2089 #define AES256_STAT_DOUTRD ((uint16_t)0x0008) /*!< All 16 bytes read from AESADOUT */ 2090 /* AES256_STAT[KEYCNT] Bits */ 2091 #define AES256_STAT_KEYCNT_OFS ( 4) /*!< AESKEYCNTx Bit Offset */ 2092 #define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /*!< AESKEYCNTx Bit Mask */ 2093 #define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /*!< KEYCNT Bit 0 */ 2094 #define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /*!< KEYCNT Bit 1 */ 2095 #define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /*!< KEYCNT Bit 2 */ 2096 #define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /*!< KEYCNT Bit 3 */ 2097 /* AES256_STAT[DINCNT] Bits */ 2098 #define AES256_STAT_DINCNT_OFS ( 8) /*!< AESDINCNTx Bit Offset */ 2099 #define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /*!< AESDINCNTx Bit Mask */ 2100 #define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /*!< DINCNT Bit 0 */ 2101 #define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /*!< DINCNT Bit 1 */ 2102 #define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /*!< DINCNT Bit 2 */ 2103 #define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /*!< DINCNT Bit 3 */ 2104 /* AES256_STAT[DOUTCNT] Bits */ 2105 #define AES256_STAT_DOUTCNT_OFS (12) /*!< AESDOUTCNTx Bit Offset */ 2106 #define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /*!< AESDOUTCNTx Bit Mask */ 2107 #define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /*!< DOUTCNT Bit 0 */ 2108 #define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /*!< DOUTCNT Bit 1 */ 2109 #define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /*!< DOUTCNT Bit 2 */ 2110 #define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /*!< DOUTCNT Bit 3 */ 2111 /* AES256_KEY[KEY0] Bits */ 2112 #define AES256_KEY_KEY0_OFS ( 0) /*!< AESKEY0x Bit Offset */ 2113 #define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /*!< AESKEY0x Bit Mask */ 2114 #define AES256_KEY_KEY00 ((uint16_t)0x0001) /*!< KEY0 Bit 0 */ 2115 #define AES256_KEY_KEY01 ((uint16_t)0x0002) /*!< KEY0 Bit 1 */ 2116 #define AES256_KEY_KEY02 ((uint16_t)0x0004) /*!< KEY0 Bit 2 */ 2117 #define AES256_KEY_KEY03 ((uint16_t)0x0008) /*!< KEY0 Bit 3 */ 2118 #define AES256_KEY_KEY04 ((uint16_t)0x0010) /*!< KEY0 Bit 4 */ 2119 #define AES256_KEY_KEY05 ((uint16_t)0x0020) /*!< KEY0 Bit 5 */ 2120 #define AES256_KEY_KEY06 ((uint16_t)0x0040) /*!< KEY0 Bit 6 */ 2121 #define AES256_KEY_KEY07 ((uint16_t)0x0080) /*!< KEY0 Bit 7 */ 2122 /* AES256_KEY[KEY1] Bits */ 2123 #define AES256_KEY_KEY1_OFS ( 8) /*!< AESKEY1x Bit Offset */ 2124 #define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /*!< AESKEY1x Bit Mask */ 2125 #define AES256_KEY_KEY10 ((uint16_t)0x0100) /*!< KEY1 Bit 0 */ 2126 #define AES256_KEY_KEY11 ((uint16_t)0x0200) /*!< KEY1 Bit 1 */ 2127 #define AES256_KEY_KEY12 ((uint16_t)0x0400) /*!< KEY1 Bit 2 */ 2128 #define AES256_KEY_KEY13 ((uint16_t)0x0800) /*!< KEY1 Bit 3 */ 2129 #define AES256_KEY_KEY14 ((uint16_t)0x1000) /*!< KEY1 Bit 4 */ 2130 #define AES256_KEY_KEY15 ((uint16_t)0x2000) /*!< KEY1 Bit 5 */ 2131 #define AES256_KEY_KEY16 ((uint16_t)0x4000) /*!< KEY1 Bit 6 */ 2132 #define AES256_KEY_KEY17 ((uint16_t)0x8000) /*!< KEY1 Bit 7 */ 2133 /* AES256_DIN[DIN0] Bits */ 2134 #define AES256_DIN_DIN0_OFS ( 0) /*!< AESDIN0x Bit Offset */ 2135 #define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /*!< AESDIN0x Bit Mask */ 2136 #define AES256_DIN_DIN00 ((uint16_t)0x0001) /*!< DIN0 Bit 0 */ 2137 #define AES256_DIN_DIN01 ((uint16_t)0x0002) /*!< DIN0 Bit 1 */ 2138 #define AES256_DIN_DIN02 ((uint16_t)0x0004) /*!< DIN0 Bit 2 */ 2139 #define AES256_DIN_DIN03 ((uint16_t)0x0008) /*!< DIN0 Bit 3 */ 2140 #define AES256_DIN_DIN04 ((uint16_t)0x0010) /*!< DIN0 Bit 4 */ 2141 #define AES256_DIN_DIN05 ((uint16_t)0x0020) /*!< DIN0 Bit 5 */ 2142 #define AES256_DIN_DIN06 ((uint16_t)0x0040) /*!< DIN0 Bit 6 */ 2143 #define AES256_DIN_DIN07 ((uint16_t)0x0080) /*!< DIN0 Bit 7 */ 2144 /* AES256_DIN[DIN1] Bits */ 2145 #define AES256_DIN_DIN1_OFS ( 8) /*!< AESDIN1x Bit Offset */ 2146 #define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /*!< AESDIN1x Bit Mask */ 2147 #define AES256_DIN_DIN10 ((uint16_t)0x0100) /*!< DIN1 Bit 0 */ 2148 #define AES256_DIN_DIN11 ((uint16_t)0x0200) /*!< DIN1 Bit 1 */ 2149 #define AES256_DIN_DIN12 ((uint16_t)0x0400) /*!< DIN1 Bit 2 */ 2150 #define AES256_DIN_DIN13 ((uint16_t)0x0800) /*!< DIN1 Bit 3 */ 2151 #define AES256_DIN_DIN14 ((uint16_t)0x1000) /*!< DIN1 Bit 4 */ 2152 #define AES256_DIN_DIN15 ((uint16_t)0x2000) /*!< DIN1 Bit 5 */ 2153 #define AES256_DIN_DIN16 ((uint16_t)0x4000) /*!< DIN1 Bit 6 */ 2154 #define AES256_DIN_DIN17 ((uint16_t)0x8000) /*!< DIN1 Bit 7 */ 2155 /* AES256_DOUT[DOUT0] Bits */ 2156 #define AES256_DOUT_DOUT0_OFS ( 0) /*!< AESDOUT0x Bit Offset */ 2157 #define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /*!< AESDOUT0x Bit Mask */ 2158 #define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /*!< DOUT0 Bit 0 */ 2159 #define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /*!< DOUT0 Bit 1 */ 2160 #define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /*!< DOUT0 Bit 2 */ 2161 #define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /*!< DOUT0 Bit 3 */ 2162 #define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /*!< DOUT0 Bit 4 */ 2163 #define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /*!< DOUT0 Bit 5 */ 2164 #define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /*!< DOUT0 Bit 6 */ 2165 #define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /*!< DOUT0 Bit 7 */ 2166 /* AES256_DOUT[DOUT1] Bits */ 2167 #define AES256_DOUT_DOUT1_OFS ( 8) /*!< AESDOUT1x Bit Offset */ 2168 #define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /*!< AESDOUT1x Bit Mask */ 2169 #define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /*!< DOUT1 Bit 0 */ 2170 #define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /*!< DOUT1 Bit 1 */ 2171 #define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /*!< DOUT1 Bit 2 */ 2172 #define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /*!< DOUT1 Bit 3 */ 2173 #define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /*!< DOUT1 Bit 4 */ 2174 #define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /*!< DOUT1 Bit 5 */ 2175 #define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /*!< DOUT1 Bit 6 */ 2176 #define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /*!< DOUT1 Bit 7 */ 2177 /* AES256_XDIN[XDIN0] Bits */ 2178 #define AES256_XDIN_XDIN0_OFS ( 0) /*!< AESXDIN0x Bit Offset */ 2179 #define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /*!< AESXDIN0x Bit Mask */ 2180 #define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /*!< XDIN0 Bit 0 */ 2181 #define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /*!< XDIN0 Bit 1 */ 2182 #define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /*!< XDIN0 Bit 2 */ 2183 #define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /*!< XDIN0 Bit 3 */ 2184 #define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /*!< XDIN0 Bit 4 */ 2185 #define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /*!< XDIN0 Bit 5 */ 2186 #define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /*!< XDIN0 Bit 6 */ 2187 #define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /*!< XDIN0 Bit 7 */ 2188 /* AES256_XDIN[XDIN1] Bits */ 2189 #define AES256_XDIN_XDIN1_OFS ( 8) /*!< AESXDIN1x Bit Offset */ 2190 #define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /*!< AESXDIN1x Bit Mask */ 2191 #define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /*!< XDIN1 Bit 0 */ 2192 #define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /*!< XDIN1 Bit 1 */ 2193 #define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /*!< XDIN1 Bit 2 */ 2194 #define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /*!< XDIN1 Bit 3 */ 2195 #define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /*!< XDIN1 Bit 4 */ 2196 #define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /*!< XDIN1 Bit 5 */ 2197 #define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /*!< XDIN1 Bit 6 */ 2198 #define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /*!< XDIN1 Bit 7 */ 2199 /* AES256_XIN[XIN0] Bits */ 2200 #define AES256_XIN_XIN0_OFS ( 0) /*!< AESXIN0x Bit Offset */ 2201 #define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /*!< AESXIN0x Bit Mask */ 2202 #define AES256_XIN_XIN00 ((uint16_t)0x0001) /*!< XIN0 Bit 0 */ 2203 #define AES256_XIN_XIN01 ((uint16_t)0x0002) /*!< XIN0 Bit 1 */ 2204 #define AES256_XIN_XIN02 ((uint16_t)0x0004) /*!< XIN0 Bit 2 */ 2205 #define AES256_XIN_XIN03 ((uint16_t)0x0008) /*!< XIN0 Bit 3 */ 2206 #define AES256_XIN_XIN04 ((uint16_t)0x0010) /*!< XIN0 Bit 4 */ 2207 #define AES256_XIN_XIN05 ((uint16_t)0x0020) /*!< XIN0 Bit 5 */ 2208 #define AES256_XIN_XIN06 ((uint16_t)0x0040) /*!< XIN0 Bit 6 */ 2209 #define AES256_XIN_XIN07 ((uint16_t)0x0080) /*!< XIN0 Bit 7 */ 2210 /* AES256_XIN[XIN1] Bits */ 2211 #define AES256_XIN_XIN1_OFS ( 8) /*!< AESXIN1x Bit Offset */ 2212 #define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /*!< AESXIN1x Bit Mask */ 2213 #define AES256_XIN_XIN10 ((uint16_t)0x0100) /*!< XIN1 Bit 0 */ 2214 #define AES256_XIN_XIN11 ((uint16_t)0x0200) /*!< XIN1 Bit 1 */ 2215 #define AES256_XIN_XIN12 ((uint16_t)0x0400) /*!< XIN1 Bit 2 */ 2216 #define AES256_XIN_XIN13 ((uint16_t)0x0800) /*!< XIN1 Bit 3 */ 2217 #define AES256_XIN_XIN14 ((uint16_t)0x1000) /*!< XIN1 Bit 4 */ 2218 #define AES256_XIN_XIN15 ((uint16_t)0x2000) /*!< XIN1 Bit 5 */ 2219 #define AES256_XIN_XIN16 ((uint16_t)0x4000) /*!< XIN1 Bit 6 */ 2220 #define AES256_XIN_XIN17 ((uint16_t)0x8000) /*!< XIN1 Bit 7 */ 2221 2222 /****************************************************************************** 2223 * CAPTIO Bits 2224 ******************************************************************************/ 2225 /* CAPTIO_CTL[PISEL] Bits */ 2226 #define CAPTIO_CTL_PISEL_OFS ( 1) /*!< CAPTIOPISELx Bit Offset */ 2227 #define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /*!< CAPTIOPISELx Bit Mask */ 2228 #define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /*!< PISEL Bit 0 */ 2229 #define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /*!< PISEL Bit 1 */ 2230 #define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /*!< PISEL Bit 2 */ 2231 #define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /*!< Px.0 */ 2232 #define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /*!< Px.1 */ 2233 #define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /*!< Px.2 */ 2234 #define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /*!< Px.3 */ 2235 #define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /*!< Px.4 */ 2236 #define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /*!< Px.5 */ 2237 #define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /*!< Px.6 */ 2238 #define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /*!< Px.7 */ 2239 /* CAPTIO_CTL[POSEL] Bits */ 2240 #define CAPTIO_CTL_POSEL_OFS ( 4) /*!< CAPTIOPOSELx Bit Offset */ 2241 #define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /*!< CAPTIOPOSELx Bit Mask */ 2242 #define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /*!< POSEL Bit 0 */ 2243 #define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /*!< POSEL Bit 1 */ 2244 #define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /*!< POSEL Bit 2 */ 2245 #define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /*!< POSEL Bit 3 */ 2246 #define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /*!< Px = PJ */ 2247 #define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /*!< Px = P1 */ 2248 #define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /*!< Px = P2 */ 2249 #define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /*!< Px = P3 */ 2250 #define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /*!< Px = P4 */ 2251 #define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /*!< Px = P5 */ 2252 #define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /*!< Px = P6 */ 2253 #define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /*!< Px = P7 */ 2254 #define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /*!< Px = P8 */ 2255 #define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /*!< Px = P9 */ 2256 #define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /*!< Px = P10 */ 2257 #define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /*!< Px = P11 */ 2258 #define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /*!< Px = P12 */ 2259 #define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /*!< Px = P13 */ 2260 #define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /*!< Px = P14 */ 2261 #define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /*!< Px = P15 */ 2262 #define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /*!< Px = PJ */ 2263 #define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /*!< Px = P1 */ 2264 #define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /*!< Px = P2 */ 2265 #define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /*!< Px = P3 */ 2266 #define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /*!< Px = P4 */ 2267 #define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /*!< Px = P5 */ 2268 #define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /*!< Px = P6 */ 2269 #define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /*!< Px = P7 */ 2270 #define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /*!< Px = P8 */ 2271 #define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /*!< Px = P9 */ 2272 #define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /*!< Px = P10 */ 2273 #define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /*!< Px = P11 */ 2274 #define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /*!< Px = P12 */ 2275 #define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /*!< Px = P13 */ 2276 #define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /*!< Px = P14 */ 2277 #define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /*!< Px = P15 */ 2278 /* CAPTIO_CTL[EN] Bits */ 2279 #define CAPTIO_CTL_EN_OFS ( 8) /*!< CAPTIOEN Bit Offset */ 2280 #define CAPTIO_CTL_EN ((uint16_t)0x0100) /*!< Capacitive Touch IO enable */ 2281 /* CAPTIO_CTL[STATE] Bits */ 2282 #define CAPTIO_CTL_STATE_OFS ( 9) /*!< CAPTIOSTATE Bit Offset */ 2283 #define CAPTIO_CTL_STATE ((uint16_t)0x0200) /*!< Capacitive Touch IO state */ 2284 2285 /****************************************************************************** 2286 * COMP_E Bits 2287 ******************************************************************************/ 2288 /* COMP_E_CTL0[IPSEL] Bits */ 2289 #define COMP_E_CTL0_IPSEL_OFS ( 0) /*!< CEIPSEL Bit Offset */ 2290 #define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /*!< CEIPSEL Bit Mask */ 2291 #define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /*!< IPSEL Bit 0 */ 2292 #define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /*!< IPSEL Bit 1 */ 2293 #define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /*!< IPSEL Bit 2 */ 2294 #define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /*!< IPSEL Bit 3 */ 2295 #define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ 2296 #define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /*!< Channel 1 selected */ 2297 #define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /*!< Channel 2 selected */ 2298 #define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /*!< Channel 3 selected */ 2299 #define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /*!< Channel 4 selected */ 2300 #define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /*!< Channel 5 selected */ 2301 #define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /*!< Channel 6 selected */ 2302 #define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /*!< Channel 7 selected */ 2303 #define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /*!< Channel 8 selected */ 2304 #define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /*!< Channel 9 selected */ 2305 #define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /*!< Channel 10 selected */ 2306 #define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /*!< Channel 11 selected */ 2307 #define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /*!< Channel 12 selected */ 2308 #define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /*!< Channel 13 selected */ 2309 #define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /*!< Channel 14 selected */ 2310 #define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /*!< Channel 15 selected */ 2311 /* COMP_E_CTL0[IPEN] Bits */ 2312 #define COMP_E_CTL0_IPEN_OFS ( 7) /*!< CEIPEN Bit Offset */ 2313 #define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /*!< Channel input enable for the V+ terminal */ 2314 /* COMP_E_CTL0[IMSEL] Bits */ 2315 #define COMP_E_CTL0_IMSEL_OFS ( 8) /*!< CEIMSEL Bit Offset */ 2316 #define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /*!< CEIMSEL Bit Mask */ 2317 #define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /*!< IMSEL Bit 0 */ 2318 #define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /*!< IMSEL Bit 1 */ 2319 #define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /*!< IMSEL Bit 2 */ 2320 #define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /*!< IMSEL Bit 3 */ 2321 #define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ 2322 #define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /*!< Channel 1 selected */ 2323 #define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /*!< Channel 2 selected */ 2324 #define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /*!< Channel 3 selected */ 2325 #define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /*!< Channel 4 selected */ 2326 #define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /*!< Channel 5 selected */ 2327 #define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /*!< Channel 6 selected */ 2328 #define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /*!< Channel 7 selected */ 2329 #define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /*!< Channel 8 selected */ 2330 #define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /*!< Channel 9 selected */ 2331 #define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /*!< Channel 10 selected */ 2332 #define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /*!< Channel 11 selected */ 2333 #define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /*!< Channel 12 selected */ 2334 #define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /*!< Channel 13 selected */ 2335 #define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /*!< Channel 14 selected */ 2336 #define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /*!< Channel 15 selected */ 2337 /* COMP_E_CTL0[IMEN] Bits */ 2338 #define COMP_E_CTL0_IMEN_OFS (15) /*!< CEIMEN Bit Offset */ 2339 #define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /*!< Channel input enable for the - terminal */ 2340 /* COMP_E_CTL1[OUT] Bits */ 2341 #define COMP_E_CTL1_OUT_OFS ( 0) /*!< CEOUT Bit Offset */ 2342 #define COMP_E_CTL1_OUT ((uint16_t)0x0001) /*!< Comparator output value */ 2343 /* COMP_E_CTL1[OUTPOL] Bits */ 2344 #define COMP_E_CTL1_OUTPOL_OFS ( 1) /*!< CEOUTPOL Bit Offset */ 2345 #define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /*!< Comparator output polarity */ 2346 /* COMP_E_CTL1[F] Bits */ 2347 #define COMP_E_CTL1_F_OFS ( 2) /*!< CEF Bit Offset */ 2348 #define COMP_E_CTL1_F ((uint16_t)0x0004) /*!< Comparator output filter */ 2349 /* COMP_E_CTL1[IES] Bits */ 2350 #define COMP_E_CTL1_IES_OFS ( 3) /*!< CEIES Bit Offset */ 2351 #define COMP_E_CTL1_IES ((uint16_t)0x0008) /*!< Interrupt edge select for CEIIFG and CEIFG */ 2352 /* COMP_E_CTL1[SHORT] Bits */ 2353 #define COMP_E_CTL1_SHORT_OFS ( 4) /*!< CESHORT Bit Offset */ 2354 #define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /*!< Input short */ 2355 /* COMP_E_CTL1[EX] Bits */ 2356 #define COMP_E_CTL1_EX_OFS ( 5) /*!< CEEX Bit Offset */ 2357 #define COMP_E_CTL1_EX ((uint16_t)0x0020) /*!< Exchange */ 2358 /* COMP_E_CTL1[FDLY] Bits */ 2359 #define COMP_E_CTL1_FDLY_OFS ( 6) /*!< CEFDLY Bit Offset */ 2360 #define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /*!< CEFDLY Bit Mask */ 2361 #define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /*!< FDLY Bit 0 */ 2362 #define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /*!< FDLY Bit 1 */ 2363 #define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /*!< Typical filter delay of TBD (450) ns */ 2364 #define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /*!< Typical filter delay of TBD (900) ns */ 2365 #define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /*!< Typical filter delay of TBD (1800) ns */ 2366 #define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /*!< Typical filter delay of TBD (3600) ns */ 2367 /* COMP_E_CTL1[PWRMD] Bits */ 2368 #define COMP_E_CTL1_PWRMD_OFS ( 8) /*!< CEPWRMD Bit Offset */ 2369 #define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /*!< CEPWRMD Bit Mask */ 2370 #define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /*!< PWRMD Bit 0 */ 2371 #define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /*!< PWRMD Bit 1 */ 2372 #define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /*!< High-speed mode */ 2373 #define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /*!< Normal mode */ 2374 #define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /*!< Ultra-low power mode */ 2375 /* COMP_E_CTL1[ON] Bits */ 2376 #define COMP_E_CTL1_ON_OFS (10) /*!< CEON Bit Offset */ 2377 #define COMP_E_CTL1_ON ((uint16_t)0x0400) /*!< Comparator On */ 2378 /* COMP_E_CTL1[MRVL] Bits */ 2379 #define COMP_E_CTL1_MRVL_OFS (11) /*!< CEMRVL Bit Offset */ 2380 #define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /*!< This bit is valid of CEMRVS is set to 1 */ 2381 /* COMP_E_CTL1[MRVS] Bits */ 2382 #define COMP_E_CTL1_MRVS_OFS (12) /*!< CEMRVS Bit Offset */ 2383 #define COMP_E_CTL1_MRVS ((uint16_t)0x1000) 2384 /* COMP_E_CTL2[REF0] Bits */ 2385 #define COMP_E_CTL2_REF0_OFS ( 0) /*!< CEREF0 Bit Offset */ 2386 #define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /*!< CEREF0 Bit Mask */ 2387 #define COMP_E_CTL2_REF00 ((uint16_t)0x0001) /*!< REF0 Bit 0 */ 2388 #define COMP_E_CTL2_REF01 ((uint16_t)0x0002) /*!< REF0 Bit 1 */ 2389 #define COMP_E_CTL2_REF02 ((uint16_t)0x0004) /*!< REF0 Bit 2 */ 2390 #define COMP_E_CTL2_REF03 ((uint16_t)0x0008) /*!< REF0 Bit 3 */ 2391 #define COMP_E_CTL2_REF04 ((uint16_t)0x0010) /*!< REF0 Bit 4 */ 2392 #define COMP_E_CTL2_REF0_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ 2393 #define COMP_E_CTL2_REF0_1 ((uint16_t)0x0001) /*!< Reference resistor tap for setting 1. */ 2394 #define COMP_E_CTL2_REF0_2 ((uint16_t)0x0002) /*!< Reference resistor tap for setting 2. */ 2395 #define COMP_E_CTL2_REF0_3 ((uint16_t)0x0003) /*!< Reference resistor tap for setting 3. */ 2396 #define COMP_E_CTL2_REF0_4 ((uint16_t)0x0004) /*!< Reference resistor tap for setting 4. */ 2397 #define COMP_E_CTL2_REF0_5 ((uint16_t)0x0005) /*!< Reference resistor tap for setting 5. */ 2398 #define COMP_E_CTL2_REF0_6 ((uint16_t)0x0006) /*!< Reference resistor tap for setting 6. */ 2399 #define COMP_E_CTL2_REF0_7 ((uint16_t)0x0007) /*!< Reference resistor tap for setting 7. */ 2400 #define COMP_E_CTL2_REF0_8 ((uint16_t)0x0008) /*!< Reference resistor tap for setting 8. */ 2401 #define COMP_E_CTL2_REF0_9 ((uint16_t)0x0009) /*!< Reference resistor tap for setting 9. */ 2402 #define COMP_E_CTL2_REF0_10 ((uint16_t)0x000A) /*!< Reference resistor tap for setting 10. */ 2403 #define COMP_E_CTL2_REF0_11 ((uint16_t)0x000B) /*!< Reference resistor tap for setting 11. */ 2404 #define COMP_E_CTL2_REF0_12 ((uint16_t)0x000C) /*!< Reference resistor tap for setting 12. */ 2405 #define COMP_E_CTL2_REF0_13 ((uint16_t)0x000D) /*!< Reference resistor tap for setting 13. */ 2406 #define COMP_E_CTL2_REF0_14 ((uint16_t)0x000E) /*!< Reference resistor tap for setting 14. */ 2407 #define COMP_E_CTL2_REF0_15 ((uint16_t)0x000F) /*!< Reference resistor tap for setting 15. */ 2408 #define COMP_E_CTL2_REF0_16 ((uint16_t)0x0010) /*!< Reference resistor tap for setting 16. */ 2409 #define COMP_E_CTL2_REF0_17 ((uint16_t)0x0011) /*!< Reference resistor tap for setting 17. */ 2410 #define COMP_E_CTL2_REF0_18 ((uint16_t)0x0012) /*!< Reference resistor tap for setting 18. */ 2411 #define COMP_E_CTL2_REF0_19 ((uint16_t)0x0013) /*!< Reference resistor tap for setting 19. */ 2412 #define COMP_E_CTL2_REF0_20 ((uint16_t)0x0014) /*!< Reference resistor tap for setting 20. */ 2413 #define COMP_E_CTL2_REF0_21 ((uint16_t)0x0015) /*!< Reference resistor tap for setting 21. */ 2414 #define COMP_E_CTL2_REF0_22 ((uint16_t)0x0016) /*!< Reference resistor tap for setting 22. */ 2415 #define COMP_E_CTL2_REF0_23 ((uint16_t)0x0017) /*!< Reference resistor tap for setting 23. */ 2416 #define COMP_E_CTL2_REF0_24 ((uint16_t)0x0018) /*!< Reference resistor tap for setting 24. */ 2417 #define COMP_E_CTL2_REF0_25 ((uint16_t)0x0019) /*!< Reference resistor tap for setting 25. */ 2418 #define COMP_E_CTL2_REF0_26 ((uint16_t)0x001A) /*!< Reference resistor tap for setting 26. */ 2419 #define COMP_E_CTL2_REF0_27 ((uint16_t)0x001B) /*!< Reference resistor tap for setting 27. */ 2420 #define COMP_E_CTL2_REF0_28 ((uint16_t)0x001C) /*!< Reference resistor tap for setting 28. */ 2421 #define COMP_E_CTL2_REF0_29 ((uint16_t)0x001D) /*!< Reference resistor tap for setting 29. */ 2422 #define COMP_E_CTL2_REF0_30 ((uint16_t)0x001E) /*!< Reference resistor tap for setting 30. */ 2423 #define COMP_E_CTL2_REF0_31 ((uint16_t)0x001F) /*!< Reference resistor tap for setting 31. */ 2424 /* COMP_E_CTL2[RSEL] Bits */ 2425 #define COMP_E_CTL2_RSEL_OFS ( 5) /*!< CERSEL Bit Offset */ 2426 #define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /*!< Reference select */ 2427 /* COMP_E_CTL2[RS] Bits */ 2428 #define COMP_E_CTL2_RS_OFS ( 6) /*!< CERS Bit Offset */ 2429 #define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /*!< CERS Bit Mask */ 2430 #define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /*!< RS Bit 0 */ 2431 #define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /*!< RS Bit 1 */ 2432 #define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /*!< No current is drawn by the reference circuitry */ 2433 #define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /*!< VCC applied to the resistor ladder */ 2434 #define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /*!< Shared reference voltage applied to the resistor ladder */ 2435 #define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ 2436 /* COMP_E_CTL2[REF1] Bits */ 2437 #define COMP_E_CTL2_REF1_OFS ( 8) /*!< CEREF1 Bit Offset */ 2438 #define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /*!< CEREF1 Bit Mask */ 2439 #define COMP_E_CTL2_REF10 ((uint16_t)0x0100) /*!< REF1 Bit 0 */ 2440 #define COMP_E_CTL2_REF11 ((uint16_t)0x0200) /*!< REF1 Bit 1 */ 2441 #define COMP_E_CTL2_REF12 ((uint16_t)0x0400) /*!< REF1 Bit 2 */ 2442 #define COMP_E_CTL2_REF13 ((uint16_t)0x0800) /*!< REF1 Bit 3 */ 2443 #define COMP_E_CTL2_REF14 ((uint16_t)0x1000) /*!< REF1 Bit 4 */ 2444 #define COMP_E_CTL2_REF1_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ 2445 #define COMP_E_CTL2_REF1_1 ((uint16_t)0x0100) /*!< Reference resistor tap for setting 1. */ 2446 #define COMP_E_CTL2_REF1_2 ((uint16_t)0x0200) /*!< Reference resistor tap for setting 2. */ 2447 #define COMP_E_CTL2_REF1_3 ((uint16_t)0x0300) /*!< Reference resistor tap for setting 3. */ 2448 #define COMP_E_CTL2_REF1_4 ((uint16_t)0x0400) /*!< Reference resistor tap for setting 4. */ 2449 #define COMP_E_CTL2_REF1_5 ((uint16_t)0x0500) /*!< Reference resistor tap for setting 5. */ 2450 #define COMP_E_CTL2_REF1_6 ((uint16_t)0x0600) /*!< Reference resistor tap for setting 6. */ 2451 #define COMP_E_CTL2_REF1_7 ((uint16_t)0x0700) /*!< Reference resistor tap for setting 7. */ 2452 #define COMP_E_CTL2_REF1_8 ((uint16_t)0x0800) /*!< Reference resistor tap for setting 8. */ 2453 #define COMP_E_CTL2_REF1_9 ((uint16_t)0x0900) /*!< Reference resistor tap for setting 9. */ 2454 #define COMP_E_CTL2_REF1_10 ((uint16_t)0x0A00) /*!< Reference resistor tap for setting 10. */ 2455 #define COMP_E_CTL2_REF1_11 ((uint16_t)0x0B00) /*!< Reference resistor tap for setting 11. */ 2456 #define COMP_E_CTL2_REF1_12 ((uint16_t)0x0C00) /*!< Reference resistor tap for setting 12. */ 2457 #define COMP_E_CTL2_REF1_13 ((uint16_t)0x0D00) /*!< Reference resistor tap for setting 13. */ 2458 #define COMP_E_CTL2_REF1_14 ((uint16_t)0x0E00) /*!< Reference resistor tap for setting 14. */ 2459 #define COMP_E_CTL2_REF1_15 ((uint16_t)0x0F00) /*!< Reference resistor tap for setting 15. */ 2460 #define COMP_E_CTL2_REF1_16 ((uint16_t)0x1000) /*!< Reference resistor tap for setting 16. */ 2461 #define COMP_E_CTL2_REF1_17 ((uint16_t)0x1100) /*!< Reference resistor tap for setting 17. */ 2462 #define COMP_E_CTL2_REF1_18 ((uint16_t)0x1200) /*!< Reference resistor tap for setting 18. */ 2463 #define COMP_E_CTL2_REF1_19 ((uint16_t)0x1300) /*!< Reference resistor tap for setting 19. */ 2464 #define COMP_E_CTL2_REF1_20 ((uint16_t)0x1400) /*!< Reference resistor tap for setting 20. */ 2465 #define COMP_E_CTL2_REF1_21 ((uint16_t)0x1500) /*!< Reference resistor tap for setting 21. */ 2466 #define COMP_E_CTL2_REF1_22 ((uint16_t)0x1600) /*!< Reference resistor tap for setting 22. */ 2467 #define COMP_E_CTL2_REF1_23 ((uint16_t)0x1700) /*!< Reference resistor tap for setting 23. */ 2468 #define COMP_E_CTL2_REF1_24 ((uint16_t)0x1800) /*!< Reference resistor tap for setting 24. */ 2469 #define COMP_E_CTL2_REF1_25 ((uint16_t)0x1900) /*!< Reference resistor tap for setting 25. */ 2470 #define COMP_E_CTL2_REF1_26 ((uint16_t)0x1A00) /*!< Reference resistor tap for setting 26. */ 2471 #define COMP_E_CTL2_REF1_27 ((uint16_t)0x1B00) /*!< Reference resistor tap for setting 27. */ 2472 #define COMP_E_CTL2_REF1_28 ((uint16_t)0x1C00) /*!< Reference resistor tap for setting 28. */ 2473 #define COMP_E_CTL2_REF1_29 ((uint16_t)0x1D00) /*!< Reference resistor tap for setting 29. */ 2474 #define COMP_E_CTL2_REF1_30 ((uint16_t)0x1E00) /*!< Reference resistor tap for setting 30. */ 2475 #define COMP_E_CTL2_REF1_31 ((uint16_t)0x1F00) /*!< Reference resistor tap for setting 31. */ 2476 /* COMP_E_CTL2[REFL] Bits */ 2477 #define COMP_E_CTL2_REFL_OFS (13) /*!< CEREFL Bit Offset */ 2478 #define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /*!< CEREFL Bit Mask */ 2479 #define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /*!< REFL Bit 0 */ 2480 #define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /*!< REFL Bit 1 */ 2481 #define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ 2482 #define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ 2483 #define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ 2484 #define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ 2485 #define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ 2486 #define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ 2487 #define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ 2488 #define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ 2489 /* COMP_E_CTL2[REFACC] Bits */ 2490 #define COMP_E_CTL2_REFACC_OFS (15) /*!< CEREFACC Bit Offset */ 2491 #define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /*!< Reference accuracy */ 2492 /* COMP_E_CTL3[PD0] Bits */ 2493 #define COMP_E_CTL3_PD0_OFS ( 0) /*!< CEPD0 Bit Offset */ 2494 #define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /*!< Port disable */ 2495 /* COMP_E_CTL3[PD1] Bits */ 2496 #define COMP_E_CTL3_PD1_OFS ( 1) /*!< CEPD1 Bit Offset */ 2497 #define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /*!< Port disable */ 2498 /* COMP_E_CTL3[PD2] Bits */ 2499 #define COMP_E_CTL3_PD2_OFS ( 2) /*!< CEPD2 Bit Offset */ 2500 #define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /*!< Port disable */ 2501 /* COMP_E_CTL3[PD3] Bits */ 2502 #define COMP_E_CTL3_PD3_OFS ( 3) /*!< CEPD3 Bit Offset */ 2503 #define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /*!< Port disable */ 2504 /* COMP_E_CTL3[PD4] Bits */ 2505 #define COMP_E_CTL3_PD4_OFS ( 4) /*!< CEPD4 Bit Offset */ 2506 #define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /*!< Port disable */ 2507 /* COMP_E_CTL3[PD5] Bits */ 2508 #define COMP_E_CTL3_PD5_OFS ( 5) /*!< CEPD5 Bit Offset */ 2509 #define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /*!< Port disable */ 2510 /* COMP_E_CTL3[PD6] Bits */ 2511 #define COMP_E_CTL3_PD6_OFS ( 6) /*!< CEPD6 Bit Offset */ 2512 #define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /*!< Port disable */ 2513 /* COMP_E_CTL3[PD7] Bits */ 2514 #define COMP_E_CTL3_PD7_OFS ( 7) /*!< CEPD7 Bit Offset */ 2515 #define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /*!< Port disable */ 2516 /* COMP_E_CTL3[PD8] Bits */ 2517 #define COMP_E_CTL3_PD8_OFS ( 8) /*!< CEPD8 Bit Offset */ 2518 #define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /*!< Port disable */ 2519 /* COMP_E_CTL3[PD9] Bits */ 2520 #define COMP_E_CTL3_PD9_OFS ( 9) /*!< CEPD9 Bit Offset */ 2521 #define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /*!< Port disable */ 2522 /* COMP_E_CTL3[PD10] Bits */ 2523 #define COMP_E_CTL3_PD10_OFS (10) /*!< CEPD10 Bit Offset */ 2524 #define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /*!< Port disable */ 2525 /* COMP_E_CTL3[PD11] Bits */ 2526 #define COMP_E_CTL3_PD11_OFS (11) /*!< CEPD11 Bit Offset */ 2527 #define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /*!< Port disable */ 2528 /* COMP_E_CTL3[PD12] Bits */ 2529 #define COMP_E_CTL3_PD12_OFS (12) /*!< CEPD12 Bit Offset */ 2530 #define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /*!< Port disable */ 2531 /* COMP_E_CTL3[PD13] Bits */ 2532 #define COMP_E_CTL3_PD13_OFS (13) /*!< CEPD13 Bit Offset */ 2533 #define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /*!< Port disable */ 2534 /* COMP_E_CTL3[PD14] Bits */ 2535 #define COMP_E_CTL3_PD14_OFS (14) /*!< CEPD14 Bit Offset */ 2536 #define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /*!< Port disable */ 2537 /* COMP_E_CTL3[PD15] Bits */ 2538 #define COMP_E_CTL3_PD15_OFS (15) /*!< CEPD15 Bit Offset */ 2539 #define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /*!< Port disable */ 2540 /* COMP_E_INT[IFG] Bits */ 2541 #define COMP_E_INT_IFG_OFS ( 0) /*!< CEIFG Bit Offset */ 2542 #define COMP_E_INT_IFG ((uint16_t)0x0001) /*!< Comparator output interrupt flag */ 2543 /* COMP_E_INT[IIFG] Bits */ 2544 #define COMP_E_INT_IIFG_OFS ( 1) /*!< CEIIFG Bit Offset */ 2545 #define COMP_E_INT_IIFG ((uint16_t)0x0002) /*!< Comparator output inverted interrupt flag */ 2546 /* COMP_E_INT[RDYIFG] Bits */ 2547 #define COMP_E_INT_RDYIFG_OFS ( 4) /*!< CERDYIFG Bit Offset */ 2548 #define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /*!< Comparator ready interrupt flag */ 2549 /* COMP_E_INT[IE] Bits */ 2550 #define COMP_E_INT_IE_OFS ( 8) /*!< CEIE Bit Offset */ 2551 #define COMP_E_INT_IE ((uint16_t)0x0100) /*!< Comparator output interrupt enable */ 2552 /* COMP_E_INT[IIE] Bits */ 2553 #define COMP_E_INT_IIE_OFS ( 9) /*!< CEIIE Bit Offset */ 2554 #define COMP_E_INT_IIE ((uint16_t)0x0200) /*!< Comparator output interrupt enable inverted polarity */ 2555 /* COMP_E_INT[RDYIE] Bits */ 2556 #define COMP_E_INT_RDYIE_OFS (12) /*!< CERDYIE Bit Offset */ 2557 #define COMP_E_INT_RDYIE ((uint16_t)0x1000) /*!< Comparator ready interrupt enable */ 2558 2559 /****************************************************************************** 2560 * COREDEBUG Bits 2561 ******************************************************************************/ 2562 2563 2564 /****************************************************************************** 2565 * CRC32 Bits 2566 ******************************************************************************/ 2567 2568 /****************************************************************************** 2569 * CS Bits 2570 ******************************************************************************/ 2571 /* CS_KEY[KEY] Bits */ 2572 #define CS_KEY_KEY_OFS ( 0) /*!< CSKEY Bit Offset */ 2573 #define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< CSKEY Bit Mask */ 2574 /* CS_CTL0[DCOTUNE] Bits */ 2575 #define CS_CTL0_DCOTUNE_OFS ( 0) /*!< DCOTUNE Bit Offset */ 2576 #define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /*!< DCOTUNE Bit Mask */ 2577 /* CS_CTL0[DCORSEL] Bits */ 2578 #define CS_CTL0_DCORSEL_OFS (16) /*!< DCORSEL Bit Offset */ 2579 #define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /*!< DCORSEL Bit Mask */ 2580 #define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /*!< DCORSEL Bit 0 */ 2581 #define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /*!< DCORSEL Bit 1 */ 2582 #define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /*!< DCORSEL Bit 2 */ 2583 #define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */ 2584 #define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */ 2585 #define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */ 2586 #define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */ 2587 #define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */ 2588 #define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */ 2589 /* CS_CTL0[DCORES] Bits */ 2590 #define CS_CTL0_DCORES_OFS (22) /*!< DCORES Bit Offset */ 2591 #define CS_CTL0_DCORES ((uint32_t)0x00400000) /*!< Enables the DCO external resistor mode */ 2592 /* CS_CTL0[DCOEN] Bits */ 2593 #define CS_CTL0_DCOEN_OFS (23) /*!< DCOEN Bit Offset */ 2594 #define CS_CTL0_DCOEN ((uint32_t)0x00800000) /*!< Enables the DCO oscillator */ 2595 /* CS_CTL1[SELM] Bits */ 2596 #define CS_CTL1_SELM_OFS ( 0) /*!< SELM Bit Offset */ 2597 #define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /*!< SELM Bit Mask */ 2598 #define CS_CTL1_SELM0 ((uint32_t)0x00000001) /*!< SELM Bit 0 */ 2599 #define CS_CTL1_SELM1 ((uint32_t)0x00000002) /*!< SELM Bit 1 */ 2600 #define CS_CTL1_SELM2 ((uint32_t)0x00000004) /*!< SELM Bit 2 */ 2601 #define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2602 #define CS_CTL1_SELM_1 ((uint32_t)0x00000001) 2603 #define CS_CTL1_SELM_2 ((uint32_t)0x00000002) 2604 #define CS_CTL1_SELM_3 ((uint32_t)0x00000003) 2605 #define CS_CTL1_SELM_4 ((uint32_t)0x00000004) 2606 #define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ 2607 #define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ 2608 #define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2609 #define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001) 2610 #define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002) 2611 #define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003) 2612 #define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004) 2613 #define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ 2614 #define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ 2615 /* CS_CTL1[SELS] Bits */ 2616 #define CS_CTL1_SELS_OFS ( 4) /*!< SELS Bit Offset */ 2617 #define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /*!< SELS Bit Mask */ 2618 #define CS_CTL1_SELS0 ((uint32_t)0x00000010) /*!< SELS Bit 0 */ 2619 #define CS_CTL1_SELS1 ((uint32_t)0x00000020) /*!< SELS Bit 1 */ 2620 #define CS_CTL1_SELS2 ((uint32_t)0x00000040) /*!< SELS Bit 2 */ 2621 #define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2622 #define CS_CTL1_SELS_1 ((uint32_t)0x00000010) 2623 #define CS_CTL1_SELS_2 ((uint32_t)0x00000020) 2624 #define CS_CTL1_SELS_3 ((uint32_t)0x00000030) 2625 #define CS_CTL1_SELS_4 ((uint32_t)0x00000040) 2626 #define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ 2627 #define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ 2628 #define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2629 #define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010) 2630 #define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020) 2631 #define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030) 2632 #define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040) 2633 #define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ 2634 #define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ 2635 /* CS_CTL1[SELA] Bits */ 2636 #define CS_CTL1_SELA_OFS ( 8) /*!< SELA Bit Offset */ 2637 #define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /*!< SELA Bit Mask */ 2638 #define CS_CTL1_SELA0 ((uint32_t)0x00000100) /*!< SELA Bit 0 */ 2639 #define CS_CTL1_SELA1 ((uint32_t)0x00000200) /*!< SELA Bit 1 */ 2640 #define CS_CTL1_SELA2 ((uint32_t)0x00000400) /*!< SELA Bit 2 */ 2641 #define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2642 #define CS_CTL1_SELA_1 ((uint32_t)0x00000100) 2643 #define CS_CTL1_SELA_2 ((uint32_t)0x00000200) 2644 #define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2645 #define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100) 2646 #define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200) 2647 /* CS_CTL1[SELB] Bits */ 2648 #define CS_CTL1_SELB_OFS (12) /*!< SELB Bit Offset */ 2649 #define CS_CTL1_SELB ((uint32_t)0x00001000) /*!< Selects the BCLK source */ 2650 /* CS_CTL1[DIVM] Bits */ 2651 #define CS_CTL1_DIVM_OFS (16) /*!< DIVM Bit Offset */ 2652 #define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /*!< DIVM Bit Mask */ 2653 #define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /*!< DIVM Bit 0 */ 2654 #define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /*!< DIVM Bit 1 */ 2655 #define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /*!< DIVM Bit 2 */ 2656 #define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ 2657 #define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ 2658 #define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ 2659 #define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ 2660 #define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ 2661 #define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ 2662 #define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ 2663 #define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ 2664 #define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ 2665 #define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ 2666 #define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ 2667 #define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ 2668 #define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ 2669 #define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ 2670 #define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ 2671 #define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ 2672 /* CS_CTL1[DIVHS] Bits */ 2673 #define CS_CTL1_DIVHS_OFS (20) /*!< DIVHS Bit Offset */ 2674 #define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /*!< DIVHS Bit Mask */ 2675 #define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /*!< DIVHS Bit 0 */ 2676 #define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /*!< DIVHS Bit 1 */ 2677 #define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /*!< DIVHS Bit 2 */ 2678 #define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ 2679 #define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ 2680 #define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ 2681 #define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ 2682 #define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ 2683 #define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ 2684 #define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ 2685 #define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ 2686 #define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ 2687 #define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ 2688 #define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ 2689 #define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ 2690 #define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ 2691 #define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ 2692 #define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ 2693 #define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ 2694 /* CS_CTL1[DIVA] Bits */ 2695 #define CS_CTL1_DIVA_OFS (24) /*!< DIVA Bit Offset */ 2696 #define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /*!< DIVA Bit Mask */ 2697 #define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /*!< DIVA Bit 0 */ 2698 #define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /*!< DIVA Bit 1 */ 2699 #define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /*!< DIVA Bit 2 */ 2700 #define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ 2701 #define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ 2702 #define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ 2703 #define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ 2704 #define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ 2705 #define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ 2706 #define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ 2707 #define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ 2708 #define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ 2709 #define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ 2710 #define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ 2711 #define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ 2712 #define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ 2713 #define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ 2714 #define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ 2715 #define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ 2716 /* CS_CTL1[DIVS] Bits */ 2717 #define CS_CTL1_DIVS_OFS (28) /*!< DIVS Bit Offset */ 2718 #define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /*!< DIVS Bit Mask */ 2719 #define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /*!< DIVS Bit 0 */ 2720 #define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /*!< DIVS Bit 1 */ 2721 #define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /*!< DIVS Bit 2 */ 2722 #define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ 2723 #define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ 2724 #define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ 2725 #define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ 2726 #define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ 2727 #define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ 2728 #define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ 2729 #define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ 2730 #define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ 2731 #define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ 2732 #define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ 2733 #define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ 2734 #define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ 2735 #define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ 2736 #define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ 2737 #define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ 2738 /* CS_CTL2[LFXTDRIVE] Bits */ 2739 #define CS_CTL2_LFXTDRIVE_OFS ( 0) /*!< LFXTDRIVE Bit Offset */ 2740 #define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /*!< LFXTDRIVE Bit Mask */ 2741 #define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /*!< LFXTDRIVE Bit 0 */ 2742 #define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /*!< LFXTDRIVE Bit 1 */ 2743 #define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /*!< Lowest drive strength and current consumption LFXT oscillator. */ 2744 #define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /*!< Increased drive strength LFXT oscillator. */ 2745 #define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /*!< Increased drive strength LFXT oscillator. */ 2746 #define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */ 2747 /* CS_CTL2[LFXT_EN] Bits */ 2748 #define CS_CTL2_LFXT_EN_OFS ( 8) /*!< LFXT_EN Bit Offset */ 2749 #define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /*!< Turns on the LFXT oscillator regardless if used as a clock resource */ 2750 /* CS_CTL2[LFXTBYPASS] Bits */ 2751 #define CS_CTL2_LFXTBYPASS_OFS ( 9) /*!< LFXTBYPASS Bit Offset */ 2752 #define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /*!< LFXT bypass select */ 2753 /* CS_CTL2[HFXTDRIVE] Bits */ 2754 #define CS_CTL2_HFXTDRIVE_OFS (16) /*!< HFXTDRIVE Bit Offset */ 2755 #define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /*!< HFXT oscillator drive selection */ 2756 /* CS_CTL2[HFXTFREQ] Bits */ 2757 #define CS_CTL2_HFXTFREQ_OFS (20) /*!< HFXTFREQ Bit Offset */ 2758 #define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /*!< HFXTFREQ Bit Mask */ 2759 #define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /*!< HFXTFREQ Bit 0 */ 2760 #define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /*!< HFXTFREQ Bit 1 */ 2761 #define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /*!< HFXTFREQ Bit 2 */ 2762 #define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /*!< 1 MHz to 4 MHz */ 2763 #define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /*!< >4 MHz to 8 MHz */ 2764 #define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /*!< >8 MHz to 16 MHz */ 2765 #define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /*!< >16 MHz to 24 MHz */ 2766 #define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /*!< >24 MHz to 32 MHz */ 2767 #define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /*!< >32 MHz to 40 MHz */ 2768 #define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /*!< >40 MHz to 48 MHz */ 2769 #define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /*!< Reserved for future use. */ 2770 /* CS_CTL2[HFXT_EN] Bits */ 2771 #define CS_CTL2_HFXT_EN_OFS (24) /*!< HFXT_EN Bit Offset */ 2772 #define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /*!< Turns on the HFXT oscillator regardless if used as a clock resource */ 2773 /* CS_CTL2[HFXTBYPASS] Bits */ 2774 #define CS_CTL2_HFXTBYPASS_OFS (25) /*!< HFXTBYPASS Bit Offset */ 2775 #define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /*!< HFXT bypass select */ 2776 /* CS_CTL3[FCNTLF] Bits */ 2777 #define CS_CTL3_FCNTLF_OFS ( 0) /*!< FCNTLF Bit Offset */ 2778 #define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /*!< FCNTLF Bit Mask */ 2779 #define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /*!< FCNTLF Bit 0 */ 2780 #define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /*!< FCNTLF Bit 1 */ 2781 #define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /*!< 4096 cycles */ 2782 #define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /*!< 8192 cycles */ 2783 #define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /*!< 16384 cycles */ 2784 #define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /*!< 32768 cycles */ 2785 #define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /*!< 4096 cycles */ 2786 #define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /*!< 8192 cycles */ 2787 #define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /*!< 16384 cycles */ 2788 #define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /*!< 32768 cycles */ 2789 /* CS_CTL3[RFCNTLF] Bits */ 2790 #define CS_CTL3_RFCNTLF_OFS ( 2) /*!< RFCNTLF Bit Offset */ 2791 #define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /*!< Reset start fault counter for LFXT */ 2792 /* CS_CTL3[FCNTLF_EN] Bits */ 2793 #define CS_CTL3_FCNTLF_EN_OFS ( 3) /*!< FCNTLF_EN Bit Offset */ 2794 #define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /*!< Enable start fault counter for LFXT */ 2795 /* CS_CTL3[FCNTHF] Bits */ 2796 #define CS_CTL3_FCNTHF_OFS ( 4) /*!< FCNTHF Bit Offset */ 2797 #define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /*!< FCNTHF Bit Mask */ 2798 #define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /*!< FCNTHF Bit 0 */ 2799 #define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /*!< FCNTHF Bit 1 */ 2800 #define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ 2801 #define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /*!< 4096 cycles */ 2802 #define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /*!< 8192 cycles */ 2803 #define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /*!< 16384 cycles */ 2804 #define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ 2805 #define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /*!< 4096 cycles */ 2806 #define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /*!< 8192 cycles */ 2807 #define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /*!< 16384 cycles */ 2808 /* CS_CTL3[RFCNTHF] Bits */ 2809 #define CS_CTL3_RFCNTHF_OFS ( 6) /*!< RFCNTHF Bit Offset */ 2810 #define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /*!< Reset start fault counter for HFXT */ 2811 /* CS_CTL3[FCNTHF_EN] Bits */ 2812 #define CS_CTL3_FCNTHF_EN_OFS ( 7) /*!< FCNTHF_EN Bit Offset */ 2813 #define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /*!< Enable start fault counter for HFXT */ 2814 /* CS_CLKEN[ACLK_EN] Bits */ 2815 #define CS_CLKEN_ACLK_EN_OFS ( 0) /*!< ACLK_EN Bit Offset */ 2816 #define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /*!< ACLK system clock conditional request enable */ 2817 /* CS_CLKEN[MCLK_EN] Bits */ 2818 #define CS_CLKEN_MCLK_EN_OFS ( 1) /*!< MCLK_EN Bit Offset */ 2819 #define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /*!< MCLK system clock conditional request enable */ 2820 /* CS_CLKEN[HSMCLK_EN] Bits */ 2821 #define CS_CLKEN_HSMCLK_EN_OFS ( 2) /*!< HSMCLK_EN Bit Offset */ 2822 #define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /*!< HSMCLK system clock conditional request enable */ 2823 /* CS_CLKEN[SMCLK_EN] Bits */ 2824 #define CS_CLKEN_SMCLK_EN_OFS ( 3) /*!< SMCLK_EN Bit Offset */ 2825 #define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /*!< SMCLK system clock conditional request enable */ 2826 /* CS_CLKEN[VLO_EN] Bits */ 2827 #define CS_CLKEN_VLO_EN_OFS ( 8) /*!< VLO_EN Bit Offset */ 2828 #define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /*!< Turns on the VLO oscillator */ 2829 /* CS_CLKEN[REFO_EN] Bits */ 2830 #define CS_CLKEN_REFO_EN_OFS ( 9) /*!< REFO_EN Bit Offset */ 2831 #define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /*!< Turns on the REFO oscillator */ 2832 /* CS_CLKEN[MODOSC_EN] Bits */ 2833 #define CS_CLKEN_MODOSC_EN_OFS (10) /*!< MODOSC_EN Bit Offset */ 2834 #define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /*!< Turns on the MODOSC oscillator */ 2835 /* CS_CLKEN[REFOFSEL] Bits */ 2836 #define CS_CLKEN_REFOFSEL_OFS (15) /*!< REFOFSEL Bit Offset */ 2837 #define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /*!< Selects REFO nominal frequency */ 2838 /* CS_STAT[DCO_ON] Bits */ 2839 #define CS_STAT_DCO_ON_OFS ( 0) /*!< DCO_ON Bit Offset */ 2840 #define CS_STAT_DCO_ON ((uint32_t)0x00000001) /*!< DCO status */ 2841 /* CS_STAT[DCOBIAS_ON] Bits */ 2842 #define CS_STAT_DCOBIAS_ON_OFS ( 1) /*!< DCOBIAS_ON Bit Offset */ 2843 #define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /*!< DCO bias status */ 2844 /* CS_STAT[HFXT_ON] Bits */ 2845 #define CS_STAT_HFXT_ON_OFS ( 2) /*!< HFXT_ON Bit Offset */ 2846 #define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /*!< HFXT status */ 2847 /* CS_STAT[MODOSC_ON] Bits */ 2848 #define CS_STAT_MODOSC_ON_OFS ( 4) /*!< MODOSC_ON Bit Offset */ 2849 #define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /*!< MODOSC status */ 2850 /* CS_STAT[VLO_ON] Bits */ 2851 #define CS_STAT_VLO_ON_OFS ( 5) /*!< VLO_ON Bit Offset */ 2852 #define CS_STAT_VLO_ON ((uint32_t)0x00000020) /*!< VLO status */ 2853 /* CS_STAT[LFXT_ON] Bits */ 2854 #define CS_STAT_LFXT_ON_OFS ( 6) /*!< LFXT_ON Bit Offset */ 2855 #define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /*!< LFXT status */ 2856 /* CS_STAT[REFO_ON] Bits */ 2857 #define CS_STAT_REFO_ON_OFS ( 7) /*!< REFO_ON Bit Offset */ 2858 #define CS_STAT_REFO_ON ((uint32_t)0x00000080) /*!< REFO status */ 2859 /* CS_STAT[ACLK_ON] Bits */ 2860 #define CS_STAT_ACLK_ON_OFS (16) /*!< ACLK_ON Bit Offset */ 2861 #define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /*!< ACLK system clock status */ 2862 /* CS_STAT[MCLK_ON] Bits */ 2863 #define CS_STAT_MCLK_ON_OFS (17) /*!< MCLK_ON Bit Offset */ 2864 #define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /*!< MCLK system clock status */ 2865 /* CS_STAT[HSMCLK_ON] Bits */ 2866 #define CS_STAT_HSMCLK_ON_OFS (18) /*!< HSMCLK_ON Bit Offset */ 2867 #define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /*!< HSMCLK system clock status */ 2868 /* CS_STAT[SMCLK_ON] Bits */ 2869 #define CS_STAT_SMCLK_ON_OFS (19) /*!< SMCLK_ON Bit Offset */ 2870 #define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /*!< SMCLK system clock status */ 2871 /* CS_STAT[MODCLK_ON] Bits */ 2872 #define CS_STAT_MODCLK_ON_OFS (20) /*!< MODCLK_ON Bit Offset */ 2873 #define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /*!< MODCLK system clock status */ 2874 /* CS_STAT[VLOCLK_ON] Bits */ 2875 #define CS_STAT_VLOCLK_ON_OFS (21) /*!< VLOCLK_ON Bit Offset */ 2876 #define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /*!< VLOCLK system clock status */ 2877 /* CS_STAT[LFXTCLK_ON] Bits */ 2878 #define CS_STAT_LFXTCLK_ON_OFS (22) /*!< LFXTCLK_ON Bit Offset */ 2879 #define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /*!< LFXTCLK system clock status */ 2880 /* CS_STAT[REFOCLK_ON] Bits */ 2881 #define CS_STAT_REFOCLK_ON_OFS (23) /*!< REFOCLK_ON Bit Offset */ 2882 #define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /*!< REFOCLK system clock status */ 2883 /* CS_STAT[ACLK_READY] Bits */ 2884 #define CS_STAT_ACLK_READY_OFS (24) /*!< ACLK_READY Bit Offset */ 2885 #define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /*!< ACLK Ready status */ 2886 /* CS_STAT[MCLK_READY] Bits */ 2887 #define CS_STAT_MCLK_READY_OFS (25) /*!< MCLK_READY Bit Offset */ 2888 #define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /*!< MCLK Ready status */ 2889 /* CS_STAT[HSMCLK_READY] Bits */ 2890 #define CS_STAT_HSMCLK_READY_OFS (26) /*!< HSMCLK_READY Bit Offset */ 2891 #define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /*!< HSMCLK Ready status */ 2892 /* CS_STAT[SMCLK_READY] Bits */ 2893 #define CS_STAT_SMCLK_READY_OFS (27) /*!< SMCLK_READY Bit Offset */ 2894 #define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /*!< SMCLK Ready status */ 2895 /* CS_STAT[BCLK_READY] Bits */ 2896 #define CS_STAT_BCLK_READY_OFS (28) /*!< BCLK_READY Bit Offset */ 2897 #define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /*!< BCLK Ready status */ 2898 /* CS_IE[LFXTIE] Bits */ 2899 #define CS_IE_LFXTIE_OFS ( 0) /*!< LFXTIE Bit Offset */ 2900 #define CS_IE_LFXTIE ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag interrupt enable */ 2901 /* CS_IE[HFXTIE] Bits */ 2902 #define CS_IE_HFXTIE_OFS ( 1) /*!< HFXTIE Bit Offset */ 2903 #define CS_IE_HFXTIE ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag interrupt enable */ 2904 /* CS_IE[DCOR_OPNIE] Bits */ 2905 #define CS_IE_DCOR_OPNIE_OFS ( 6) /*!< DCOR_OPNIE Bit Offset */ 2906 #define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag interrupt enable. */ 2907 /* CS_IE[FCNTLFIE] Bits */ 2908 #define CS_IE_FCNTLFIE_OFS ( 8) /*!< FCNTLFIE Bit Offset */ 2909 #define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /*!< Start fault counter interrupt enable LFXT */ 2910 /* CS_IE[FCNTHFIE] Bits */ 2911 #define CS_IE_FCNTHFIE_OFS ( 9) /*!< FCNTHFIE Bit Offset */ 2912 #define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /*!< Start fault counter interrupt enable HFXT */ 2913 /* CS_IFG[LFXTIFG] Bits */ 2914 #define CS_IFG_LFXTIFG_OFS ( 0) /*!< LFXTIFG Bit Offset */ 2915 #define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag */ 2916 /* CS_IFG[HFXTIFG] Bits */ 2917 #define CS_IFG_HFXTIFG_OFS ( 1) /*!< HFXTIFG Bit Offset */ 2918 #define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag */ 2919 /* CS_IFG[DCOR_SHTIFG] Bits */ 2920 #define CS_IFG_DCOR_SHTIFG_OFS ( 5) /*!< DCOR_SHTIFG Bit Offset */ 2921 #define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /*!< DCO external resistor short circuit fault flag. */ 2922 /* CS_IFG[DCOR_OPNIFG] Bits */ 2923 #define CS_IFG_DCOR_OPNIFG_OFS ( 6) /*!< DCOR_OPNIFG Bit Offset */ 2924 #define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag. */ 2925 /* CS_IFG[FCNTLFIFG] Bits */ 2926 #define CS_IFG_FCNTLFIFG_OFS ( 8) /*!< FCNTLFIFG Bit Offset */ 2927 #define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter interrupt flag LFXT */ 2928 /* CS_IFG[FCNTHFIFG] Bits */ 2929 #define CS_IFG_FCNTHFIFG_OFS ( 9) /*!< FCNTHFIFG Bit Offset */ 2930 #define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter interrupt flag HFXT */ 2931 /* CS_CLRIFG[CLR_LFXTIFG] Bits */ 2932 #define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /*!< CLR_LFXTIFG Bit Offset */ 2933 #define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /*!< Clear LFXT oscillator fault interrupt flag */ 2934 /* CS_CLRIFG[CLR_HFXTIFG] Bits */ 2935 #define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /*!< CLR_HFXTIFG Bit Offset */ 2936 #define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /*!< Clear HFXT oscillator fault interrupt flag */ 2937 /* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */ 2938 #define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /*!< CLR_DCOR_OPNIFG Bit Offset */ 2939 #define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Clear DCO external resistor open circuit fault interrupt flag. */ 2940 /* CS_CLRIFG[CLR_FCNTLFIFG] Bits */ 2941 #define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /*!< CLR_FCNTLFIFG Bit Offset */ 2942 #define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter clear interrupt flag LFXT */ 2943 /* CS_CLRIFG[CLR_FCNTHFIFG] Bits */ 2944 #define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /*!< CLR_FCNTHFIFG Bit Offset */ 2945 #define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter clear interrupt flag HFXT */ 2946 /* CS_SETIFG[SET_LFXTIFG] Bits */ 2947 #define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /*!< SET_LFXTIFG Bit Offset */ 2948 #define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /*!< Set LFXT oscillator fault interrupt flag */ 2949 /* CS_SETIFG[SET_HFXTIFG] Bits */ 2950 #define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /*!< SET_HFXTIFG Bit Offset */ 2951 #define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /*!< Set HFXT oscillator fault interrupt flag */ 2952 /* CS_SETIFG[SET_DCOR_OPNIFG] Bits */ 2953 #define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /*!< SET_DCOR_OPNIFG Bit Offset */ 2954 #define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Set DCO external resistor open circuit fault interrupt flag. */ 2955 /* CS_SETIFG[SET_FCNTHFIFG] Bits */ 2956 #define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /*!< SET_FCNTHFIFG Bit Offset */ 2957 #define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter set interrupt flag HFXT */ 2958 /* CS_SETIFG[SET_FCNTLFIFG] Bits */ 2959 #define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /*!< SET_FCNTLFIFG Bit Offset */ 2960 #define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter set interrupt flag LFXT */ 2961 /* CS_DCOERCAL0[DCO_TCCAL] Bits */ 2962 #define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /*!< DCO_TCCAL Bit Offset */ 2963 #define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /*!< DCO_TCCAL Bit Mask */ 2964 /* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */ 2965 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /*!< DCO_FCAL_RSEL04 Bit Offset */ 2966 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /*!< DCO_FCAL_RSEL04 Bit Mask */ 2967 /* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */ 2968 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /*!< DCO_FCAL_RSEL5 Bit Offset */ 2969 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /*!< DCO_FCAL_RSEL5 Bit Mask */ 2970 /* Pre-defined bitfield values */ 2971 #define CS_KEY_VAL ((uint32_t)0x0000695A) /*!< CS control key value */ 2972 2973 /****************************************************************************** 2974 * DIO Bits 2975 ******************************************************************************/ 2976 /* DIO_IV[IV] Bits */ 2977 #define DIO_PORT_IV_OFS ( 0) /*!< DIO Port IV Bit Offset */ 2978 #define DIO_PORT_IV_MASK ((uint16_t)0x001F) /*!< DIO Port IV Bit Mask */ 2979 #define DIO_PORT_IV0 ((uint16_t)0x0001) /*!< DIO Port IV Bit 0 */ 2980 #define DIO_PORT_IV1 ((uint16_t)0x0002) /*!< DIO Port IV Bit 1 */ 2981 #define DIO_PORT_IV2 ((uint16_t)0x0004) /*!< DIO Port IV Bit 2 */ 2982 #define DIO_PORT_IV3 ((uint16_t)0x0008) /*!< DIO Port IV Bit 3 */ 2983 #define DIO_PORT_IV4 ((uint16_t)0x0010) /*!< DIO Port IV Bit 4 */ 2984 #define DIO_PORT_IV_0 ((uint16_t)0x0000) /*!< No interrupt pending */ 2985 #define DIO_PORT_IV_2 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ 2986 /* Priority: Highest */ 2987 #define DIO_PORT_IV_4 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ 2988 #define DIO_PORT_IV_6 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ 2989 #define DIO_PORT_IV_8 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ 2990 #define DIO_PORT_IV_10 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ 2991 #define DIO_PORT_IV_12 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ 2992 #define DIO_PORT_IV_14 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ 2993 #define DIO_PORT_IV_16 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ 2994 /* Priority: Lowest */ 2995 #define DIO_PORT_IV__NONE ((uint16_t)0x0000) /*!< No interrupt pending */ 2996 #define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ 2997 /* Priority: Highest */ 2998 #define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ 2999 #define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ 3000 #define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ 3001 #define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ 3002 #define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ 3003 #define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ 3004 #define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ 3005 /* Priority: Lowest */ 3006 3007 3008 /****************************************************************************** 3009 * DMA Bits 3010 ******************************************************************************/ 3011 /* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */ 3012 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /*!< NUM_DMA_CHANNELS Bit Offset */ 3013 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /*!< NUM_DMA_CHANNELS Bit Mask */ 3014 /* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */ 3015 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /*!< NUM_SRC_PER_CHANNEL Bit Offset */ 3016 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /*!< NUM_SRC_PER_CHANNEL Bit Mask */ 3017 /* DMA_SW_CHTRIG[CH0] Bits */ 3018 #define DMA_SW_CHTRIG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ 3019 #define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /*!< Write 1, triggers DMA_CHANNEL0 */ 3020 /* DMA_SW_CHTRIG[CH1] Bits */ 3021 #define DMA_SW_CHTRIG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ 3022 #define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /*!< Write 1, triggers DMA_CHANNEL1 */ 3023 /* DMA_SW_CHTRIG[CH2] Bits */ 3024 #define DMA_SW_CHTRIG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ 3025 #define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /*!< Write 1, triggers DMA_CHANNEL2 */ 3026 /* DMA_SW_CHTRIG[CH3] Bits */ 3027 #define DMA_SW_CHTRIG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ 3028 #define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /*!< Write 1, triggers DMA_CHANNEL3 */ 3029 /* DMA_SW_CHTRIG[CH4] Bits */ 3030 #define DMA_SW_CHTRIG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ 3031 #define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /*!< Write 1, triggers DMA_CHANNEL4 */ 3032 /* DMA_SW_CHTRIG[CH5] Bits */ 3033 #define DMA_SW_CHTRIG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ 3034 #define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /*!< Write 1, triggers DMA_CHANNEL5 */ 3035 /* DMA_SW_CHTRIG[CH6] Bits */ 3036 #define DMA_SW_CHTRIG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ 3037 #define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /*!< Write 1, triggers DMA_CHANNEL6 */ 3038 /* DMA_SW_CHTRIG[CH7] Bits */ 3039 #define DMA_SW_CHTRIG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ 3040 #define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /*!< Write 1, triggers DMA_CHANNEL7 */ 3041 /* DMA_SW_CHTRIG[CH8] Bits */ 3042 #define DMA_SW_CHTRIG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ 3043 #define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /*!< Write 1, triggers DMA_CHANNEL8 */ 3044 /* DMA_SW_CHTRIG[CH9] Bits */ 3045 #define DMA_SW_CHTRIG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ 3046 #define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /*!< Write 1, triggers DMA_CHANNEL9 */ 3047 /* DMA_SW_CHTRIG[CH10] Bits */ 3048 #define DMA_SW_CHTRIG_CH10_OFS (10) /*!< CH10 Bit Offset */ 3049 #define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /*!< Write 1, triggers DMA_CHANNEL10 */ 3050 /* DMA_SW_CHTRIG[CH11] Bits */ 3051 #define DMA_SW_CHTRIG_CH11_OFS (11) /*!< CH11 Bit Offset */ 3052 #define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /*!< Write 1, triggers DMA_CHANNEL11 */ 3053 /* DMA_SW_CHTRIG[CH12] Bits */ 3054 #define DMA_SW_CHTRIG_CH12_OFS (12) /*!< CH12 Bit Offset */ 3055 #define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /*!< Write 1, triggers DMA_CHANNEL12 */ 3056 /* DMA_SW_CHTRIG[CH13] Bits */ 3057 #define DMA_SW_CHTRIG_CH13_OFS (13) /*!< CH13 Bit Offset */ 3058 #define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /*!< Write 1, triggers DMA_CHANNEL13 */ 3059 /* DMA_SW_CHTRIG[CH14] Bits */ 3060 #define DMA_SW_CHTRIG_CH14_OFS (14) /*!< CH14 Bit Offset */ 3061 #define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /*!< Write 1, triggers DMA_CHANNEL14 */ 3062 /* DMA_SW_CHTRIG[CH15] Bits */ 3063 #define DMA_SW_CHTRIG_CH15_OFS (15) /*!< CH15 Bit Offset */ 3064 #define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /*!< Write 1, triggers DMA_CHANNEL15 */ 3065 /* DMA_SW_CHTRIG[CH16] Bits */ 3066 #define DMA_SW_CHTRIG_CH16_OFS (16) /*!< CH16 Bit Offset */ 3067 #define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /*!< Write 1, triggers DMA_CHANNEL16 */ 3068 /* DMA_SW_CHTRIG[CH17] Bits */ 3069 #define DMA_SW_CHTRIG_CH17_OFS (17) /*!< CH17 Bit Offset */ 3070 #define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /*!< Write 1, triggers DMA_CHANNEL17 */ 3071 /* DMA_SW_CHTRIG[CH18] Bits */ 3072 #define DMA_SW_CHTRIG_CH18_OFS (18) /*!< CH18 Bit Offset */ 3073 #define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /*!< Write 1, triggers DMA_CHANNEL18 */ 3074 /* DMA_SW_CHTRIG[CH19] Bits */ 3075 #define DMA_SW_CHTRIG_CH19_OFS (19) /*!< CH19 Bit Offset */ 3076 #define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /*!< Write 1, triggers DMA_CHANNEL19 */ 3077 /* DMA_SW_CHTRIG[CH20] Bits */ 3078 #define DMA_SW_CHTRIG_CH20_OFS (20) /*!< CH20 Bit Offset */ 3079 #define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /*!< Write 1, triggers DMA_CHANNEL20 */ 3080 /* DMA_SW_CHTRIG[CH21] Bits */ 3081 #define DMA_SW_CHTRIG_CH21_OFS (21) /*!< CH21 Bit Offset */ 3082 #define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /*!< Write 1, triggers DMA_CHANNEL21 */ 3083 /* DMA_SW_CHTRIG[CH22] Bits */ 3084 #define DMA_SW_CHTRIG_CH22_OFS (22) /*!< CH22 Bit Offset */ 3085 #define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /*!< Write 1, triggers DMA_CHANNEL22 */ 3086 /* DMA_SW_CHTRIG[CH23] Bits */ 3087 #define DMA_SW_CHTRIG_CH23_OFS (23) /*!< CH23 Bit Offset */ 3088 #define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /*!< Write 1, triggers DMA_CHANNEL23 */ 3089 /* DMA_SW_CHTRIG[CH24] Bits */ 3090 #define DMA_SW_CHTRIG_CH24_OFS (24) /*!< CH24 Bit Offset */ 3091 #define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /*!< Write 1, triggers DMA_CHANNEL24 */ 3092 /* DMA_SW_CHTRIG[CH25] Bits */ 3093 #define DMA_SW_CHTRIG_CH25_OFS (25) /*!< CH25 Bit Offset */ 3094 #define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /*!< Write 1, triggers DMA_CHANNEL25 */ 3095 /* DMA_SW_CHTRIG[CH26] Bits */ 3096 #define DMA_SW_CHTRIG_CH26_OFS (26) /*!< CH26 Bit Offset */ 3097 #define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /*!< Write 1, triggers DMA_CHANNEL26 */ 3098 /* DMA_SW_CHTRIG[CH27] Bits */ 3099 #define DMA_SW_CHTRIG_CH27_OFS (27) /*!< CH27 Bit Offset */ 3100 #define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /*!< Write 1, triggers DMA_CHANNEL27 */ 3101 /* DMA_SW_CHTRIG[CH28] Bits */ 3102 #define DMA_SW_CHTRIG_CH28_OFS (28) /*!< CH28 Bit Offset */ 3103 #define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /*!< Write 1, triggers DMA_CHANNEL28 */ 3104 /* DMA_SW_CHTRIG[CH29] Bits */ 3105 #define DMA_SW_CHTRIG_CH29_OFS (29) /*!< CH29 Bit Offset */ 3106 #define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /*!< Write 1, triggers DMA_CHANNEL29 */ 3107 /* DMA_SW_CHTRIG[CH30] Bits */ 3108 #define DMA_SW_CHTRIG_CH30_OFS (30) /*!< CH30 Bit Offset */ 3109 #define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /*!< Write 1, triggers DMA_CHANNEL30 */ 3110 /* DMA_SW_CHTRIG[CH31] Bits */ 3111 #define DMA_SW_CHTRIG_CH31_OFS (31) /*!< CH31 Bit Offset */ 3112 #define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /*!< Write 1, triggers DMA_CHANNEL31 */ 3113 /* DMA_CHN_SRCCFG[DMA_SRC] Bits */ 3114 #define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /*!< DMA_SRC Bit Offset */ 3115 #define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /*!< DMA_SRC Bit Mask */ 3116 /* DMA_INT1_SRCCFG[INT_SRC] Bits */ 3117 #define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ 3118 #define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ 3119 /* DMA_INT1_SRCCFG[EN] Bits */ 3120 #define DMA_INT1_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ 3121 #define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT1 mapping */ 3122 /* DMA_INT2_SRCCFG[INT_SRC] Bits */ 3123 #define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ 3124 #define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ 3125 /* DMA_INT2_SRCCFG[EN] Bits */ 3126 #define DMA_INT2_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ 3127 #define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT2 mapping */ 3128 /* DMA_INT3_SRCCFG[INT_SRC] Bits */ 3129 #define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ 3130 #define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ 3131 /* DMA_INT3_SRCCFG[EN] Bits */ 3132 #define DMA_INT3_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ 3133 #define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT3 mapping */ 3134 /* DMA_INT0_SRCFLG[CH0] Bits */ 3135 #define DMA_INT0_SRCFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ 3136 #define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /*!< Channel 0 was the source of DMA_INT0 */ 3137 /* DMA_INT0_SRCFLG[CH1] Bits */ 3138 #define DMA_INT0_SRCFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ 3139 #define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /*!< Channel 1 was the source of DMA_INT0 */ 3140 /* DMA_INT0_SRCFLG[CH2] Bits */ 3141 #define DMA_INT0_SRCFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ 3142 #define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /*!< Channel 2 was the source of DMA_INT0 */ 3143 /* DMA_INT0_SRCFLG[CH3] Bits */ 3144 #define DMA_INT0_SRCFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ 3145 #define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /*!< Channel 3 was the source of DMA_INT0 */ 3146 /* DMA_INT0_SRCFLG[CH4] Bits */ 3147 #define DMA_INT0_SRCFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ 3148 #define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /*!< Channel 4 was the source of DMA_INT0 */ 3149 /* DMA_INT0_SRCFLG[CH5] Bits */ 3150 #define DMA_INT0_SRCFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ 3151 #define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /*!< Channel 5 was the source of DMA_INT0 */ 3152 /* DMA_INT0_SRCFLG[CH6] Bits */ 3153 #define DMA_INT0_SRCFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ 3154 #define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /*!< Channel 6 was the source of DMA_INT0 */ 3155 /* DMA_INT0_SRCFLG[CH7] Bits */ 3156 #define DMA_INT0_SRCFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ 3157 #define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /*!< Channel 7 was the source of DMA_INT0 */ 3158 /* DMA_INT0_SRCFLG[CH8] Bits */ 3159 #define DMA_INT0_SRCFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ 3160 #define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /*!< Channel 8 was the source of DMA_INT0 */ 3161 /* DMA_INT0_SRCFLG[CH9] Bits */ 3162 #define DMA_INT0_SRCFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ 3163 #define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /*!< Channel 9 was the source of DMA_INT0 */ 3164 /* DMA_INT0_SRCFLG[CH10] Bits */ 3165 #define DMA_INT0_SRCFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ 3166 #define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /*!< Channel 10 was the source of DMA_INT0 */ 3167 /* DMA_INT0_SRCFLG[CH11] Bits */ 3168 #define DMA_INT0_SRCFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ 3169 #define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /*!< Channel 11 was the source of DMA_INT0 */ 3170 /* DMA_INT0_SRCFLG[CH12] Bits */ 3171 #define DMA_INT0_SRCFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ 3172 #define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /*!< Channel 12 was the source of DMA_INT0 */ 3173 /* DMA_INT0_SRCFLG[CH13] Bits */ 3174 #define DMA_INT0_SRCFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ 3175 #define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /*!< Channel 13 was the source of DMA_INT0 */ 3176 /* DMA_INT0_SRCFLG[CH14] Bits */ 3177 #define DMA_INT0_SRCFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ 3178 #define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /*!< Channel 14 was the source of DMA_INT0 */ 3179 /* DMA_INT0_SRCFLG[CH15] Bits */ 3180 #define DMA_INT0_SRCFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ 3181 #define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /*!< Channel 15 was the source of DMA_INT0 */ 3182 /* DMA_INT0_SRCFLG[CH16] Bits */ 3183 #define DMA_INT0_SRCFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ 3184 #define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /*!< Channel 16 was the source of DMA_INT0 */ 3185 /* DMA_INT0_SRCFLG[CH17] Bits */ 3186 #define DMA_INT0_SRCFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ 3187 #define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /*!< Channel 17 was the source of DMA_INT0 */ 3188 /* DMA_INT0_SRCFLG[CH18] Bits */ 3189 #define DMA_INT0_SRCFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ 3190 #define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /*!< Channel 18 was the source of DMA_INT0 */ 3191 /* DMA_INT0_SRCFLG[CH19] Bits */ 3192 #define DMA_INT0_SRCFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ 3193 #define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /*!< Channel 19 was the source of DMA_INT0 */ 3194 /* DMA_INT0_SRCFLG[CH20] Bits */ 3195 #define DMA_INT0_SRCFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ 3196 #define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /*!< Channel 20 was the source of DMA_INT0 */ 3197 /* DMA_INT0_SRCFLG[CH21] Bits */ 3198 #define DMA_INT0_SRCFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ 3199 #define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /*!< Channel 21 was the source of DMA_INT0 */ 3200 /* DMA_INT0_SRCFLG[CH22] Bits */ 3201 #define DMA_INT0_SRCFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ 3202 #define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /*!< Channel 22 was the source of DMA_INT0 */ 3203 /* DMA_INT0_SRCFLG[CH23] Bits */ 3204 #define DMA_INT0_SRCFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ 3205 #define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /*!< Channel 23 was the source of DMA_INT0 */ 3206 /* DMA_INT0_SRCFLG[CH24] Bits */ 3207 #define DMA_INT0_SRCFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ 3208 #define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /*!< Channel 24 was the source of DMA_INT0 */ 3209 /* DMA_INT0_SRCFLG[CH25] Bits */ 3210 #define DMA_INT0_SRCFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ 3211 #define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /*!< Channel 25 was the source of DMA_INT0 */ 3212 /* DMA_INT0_SRCFLG[CH26] Bits */ 3213 #define DMA_INT0_SRCFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ 3214 #define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /*!< Channel 26 was the source of DMA_INT0 */ 3215 /* DMA_INT0_SRCFLG[CH27] Bits */ 3216 #define DMA_INT0_SRCFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ 3217 #define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /*!< Channel 27 was the source of DMA_INT0 */ 3218 /* DMA_INT0_SRCFLG[CH28] Bits */ 3219 #define DMA_INT0_SRCFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ 3220 #define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /*!< Channel 28 was the source of DMA_INT0 */ 3221 /* DMA_INT0_SRCFLG[CH29] Bits */ 3222 #define DMA_INT0_SRCFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ 3223 #define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /*!< Channel 29 was the source of DMA_INT0 */ 3224 /* DMA_INT0_SRCFLG[CH30] Bits */ 3225 #define DMA_INT0_SRCFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ 3226 #define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /*!< Channel 30 was the source of DMA_INT0 */ 3227 /* DMA_INT0_SRCFLG[CH31] Bits */ 3228 #define DMA_INT0_SRCFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ 3229 #define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /*!< Channel 31 was the source of DMA_INT0 */ 3230 /* DMA_INT0_CLRFLG[CH0] Bits */ 3231 #define DMA_INT0_CLRFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ 3232 #define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3233 /* DMA_INT0_CLRFLG[CH1] Bits */ 3234 #define DMA_INT0_CLRFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ 3235 #define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3236 /* DMA_INT0_CLRFLG[CH2] Bits */ 3237 #define DMA_INT0_CLRFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ 3238 #define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3239 /* DMA_INT0_CLRFLG[CH3] Bits */ 3240 #define DMA_INT0_CLRFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ 3241 #define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3242 /* DMA_INT0_CLRFLG[CH4] Bits */ 3243 #define DMA_INT0_CLRFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ 3244 #define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3245 /* DMA_INT0_CLRFLG[CH5] Bits */ 3246 #define DMA_INT0_CLRFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ 3247 #define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3248 /* DMA_INT0_CLRFLG[CH6] Bits */ 3249 #define DMA_INT0_CLRFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ 3250 #define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3251 /* DMA_INT0_CLRFLG[CH7] Bits */ 3252 #define DMA_INT0_CLRFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ 3253 #define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3254 /* DMA_INT0_CLRFLG[CH8] Bits */ 3255 #define DMA_INT0_CLRFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ 3256 #define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3257 /* DMA_INT0_CLRFLG[CH9] Bits */ 3258 #define DMA_INT0_CLRFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ 3259 #define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3260 /* DMA_INT0_CLRFLG[CH10] Bits */ 3261 #define DMA_INT0_CLRFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ 3262 #define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3263 /* DMA_INT0_CLRFLG[CH11] Bits */ 3264 #define DMA_INT0_CLRFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ 3265 #define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3266 /* DMA_INT0_CLRFLG[CH12] Bits */ 3267 #define DMA_INT0_CLRFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ 3268 #define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3269 /* DMA_INT0_CLRFLG[CH13] Bits */ 3270 #define DMA_INT0_CLRFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ 3271 #define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3272 /* DMA_INT0_CLRFLG[CH14] Bits */ 3273 #define DMA_INT0_CLRFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ 3274 #define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3275 /* DMA_INT0_CLRFLG[CH15] Bits */ 3276 #define DMA_INT0_CLRFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ 3277 #define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3278 /* DMA_INT0_CLRFLG[CH16] Bits */ 3279 #define DMA_INT0_CLRFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ 3280 #define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3281 /* DMA_INT0_CLRFLG[CH17] Bits */ 3282 #define DMA_INT0_CLRFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ 3283 #define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3284 /* DMA_INT0_CLRFLG[CH18] Bits */ 3285 #define DMA_INT0_CLRFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ 3286 #define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3287 /* DMA_INT0_CLRFLG[CH19] Bits */ 3288 #define DMA_INT0_CLRFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ 3289 #define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3290 /* DMA_INT0_CLRFLG[CH20] Bits */ 3291 #define DMA_INT0_CLRFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ 3292 #define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3293 /* DMA_INT0_CLRFLG[CH21] Bits */ 3294 #define DMA_INT0_CLRFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ 3295 #define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3296 /* DMA_INT0_CLRFLG[CH22] Bits */ 3297 #define DMA_INT0_CLRFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ 3298 #define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3299 /* DMA_INT0_CLRFLG[CH23] Bits */ 3300 #define DMA_INT0_CLRFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ 3301 #define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3302 /* DMA_INT0_CLRFLG[CH24] Bits */ 3303 #define DMA_INT0_CLRFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ 3304 #define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3305 /* DMA_INT0_CLRFLG[CH25] Bits */ 3306 #define DMA_INT0_CLRFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ 3307 #define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3308 /* DMA_INT0_CLRFLG[CH26] Bits */ 3309 #define DMA_INT0_CLRFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ 3310 #define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3311 /* DMA_INT0_CLRFLG[CH27] Bits */ 3312 #define DMA_INT0_CLRFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ 3313 #define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3314 /* DMA_INT0_CLRFLG[CH28] Bits */ 3315 #define DMA_INT0_CLRFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ 3316 #define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3317 /* DMA_INT0_CLRFLG[CH29] Bits */ 3318 #define DMA_INT0_CLRFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ 3319 #define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3320 /* DMA_INT0_CLRFLG[CH30] Bits */ 3321 #define DMA_INT0_CLRFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ 3322 #define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3323 /* DMA_INT0_CLRFLG[CH31] Bits */ 3324 #define DMA_INT0_CLRFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ 3325 #define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3326 /* DMA_STAT[MASTEN] Bits */ 3327 #define DMA_STAT_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ 3328 #define DMA_STAT_MASTEN ((uint32_t)0x00000001) 3329 /* DMA_STAT[STATE] Bits */ 3330 #define DMA_STAT_STATE_OFS ( 4) /*!< STATE Bit Offset */ 3331 #define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /*!< STATE Bit Mask */ 3332 #define DMA_STAT_STATE0 ((uint32_t)0x00000010) /*!< STATE Bit 0 */ 3333 #define DMA_STAT_STATE1 ((uint32_t)0x00000020) /*!< STATE Bit 1 */ 3334 #define DMA_STAT_STATE2 ((uint32_t)0x00000040) /*!< STATE Bit 2 */ 3335 #define DMA_STAT_STATE3 ((uint32_t)0x00000080) /*!< STATE Bit 3 */ 3336 #define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /*!< idle */ 3337 #define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /*!< reading channel controller data */ 3338 #define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /*!< reading source data end pointer */ 3339 #define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /*!< reading destination data end pointer */ 3340 #define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /*!< reading source data */ 3341 #define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /*!< writing destination data */ 3342 #define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /*!< waiting for DMA request to clear */ 3343 #define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /*!< writing channel controller data */ 3344 #define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /*!< stalled */ 3345 #define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /*!< done */ 3346 #define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /*!< peripheral scatter-gather transition */ 3347 #define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /*!< Reserved */ 3348 #define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /*!< Reserved */ 3349 #define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /*!< Reserved */ 3350 #define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /*!< Reserved */ 3351 #define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /*!< Reserved */ 3352 /* DMA_STAT[DMACHANS] Bits */ 3353 #define DMA_STAT_DMACHANS_OFS (16) /*!< DMACHANS Bit Offset */ 3354 #define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /*!< DMACHANS Bit Mask */ 3355 #define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /*!< DMACHANS Bit 0 */ 3356 #define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /*!< DMACHANS Bit 1 */ 3357 #define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /*!< DMACHANS Bit 2 */ 3358 #define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /*!< DMACHANS Bit 3 */ 3359 #define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /*!< DMACHANS Bit 4 */ 3360 #define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /*!< Controller configured to use 1 DMA channel */ 3361 #define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /*!< Controller configured to use 2 DMA channels */ 3362 #define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /*!< Controller configured to use 31 DMA channels */ 3363 #define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /*!< Controller configured to use 32 DMA channels */ 3364 /* DMA_STAT[TESTSTAT] Bits */ 3365 #define DMA_STAT_TESTSTAT_OFS (28) /*!< TESTSTAT Bit Offset */ 3366 #define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /*!< TESTSTAT Bit Mask */ 3367 #define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /*!< TESTSTAT Bit 0 */ 3368 #define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /*!< TESTSTAT Bit 1 */ 3369 #define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /*!< TESTSTAT Bit 2 */ 3370 #define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /*!< TESTSTAT Bit 3 */ 3371 #define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /*!< Controller does not include the integration test logic */ 3372 #define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /*!< Controller includes the integration test logic */ 3373 /* DMA_CFG[MASTEN] Bits */ 3374 #define DMA_CFG_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ 3375 #define DMA_CFG_MASTEN ((uint32_t)0x00000001) 3376 /* DMA_CFG[CHPROTCTRL] Bits */ 3377 #define DMA_CFG_CHPROTCTRL_OFS ( 5) /*!< CHPROTCTRL Bit Offset */ 3378 #define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /*!< CHPROTCTRL Bit Mask */ 3379 /* DMA_CTLBASE[ADDR] Bits */ 3380 #define DMA_CTLBASE_ADDR_OFS ( 5) /*!< ADDR Bit Offset */ 3381 #define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /*!< ADDR Bit Mask */ 3382 /* DMA_ERRCLR[ERRCLR] Bits */ 3383 #define DMA_ERRCLR_ERRCLR_OFS ( 0) /*!< ERRCLR Bit Offset */ 3384 #define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) 3385 /* DMA channel definitions and memory structure alignment */ 3386 #define __MCU_NUM_DMA_CHANNELS__ 8 3387 #define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10 3388 #define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE) 3389 3390 /* UDMA_STAT Control Bits */ 3391 #define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /*!< Available uDMA Channels Minus 1 */ 3392 #define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /*!< Control State Machine Status */ 3393 #define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /*!< Idle */ 3394 #define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /*!< Reading channel controller data */ 3395 #define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /*!< Reading source end pointer */ 3396 #define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /*!< Reading destination end pointer */ 3397 #define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /*!< Reading source data */ 3398 #define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /*!< Writing destination data */ 3399 #define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /*!< Waiting for uDMA request to clear */ 3400 #define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /*!< Writing channel controller data */ 3401 #define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /*!< Stalled */ 3402 #define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /*!< Done */ 3403 #define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /*!< Undefined */ 3404 #define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /*!< Master Enable Status */ 3405 #define UDMA_STAT_DMACHANS_S (16) 3406 3407 /* UDMA_CFG Control Bits */ 3408 #define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /*!< Controller Master Enable */ 3409 3410 /* UDMA_CTLBASE Control Bits */ 3411 #define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /*!< Channel Control Base Address */ 3412 #define UDMA_CTLBASE_ADDR_S (10) 3413 3414 /* UDMA_ALTBASE Control Bits */ 3415 #define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Alternate Channel Address Pointer */ 3416 #define UDMA_ALTBASE_ADDR_S ( 0) 3417 3418 /* UDMA_WAITSTAT Control Bits */ 3419 #define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Wait Status */ 3420 3421 /* UDMA_SWREQ Control Bits */ 3422 #define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Software Request */ 3423 3424 /* UDMA_USEBURSTSET Control Bits */ 3425 #define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Set */ 3426 3427 /* UDMA_USEBURSTCLR Control Bits */ 3428 #define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Clear */ 3429 3430 /* UDMA_REQMASKSET Control Bits */ 3431 #define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Set */ 3432 3433 /* UDMA_REQMASKCLR Control Bits */ 3434 #define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Clear */ 3435 3436 /* UDMA_ENASET Control Bits */ 3437 #define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Enable Set */ 3438 3439 /* UDMA_ENACLR Control Bits */ 3440 #define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Clear Channel [n] Enable Clear */ 3441 3442 /* UDMA_ALTSET Control Bits */ 3443 #define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Set */ 3444 3445 /* UDMA_ALTCLR Control Bits */ 3446 #define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Clear */ 3447 3448 /* UDMA_PRIOSET Control Bits */ 3449 #define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Set */ 3450 3451 /* UDMA_PRIOCLR Control Bits */ 3452 #define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Clear */ 3453 3454 /* UDMA_ERRCLR Control Bits */ 3455 #define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /*!< uDMA Bus Error Status */ 3456 3457 /* UDMA_CHASGN Control Bits */ 3458 #define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Assignment Select */ 3459 #define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /*!< Use the primary channel assignment */ 3460 #define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /*!< Use the secondary channel assignment */ 3461 3462 /* Micro Direct Memory Access (uDMA) offsets */ 3463 #define UDMA_O_SRCENDP ((uint32_t)0x00000000) /*!< DMA Channel Source Address End Pointer */ 3464 #define UDMA_O_DSTENDP ((uint32_t)0x00000004) /*!< DMA Channel Destination Address End Pointer */ 3465 #define UDMA_O_CHCTL ((uint32_t)0x00000008) /*!< DMA Channel Control Word */ 3466 3467 /* UDMA_O_SRCENDP Control Bits */ 3468 #define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Source Address End Pointer */ 3469 #define UDMA_SRCENDP_ADDR_S ( 0) 3470 3471 /* UDMA_O_DSTENDP Control Bits */ 3472 #define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Destination Address End Pointer */ 3473 #define UDMA_DSTENDP_ADDR_S ( 0) 3474 3475 /* UDMA_O_CHCTL Control Bits */ 3476 #define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /*!< Destination Address Increment */ 3477 #define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /*!< Byte */ 3478 #define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /*!< Half-word */ 3479 #define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /*!< Word */ 3480 #define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /*!< No increment */ 3481 #define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /*!< Destination Data Size */ 3482 #define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ 3483 #define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /*!< Half-word */ 3484 #define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /*!< Word */ 3485 #define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /*!< Source Address Increment */ 3486 #define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /*!< Byte */ 3487 #define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /*!< Half-word */ 3488 #define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /*!< Word */ 3489 #define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /*!< No increment */ 3490 #define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /*!< Source Data Size */ 3491 #define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ 3492 #define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /*!< Half-word */ 3493 #define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /*!< Word */ 3494 #define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /*!< Arbitration Size */ 3495 #define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /*!< 1 Transfer */ 3496 #define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /*!< 2 Transfers */ 3497 #define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /*!< 4 Transfers */ 3498 #define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /*!< 8 Transfers */ 3499 #define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /*!< 16 Transfers */ 3500 #define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /*!< 32 Transfers */ 3501 #define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /*!< 64 Transfers */ 3502 #define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /*!< 128 Transfers */ 3503 #define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /*!< 256 Transfers */ 3504 #define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /*!< 512 Transfers */ 3505 #define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /*!< 1024 Transfers */ 3506 #define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /*!< Transfer Size (minus 1) */ 3507 #define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /*!< Next Useburst */ 3508 #define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /*!< uDMA Transfer Mode */ 3509 #define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /*!< Stop */ 3510 #define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /*!< Basic */ 3511 #define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /*!< Auto-Request */ 3512 #define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /*!< Ping-Pong */ 3513 #define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /*!< Memory Scatter-Gather */ 3514 #define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /*!< Alternate Memory Scatter-Gather */ 3515 #define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /*!< Peripheral Scatter-Gather */ 3516 #define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /*!< Alternate Peripheral Scatter-Gather */ 3517 3518 #define UDMA_CHCTL_XFERSIZE_S ( 4) 3519 3520 3521 /****************************************************************************** 3522 * DWT Bits 3523 ******************************************************************************/ 3524 3525 3526 /****************************************************************************** 3527 * EUSCI_A Bits 3528 ******************************************************************************/ 3529 /* EUSCI_A_CTLW0[SWRST] Bits */ 3530 #define EUSCI_A_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ 3531 #define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ 3532 /* EUSCI_A_CTLW0[TXBRK] Bits */ 3533 #define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /*!< UCTXBRK Bit Offset */ 3534 #define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /*!< Transmit break */ 3535 /* EUSCI_A_CTLW0[TXADDR] Bits */ 3536 #define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /*!< UCTXADDR Bit Offset */ 3537 #define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /*!< Transmit address */ 3538 /* EUSCI_A_CTLW0[DORM] Bits */ 3539 #define EUSCI_A_CTLW0_DORM_OFS ( 3) /*!< UCDORM Bit Offset */ 3540 #define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /*!< Dormant */ 3541 /* EUSCI_A_CTLW0[BRKIE] Bits */ 3542 #define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /*!< UCBRKIE Bit Offset */ 3543 #define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /*!< Receive break character interrupt enable */ 3544 /* EUSCI_A_CTLW0[RXEIE] Bits */ 3545 #define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /*!< UCRXEIE Bit Offset */ 3546 #define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /*!< Receive erroneous-character interrupt enable */ 3547 /* EUSCI_A_CTLW0[SSEL] Bits */ 3548 #define EUSCI_A_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ 3549 #define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ 3550 #define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ 3551 #define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ 3552 #define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLK */ 3553 #define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ 3554 #define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ 3555 #define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /*!< UCLK */ 3556 #define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ 3557 #define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ 3558 /* EUSCI_A_CTLW0[SYNC] Bits */ 3559 #define EUSCI_A_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ 3560 #define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ 3561 /* EUSCI_A_CTLW0[MODE] Bits */ 3562 #define EUSCI_A_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ 3563 #define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ 3564 #define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ 3565 #define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ 3566 #define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< UART mode */ 3567 #define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< Idle-line multiprocessor mode */ 3568 #define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< Address-bit multiprocessor mode */ 3569 #define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< UART mode with automatic baud-rate detection */ 3570 /* EUSCI_A_CTLW0[SPB] Bits */ 3571 #define EUSCI_A_CTLW0_SPB_OFS (11) /*!< UCSPB Bit Offset */ 3572 #define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /*!< Stop bit select */ 3573 /* EUSCI_A_CTLW0[SEVENBIT] Bits */ 3574 #define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ 3575 #define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ 3576 /* EUSCI_A_CTLW0[MSB] Bits */ 3577 #define EUSCI_A_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ 3578 #define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ 3579 /* EUSCI_A_CTLW0[PAR] Bits */ 3580 #define EUSCI_A_CTLW0_PAR_OFS (14) /*!< UCPAR Bit Offset */ 3581 #define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /*!< Parity select */ 3582 /* EUSCI_A_CTLW0[PEN] Bits */ 3583 #define EUSCI_A_CTLW0_PEN_OFS (15) /*!< UCPEN Bit Offset */ 3584 #define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /*!< Parity enable */ 3585 /* EUSCI_A_CTLW0[STEM] Bits */ 3586 #define EUSCI_A_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ 3587 #define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ 3588 /* EUSCI_A_CTLW0[MST] Bits */ 3589 #define EUSCI_A_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ 3590 #define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ 3591 /* EUSCI_A_CTLW0[CKPL] Bits */ 3592 #define EUSCI_A_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ 3593 #define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ 3594 /* EUSCI_A_CTLW0[CKPH] Bits */ 3595 #define EUSCI_A_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ 3596 #define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ 3597 /* EUSCI_A_CTLW1[GLIT] Bits */ 3598 #define EUSCI_A_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ 3599 #define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ 3600 #define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ 3601 #define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ 3602 #define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< Approximately 2 ns (equivalent of 1 delay element) */ 3603 #define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< Approximately 50 ns */ 3604 #define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< Approximately 100 ns */ 3605 #define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< Approximately 200 ns */ 3606 /* EUSCI_A_MCTLW[OS16] Bits */ 3607 #define EUSCI_A_MCTLW_OS16_OFS ( 0) /*!< UCOS16 Bit Offset */ 3608 #define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /*!< Oversampling mode enabled */ 3609 /* EUSCI_A_MCTLW[BRF] Bits */ 3610 #define EUSCI_A_MCTLW_BRF_OFS ( 4) /*!< UCBRF Bit Offset */ 3611 #define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /*!< UCBRF Bit Mask */ 3612 /* EUSCI_A_MCTLW[BRS] Bits */ 3613 #define EUSCI_A_MCTLW_BRS_OFS ( 8) /*!< UCBRS Bit Offset */ 3614 #define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /*!< UCBRS Bit Mask */ 3615 /* EUSCI_A_STATW[BUSY] Bits */ 3616 #define EUSCI_A_STATW_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ 3617 #define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ 3618 /* EUSCI_A_STATW[ADDR_IDLE] Bits */ 3619 #define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /*!< UCADDR_UCIDLE Bit Offset */ 3620 #define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /*!< Address received / Idle line detected */ 3621 /* EUSCI_A_STATW[RXERR] Bits */ 3622 #define EUSCI_A_STATW_RXERR_OFS ( 2) /*!< UCRXERR Bit Offset */ 3623 #define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /*!< Receive error flag */ 3624 /* EUSCI_A_STATW[BRK] Bits */ 3625 #define EUSCI_A_STATW_BRK_OFS ( 3) /*!< UCBRK Bit Offset */ 3626 #define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /*!< Break detect flag */ 3627 /* EUSCI_A_STATW[PE] Bits */ 3628 #define EUSCI_A_STATW_PE_OFS ( 4) /*!< UCPE Bit Offset */ 3629 #define EUSCI_A_STATW_PE ((uint16_t)0x0010) 3630 /* EUSCI_A_STATW[OE] Bits */ 3631 #define EUSCI_A_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ 3632 #define EUSCI_A_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ 3633 /* EUSCI_A_STATW[FE] Bits */ 3634 #define EUSCI_A_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ 3635 #define EUSCI_A_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ 3636 /* EUSCI_A_STATW[LISTEN] Bits */ 3637 #define EUSCI_A_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ 3638 #define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ 3639 /* EUSCI_A_STATW[SPI_BUSY] Bits */ 3640 #define EUSCI_A_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ 3641 #define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ 3642 /* EUSCI_A_RXBUF[RXBUF] Bits */ 3643 #define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ 3644 #define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ 3645 /* EUSCI_A_TXBUF[TXBUF] Bits */ 3646 #define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ 3647 #define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ 3648 /* EUSCI_A_ABCTL[ABDEN] Bits */ 3649 #define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /*!< UCABDEN Bit Offset */ 3650 #define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /*!< Automatic baud-rate detect enable */ 3651 /* EUSCI_A_ABCTL[BTOE] Bits */ 3652 #define EUSCI_A_ABCTL_BTOE_OFS ( 2) /*!< UCBTOE Bit Offset */ 3653 #define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /*!< Break time out error */ 3654 /* EUSCI_A_ABCTL[STOE] Bits */ 3655 #define EUSCI_A_ABCTL_STOE_OFS ( 3) /*!< UCSTOE Bit Offset */ 3656 #define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /*!< Synch field time out error */ 3657 /* EUSCI_A_ABCTL[DELIM] Bits */ 3658 #define EUSCI_A_ABCTL_DELIM_OFS ( 4) /*!< UCDELIM Bit Offset */ 3659 #define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /*!< UCDELIM Bit Mask */ 3660 #define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /*!< DELIM Bit 0 */ 3661 #define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /*!< DELIM Bit 1 */ 3662 #define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /*!< 1 bit time */ 3663 #define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /*!< 2 bit times */ 3664 #define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /*!< 3 bit times */ 3665 #define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /*!< 4 bit times */ 3666 /* EUSCI_A_IRCTL[IREN] Bits */ 3667 #define EUSCI_A_IRCTL_IREN_OFS ( 0) /*!< UCIREN Bit Offset */ 3668 #define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /*!< IrDA encoder/decoder enable */ 3669 /* EUSCI_A_IRCTL[IRTXCLK] Bits */ 3670 #define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /*!< UCIRTXCLK Bit Offset */ 3671 #define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /*!< IrDA transmit pulse clock select */ 3672 /* EUSCI_A_IRCTL[IRTXPL] Bits */ 3673 #define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /*!< UCIRTXPL Bit Offset */ 3674 #define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /*!< UCIRTXPL Bit Mask */ 3675 /* EUSCI_A_IRCTL[IRRXFE] Bits */ 3676 #define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /*!< UCIRRXFE Bit Offset */ 3677 #define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /*!< IrDA receive filter enabled */ 3678 /* EUSCI_A_IRCTL[IRRXPL] Bits */ 3679 #define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /*!< UCIRRXPL Bit Offset */ 3680 #define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /*!< IrDA receive input UCAxRXD polarity */ 3681 /* EUSCI_A_IRCTL[IRRXFL] Bits */ 3682 #define EUSCI_A_IRCTL_IRRXFL_OFS (10) /*!< UCIRRXFL Bit Offset */ 3683 #define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /*!< UCIRRXFL Bit Mask */ 3684 /* EUSCI_A_IE[RXIE] Bits */ 3685 #define EUSCI_A_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ 3686 #define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ 3687 /* EUSCI_A_IE[TXIE] Bits */ 3688 #define EUSCI_A_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ 3689 #define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ 3690 /* EUSCI_A_IE[STTIE] Bits */ 3691 #define EUSCI_A_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ 3692 #define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /*!< Start bit interrupt enable */ 3693 /* EUSCI_A_IE[TXCPTIE] Bits */ 3694 #define EUSCI_A_IE_TXCPTIE_OFS ( 3) /*!< UCTXCPTIE Bit Offset */ 3695 #define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /*!< Transmit complete interrupt enable */ 3696 /* EUSCI_A_IFG[RXIFG] Bits */ 3697 #define EUSCI_A_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ 3698 #define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ 3699 /* EUSCI_A_IFG[TXIFG] Bits */ 3700 #define EUSCI_A_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ 3701 #define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ 3702 /* EUSCI_A_IFG[STTIFG] Bits */ 3703 #define EUSCI_A_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ 3704 #define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /*!< Start bit interrupt flag */ 3705 /* EUSCI_A_IFG[TXCPTIFG] Bits */ 3706 #define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /*!< UCTXCPTIFG Bit Offset */ 3707 #define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /*!< Transmit ready interrupt enable */ 3708 /* legacy definitions for backward compatibility to version 2100 */ 3709 #define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ 3710 #define EUSCI_A__RXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ 3711 #define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ 3712 #define EUSCI_A__TXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ 3713 3714 3715 /****************************************************************************** 3716 * EUSCI_B Bits 3717 ******************************************************************************/ 3718 /* EUSCI_B_CTLW0[SWRST] Bits */ 3719 #define EUSCI_B_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ 3720 #define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ 3721 /* EUSCI_B_CTLW0[TXSTT] Bits */ 3722 #define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /*!< UCTXSTT Bit Offset */ 3723 #define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /*!< Transmit START condition in master mode */ 3724 /* EUSCI_B_CTLW0[TXSTP] Bits */ 3725 #define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /*!< UCTXSTP Bit Offset */ 3726 #define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /*!< Transmit STOP condition in master mode */ 3727 /* EUSCI_B_CTLW0[TXNACK] Bits */ 3728 #define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /*!< UCTXNACK Bit Offset */ 3729 #define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /*!< Transmit a NACK */ 3730 /* EUSCI_B_CTLW0[TR] Bits */ 3731 #define EUSCI_B_CTLW0_TR_OFS ( 4) /*!< UCTR Bit Offset */ 3732 #define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /*!< Transmitter/receiver */ 3733 /* EUSCI_B_CTLW0[TXACK] Bits */ 3734 #define EUSCI_B_CTLW0_TXACK_OFS ( 5) /*!< UCTXACK Bit Offset */ 3735 #define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /*!< Transmit ACK condition in slave mode */ 3736 /* EUSCI_B_CTLW0[SSEL] Bits */ 3737 #define EUSCI_B_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ 3738 #define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ 3739 #define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ 3740 #define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ 3741 #define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLKI */ 3742 #define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ 3743 #define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ 3744 #define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ 3745 #define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /*!< UCLKI */ 3746 #define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ 3747 #define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ 3748 /* EUSCI_B_CTLW0[SYNC] Bits */ 3749 #define EUSCI_B_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ 3750 #define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ 3751 /* EUSCI_B_CTLW0[MODE] Bits */ 3752 #define EUSCI_B_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ 3753 #define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ 3754 #define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ 3755 #define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ 3756 #define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< 3-pin SPI */ 3757 #define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< 4-pin SPI (master or slave enabled if STE = 1) */ 3758 #define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< 4-pin SPI (master or slave enabled if STE = 0) */ 3759 #define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< I2C mode */ 3760 /* EUSCI_B_CTLW0[MST] Bits */ 3761 #define EUSCI_B_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ 3762 #define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ 3763 /* EUSCI_B_CTLW0[MM] Bits */ 3764 #define EUSCI_B_CTLW0_MM_OFS (13) /*!< UCMM Bit Offset */ 3765 #define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /*!< Multi-master environment select */ 3766 /* EUSCI_B_CTLW0[SLA10] Bits */ 3767 #define EUSCI_B_CTLW0_SLA10_OFS (14) /*!< UCSLA10 Bit Offset */ 3768 #define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /*!< Slave addressing mode select */ 3769 /* EUSCI_B_CTLW0[A10] Bits */ 3770 #define EUSCI_B_CTLW0_A10_OFS (15) /*!< UCA10 Bit Offset */ 3771 #define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /*!< Own addressing mode select */ 3772 /* EUSCI_B_CTLW0[STEM] Bits */ 3773 #define EUSCI_B_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ 3774 #define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ 3775 /* EUSCI_B_CTLW0[SEVENBIT] Bits */ 3776 #define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ 3777 #define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ 3778 /* EUSCI_B_CTLW0[MSB] Bits */ 3779 #define EUSCI_B_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ 3780 #define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ 3781 /* EUSCI_B_CTLW0[CKPL] Bits */ 3782 #define EUSCI_B_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ 3783 #define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ 3784 /* EUSCI_B_CTLW0[CKPH] Bits */ 3785 #define EUSCI_B_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ 3786 #define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ 3787 /* EUSCI_B_CTLW1[GLIT] Bits */ 3788 #define EUSCI_B_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ 3789 #define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ 3790 #define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ 3791 #define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ 3792 #define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< 50 ns */ 3793 #define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< 25 ns */ 3794 #define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< 12.5 ns */ 3795 #define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< 6.25 ns */ 3796 /* EUSCI_B_CTLW1[ASTP] Bits */ 3797 #define EUSCI_B_CTLW1_ASTP_OFS ( 2) /*!< UCASTP Bit Offset */ 3798 #define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /*!< UCASTP Bit Mask */ 3799 #define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /*!< ASTP Bit 0 */ 3800 #define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /*!< ASTP Bit 1 */ 3801 #define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /*!< No automatic STOP generation. The STOP condition is generated after the user */ 3802 /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ 3803 #define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ 3804 /* UCBxTBCNT */ 3805 #define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /*!< A STOP condition is generated automatically after the byte counter value */ 3806 /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ 3807 /* threshold */ 3808 /* EUSCI_B_CTLW1[SWACK] Bits */ 3809 #define EUSCI_B_CTLW1_SWACK_OFS ( 4) /*!< UCSWACK Bit Offset */ 3810 #define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /*!< SW or HW ACK control */ 3811 /* EUSCI_B_CTLW1[STPNACK] Bits */ 3812 #define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /*!< UCSTPNACK Bit Offset */ 3813 #define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /*!< ACK all master bytes */ 3814 /* EUSCI_B_CTLW1[CLTO] Bits */ 3815 #define EUSCI_B_CTLW1_CLTO_OFS ( 6) /*!< UCCLTO Bit Offset */ 3816 #define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /*!< UCCLTO Bit Mask */ 3817 #define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /*!< CLTO Bit 0 */ 3818 #define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /*!< CLTO Bit 1 */ 3819 #define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /*!< Disable clock low timeout counter */ 3820 #define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ 3821 #define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ 3822 #define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ 3823 /* EUSCI_B_CTLW1[ETXINT] Bits */ 3824 #define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /*!< UCETXINT Bit Offset */ 3825 #define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /*!< Early UCTXIFG0 */ 3826 /* EUSCI_B_STATW[BBUSY] Bits */ 3827 #define EUSCI_B_STATW_BBUSY_OFS ( 4) /*!< UCBBUSY Bit Offset */ 3828 #define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /*!< Bus busy */ 3829 /* EUSCI_B_STATW[GC] Bits */ 3830 #define EUSCI_B_STATW_GC_OFS ( 5) /*!< UCGC Bit Offset */ 3831 #define EUSCI_B_STATW_GC ((uint16_t)0x0020) /*!< General call address received */ 3832 /* EUSCI_B_STATW[SCLLOW] Bits */ 3833 #define EUSCI_B_STATW_SCLLOW_OFS ( 6) /*!< UCSCLLOW Bit Offset */ 3834 #define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /*!< SCL low */ 3835 /* EUSCI_B_STATW[BCNT] Bits */ 3836 #define EUSCI_B_STATW_BCNT_OFS ( 8) /*!< UCBCNT Bit Offset */ 3837 #define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /*!< UCBCNT Bit Mask */ 3838 /* EUSCI_B_STATW[SPI_BUSY] Bits */ 3839 #define EUSCI_B_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ 3840 #define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_B busy */ 3841 /* EUSCI_B_STATW[OE] Bits */ 3842 #define EUSCI_B_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ 3843 #define EUSCI_B_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ 3844 /* EUSCI_B_STATW[FE] Bits */ 3845 #define EUSCI_B_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ 3846 #define EUSCI_B_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ 3847 /* EUSCI_B_STATW[LISTEN] Bits */ 3848 #define EUSCI_B_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ 3849 #define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ 3850 /* EUSCI_B_TBCNT[TBCNT] Bits */ 3851 #define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /*!< UCTBCNT Bit Offset */ 3852 #define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /*!< UCTBCNT Bit Mask */ 3853 /* EUSCI_B_RXBUF[RXBUF] Bits */ 3854 #define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ 3855 #define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ 3856 /* EUSCI_B_TXBUF[TXBUF] Bits */ 3857 #define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ 3858 #define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ 3859 /* EUSCI_B_I2COA0[I2COA0] Bits */ 3860 #define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /*!< I2COA0 Bit Offset */ 3861 #define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /*!< I2COA0 Bit Mask */ 3862 /* EUSCI_B_I2COA0[OAEN] Bits */ 3863 #define EUSCI_B_I2COA0_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3864 #define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3865 /* EUSCI_B_I2COA0[GCEN] Bits */ 3866 #define EUSCI_B_I2COA0_GCEN_OFS (15) /*!< UCGCEN Bit Offset */ 3867 #define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /*!< General call response enable */ 3868 /* EUSCI_B_I2COA1[I2COA1] Bits */ 3869 #define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /*!< I2COA1 Bit Offset */ 3870 #define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /*!< I2COA1 Bit Mask */ 3871 /* EUSCI_B_I2COA1[OAEN] Bits */ 3872 #define EUSCI_B_I2COA1_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3873 #define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3874 /* EUSCI_B_I2COA2[I2COA2] Bits */ 3875 #define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /*!< I2COA2 Bit Offset */ 3876 #define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /*!< I2COA2 Bit Mask */ 3877 /* EUSCI_B_I2COA2[OAEN] Bits */ 3878 #define EUSCI_B_I2COA2_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3879 #define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3880 /* EUSCI_B_I2COA3[I2COA3] Bits */ 3881 #define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /*!< I2COA3 Bit Offset */ 3882 #define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /*!< I2COA3 Bit Mask */ 3883 /* EUSCI_B_I2COA3[OAEN] Bits */ 3884 #define EUSCI_B_I2COA3_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3885 #define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3886 /* EUSCI_B_ADDRX[ADDRX] Bits */ 3887 #define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /*!< ADDRX Bit Offset */ 3888 #define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /*!< ADDRX Bit Mask */ 3889 #define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001) /*!< ADDRX Bit 0 */ 3890 #define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002) /*!< ADDRX Bit 1 */ 3891 #define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004) /*!< ADDRX Bit 2 */ 3892 #define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008) /*!< ADDRX Bit 3 */ 3893 #define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010) /*!< ADDRX Bit 4 */ 3894 #define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020) /*!< ADDRX Bit 5 */ 3895 #define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040) /*!< ADDRX Bit 6 */ 3896 #define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080) /*!< ADDRX Bit 7 */ 3897 #define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100) /*!< ADDRX Bit 8 */ 3898 #define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200) /*!< ADDRX Bit 9 */ 3899 /* EUSCI_B_ADDMASK[ADDMASK] Bits */ 3900 #define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /*!< ADDMASK Bit Offset */ 3901 #define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /*!< ADDMASK Bit Mask */ 3902 /* EUSCI_B_I2CSA[I2CSA] Bits */ 3903 #define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /*!< I2CSA Bit Offset */ 3904 #define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /*!< I2CSA Bit Mask */ 3905 /* EUSCI_B_IE[RXIE0] Bits */ 3906 #define EUSCI_B_IE_RXIE0_OFS ( 0) /*!< UCRXIE0 Bit Offset */ 3907 #define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /*!< Receive interrupt enable 0 */ 3908 /* EUSCI_B_IE[TXIE0] Bits */ 3909 #define EUSCI_B_IE_TXIE0_OFS ( 1) /*!< UCTXIE0 Bit Offset */ 3910 #define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /*!< Transmit interrupt enable 0 */ 3911 /* EUSCI_B_IE[STTIE] Bits */ 3912 #define EUSCI_B_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ 3913 #define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /*!< START condition interrupt enable */ 3914 /* EUSCI_B_IE[STPIE] Bits */ 3915 #define EUSCI_B_IE_STPIE_OFS ( 3) /*!< UCSTPIE Bit Offset */ 3916 #define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /*!< STOP condition interrupt enable */ 3917 /* EUSCI_B_IE[ALIE] Bits */ 3918 #define EUSCI_B_IE_ALIE_OFS ( 4) /*!< UCALIE Bit Offset */ 3919 #define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /*!< Arbitration lost interrupt enable */ 3920 /* EUSCI_B_IE[NACKIE] Bits */ 3921 #define EUSCI_B_IE_NACKIE_OFS ( 5) /*!< UCNACKIE Bit Offset */ 3922 #define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /*!< Not-acknowledge interrupt enable */ 3923 /* EUSCI_B_IE[BCNTIE] Bits */ 3924 #define EUSCI_B_IE_BCNTIE_OFS ( 6) /*!< UCBCNTIE Bit Offset */ 3925 #define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /*!< Byte counter interrupt enable */ 3926 /* EUSCI_B_IE[CLTOIE] Bits */ 3927 #define EUSCI_B_IE_CLTOIE_OFS ( 7) /*!< UCCLTOIE Bit Offset */ 3928 #define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /*!< Clock low timeout interrupt enable */ 3929 /* EUSCI_B_IE[RXIE1] Bits */ 3930 #define EUSCI_B_IE_RXIE1_OFS ( 8) /*!< UCRXIE1 Bit Offset */ 3931 #define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /*!< Receive interrupt enable 1 */ 3932 /* EUSCI_B_IE[TXIE1] Bits */ 3933 #define EUSCI_B_IE_TXIE1_OFS ( 9) /*!< UCTXIE1 Bit Offset */ 3934 #define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /*!< Transmit interrupt enable 1 */ 3935 /* EUSCI_B_IE[RXIE2] Bits */ 3936 #define EUSCI_B_IE_RXIE2_OFS (10) /*!< UCRXIE2 Bit Offset */ 3937 #define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /*!< Receive interrupt enable 2 */ 3938 /* EUSCI_B_IE[TXIE2] Bits */ 3939 #define EUSCI_B_IE_TXIE2_OFS (11) /*!< UCTXIE2 Bit Offset */ 3940 #define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /*!< Transmit interrupt enable 2 */ 3941 /* EUSCI_B_IE[RXIE3] Bits */ 3942 #define EUSCI_B_IE_RXIE3_OFS (12) /*!< UCRXIE3 Bit Offset */ 3943 #define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /*!< Receive interrupt enable 3 */ 3944 /* EUSCI_B_IE[TXIE3] Bits */ 3945 #define EUSCI_B_IE_TXIE3_OFS (13) /*!< UCTXIE3 Bit Offset */ 3946 #define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /*!< Transmit interrupt enable 3 */ 3947 /* EUSCI_B_IE[BIT9IE] Bits */ 3948 #define EUSCI_B_IE_BIT9IE_OFS (14) /*!< UCBIT9IE Bit Offset */ 3949 #define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /*!< Bit position 9 interrupt enable */ 3950 /* EUSCI_B_IE[RXIE] Bits */ 3951 #define EUSCI_B_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ 3952 #define EUSCI_B_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ 3953 /* EUSCI_B_IE[TXIE] Bits */ 3954 #define EUSCI_B_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ 3955 #define EUSCI_B_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ 3956 /* EUSCI_B_IFG[RXIFG0] Bits */ 3957 #define EUSCI_B_IFG_RXIFG0_OFS ( 0) /*!< UCRXIFG0 Bit Offset */ 3958 #define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /*!< eUSCI_B receive interrupt flag 0 */ 3959 /* EUSCI_B_IFG[TXIFG0] Bits */ 3960 #define EUSCI_B_IFG_TXIFG0_OFS ( 1) /*!< UCTXIFG0 Bit Offset */ 3961 #define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /*!< eUSCI_B transmit interrupt flag 0 */ 3962 /* EUSCI_B_IFG[STTIFG] Bits */ 3963 #define EUSCI_B_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ 3964 #define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /*!< START condition interrupt flag */ 3965 /* EUSCI_B_IFG[STPIFG] Bits */ 3966 #define EUSCI_B_IFG_STPIFG_OFS ( 3) /*!< UCSTPIFG Bit Offset */ 3967 #define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /*!< STOP condition interrupt flag */ 3968 /* EUSCI_B_IFG[ALIFG] Bits */ 3969 #define EUSCI_B_IFG_ALIFG_OFS ( 4) /*!< UCALIFG Bit Offset */ 3970 #define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /*!< Arbitration lost interrupt flag */ 3971 /* EUSCI_B_IFG[NACKIFG] Bits */ 3972 #define EUSCI_B_IFG_NACKIFG_OFS ( 5) /*!< UCNACKIFG Bit Offset */ 3973 #define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /*!< Not-acknowledge received interrupt flag */ 3974 /* EUSCI_B_IFG[BCNTIFG] Bits */ 3975 #define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /*!< UCBCNTIFG Bit Offset */ 3976 #define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /*!< Byte counter interrupt flag */ 3977 /* EUSCI_B_IFG[CLTOIFG] Bits */ 3978 #define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /*!< UCCLTOIFG Bit Offset */ 3979 #define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /*!< Clock low timeout interrupt flag */ 3980 /* EUSCI_B_IFG[RXIFG1] Bits */ 3981 #define EUSCI_B_IFG_RXIFG1_OFS ( 8) /*!< UCRXIFG1 Bit Offset */ 3982 #define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /*!< eUSCI_B receive interrupt flag 1 */ 3983 /* EUSCI_B_IFG[TXIFG1] Bits */ 3984 #define EUSCI_B_IFG_TXIFG1_OFS ( 9) /*!< UCTXIFG1 Bit Offset */ 3985 #define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /*!< eUSCI_B transmit interrupt flag 1 */ 3986 /* EUSCI_B_IFG[RXIFG2] Bits */ 3987 #define EUSCI_B_IFG_RXIFG2_OFS (10) /*!< UCRXIFG2 Bit Offset */ 3988 #define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /*!< eUSCI_B receive interrupt flag 2 */ 3989 /* EUSCI_B_IFG[TXIFG2] Bits */ 3990 #define EUSCI_B_IFG_TXIFG2_OFS (11) /*!< UCTXIFG2 Bit Offset */ 3991 #define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /*!< eUSCI_B transmit interrupt flag 2 */ 3992 /* EUSCI_B_IFG[RXIFG3] Bits */ 3993 #define EUSCI_B_IFG_RXIFG3_OFS (12) /*!< UCRXIFG3 Bit Offset */ 3994 #define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /*!< eUSCI_B receive interrupt flag 3 */ 3995 /* EUSCI_B_IFG[TXIFG3] Bits */ 3996 #define EUSCI_B_IFG_TXIFG3_OFS (13) /*!< UCTXIFG3 Bit Offset */ 3997 #define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /*!< eUSCI_B transmit interrupt flag 3 */ 3998 /* EUSCI_B_IFG[BIT9IFG] Bits */ 3999 #define EUSCI_B_IFG_BIT9IFG_OFS (14) /*!< UCBIT9IFG Bit Offset */ 4000 #define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /*!< Bit position 9 interrupt flag */ 4001 /* EUSCI_B_IFG[RXIFG] Bits */ 4002 #define EUSCI_B_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ 4003 #define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ 4004 /* EUSCI_B_IFG[TXIFG] Bits */ 4005 #define EUSCI_B_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ 4006 #define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ 4007 /* legacy definitions for backward compatibility to version 2100 */ 4008 #define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ 4009 #define EUSCI_B__RXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ 4010 #define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ 4011 #define EUSCI_B__TXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ 4012 4013 4014 /****************************************************************************** 4015 * FLCTL Bits 4016 ******************************************************************************/ 4017 /* FLCTL_POWER_STAT[PSTAT] Bits */ 4018 #define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ 4019 #define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ 4020 #define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ 4021 #define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ 4022 #define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ 4023 #define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ 4024 #define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ 4025 #define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ 4026 #define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ 4027 #define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ 4028 #define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ 4029 #define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ 4030 #define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ 4031 /* FLCTL_POWER_STAT[LDOSTAT] Bits */ 4032 #define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ 4033 #define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ 4034 /* FLCTL_POWER_STAT[VREFSTAT] Bits */ 4035 #define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ 4036 #define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ 4037 /* FLCTL_POWER_STAT[IREFSTAT] Bits */ 4038 #define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ 4039 #define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ 4040 /* FLCTL_POWER_STAT[TRIMSTAT] Bits */ 4041 #define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ 4042 #define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ 4043 /* FLCTL_POWER_STAT[RD_2T] Bits */ 4044 #define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ 4045 #define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ 4046 /* FLCTL_BANK0_RDCTL[RD_MODE] Bits */ 4047 #define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ 4048 #define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ 4049 #define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ 4050 #define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ 4051 #define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ 4052 #define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ 4053 #define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4054 #define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ 4055 #define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ 4056 #define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ 4057 #define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ 4058 #define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ 4059 #define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ 4060 #define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ 4061 /* FLCTL_BANK0_RDCTL[BUFI] Bits */ 4062 #define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ 4063 #define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ 4064 /* FLCTL_BANK0_RDCTL[BUFD] Bits */ 4065 #define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ 4066 #define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ 4067 /* FLCTL_BANK0_RDCTL[WAIT] Bits */ 4068 #define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ 4069 #define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ 4070 #define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ 4071 #define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ 4072 #define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ 4073 #define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ 4074 #define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ 4075 #define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ 4076 #define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ 4077 #define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ 4078 #define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ 4079 #define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ 4080 #define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ 4081 #define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ 4082 #define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ 4083 #define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ 4084 #define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ 4085 #define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ 4086 #define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ 4087 #define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ 4088 #define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ 4089 #define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ 4090 /* FLCTL_BANK0_RDCTL[RD_MODE_STATUS] Bits */ 4091 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ 4092 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ 4093 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ 4094 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ 4095 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ 4096 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ 4097 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4098 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ 4099 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ 4100 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ 4101 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ 4102 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ 4103 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ 4104 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ 4105 /* FLCTL_BANK1_RDCTL[RD_MODE] Bits */ 4106 #define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ 4107 #define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ 4108 #define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ 4109 #define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ 4110 #define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ 4111 #define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ 4112 #define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4113 #define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ 4114 #define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ 4115 #define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ 4116 #define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ 4117 #define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ 4118 #define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ 4119 #define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ 4120 /* FLCTL_BANK1_RDCTL[BUFI] Bits */ 4121 #define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ 4122 #define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ 4123 /* FLCTL_BANK1_RDCTL[BUFD] Bits */ 4124 #define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ 4125 #define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ 4126 /* FLCTL_BANK1_RDCTL[RD_MODE_STATUS] Bits */ 4127 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ 4128 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ 4129 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ 4130 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ 4131 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ 4132 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ 4133 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4134 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ 4135 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ 4136 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ 4137 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ 4138 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ 4139 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ 4140 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ 4141 /* FLCTL_BANK1_RDCTL[WAIT] Bits */ 4142 #define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ 4143 #define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ 4144 #define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ 4145 #define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ 4146 #define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ 4147 #define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ 4148 #define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ 4149 #define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ 4150 #define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ 4151 #define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ 4152 #define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ 4153 #define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ 4154 #define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ 4155 #define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ 4156 #define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ 4157 #define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ 4158 #define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ 4159 #define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ 4160 #define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ 4161 #define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ 4162 #define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ 4163 #define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ 4164 /* FLCTL_RDBRST_CTLSTAT[START] Bits */ 4165 #define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ 4166 #define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ 4167 /* FLCTL_RDBRST_CTLSTAT[MEM_TYPE] Bits */ 4168 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ 4169 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ 4170 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ 4171 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ 4172 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ 4173 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ 4174 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ 4175 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ 4176 /* FLCTL_RDBRST_CTLSTAT[STOP_FAIL] Bits */ 4177 #define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ 4178 #define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ 4179 /* FLCTL_RDBRST_CTLSTAT[DATA_CMP] Bits */ 4180 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ 4181 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ 4182 /* FLCTL_RDBRST_CTLSTAT[TEST_EN] Bits */ 4183 #define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ 4184 #define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ 4185 /* FLCTL_RDBRST_CTLSTAT[BRST_STAT] Bits */ 4186 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ 4187 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ 4188 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ 4189 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ 4190 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ 4191 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ 4192 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ 4193 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ 4194 /* explicitly cleared by SW) */ 4195 /* FLCTL_RDBRST_CTLSTAT[CMP_ERR] Bits */ 4196 #define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ 4197 #define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ 4198 /* FLCTL_RDBRST_CTLSTAT[ADDR_ERR] Bits */ 4199 #define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ 4200 #define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ 4201 /* FLCTL_RDBRST_CTLSTAT[CLR_STAT] Bits */ 4202 #define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ 4203 #define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ 4204 /* FLCTL_RDBRST_STARTADDR[START_ADDRESS] Bits */ 4205 #define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ 4206 #define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ 4207 /* FLCTL_RDBRST_LEN[BURST_LENGTH] Bits */ 4208 #define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ 4209 #define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ 4210 /* FLCTL_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */ 4211 #define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ 4212 #define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ 4213 /* FLCTL_RDBRST_FAILCNT[FAIL_COUNT] Bits */ 4214 #define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ 4215 #define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ 4216 /* FLCTL_PRG_CTLSTAT[ENABLE] Bits */ 4217 #define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ 4218 #define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ 4219 /* FLCTL_PRG_CTLSTAT[MODE] Bits */ 4220 #define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ 4221 #define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ 4222 /* FLCTL_PRG_CTLSTAT[VER_PRE] Bits */ 4223 #define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ 4224 #define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ 4225 /* FLCTL_PRG_CTLSTAT[VER_PST] Bits */ 4226 #define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ 4227 #define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ 4228 /* FLCTL_PRG_CTLSTAT[STATUS] Bits */ 4229 #define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ 4230 #define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ 4231 #define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ 4232 #define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ 4233 #define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ 4234 #define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ 4235 #define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ 4236 #define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ 4237 /* FLCTL_PRG_CTLSTAT[BNK_ACT] Bits */ 4238 #define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ 4239 #define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ 4240 /* FLCTL_PRGBRST_CTLSTAT[START] Bits */ 4241 #define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ 4242 #define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ 4243 /* FLCTL_PRGBRST_CTLSTAT[TYPE] Bits */ 4244 #define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ 4245 #define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ 4246 #define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ 4247 #define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ 4248 #define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ 4249 #define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ 4250 #define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ 4251 #define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ 4252 /* FLCTL_PRGBRST_CTLSTAT[LEN] Bits */ 4253 #define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ 4254 #define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ 4255 #define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ 4256 #define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ 4257 #define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ 4258 #define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ 4259 #define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ 4260 /* FLCTL_PRGBRST_STARTADDR Register */ 4261 #define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ 4262 /* Register */ 4263 #define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ 4264 /* Register */ 4265 #define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ 4266 /* Register */ 4267 /* FLCTL_PRGBRST_CTLSTAT[AUTO_PRE] Bits */ 4268 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ 4269 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ 4270 /* FLCTL_PRGBRST_CTLSTAT[AUTO_PST] Bits */ 4271 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ 4272 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ 4273 /* FLCTL_PRGBRST_CTLSTAT[BURST_STATUS] Bits */ 4274 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ 4275 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ 4276 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ 4277 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ 4278 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ 4279 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ 4280 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ 4281 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ 4282 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ 4283 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ 4284 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ 4285 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ 4286 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ 4287 /* explicitly cleared by SW) */ 4288 /* FLCTL_PRGBRST_CTLSTAT[PRE_ERR] Bits */ 4289 #define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ 4290 #define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ 4291 /* FLCTL_PRGBRST_CTLSTAT[PST_ERR] Bits */ 4292 #define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ 4293 #define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ 4294 /* FLCTL_PRGBRST_CTLSTAT[ADDR_ERR] Bits */ 4295 #define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ 4296 #define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ 4297 /* FLCTL_PRGBRST_CTLSTAT[CLR_STAT] Bits */ 4298 #define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ 4299 #define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ 4300 /* FLCTL_PRGBRST_STARTADDR[START_ADDRESS] Bits */ 4301 #define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ 4302 #define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ 4303 /* FLCTL_ERASE_CTLSTAT[START] Bits */ 4304 #define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ 4305 #define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ 4306 /* FLCTL_ERASE_CTLSTAT[MODE] Bits */ 4307 #define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ 4308 #define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ 4309 /* FLCTL_ERASE_CTLSTAT[TYPE] Bits */ 4310 #define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ 4311 #define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ 4312 #define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ 4313 #define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ 4314 #define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ 4315 #define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ 4316 #define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ 4317 #define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ 4318 /* FLCTL_ERASE_CTLSTAT[STATUS] Bits */ 4319 #define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ 4320 #define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ 4321 #define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ 4322 #define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ 4323 #define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ 4324 #define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ 4325 #define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ 4326 #define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ 4327 /* unless explicitly cleared by SW) */ 4328 /* FLCTL_ERASE_CTLSTAT[ADDR_ERR] Bits */ 4329 #define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ 4330 #define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ 4331 /* address */ 4332 /* FLCTL_ERASE_CTLSTAT[CLR_STAT] Bits */ 4333 #define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ 4334 #define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ 4335 /* FLCTL_ERASE_SECTADDR[SECT_ADDRESS] Bits */ 4336 #define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ 4337 #define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ 4338 /* FLCTL_BANK0_INFO_WEPROT[PROT0] Bits */ 4339 #define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4340 #define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ 4341 /* FLCTL_BANK0_INFO_WEPROT[PROT1] Bits */ 4342 #define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4343 #define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ 4344 /* FLCTL_BANK0_MAIN_WEPROT[PROT0] Bits */ 4345 #define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4346 #define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ 4347 /* FLCTL_BANK0_MAIN_WEPROT[PROT1] Bits */ 4348 #define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4349 #define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ 4350 /* FLCTL_BANK0_MAIN_WEPROT[PROT2] Bits */ 4351 #define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ 4352 #define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ 4353 /* FLCTL_BANK0_MAIN_WEPROT[PROT3] Bits */ 4354 #define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ 4355 #define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ 4356 /* FLCTL_BANK0_MAIN_WEPROT[PROT4] Bits */ 4357 #define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ 4358 #define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ 4359 /* FLCTL_BANK0_MAIN_WEPROT[PROT5] Bits */ 4360 #define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ 4361 #define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ 4362 /* FLCTL_BANK0_MAIN_WEPROT[PROT6] Bits */ 4363 #define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ 4364 #define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ 4365 /* FLCTL_BANK0_MAIN_WEPROT[PROT7] Bits */ 4366 #define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ 4367 #define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ 4368 /* FLCTL_BANK0_MAIN_WEPROT[PROT8] Bits */ 4369 #define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ 4370 #define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ 4371 /* FLCTL_BANK0_MAIN_WEPROT[PROT9] Bits */ 4372 #define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ 4373 #define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ 4374 /* FLCTL_BANK0_MAIN_WEPROT[PROT10] Bits */ 4375 #define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ 4376 #define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ 4377 /* FLCTL_BANK0_MAIN_WEPROT[PROT11] Bits */ 4378 #define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ 4379 #define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ 4380 /* FLCTL_BANK0_MAIN_WEPROT[PROT12] Bits */ 4381 #define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ 4382 #define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ 4383 /* FLCTL_BANK0_MAIN_WEPROT[PROT13] Bits */ 4384 #define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ 4385 #define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ 4386 /* FLCTL_BANK0_MAIN_WEPROT[PROT14] Bits */ 4387 #define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ 4388 #define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ 4389 /* FLCTL_BANK0_MAIN_WEPROT[PROT15] Bits */ 4390 #define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ 4391 #define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ 4392 /* FLCTL_BANK0_MAIN_WEPROT[PROT16] Bits */ 4393 #define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ 4394 #define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ 4395 /* FLCTL_BANK0_MAIN_WEPROT[PROT17] Bits */ 4396 #define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ 4397 #define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ 4398 /* FLCTL_BANK0_MAIN_WEPROT[PROT18] Bits */ 4399 #define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ 4400 #define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ 4401 /* FLCTL_BANK0_MAIN_WEPROT[PROT19] Bits */ 4402 #define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ 4403 #define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ 4404 /* FLCTL_BANK0_MAIN_WEPROT[PROT20] Bits */ 4405 #define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ 4406 #define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ 4407 /* FLCTL_BANK0_MAIN_WEPROT[PROT21] Bits */ 4408 #define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ 4409 #define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ 4410 /* FLCTL_BANK0_MAIN_WEPROT[PROT22] Bits */ 4411 #define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ 4412 #define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ 4413 /* FLCTL_BANK0_MAIN_WEPROT[PROT23] Bits */ 4414 #define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ 4415 #define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ 4416 /* FLCTL_BANK0_MAIN_WEPROT[PROT24] Bits */ 4417 #define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ 4418 #define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ 4419 /* FLCTL_BANK0_MAIN_WEPROT[PROT25] Bits */ 4420 #define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ 4421 #define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ 4422 /* FLCTL_BANK0_MAIN_WEPROT[PROT26] Bits */ 4423 #define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ 4424 #define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ 4425 /* FLCTL_BANK0_MAIN_WEPROT[PROT27] Bits */ 4426 #define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ 4427 #define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ 4428 /* FLCTL_BANK0_MAIN_WEPROT[PROT28] Bits */ 4429 #define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ 4430 #define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ 4431 /* FLCTL_BANK0_MAIN_WEPROT[PROT29] Bits */ 4432 #define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ 4433 #define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ 4434 /* FLCTL_BANK0_MAIN_WEPROT[PROT30] Bits */ 4435 #define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ 4436 #define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ 4437 /* FLCTL_BANK0_MAIN_WEPROT[PROT31] Bits */ 4438 #define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ 4439 #define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ 4440 /* FLCTL_BANK1_INFO_WEPROT[PROT0] Bits */ 4441 #define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4442 #define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ 4443 /* FLCTL_BANK1_INFO_WEPROT[PROT1] Bits */ 4444 #define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4445 #define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ 4446 /* FLCTL_BANK1_MAIN_WEPROT[PROT0] Bits */ 4447 #define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4448 #define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ 4449 /* FLCTL_BANK1_MAIN_WEPROT[PROT1] Bits */ 4450 #define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4451 #define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ 4452 /* FLCTL_BANK1_MAIN_WEPROT[PROT2] Bits */ 4453 #define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ 4454 #define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ 4455 /* FLCTL_BANK1_MAIN_WEPROT[PROT3] Bits */ 4456 #define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ 4457 #define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ 4458 /* FLCTL_BANK1_MAIN_WEPROT[PROT4] Bits */ 4459 #define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ 4460 #define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ 4461 /* FLCTL_BANK1_MAIN_WEPROT[PROT5] Bits */ 4462 #define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ 4463 #define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ 4464 /* FLCTL_BANK1_MAIN_WEPROT[PROT6] Bits */ 4465 #define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ 4466 #define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ 4467 /* FLCTL_BANK1_MAIN_WEPROT[PROT7] Bits */ 4468 #define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ 4469 #define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ 4470 /* FLCTL_BANK1_MAIN_WEPROT[PROT8] Bits */ 4471 #define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ 4472 #define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ 4473 /* FLCTL_BANK1_MAIN_WEPROT[PROT9] Bits */ 4474 #define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ 4475 #define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ 4476 /* FLCTL_BANK1_MAIN_WEPROT[PROT10] Bits */ 4477 #define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ 4478 #define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ 4479 /* FLCTL_BANK1_MAIN_WEPROT[PROT11] Bits */ 4480 #define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ 4481 #define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ 4482 /* FLCTL_BANK1_MAIN_WEPROT[PROT12] Bits */ 4483 #define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ 4484 #define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ 4485 /* FLCTL_BANK1_MAIN_WEPROT[PROT13] Bits */ 4486 #define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ 4487 #define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ 4488 /* FLCTL_BANK1_MAIN_WEPROT[PROT14] Bits */ 4489 #define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ 4490 #define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ 4491 /* FLCTL_BANK1_MAIN_WEPROT[PROT15] Bits */ 4492 #define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ 4493 #define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ 4494 /* FLCTL_BANK1_MAIN_WEPROT[PROT16] Bits */ 4495 #define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ 4496 #define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ 4497 /* FLCTL_BANK1_MAIN_WEPROT[PROT17] Bits */ 4498 #define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ 4499 #define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ 4500 /* FLCTL_BANK1_MAIN_WEPROT[PROT18] Bits */ 4501 #define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ 4502 #define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ 4503 /* FLCTL_BANK1_MAIN_WEPROT[PROT19] Bits */ 4504 #define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ 4505 #define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ 4506 /* FLCTL_BANK1_MAIN_WEPROT[PROT20] Bits */ 4507 #define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ 4508 #define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ 4509 /* FLCTL_BANK1_MAIN_WEPROT[PROT21] Bits */ 4510 #define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ 4511 #define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ 4512 /* FLCTL_BANK1_MAIN_WEPROT[PROT22] Bits */ 4513 #define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ 4514 #define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ 4515 /* FLCTL_BANK1_MAIN_WEPROT[PROT23] Bits */ 4516 #define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ 4517 #define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ 4518 /* FLCTL_BANK1_MAIN_WEPROT[PROT24] Bits */ 4519 #define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ 4520 #define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ 4521 /* FLCTL_BANK1_MAIN_WEPROT[PROT25] Bits */ 4522 #define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ 4523 #define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ 4524 /* FLCTL_BANK1_MAIN_WEPROT[PROT26] Bits */ 4525 #define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ 4526 #define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ 4527 /* FLCTL_BANK1_MAIN_WEPROT[PROT27] Bits */ 4528 #define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ 4529 #define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ 4530 /* FLCTL_BANK1_MAIN_WEPROT[PROT28] Bits */ 4531 #define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ 4532 #define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ 4533 /* FLCTL_BANK1_MAIN_WEPROT[PROT29] Bits */ 4534 #define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ 4535 #define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ 4536 /* FLCTL_BANK1_MAIN_WEPROT[PROT30] Bits */ 4537 #define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ 4538 #define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ 4539 /* FLCTL_BANK1_MAIN_WEPROT[PROT31] Bits */ 4540 #define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ 4541 #define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ 4542 /* FLCTL_BMRK_CTLSTAT[I_BMRK] Bits */ 4543 #define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ 4544 #define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) 4545 /* FLCTL_BMRK_CTLSTAT[D_BMRK] Bits */ 4546 #define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ 4547 #define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) 4548 /* FLCTL_BMRK_CTLSTAT[CMP_EN] Bits */ 4549 #define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ 4550 #define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) 4551 /* FLCTL_BMRK_CTLSTAT[CMP_SEL] Bits */ 4552 #define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ 4553 #define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) 4554 /* FLCTL_IFG[RDBRST] Bits */ 4555 #define FLCTL_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4556 #define FLCTL_IFG_RDBRST ((uint32_t)0x00000001) 4557 /* FLCTL_IFG[AVPRE] Bits */ 4558 #define FLCTL_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4559 #define FLCTL_IFG_AVPRE ((uint32_t)0x00000002) 4560 /* FLCTL_IFG[AVPST] Bits */ 4561 #define FLCTL_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4562 #define FLCTL_IFG_AVPST ((uint32_t)0x00000004) 4563 /* FLCTL_IFG[PRG] Bits */ 4564 #define FLCTL_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4565 #define FLCTL_IFG_PRG ((uint32_t)0x00000008) 4566 /* FLCTL_IFG[PRGB] Bits */ 4567 #define FLCTL_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4568 #define FLCTL_IFG_PRGB ((uint32_t)0x00000010) 4569 /* FLCTL_IFG[ERASE] Bits */ 4570 #define FLCTL_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4571 #define FLCTL_IFG_ERASE ((uint32_t)0x00000020) 4572 /* FLCTL_IFG[BMRK] Bits */ 4573 #define FLCTL_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4574 #define FLCTL_IFG_BMRK ((uint32_t)0x00000100) 4575 /* FLCTL_IFG[PRG_ERR] Bits */ 4576 #define FLCTL_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4577 #define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200) 4578 /* FLCTL_IE[RDBRST] Bits */ 4579 #define FLCTL_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4580 #define FLCTL_IE_RDBRST ((uint32_t)0x00000001) 4581 /* FLCTL_IE[AVPRE] Bits */ 4582 #define FLCTL_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4583 #define FLCTL_IE_AVPRE ((uint32_t)0x00000002) 4584 /* FLCTL_IE[AVPST] Bits */ 4585 #define FLCTL_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4586 #define FLCTL_IE_AVPST ((uint32_t)0x00000004) 4587 /* FLCTL_IE[PRG] Bits */ 4588 #define FLCTL_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4589 #define FLCTL_IE_PRG ((uint32_t)0x00000008) 4590 /* FLCTL_IE[PRGB] Bits */ 4591 #define FLCTL_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4592 #define FLCTL_IE_PRGB ((uint32_t)0x00000010) 4593 /* FLCTL_IE[ERASE] Bits */ 4594 #define FLCTL_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4595 #define FLCTL_IE_ERASE ((uint32_t)0x00000020) 4596 /* FLCTL_IE[BMRK] Bits */ 4597 #define FLCTL_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4598 #define FLCTL_IE_BMRK ((uint32_t)0x00000100) 4599 /* FLCTL_IE[PRG_ERR] Bits */ 4600 #define FLCTL_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4601 #define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200) 4602 /* FLCTL_CLRIFG[RDBRST] Bits */ 4603 #define FLCTL_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4604 #define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001) 4605 /* FLCTL_CLRIFG[AVPRE] Bits */ 4606 #define FLCTL_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4607 #define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002) 4608 /* FLCTL_CLRIFG[AVPST] Bits */ 4609 #define FLCTL_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4610 #define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004) 4611 /* FLCTL_CLRIFG[PRG] Bits */ 4612 #define FLCTL_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4613 #define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008) 4614 /* FLCTL_CLRIFG[PRGB] Bits */ 4615 #define FLCTL_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4616 #define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010) 4617 /* FLCTL_CLRIFG[ERASE] Bits */ 4618 #define FLCTL_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4619 #define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020) 4620 /* FLCTL_CLRIFG[BMRK] Bits */ 4621 #define FLCTL_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4622 #define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100) 4623 /* FLCTL_CLRIFG[PRG_ERR] Bits */ 4624 #define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4625 #define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200) 4626 /* FLCTL_SETIFG[RDBRST] Bits */ 4627 #define FLCTL_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4628 #define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001) 4629 /* FLCTL_SETIFG[AVPRE] Bits */ 4630 #define FLCTL_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4631 #define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002) 4632 /* FLCTL_SETIFG[AVPST] Bits */ 4633 #define FLCTL_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4634 #define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004) 4635 /* FLCTL_SETIFG[PRG] Bits */ 4636 #define FLCTL_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4637 #define FLCTL_SETIFG_PRG ((uint32_t)0x00000008) 4638 /* FLCTL_SETIFG[PRGB] Bits */ 4639 #define FLCTL_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4640 #define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010) 4641 /* FLCTL_SETIFG[ERASE] Bits */ 4642 #define FLCTL_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4643 #define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020) 4644 /* FLCTL_SETIFG[BMRK] Bits */ 4645 #define FLCTL_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4646 #define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100) 4647 /* FLCTL_SETIFG[PRG_ERR] Bits */ 4648 #define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4649 #define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200) 4650 /* FLCTL_READ_TIMCTL[SETUP] Bits */ 4651 #define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4652 #define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4653 /* FLCTL_READ_TIMCTL[IREF_BOOST1] Bits */ 4654 #define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ 4655 #define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ 4656 /* FLCTL_READ_TIMCTL[SETUP_LONG] Bits */ 4657 #define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ 4658 #define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ 4659 /* FLCTL_READMARGIN_TIMCTL[SETUP] Bits */ 4660 #define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4661 #define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4662 /* FLCTL_PRGVER_TIMCTL[SETUP] Bits */ 4663 #define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4664 #define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4665 /* FLCTL_PRGVER_TIMCTL[ACTIVE] Bits */ 4666 #define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4667 #define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ 4668 /* FLCTL_PRGVER_TIMCTL[HOLD] Bits */ 4669 #define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ 4670 #define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ 4671 /* FLCTL_ERSVER_TIMCTL[SETUP] Bits */ 4672 #define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4673 #define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4674 /* FLCTL_LKGVER_TIMCTL[SETUP] Bits */ 4675 #define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4676 #define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4677 /* FLCTL_PROGRAM_TIMCTL[SETUP] Bits */ 4678 #define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4679 #define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4680 /* FLCTL_PROGRAM_TIMCTL[ACTIVE] Bits */ 4681 #define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4682 #define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ 4683 /* FLCTL_PROGRAM_TIMCTL[HOLD] Bits */ 4684 #define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ 4685 #define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ 4686 /* FLCTL_ERASE_TIMCTL[SETUP] Bits */ 4687 #define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4688 #define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4689 /* FLCTL_ERASE_TIMCTL[ACTIVE] Bits */ 4690 #define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4691 #define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ 4692 /* FLCTL_ERASE_TIMCTL[HOLD] Bits */ 4693 #define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ 4694 #define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ 4695 /* FLCTL_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */ 4696 #define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ 4697 #define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ 4698 /* FLCTL_MASSERASE_TIMCTL[BOOST_HOLD] Bits */ 4699 #define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ 4700 #define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ 4701 /* FLCTL_BURSTPRG_TIMCTL[ACTIVE] Bits */ 4702 #define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4703 #define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ 4704 4705 /****************************************************************************** 4706 * FL_BOOTOVER_MAILBOX Bits 4707 ******************************************************************************/ 4708 4709 /****************************************************************************** 4710 * FPB Bits 4711 ******************************************************************************/ 4712 4713 4714 /****************************************************************************** 4715 * FPU Bits 4716 ******************************************************************************/ 4717 4718 4719 /****************************************************************************** 4720 * ITM Bits 4721 ******************************************************************************/ 4722 4723 4724 /****************************************************************************** 4725 * MPU Bits 4726 ******************************************************************************/ 4727 4728 /* Pre-defined bitfield values */ 4729 4730 /* MPU_RASR_SIZE Bitfield Bits */ 4731 #define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /*!< 32B */ 4732 #define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /*!< 64B */ 4733 #define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /*!< 128B */ 4734 #define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /*!< 256B */ 4735 #define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /*!< 512B */ 4736 #define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /*!< 1KB */ 4737 #define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /*!< 2KB */ 4738 #define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /*!< 4KB */ 4739 #define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /*!< 8KB */ 4740 #define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /*!< 16KB */ 4741 #define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /*!< 32KB */ 4742 #define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /*!< 64KB */ 4743 #define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /*!< 128KB */ 4744 #define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /*!< 256KB */ 4745 #define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /*!< 512KB */ 4746 #define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /*!< 1MB */ 4747 #define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /*!< 2MB */ 4748 #define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /*!< 4MB */ 4749 #define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /*!< 8MB */ 4750 #define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /*!< 16MB */ 4751 #define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /*!< 32MB */ 4752 #define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /*!< 64MB */ 4753 #define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /*!< 128MB */ 4754 #define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /*!< 256MB */ 4755 #define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /*!< 512MB */ 4756 #define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /*!< 1GB */ 4757 #define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /*!< 2GB */ 4758 #define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /*!< 4GB */ 4759 4760 /* MPU_RASR_AP Bitfield Bits */ 4761 #define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /*!< Privileged permissions: No access. User permissions: No access. */ 4762 #define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /*!< Privileged permissions: Read-write. User permissions: No access. */ 4763 #define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /*!< Privileged permissions: Read-write. User permissions: Read-only. */ 4764 #define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /*!< Privileged permissions: Read-write. User permissions: Read-write. */ 4765 #define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /*!< Privileged permissions: Read-only. User permissions: No access. */ 4766 #define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /*!< Privileged permissions: Read-only. User permissions: Read-only. */ 4767 4768 /* MPU_RASR_XN Bitfield Bits */ 4769 #define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /*!< Instruction access enabled */ 4770 #define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /*!< Instruction access disabled */ 4771 4772 4773 /****************************************************************************** 4774 * NVIC Bits 4775 ******************************************************************************/ 4776 4777 /* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */ 4778 #define NVIC_IPR0_PRI_0_OFS ( 0) /*!< PRI_0 Offset */ 4779 #define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */ 4780 /* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */ 4781 #define NVIC_IPR0_PRI_1_OFS ( 8) /*!< PRI_1 Offset */ 4782 #define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */ 4783 /* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */ 4784 #define NVIC_IPR0_PRI_2_OFS (16) /*!< PRI_2 Offset */ 4785 #define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */ 4786 /* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */ 4787 #define NVIC_IPR0_PRI_3_OFS (24) /*!< PRI_3 Offset */ 4788 #define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */ 4789 /* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */ 4790 #define NVIC_IPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ 4791 #define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ 4792 /* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */ 4793 #define NVIC_IPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ 4794 #define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ 4795 /* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */ 4796 #define NVIC_IPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ 4797 #define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ 4798 /* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */ 4799 #define NVIC_IPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ 4800 #define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */ 4801 /* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */ 4802 #define NVIC_IPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ 4803 #define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ 4804 /* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */ 4805 #define NVIC_IPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ 4806 #define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ 4807 /* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */ 4808 #define NVIC_IPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ 4809 #define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ 4810 /* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */ 4811 #define NVIC_IPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ 4812 #define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */ 4813 /* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */ 4814 #define NVIC_IPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ 4815 #define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ 4816 /* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */ 4817 #define NVIC_IPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ 4818 #define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ 4819 /* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */ 4820 #define NVIC_IPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ 4821 #define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ 4822 /* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */ 4823 #define NVIC_IPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ 4824 #define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */ 4825 /* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */ 4826 #define NVIC_IPR4_PRI_16_OFS ( 0) /*!< PRI_16 Offset */ 4827 #define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */ 4828 /* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */ 4829 #define NVIC_IPR4_PRI_17_OFS ( 8) /*!< PRI_17 Offset */ 4830 #define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */ 4831 /* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */ 4832 #define NVIC_IPR4_PRI_18_OFS (16) /*!< PRI_18 Offset */ 4833 #define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */ 4834 /* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */ 4835 #define NVIC_IPR4_PRI_19_OFS (24) /*!< PRI_19 Offset */ 4836 #define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */ 4837 /* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */ 4838 #define NVIC_IPR5_PRI_20_OFS ( 0) /*!< PRI_20 Offset */ 4839 #define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */ 4840 /* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */ 4841 #define NVIC_IPR5_PRI_21_OFS ( 8) /*!< PRI_21 Offset */ 4842 #define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */ 4843 /* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */ 4844 #define NVIC_IPR5_PRI_22_OFS (16) /*!< PRI_22 Offset */ 4845 #define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */ 4846 /* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */ 4847 #define NVIC_IPR5_PRI_23_OFS (24) /*!< PRI_23 Offset */ 4848 #define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */ 4849 /* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */ 4850 #define NVIC_IPR6_PRI_24_OFS ( 0) /*!< PRI_24 Offset */ 4851 #define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */ 4852 /* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */ 4853 #define NVIC_IPR6_PRI_25_OFS ( 8) /*!< PRI_25 Offset */ 4854 #define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */ 4855 /* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */ 4856 #define NVIC_IPR6_PRI_26_OFS (16) /*!< PRI_26 Offset */ 4857 #define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */ 4858 /* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */ 4859 #define NVIC_IPR6_PRI_27_OFS (24) /*!< PRI_27 Offset */ 4860 #define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */ 4861 /* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */ 4862 #define NVIC_IPR7_PRI_28_OFS ( 0) /*!< PRI_28 Offset */ 4863 #define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */ 4864 /* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */ 4865 #define NVIC_IPR7_PRI_29_OFS ( 8) /*!< PRI_29 Offset */ 4866 #define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */ 4867 /* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */ 4868 #define NVIC_IPR7_PRI_30_OFS (16) /*!< PRI_30 Offset */ 4869 #define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */ 4870 /* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */ 4871 #define NVIC_IPR7_PRI_31_OFS (24) /*!< PRI_31 Offset */ 4872 #define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */ 4873 /* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */ 4874 #define NVIC_IPR8_PRI_32_OFS ( 0) /*!< PRI_32 Offset */ 4875 #define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */ 4876 /* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */ 4877 #define NVIC_IPR8_PRI_33_OFS ( 8) /*!< PRI_33 Offset */ 4878 #define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */ 4879 /* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */ 4880 #define NVIC_IPR8_PRI_34_OFS (16) /*!< PRI_34 Offset */ 4881 #define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */ 4882 /* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */ 4883 #define NVIC_IPR8_PRI_35_OFS (24) /*!< PRI_35 Offset */ 4884 #define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */ 4885 /* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */ 4886 #define NVIC_IPR9_PRI_36_OFS ( 0) /*!< PRI_36 Offset */ 4887 #define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */ 4888 /* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */ 4889 #define NVIC_IPR9_PRI_37_OFS ( 8) /*!< PRI_37 Offset */ 4890 #define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */ 4891 /* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */ 4892 #define NVIC_IPR9_PRI_38_OFS (16) /*!< PRI_38 Offset */ 4893 #define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */ 4894 /* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */ 4895 #define NVIC_IPR9_PRI_39_OFS (24) /*!< PRI_39 Offset */ 4896 #define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */ 4897 /* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */ 4898 #define NVIC_IPR10_PRI_40_OFS ( 0) /*!< PRI_40 Offset */ 4899 #define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */ 4900 /* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */ 4901 #define NVIC_IPR10_PRI_41_OFS ( 8) /*!< PRI_41 Offset */ 4902 #define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */ 4903 /* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */ 4904 #define NVIC_IPR10_PRI_42_OFS (16) /*!< PRI_42 Offset */ 4905 #define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */ 4906 /* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */ 4907 #define NVIC_IPR10_PRI_43_OFS (24) /*!< PRI_43 Offset */ 4908 #define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */ 4909 /* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */ 4910 #define NVIC_IPR11_PRI_44_OFS ( 0) /*!< PRI_44 Offset */ 4911 #define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */ 4912 /* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */ 4913 #define NVIC_IPR11_PRI_45_OFS ( 8) /*!< PRI_45 Offset */ 4914 #define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */ 4915 /* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */ 4916 #define NVIC_IPR11_PRI_46_OFS (16) /*!< PRI_46 Offset */ 4917 #define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */ 4918 /* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */ 4919 #define NVIC_IPR11_PRI_47_OFS (24) /*!< PRI_47 Offset */ 4920 #define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */ 4921 /* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */ 4922 #define NVIC_IPR12_PRI_48_OFS ( 0) /*!< PRI_48 Offset */ 4923 #define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */ 4924 /* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */ 4925 #define NVIC_IPR12_PRI_49_OFS ( 8) /*!< PRI_49 Offset */ 4926 #define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */ 4927 /* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */ 4928 #define NVIC_IPR12_PRI_50_OFS (16) /*!< PRI_50 Offset */ 4929 #define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */ 4930 /* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */ 4931 #define NVIC_IPR12_PRI_51_OFS (24) /*!< PRI_51 Offset */ 4932 #define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */ 4933 /* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */ 4934 #define NVIC_IPR13_PRI_52_OFS ( 0) /*!< PRI_52 Offset */ 4935 #define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */ 4936 /* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */ 4937 #define NVIC_IPR13_PRI_53_OFS ( 8) /*!< PRI_53 Offset */ 4938 #define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */ 4939 /* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */ 4940 #define NVIC_IPR13_PRI_54_OFS (16) /*!< PRI_54 Offset */ 4941 #define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */ 4942 /* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */ 4943 #define NVIC_IPR13_PRI_55_OFS (24) /*!< PRI_55 Offset */ 4944 #define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */ 4945 /* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */ 4946 #define NVIC_IPR14_PRI_56_OFS ( 0) /*!< PRI_56 Offset */ 4947 #define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */ 4948 /* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */ 4949 #define NVIC_IPR14_PRI_57_OFS ( 8) /*!< PRI_57 Offset */ 4950 #define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */ 4951 /* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */ 4952 #define NVIC_IPR14_PRI_58_OFS (16) /*!< PRI_58 Offset */ 4953 #define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */ 4954 /* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */ 4955 #define NVIC_IPR14_PRI_59_OFS (24) /*!< PRI_59 Offset */ 4956 #define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */ 4957 /* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */ 4958 #define NVIC_IPR15_PRI_60_OFS ( 0) /*!< PRI_60 Offset */ 4959 #define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */ 4960 /* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */ 4961 #define NVIC_IPR15_PRI_61_OFS ( 8) /*!< PRI_61 Offset */ 4962 #define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */ 4963 /* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */ 4964 #define NVIC_IPR15_PRI_62_OFS (16) /*!< PRI_62 Offset */ 4965 #define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */ 4966 /* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */ 4967 #define NVIC_IPR15_PRI_63_OFS (24) /*!< PRI_63 Offset */ 4968 #define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */ 4969 4970 4971 /****************************************************************************** 4972 * PCM Bits 4973 ******************************************************************************/ 4974 /* PCM_CTL0[AMR] Bits */ 4975 #define PCM_CTL0_AMR_OFS ( 0) /*!< AMR Bit Offset */ 4976 #define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /*!< AMR Bit Mask */ 4977 #define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /*!< AMR Bit 0 */ 4978 #define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /*!< AMR Bit 1 */ 4979 #define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /*!< AMR Bit 2 */ 4980 #define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /*!< AMR Bit 3 */ 4981 #define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 4982 #define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ 4983 #define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 4984 #define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 4985 #define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 4986 #define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 4987 #define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 4988 #define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ 4989 #define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 4990 #define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 4991 #define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 4992 #define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 4993 /* PCM_CTL0[LPMR] Bits */ 4994 #define PCM_CTL0_LPMR_OFS ( 4) /*!< LPMR Bit Offset */ 4995 #define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /*!< LPMR Bit Mask */ 4996 #define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /*!< LPMR Bit 0 */ 4997 #define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /*!< LPMR Bit 1 */ 4998 #define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /*!< LPMR Bit 2 */ 4999 #define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /*!< LPMR Bit 3 */ 5000 #define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ 5001 /* entered. */ 5002 #define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ 5003 #define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /*!< LPM4.5 */ 5004 #define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ 5005 /* entered. */ 5006 #define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ 5007 #define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /*!< LPM4.5 */ 5008 /* PCM_CTL0[CPM] Bits */ 5009 #define PCM_CTL0_CPM_OFS ( 8) /*!< CPM Bit Offset */ 5010 #define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /*!< CPM Bit Mask */ 5011 #define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /*!< CPM Bit 0 */ 5012 #define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /*!< CPM Bit 1 */ 5013 #define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /*!< CPM Bit 2 */ 5014 #define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /*!< CPM Bit 3 */ 5015 #define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /*!< CPM Bit 4 */ 5016 #define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /*!< CPM Bit 5 */ 5017 #define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 5018 #define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ 5019 #define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 5020 #define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 5021 #define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 5022 #define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 5023 #define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ 5024 #define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ 5025 #define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ 5026 #define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ 5027 #define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ 5028 #define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ 5029 #define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /*!< LPM3 */ 5030 #define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 5031 #define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ 5032 #define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 5033 #define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 5034 #define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 5035 #define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 5036 #define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ 5037 #define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ 5038 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ 5039 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ 5040 #define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ 5041 #define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ 5042 #define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /*!< LPM3 */ 5043 /* PCM_CTL0[KEY] Bits */ 5044 #define PCM_CTL0_KEY_OFS (16) /*!< PCMKEY Bit Offset */ 5045 #define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ 5046 /* PCM_CTL1[LOCKLPM5] Bits */ 5047 #define PCM_CTL1_LOCKLPM5_OFS ( 0) /*!< LOCKLPM5 Bit Offset */ 5048 #define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /*!< Lock LPM5 */ 5049 /* PCM_CTL1[LOCKBKUP] Bits */ 5050 #define PCM_CTL1_LOCKBKUP_OFS ( 1) /*!< LOCKBKUP Bit Offset */ 5051 #define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /*!< Lock Backup */ 5052 /* PCM_CTL1[FORCE_LPM_ENTRY] Bits */ 5053 #define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /*!< FORCE_LPM_ENTRY Bit Offset */ 5054 #define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /*!< Force LPM entry */ 5055 /* PCM_CTL1[PMR_BUSY] Bits */ 5056 #define PCM_CTL1_PMR_BUSY_OFS ( 8) /*!< PMR_BUSY Bit Offset */ 5057 #define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /*!< Power mode request busy flag */ 5058 /* PCM_CTL1[KEY] Bits */ 5059 #define PCM_CTL1_KEY_OFS (16) /*!< PCMKEY Bit Offset */ 5060 #define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ 5061 /* PCM_IE[LPM_INVALID_TR_IE] Bits */ 5062 #define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /*!< LPM_INVALID_TR_IE Bit Offset */ 5063 #define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /*!< LPM invalid transition interrupt enable */ 5064 /* PCM_IE[LPM_INVALID_CLK_IE] Bits */ 5065 #define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /*!< LPM_INVALID_CLK_IE Bit Offset */ 5066 #define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /*!< LPM invalid clock interrupt enable */ 5067 /* PCM_IE[AM_INVALID_TR_IE] Bits */ 5068 #define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /*!< AM_INVALID_TR_IE Bit Offset */ 5069 #define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /*!< Active mode invalid transition interrupt enable */ 5070 /* PCM_IE[DCDC_ERROR_IE] Bits */ 5071 #define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /*!< DCDC_ERROR_IE Bit Offset */ 5072 #define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /*!< DC-DC error interrupt enable */ 5073 /* PCM_IFG[LPM_INVALID_TR_IFG] Bits */ 5074 #define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /*!< LPM_INVALID_TR_IFG Bit Offset */ 5075 #define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< LPM invalid transition flag */ 5076 /* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */ 5077 #define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< LPM_INVALID_CLK_IFG Bit Offset */ 5078 #define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< LPM invalid clock flag */ 5079 /* PCM_IFG[AM_INVALID_TR_IFG] Bits */ 5080 #define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /*!< AM_INVALID_TR_IFG Bit Offset */ 5081 #define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Active mode invalid transition flag */ 5082 /* PCM_IFG[DCDC_ERROR_IFG] Bits */ 5083 #define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /*!< DCDC_ERROR_IFG Bit Offset */ 5084 #define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< DC-DC error flag */ 5085 /* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */ 5086 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */ 5087 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< Clear LPM invalid transition flag */ 5088 /* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */ 5089 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */ 5090 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< Clear LPM invalid clock flag */ 5091 /* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */ 5092 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /*!< CLR_AM_INVALID_TR_IFG Bit Offset */ 5093 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Clear active mode invalid transition flag */ 5094 /* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */ 5095 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /*!< CLR_DCDC_ERROR_IFG Bit Offset */ 5096 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< Clear DC-DC error flag */ 5097 /* Pre-defined bitfield values */ 5098 #define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ 5099 #define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ 5100 5101 5102 /****************************************************************************** 5103 * PMAP Bits 5104 ******************************************************************************/ 5105 /* PMAP_CTL[LOCKED] Bits */ 5106 #define PMAP_CTL_LOCKED_OFS ( 0) /*!< PMAPLOCKED Bit Offset */ 5107 #define PMAP_CTL_LOCKED ((uint16_t)0x0001) /*!< Port mapping lock bit */ 5108 /* PMAP_CTL[PRECFG] Bits */ 5109 #define PMAP_CTL_PRECFG_OFS ( 1) /*!< PMAPRECFG Bit Offset */ 5110 #define PMAP_CTL_PRECFG ((uint16_t)0x0002) /*!< Port mapping reconfiguration control bit */ 5111 /* Pre-defined bitfield values */ 5112 #define PMAP_NONE 0 5113 #define PMAP_UCA0CLK 1 5114 #define PMAP_UCA0RXD 2 5115 #define PMAP_UCA0SOMI 2 5116 #define PMAP_UCA0TXD 3 5117 #define PMAP_UCA0SIMO 3 5118 #define PMAP_UCB0CLK 4 5119 #define PMAP_UCB0SDA 5 5120 #define PMAP_UCB0SIMO 5 5121 #define PMAP_UCB0SCL 6 5122 #define PMAP_UCB0SOMI 6 5123 #define PMAP_UCA1STE 7 5124 #define PMAP_UCA1CLK 8 5125 #define PMAP_UCA1RXD 9 5126 #define PMAP_UCA1SOMI 9 5127 #define PMAP_UCA1TXD 10 5128 #define PMAP_UCA1SIMO 10 5129 #define PMAP_UCA2STE 11 5130 #define PMAP_UCA2CLK 12 5131 #define PMAP_UCA2RXD 13 5132 #define PMAP_UCA2SOMI 13 5133 #define PMAP_UCA2TXD 14 5134 #define PMAP_UCA2SIMO 14 5135 #define PMAP_UCB2STE 15 5136 #define PMAP_UCB2CLK 16 5137 #define PMAP_UCB2SDA 17 5138 #define PMAP_UCB2SIMO 17 5139 #define PMAP_UCB2SCL 18 5140 #define PMAP_UCB2SOMI 18 5141 #define PMAP_TA0CCR0A 19 5142 #define PMAP_TA0CCR1A 20 5143 #define PMAP_TA0CCR2A 21 5144 #define PMAP_TA0CCR3A 22 5145 #define PMAP_TA0CCR4A 23 5146 #define PMAP_TA1CCR1A 24 5147 #define PMAP_TA1CCR2A 25 5148 #define PMAP_TA1CCR3A 26 5149 #define PMAP_TA1CCR4A 27 5150 #define PMAP_TA0CLK 28 5151 #define PMAP_CE0OUT 28 5152 #define PMAP_TA1CLK 29 5153 #define PMAP_CE1OUT 29 5154 #define PMAP_DMAE0 30 5155 #define PMAP_SMCLK 30 5156 #define PMAP_ANALOG 31 5157 5158 #define PMAP_KEYID_VAL ((uint16_t)0x2D52) /*!< Port Mapping Key */ 5159 5160 5161 /****************************************************************************** 5162 * PSS Bits 5163 ******************************************************************************/ 5164 /* PSS_KEY[KEY] Bits */ 5165 #define PSS_KEY_KEY_OFS ( 0) /*!< PSSKEY Bit Offset */ 5166 #define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< PSSKEY Bit Mask */ 5167 /* PSS_CTL0[SVSMHOFF] Bits */ 5168 #define PSS_CTL0_SVSMHOFF_OFS ( 0) /*!< SVSMHOFF Bit Offset */ 5169 #define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /*!< SVSM high-side off */ 5170 /* PSS_CTL0[SVSMHLP] Bits */ 5171 #define PSS_CTL0_SVSMHLP_OFS ( 1) /*!< SVSMHLP Bit Offset */ 5172 #define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /*!< SVSM high-side low power normal performance mode */ 5173 /* PSS_CTL0[SVSMHS] Bits */ 5174 #define PSS_CTL0_SVSMHS_OFS ( 2) /*!< SVSMHS Bit Offset */ 5175 #define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /*!< Supply supervisor or monitor selection for the high-side */ 5176 /* PSS_CTL0[SVSMHTH] Bits */ 5177 #define PSS_CTL0_SVSMHTH_OFS ( 3) /*!< SVSMHTH Bit Offset */ 5178 #define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /*!< SVSMHTH Bit Mask */ 5179 /* PSS_CTL0[SVMHOE] Bits */ 5180 #define PSS_CTL0_SVMHOE_OFS ( 6) /*!< SVMHOE Bit Offset */ 5181 #define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /*!< SVSM high-side output enable */ 5182 /* PSS_CTL0[SVMHOUTPOLAL] Bits */ 5183 #define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /*!< SVMHOUTPOLAL Bit Offset */ 5184 #define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /*!< SVMHOUT pin polarity active low */ 5185 /* PSS_CTL0[DCDC_FORCE] Bits */ 5186 #define PSS_CTL0_DCDC_FORCE_OFS (10) /*!< DCDC_FORCE Bit Offset */ 5187 #define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /*!< Force DC-DC regulator operation */ 5188 /* PSS_CTL0[VCORETRAN] Bits */ 5189 #define PSS_CTL0_VCORETRAN_OFS (12) /*!< VCORETRAN Bit Offset */ 5190 #define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /*!< VCORETRAN Bit Mask */ 5191 #define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /*!< VCORETRAN Bit 0 */ 5192 #define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /*!< VCORETRAN Bit 1 */ 5193 #define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ 5194 #define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ 5195 #define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ 5196 #define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ 5197 #define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ 5198 #define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ 5199 #define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ 5200 #define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ 5201 /* PSS_IE[SVSMHIE] Bits */ 5202 #define PSS_IE_SVSMHIE_OFS ( 1) /*!< SVSMHIE Bit Offset */ 5203 #define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /*!< High-side SVSM interrupt enable */ 5204 /* PSS_IFG[SVSMHIFG] Bits */ 5205 #define PSS_IFG_SVSMHIFG_OFS ( 1) /*!< SVSMHIFG Bit Offset */ 5206 #define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /*!< High-side SVSM interrupt flag */ 5207 /* PSS_CLRIFG[CLRSVSMHIFG] Bits */ 5208 #define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /*!< CLRSVSMHIFG Bit Offset */ 5209 #define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /*!< SVSMH clear interrupt flag */ 5210 /* Pre-defined bitfield values */ 5211 #define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /*!< PSS control key value */ 5212 5213 5214 /****************************************************************************** 5215 * REF_A Bits 5216 ******************************************************************************/ 5217 /* REF_A_CTL0[ON] Bits */ 5218 #define REF_A_CTL0_ON_OFS ( 0) /*!< REFON Bit Offset */ 5219 #define REF_A_CTL0_ON ((uint16_t)0x0001) /*!< Reference enable */ 5220 /* REF_A_CTL0[OUT] Bits */ 5221 #define REF_A_CTL0_OUT_OFS ( 1) /*!< REFOUT Bit Offset */ 5222 #define REF_A_CTL0_OUT ((uint16_t)0x0002) /*!< Reference output buffer */ 5223 /* REF_A_CTL0[TCOFF] Bits */ 5224 #define REF_A_CTL0_TCOFF_OFS ( 3) /*!< REFTCOFF Bit Offset */ 5225 #define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /*!< Temperature sensor disabled */ 5226 /* REF_A_CTL0[VSEL] Bits */ 5227 #define REF_A_CTL0_VSEL_OFS ( 4) /*!< REFVSEL Bit Offset */ 5228 #define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /*!< REFVSEL Bit Mask */ 5229 #define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /*!< VSEL Bit 0 */ 5230 #define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /*!< VSEL Bit 1 */ 5231 #define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /*!< 1.2 V available when reference requested or REFON = 1 */ 5232 #define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /*!< 1.45 V available when reference requested or REFON = 1 */ 5233 #define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /*!< 2.5 V available when reference requested or REFON = 1 */ 5234 /* REF_A_CTL0[GENOT] Bits */ 5235 #define REF_A_CTL0_GENOT_OFS ( 6) /*!< REFGENOT Bit Offset */ 5236 #define REF_A_CTL0_GENOT ((uint16_t)0x0040) /*!< Reference generator one-time trigger */ 5237 /* REF_A_CTL0[BGOT] Bits */ 5238 #define REF_A_CTL0_BGOT_OFS ( 7) /*!< REFBGOT Bit Offset */ 5239 #define REF_A_CTL0_BGOT ((uint16_t)0x0080) /*!< Bandgap and bandgap buffer one-time trigger */ 5240 /* REF_A_CTL0[GENACT] Bits */ 5241 #define REF_A_CTL0_GENACT_OFS ( 8) /*!< REFGENACT Bit Offset */ 5242 #define REF_A_CTL0_GENACT ((uint16_t)0x0100) /*!< Reference generator active */ 5243 /* REF_A_CTL0[BGACT] Bits */ 5244 #define REF_A_CTL0_BGACT_OFS ( 9) /*!< REFBGACT Bit Offset */ 5245 #define REF_A_CTL0_BGACT ((uint16_t)0x0200) /*!< Reference bandgap active */ 5246 /* REF_A_CTL0[GENBUSY] Bits */ 5247 #define REF_A_CTL0_GENBUSY_OFS (10) /*!< REFGENBUSY Bit Offset */ 5248 #define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /*!< Reference generator busy */ 5249 /* REF_A_CTL0[BGMODE] Bits */ 5250 #define REF_A_CTL0_BGMODE_OFS (11) /*!< BGMODE Bit Offset */ 5251 #define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /*!< Bandgap mode */ 5252 /* REF_A_CTL0[GENRDY] Bits */ 5253 #define REF_A_CTL0_GENRDY_OFS (12) /*!< REFGENRDY Bit Offset */ 5254 #define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /*!< Variable reference voltage ready status */ 5255 /* REF_A_CTL0[BGRDY] Bits */ 5256 #define REF_A_CTL0_BGRDY_OFS (13) /*!< REFBGRDY Bit Offset */ 5257 #define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /*!< Buffered bandgap voltage ready status */ 5258 5259 /****************************************************************************** 5260 * RSTCTL Bits 5261 ******************************************************************************/ 5262 /* RSTCTL_RESET_REQ[SOFT_REQ] Bits */ 5263 #define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /*!< SOFT_REQ Bit Offset */ 5264 #define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /*!< Soft Reset request */ 5265 /* RSTCTL_RESET_REQ[HARD_REQ] Bits */ 5266 #define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /*!< HARD_REQ Bit Offset */ 5267 #define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /*!< Hard Reset request */ 5268 /* RSTCTL_RESET_REQ[RSTKEY] Bits */ 5269 #define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /*!< RSTKEY Bit Offset */ 5270 #define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /*!< RSTKEY Bit Mask */ 5271 /* RSTCTL_HARDRESET_STAT[SRC0] Bits */ 5272 #define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5273 #define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< Indicates that SRC0 was the source of the Hard Reset */ 5274 /* RSTCTL_HARDRESET_STAT[SRC1] Bits */ 5275 #define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5276 #define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< Indicates that SRC1 was the source of the Hard Reset */ 5277 /* RSTCTL_HARDRESET_STAT[SRC2] Bits */ 5278 #define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5279 #define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< Indicates that SRC2 was the source of the Hard Reset */ 5280 /* RSTCTL_HARDRESET_STAT[SRC3] Bits */ 5281 #define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5282 #define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< Indicates that SRC3 was the source of the Hard Reset */ 5283 /* RSTCTL_HARDRESET_STAT[SRC4] Bits */ 5284 #define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5285 #define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< Indicates that SRC4 was the source of the Hard Reset */ 5286 /* RSTCTL_HARDRESET_STAT[SRC5] Bits */ 5287 #define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5288 #define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< Indicates that SRC5 was the source of the Hard Reset */ 5289 /* RSTCTL_HARDRESET_STAT[SRC6] Bits */ 5290 #define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5291 #define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< Indicates that SRC6 was the source of the Hard Reset */ 5292 /* RSTCTL_HARDRESET_STAT[SRC7] Bits */ 5293 #define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5294 #define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< Indicates that SRC7 was the source of the Hard Reset */ 5295 /* RSTCTL_HARDRESET_STAT[SRC8] Bits */ 5296 #define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5297 #define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< Indicates that SRC8 was the source of the Hard Reset */ 5298 /* RSTCTL_HARDRESET_STAT[SRC9] Bits */ 5299 #define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5300 #define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< Indicates that SRC9 was the source of the Hard Reset */ 5301 /* RSTCTL_HARDRESET_STAT[SRC10] Bits */ 5302 #define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5303 #define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< Indicates that SRC10 was the source of the Hard Reset */ 5304 /* RSTCTL_HARDRESET_STAT[SRC11] Bits */ 5305 #define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5306 #define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< Indicates that SRC11 was the source of the Hard Reset */ 5307 /* RSTCTL_HARDRESET_STAT[SRC12] Bits */ 5308 #define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5309 #define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< Indicates that SRC12 was the source of the Hard Reset */ 5310 /* RSTCTL_HARDRESET_STAT[SRC13] Bits */ 5311 #define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5312 #define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< Indicates that SRC13 was the source of the Hard Reset */ 5313 /* RSTCTL_HARDRESET_STAT[SRC14] Bits */ 5314 #define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5315 #define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< Indicates that SRC14 was the source of the Hard Reset */ 5316 /* RSTCTL_HARDRESET_STAT[SRC15] Bits */ 5317 #define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5318 #define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< Indicates that SRC15 was the source of the Hard Reset */ 5319 /* RSTCTL_HARDRESET_CLR[SRC0] Bits */ 5320 #define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5321 #define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5322 /* RSTCTL_HARDRESET_CLR[SRC1] Bits */ 5323 #define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5324 #define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5325 /* RSTCTL_HARDRESET_CLR[SRC2] Bits */ 5326 #define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5327 #define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5328 /* RSTCTL_HARDRESET_CLR[SRC3] Bits */ 5329 #define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5330 #define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5331 /* RSTCTL_HARDRESET_CLR[SRC4] Bits */ 5332 #define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5333 #define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5334 /* RSTCTL_HARDRESET_CLR[SRC5] Bits */ 5335 #define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5336 #define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5337 /* RSTCTL_HARDRESET_CLR[SRC6] Bits */ 5338 #define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5339 #define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5340 /* RSTCTL_HARDRESET_CLR[SRC7] Bits */ 5341 #define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5342 #define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5343 /* RSTCTL_HARDRESET_CLR[SRC8] Bits */ 5344 #define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5345 #define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5346 /* RSTCTL_HARDRESET_CLR[SRC9] Bits */ 5347 #define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5348 #define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5349 /* RSTCTL_HARDRESET_CLR[SRC10] Bits */ 5350 #define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5351 #define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5352 /* RSTCTL_HARDRESET_CLR[SRC11] Bits */ 5353 #define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5354 #define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5355 /* RSTCTL_HARDRESET_CLR[SRC12] Bits */ 5356 #define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5357 #define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5358 /* RSTCTL_HARDRESET_CLR[SRC13] Bits */ 5359 #define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5360 #define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5361 /* RSTCTL_HARDRESET_CLR[SRC14] Bits */ 5362 #define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5363 #define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5364 /* RSTCTL_HARDRESET_CLR[SRC15] Bits */ 5365 #define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5366 #define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */ 5367 /* RSTCTL_HARDRESET_SET[SRC0] Bits */ 5368 #define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5369 #define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5370 /* initiates a Hard Reset) */ 5371 /* RSTCTL_HARDRESET_SET[SRC1] Bits */ 5372 #define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5373 #define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5374 /* initiates a Hard Reset) */ 5375 /* RSTCTL_HARDRESET_SET[SRC2] Bits */ 5376 #define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5377 #define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5378 /* initiates a Hard Reset) */ 5379 /* RSTCTL_HARDRESET_SET[SRC3] Bits */ 5380 #define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5381 #define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5382 /* initiates a Hard Reset) */ 5383 /* RSTCTL_HARDRESET_SET[SRC4] Bits */ 5384 #define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5385 #define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5386 /* initiates a Hard Reset) */ 5387 /* RSTCTL_HARDRESET_SET[SRC5] Bits */ 5388 #define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5389 #define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5390 /* initiates a Hard Reset) */ 5391 /* RSTCTL_HARDRESET_SET[SRC6] Bits */ 5392 #define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5393 #define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5394 /* initiates a Hard Reset) */ 5395 /* RSTCTL_HARDRESET_SET[SRC7] Bits */ 5396 #define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5397 #define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5398 /* initiates a Hard Reset) */ 5399 /* RSTCTL_HARDRESET_SET[SRC8] Bits */ 5400 #define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5401 #define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5402 /* initiates a Hard Reset) */ 5403 /* RSTCTL_HARDRESET_SET[SRC9] Bits */ 5404 #define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5405 #define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5406 /* initiates a Hard Reset) */ 5407 /* RSTCTL_HARDRESET_SET[SRC10] Bits */ 5408 #define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5409 #define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5410 /* initiates a Hard Reset) */ 5411 /* RSTCTL_HARDRESET_SET[SRC11] Bits */ 5412 #define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5413 #define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5414 /* initiates a Hard Reset) */ 5415 /* RSTCTL_HARDRESET_SET[SRC12] Bits */ 5416 #define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5417 #define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5418 /* initiates a Hard Reset) */ 5419 /* RSTCTL_HARDRESET_SET[SRC13] Bits */ 5420 #define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5421 #define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5422 /* initiates a Hard Reset) */ 5423 /* RSTCTL_HARDRESET_SET[SRC14] Bits */ 5424 #define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5425 #define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5426 /* initiates a Hard Reset) */ 5427 /* RSTCTL_HARDRESET_SET[SRC15] Bits */ 5428 #define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5429 #define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5430 /* initiates a Hard Reset) */ 5431 /* RSTCTL_SOFTRESET_STAT[SRC0] Bits */ 5432 #define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5433 #define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< If 1, indicates that SRC0 was the source of the Soft Reset */ 5434 /* RSTCTL_SOFTRESET_STAT[SRC1] Bits */ 5435 #define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5436 #define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */ 5437 /* RSTCTL_SOFTRESET_STAT[SRC2] Bits */ 5438 #define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5439 #define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< If 1, indicates that SRC2 was the source of the Soft Reset */ 5440 /* RSTCTL_SOFTRESET_STAT[SRC3] Bits */ 5441 #define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5442 #define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< If 1, indicates that SRC3 was the source of the Soft Reset */ 5443 /* RSTCTL_SOFTRESET_STAT[SRC4] Bits */ 5444 #define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5445 #define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< If 1, indicates that SRC4 was the source of the Soft Reset */ 5446 /* RSTCTL_SOFTRESET_STAT[SRC5] Bits */ 5447 #define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5448 #define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< If 1, indicates that SRC5 was the source of the Soft Reset */ 5449 /* RSTCTL_SOFTRESET_STAT[SRC6] Bits */ 5450 #define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5451 #define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< If 1, indicates that SRC6 was the source of the Soft Reset */ 5452 /* RSTCTL_SOFTRESET_STAT[SRC7] Bits */ 5453 #define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5454 #define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< If 1, indicates that SRC7 was the source of the Soft Reset */ 5455 /* RSTCTL_SOFTRESET_STAT[SRC8] Bits */ 5456 #define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5457 #define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< If 1, indicates that SRC8 was the source of the Soft Reset */ 5458 /* RSTCTL_SOFTRESET_STAT[SRC9] Bits */ 5459 #define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5460 #define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< If 1, indicates that SRC9 was the source of the Soft Reset */ 5461 /* RSTCTL_SOFTRESET_STAT[SRC10] Bits */ 5462 #define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5463 #define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< If 1, indicates that SRC10 was the source of the Soft Reset */ 5464 /* RSTCTL_SOFTRESET_STAT[SRC11] Bits */ 5465 #define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5466 #define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< If 1, indicates that SRC11 was the source of the Soft Reset */ 5467 /* RSTCTL_SOFTRESET_STAT[SRC12] Bits */ 5468 #define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5469 #define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< If 1, indicates that SRC12 was the source of the Soft Reset */ 5470 /* RSTCTL_SOFTRESET_STAT[SRC13] Bits */ 5471 #define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5472 #define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< If 1, indicates that SRC13 was the source of the Soft Reset */ 5473 /* RSTCTL_SOFTRESET_STAT[SRC14] Bits */ 5474 #define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5475 #define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< If 1, indicates that SRC14 was the source of the Soft Reset */ 5476 /* RSTCTL_SOFTRESET_STAT[SRC15] Bits */ 5477 #define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5478 #define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< If 1, indicates that SRC15 was the source of the Soft Reset */ 5479 /* RSTCTL_SOFTRESET_CLR[SRC0] Bits */ 5480 #define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5481 #define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5482 /* RSTCTL_SOFTRESET_CLR[SRC1] Bits */ 5483 #define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5484 #define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5485 /* RSTCTL_SOFTRESET_CLR[SRC2] Bits */ 5486 #define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5487 #define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5488 /* RSTCTL_SOFTRESET_CLR[SRC3] Bits */ 5489 #define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5490 #define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5491 /* RSTCTL_SOFTRESET_CLR[SRC4] Bits */ 5492 #define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5493 #define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5494 /* RSTCTL_SOFTRESET_CLR[SRC5] Bits */ 5495 #define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5496 #define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5497 /* RSTCTL_SOFTRESET_CLR[SRC6] Bits */ 5498 #define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5499 #define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5500 /* RSTCTL_SOFTRESET_CLR[SRC7] Bits */ 5501 #define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5502 #define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5503 /* RSTCTL_SOFTRESET_CLR[SRC8] Bits */ 5504 #define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5505 #define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5506 /* RSTCTL_SOFTRESET_CLR[SRC9] Bits */ 5507 #define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5508 #define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5509 /* RSTCTL_SOFTRESET_CLR[SRC10] Bits */ 5510 #define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5511 #define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5512 /* RSTCTL_SOFTRESET_CLR[SRC11] Bits */ 5513 #define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5514 #define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5515 /* RSTCTL_SOFTRESET_CLR[SRC12] Bits */ 5516 #define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5517 #define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5518 /* RSTCTL_SOFTRESET_CLR[SRC13] Bits */ 5519 #define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5520 #define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5521 /* RSTCTL_SOFTRESET_CLR[SRC14] Bits */ 5522 #define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5523 #define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5524 /* RSTCTL_SOFTRESET_CLR[SRC15] Bits */ 5525 #define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5526 #define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5527 /* RSTCTL_SOFTRESET_SET[SRC0] Bits */ 5528 #define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5529 #define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5530 /* initiates a Soft Reset) */ 5531 /* RSTCTL_SOFTRESET_SET[SRC1] Bits */ 5532 #define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5533 #define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5534 /* initiates a Soft Reset) */ 5535 /* RSTCTL_SOFTRESET_SET[SRC2] Bits */ 5536 #define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5537 #define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5538 /* initiates a Soft Reset) */ 5539 /* RSTCTL_SOFTRESET_SET[SRC3] Bits */ 5540 #define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5541 #define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5542 /* initiates a Soft Reset) */ 5543 /* RSTCTL_SOFTRESET_SET[SRC4] Bits */ 5544 #define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5545 #define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5546 /* initiates a Soft Reset) */ 5547 /* RSTCTL_SOFTRESET_SET[SRC5] Bits */ 5548 #define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5549 #define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5550 /* initiates a Soft Reset) */ 5551 /* RSTCTL_SOFTRESET_SET[SRC6] Bits */ 5552 #define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5553 #define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5554 /* initiates a Soft Reset) */ 5555 /* RSTCTL_SOFTRESET_SET[SRC7] Bits */ 5556 #define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5557 #define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5558 /* initiates a Soft Reset) */ 5559 /* RSTCTL_SOFTRESET_SET[SRC8] Bits */ 5560 #define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5561 #define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5562 /* initiates a Soft Reset) */ 5563 /* RSTCTL_SOFTRESET_SET[SRC9] Bits */ 5564 #define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5565 #define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5566 /* initiates a Soft Reset) */ 5567 /* RSTCTL_SOFTRESET_SET[SRC10] Bits */ 5568 #define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5569 #define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5570 /* initiates a Soft Reset) */ 5571 /* RSTCTL_SOFTRESET_SET[SRC11] Bits */ 5572 #define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5573 #define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5574 /* initiates a Soft Reset) */ 5575 /* RSTCTL_SOFTRESET_SET[SRC12] Bits */ 5576 #define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5577 #define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5578 /* initiates a Soft Reset) */ 5579 /* RSTCTL_SOFTRESET_SET[SRC13] Bits */ 5580 #define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5581 #define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5582 /* initiates a Soft Reset) */ 5583 /* RSTCTL_SOFTRESET_SET[SRC14] Bits */ 5584 #define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5585 #define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5586 /* initiates a Soft Reset) */ 5587 /* RSTCTL_SOFTRESET_SET[SRC15] Bits */ 5588 #define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5589 #define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5590 /* initiates a Soft Reset) */ 5591 /* RSTCTL_PSSRESET_STAT[SVSMH] Bits */ 5592 #define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /*!< SVSMH Bit Offset */ 5593 #define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */ 5594 /* RSTCTL_PSSRESET_STAT[BGREF] Bits */ 5595 #define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /*!< BGREF Bit Offset */ 5596 #define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */ 5597 /* RSTCTL_PSSRESET_STAT[VCCDET] Bits */ 5598 #define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /*!< VCCDET Bit Offset */ 5599 #define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */ 5600 /* RSTCTL_PSSRESET_CLR[CLR] Bits */ 5601 #define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 5602 #define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */ 5603 /* RSTCTL_PCMRESET_STAT[LPM35] Bits */ 5604 #define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /*!< LPM35 Bit Offset */ 5605 #define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */ 5606 /* RSTCTL_PCMRESET_STAT[LPM45] Bits */ 5607 #define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /*!< LPM45 Bit Offset */ 5608 #define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */ 5609 /* RSTCTL_PCMRESET_CLR[CLR] Bits */ 5610 #define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 5611 #define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */ 5612 /* RSTCTL_PINRESET_STAT[RSTNMI] Bits */ 5613 #define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /*!< RSTNMI Bit Offset */ 5614 #define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /*!< POR was caused by RSTn/NMI pin based reset event */ 5615 /* RSTCTL_PINRESET_CLR[CLR] Bits */ 5616 #define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 5617 #define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */ 5618 /* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */ 5619 #define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ 5620 #define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /*!< Indicates if Reboot reset was caused by the SYSCTL module. */ 5621 /* RSTCTL_REBOOTRESET_CLR[CLR] Bits */ 5622 #define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 5623 #define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */ 5624 /* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */ 5625 #define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /*!< DCOR_SHT Bit Offset */ 5626 #define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /*!< Indicates if POR was caused by DCO short circuit fault in the external */ 5627 /* resistor mode */ 5628 /* RSTCTL_CSRESET_CLR[CLR] Bits */ 5629 #define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 5630 #define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as */ 5631 /* DCOR_SHTIFG flag in CSIFG register of clock system */ 5632 /* Pre-defined bitfield values */ 5633 #define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bits 1-0 */ 5634 5635 5636 /****************************************************************************** 5637 * RTC_C Bits 5638 ******************************************************************************/ 5639 /* RTC_C_CTL0[RDYIFG] Bits */ 5640 #define RTC_C_CTL0_RDYIFG_OFS ( 0) /*!< RTCRDYIFG Bit Offset */ 5641 #define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /*!< Real-time clock ready interrupt flag */ 5642 /* RTC_C_CTL0[AIFG] Bits */ 5643 #define RTC_C_CTL0_AIFG_OFS ( 1) /*!< RTCAIFG Bit Offset */ 5644 #define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /*!< Real-time clock alarm interrupt flag */ 5645 /* RTC_C_CTL0[TEVIFG] Bits */ 5646 #define RTC_C_CTL0_TEVIFG_OFS ( 2) /*!< RTCTEVIFG Bit Offset */ 5647 #define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /*!< Real-time clock time event interrupt flag */ 5648 /* RTC_C_CTL0[OFIFG] Bits */ 5649 #define RTC_C_CTL0_OFIFG_OFS ( 3) /*!< RTCOFIFG Bit Offset */ 5650 #define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /*!< 32-kHz crystal oscillator fault interrupt flag */ 5651 /* RTC_C_CTL0[RDYIE] Bits */ 5652 #define RTC_C_CTL0_RDYIE_OFS ( 4) /*!< RTCRDYIE Bit Offset */ 5653 #define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /*!< Real-time clock ready interrupt enable */ 5654 /* RTC_C_CTL0[AIE] Bits */ 5655 #define RTC_C_CTL0_AIE_OFS ( 5) /*!< RTCAIE Bit Offset */ 5656 #define RTC_C_CTL0_AIE ((uint16_t)0x0020) /*!< Real-time clock alarm interrupt enable */ 5657 /* RTC_C_CTL0[TEVIE] Bits */ 5658 #define RTC_C_CTL0_TEVIE_OFS ( 6) /*!< RTCTEVIE Bit Offset */ 5659 #define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /*!< Real-time clock time event interrupt enable */ 5660 /* RTC_C_CTL0[OFIE] Bits */ 5661 #define RTC_C_CTL0_OFIE_OFS ( 7) /*!< RTCOFIE Bit Offset */ 5662 #define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /*!< 32-kHz crystal oscillator fault interrupt enable */ 5663 /* RTC_C_CTL0[KEY] Bits */ 5664 #define RTC_C_CTL0_KEY_OFS ( 8) /*!< RTCKEY Bit Offset */ 5665 #define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /*!< RTCKEY Bit Mask */ 5666 /* RTC_C_CTL13[TEV] Bits */ 5667 #define RTC_C_CTL13_TEV_OFS ( 0) /*!< RTCTEV Bit Offset */ 5668 #define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /*!< RTCTEV Bit Mask */ 5669 #define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /*!< TEV Bit 0 */ 5670 #define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /*!< TEV Bit 1 */ 5671 #define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /*!< Minute changed */ 5672 #define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /*!< Hour changed */ 5673 #define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /*!< Every day at midnight (00:00) */ 5674 #define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /*!< Every day at noon (12:00) */ 5675 /* RTC_C_CTL13[SSEL] Bits */ 5676 #define RTC_C_CTL13_SSEL_OFS ( 2) /*!< RTCSSEL Bit Offset */ 5677 #define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /*!< RTCSSEL Bit Mask */ 5678 #define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /*!< SSEL Bit 0 */ 5679 #define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /*!< SSEL Bit 1 */ 5680 #define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /*!< BCLK */ 5681 #define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /*!< BCLK */ 5682 /* RTC_C_CTL13[RDY] Bits */ 5683 #define RTC_C_CTL13_RDY_OFS ( 4) /*!< RTCRDY Bit Offset */ 5684 #define RTC_C_CTL13_RDY ((uint16_t)0x0010) /*!< Real-time clock ready */ 5685 /* RTC_C_CTL13[MODE] Bits */ 5686 #define RTC_C_CTL13_MODE_OFS ( 5) /*!< RTCMODE Bit Offset */ 5687 #define RTC_C_CTL13_MODE ((uint16_t)0x0020) 5688 /* RTC_C_CTL13[HOLD] Bits */ 5689 #define RTC_C_CTL13_HOLD_OFS ( 6) /*!< RTCHOLD Bit Offset */ 5690 #define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /*!< Real-time clock hold */ 5691 /* RTC_C_CTL13[BCD] Bits */ 5692 #define RTC_C_CTL13_BCD_OFS ( 7) /*!< RTCBCD Bit Offset */ 5693 #define RTC_C_CTL13_BCD ((uint16_t)0x0080) /*!< Real-time clock BCD select */ 5694 /* RTC_C_CTL13[CALF] Bits */ 5695 #define RTC_C_CTL13_CALF_OFS ( 8) /*!< RTCCALF Bit Offset */ 5696 #define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /*!< RTCCALF Bit Mask */ 5697 #define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /*!< CALF Bit 0 */ 5698 #define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /*!< CALF Bit 1 */ 5699 #define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ 5700 #define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /*!< 512 Hz */ 5701 #define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /*!< 256 Hz */ 5702 #define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /*!< 1 Hz */ 5703 #define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ 5704 #define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /*!< 512 Hz */ 5705 #define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /*!< 256 Hz */ 5706 #define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /*!< 1 Hz */ 5707 /* RTC_C_OCAL[OCAL] Bits */ 5708 #define RTC_C_OCAL_OCAL_OFS ( 0) /*!< RTCOCAL Bit Offset */ 5709 #define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /*!< RTCOCAL Bit Mask */ 5710 /* RTC_C_OCAL[OCALS] Bits */ 5711 #define RTC_C_OCAL_OCALS_OFS (15) /*!< RTCOCALS Bit Offset */ 5712 #define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /*!< Real-time clock offset error calibration sign */ 5713 /* RTC_C_TCMP[TCMPx] Bits */ 5714 #define RTC_C_TCMP_TCMPX_OFS ( 0) /*!< RTCTCMP Bit Offset */ 5715 #define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /*!< RTCTCMP Bit Mask */ 5716 /* RTC_C_TCMP[TCOK] Bits */ 5717 #define RTC_C_TCMP_TCOK_OFS (13) /*!< RTCTCOK Bit Offset */ 5718 #define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /*!< Real-time clock temperature compensation write OK */ 5719 /* RTC_C_TCMP[TCRDY] Bits */ 5720 #define RTC_C_TCMP_TCRDY_OFS (14) /*!< RTCTCRDY Bit Offset */ 5721 #define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /*!< Real-time clock temperature compensation ready */ 5722 /* RTC_C_TCMP[TCMPS] Bits */ 5723 #define RTC_C_TCMP_TCMPS_OFS (15) /*!< RTCTCMPS Bit Offset */ 5724 #define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /*!< Real-time clock temperature compensation sign */ 5725 /* RTC_C_PS0CTL[RT0PSIFG] Bits */ 5726 #define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /*!< RT0PSIFG Bit Offset */ 5727 #define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /*!< Prescale timer 0 interrupt flag */ 5728 /* RTC_C_PS0CTL[RT0PSIE] Bits */ 5729 #define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /*!< RT0PSIE Bit Offset */ 5730 #define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /*!< Prescale timer 0 interrupt enable */ 5731 /* RTC_C_PS0CTL[RT0IP] Bits */ 5732 #define RTC_C_PS0CTL_RT0IP_OFS ( 2) /*!< RT0IP Bit Offset */ 5733 #define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /*!< RT0IP Bit Mask */ 5734 #define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /*!< RT0IP Bit 0 */ 5735 #define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /*!< RT0IP Bit 1 */ 5736 #define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /*!< RT0IP Bit 2 */ 5737 #define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ 5738 #define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ 5739 #define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ 5740 #define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ 5741 #define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ 5742 #define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ 5743 #define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ 5744 #define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ 5745 #define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ 5746 #define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ 5747 #define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ 5748 #define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ 5749 #define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ 5750 #define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ 5751 #define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ 5752 #define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ 5753 /* RTC_C_PS1CTL[RT1PSIFG] Bits */ 5754 #define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /*!< RT1PSIFG Bit Offset */ 5755 #define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /*!< Prescale timer 1 interrupt flag */ 5756 /* RTC_C_PS1CTL[RT1PSIE] Bits */ 5757 #define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /*!< RT1PSIE Bit Offset */ 5758 #define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /*!< Prescale timer 1 interrupt enable */ 5759 /* RTC_C_PS1CTL[RT1IP] Bits */ 5760 #define RTC_C_PS1CTL_RT1IP_OFS ( 2) /*!< RT1IP Bit Offset */ 5761 #define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /*!< RT1IP Bit Mask */ 5762 #define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /*!< RT1IP Bit 0 */ 5763 #define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /*!< RT1IP Bit 1 */ 5764 #define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /*!< RT1IP Bit 2 */ 5765 #define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ 5766 #define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ 5767 #define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ 5768 #define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ 5769 #define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ 5770 #define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ 5771 #define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ 5772 #define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ 5773 #define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ 5774 #define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ 5775 #define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ 5776 #define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ 5777 #define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ 5778 #define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ 5779 #define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ 5780 #define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ 5781 /* RTC_C_PS[RT0PS] Bits */ 5782 #define RTC_C_PS_RT0PS_OFS ( 0) /*!< RT0PS Bit Offset */ 5783 #define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /*!< RT0PS Bit Mask */ 5784 /* RTC_C_PS[RT1PS] Bits */ 5785 #define RTC_C_PS_RT1PS_OFS ( 8) /*!< RT1PS Bit Offset */ 5786 #define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /*!< RT1PS Bit Mask */ 5787 /* RTC_C_TIM0[SEC] Bits */ 5788 #define RTC_C_TIM0_SEC_OFS ( 0) /*!< Seconds Bit Offset */ 5789 #define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /*!< Seconds Bit Mask */ 5790 /* RTC_C_TIM0[MIN] Bits */ 5791 #define RTC_C_TIM0_MIN_OFS ( 8) /*!< Minutes Bit Offset */ 5792 #define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /*!< Minutes Bit Mask */ 5793 /* RTC_C_TIM0[SEC_LD] Bits */ 5794 #define RTC_C_TIM0_SEC_LD_OFS ( 0) /*!< SecondsLowDigit Bit Offset */ 5795 #define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /*!< SecondsLowDigit Bit Mask */ 5796 /* RTC_C_TIM0[SEC_HD] Bits */ 5797 #define RTC_C_TIM0_SEC_HD_OFS ( 4) /*!< SecondsHighDigit Bit Offset */ 5798 #define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /*!< SecondsHighDigit Bit Mask */ 5799 /* RTC_C_TIM0[MIN_LD] Bits */ 5800 #define RTC_C_TIM0_MIN_LD_OFS ( 8) /*!< MinutesLowDigit Bit Offset */ 5801 #define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /*!< MinutesLowDigit Bit Mask */ 5802 /* RTC_C_TIM0[MIN_HD] Bits */ 5803 #define RTC_C_TIM0_MIN_HD_OFS (12) /*!< MinutesHighDigit Bit Offset */ 5804 #define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /*!< MinutesHighDigit Bit Mask */ 5805 /* RTC_C_TIM1[HOUR] Bits */ 5806 #define RTC_C_TIM1_HOUR_OFS ( 0) /*!< Hours Bit Offset */ 5807 #define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /*!< Hours Bit Mask */ 5808 /* RTC_C_TIM1[DOW] Bits */ 5809 #define RTC_C_TIM1_DOW_OFS ( 8) /*!< DayofWeek Bit Offset */ 5810 #define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /*!< DayofWeek Bit Mask */ 5811 /* RTC_C_TIM1[HOUR_LD] Bits */ 5812 #define RTC_C_TIM1_HOUR_LD_OFS ( 0) /*!< HoursLowDigit Bit Offset */ 5813 #define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /*!< HoursLowDigit Bit Mask */ 5814 /* RTC_C_TIM1[HOUR_HD] Bits */ 5815 #define RTC_C_TIM1_HOUR_HD_OFS ( 4) /*!< HoursHighDigit Bit Offset */ 5816 #define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /*!< HoursHighDigit Bit Mask */ 5817 /* RTC_C_DATE[DAY] Bits */ 5818 #define RTC_C_DATE_DAY_OFS ( 0) /*!< Day Bit Offset */ 5819 #define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /*!< Day Bit Mask */ 5820 /* RTC_C_DATE[MON] Bits */ 5821 #define RTC_C_DATE_MON_OFS ( 8) /*!< Month Bit Offset */ 5822 #define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /*!< Month Bit Mask */ 5823 /* RTC_C_DATE[DAY_LD] Bits */ 5824 #define RTC_C_DATE_DAY_LD_OFS ( 0) /*!< DayLowDigit Bit Offset */ 5825 #define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /*!< DayLowDigit Bit Mask */ 5826 /* RTC_C_DATE[DAY_HD] Bits */ 5827 #define RTC_C_DATE_DAY_HD_OFS ( 4) /*!< DayHighDigit Bit Offset */ 5828 #define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /*!< DayHighDigit Bit Mask */ 5829 /* RTC_C_DATE[MON_LD] Bits */ 5830 #define RTC_C_DATE_MON_LD_OFS ( 8) /*!< MonthLowDigit Bit Offset */ 5831 #define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /*!< MonthLowDigit Bit Mask */ 5832 /* RTC_C_DATE[MON_HD] Bits */ 5833 #define RTC_C_DATE_MON_HD_OFS (12) /*!< MonthHighDigit Bit Offset */ 5834 #define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /*!< Month high digit (0 or 1) */ 5835 /* RTC_C_YEAR[YEAR_LB] Bits */ 5836 #define RTC_C_YEAR_YEAR_LB_OFS ( 0) /*!< YearLowByte Bit Offset */ 5837 #define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /*!< YearLowByte Bit Mask */ 5838 /* RTC_C_YEAR[YEAR_HB] Bits */ 5839 #define RTC_C_YEAR_YEAR_HB_OFS ( 8) /*!< YearHighByte Bit Offset */ 5840 #define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /*!< YearHighByte Bit Mask */ 5841 /* RTC_C_YEAR[YEAR] Bits */ 5842 #define RTC_C_YEAR_YEAR_OFS ( 0) /*!< Year Bit Offset */ 5843 #define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /*!< Year Bit Mask */ 5844 /* RTC_C_YEAR[DEC] Bits */ 5845 #define RTC_C_YEAR_DEC_OFS ( 4) /*!< Decade Bit Offset */ 5846 #define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /*!< Decade Bit Mask */ 5847 /* RTC_C_YEAR[CENT_LD] Bits */ 5848 #define RTC_C_YEAR_CENT_LD_OFS ( 8) /*!< CenturyLowDigit Bit Offset */ 5849 #define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /*!< CenturyLowDigit Bit Mask */ 5850 /* RTC_C_YEAR[CENT_HD] Bits */ 5851 #define RTC_C_YEAR_CENT_HD_OFS (12) /*!< CenturyHighDigit Bit Offset */ 5852 #define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /*!< CenturyHighDigit Bit Mask */ 5853 /* RTC_C_AMINHR[MIN] Bits */ 5854 #define RTC_C_AMINHR_MIN_OFS ( 0) /*!< Minutes Bit Offset */ 5855 #define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /*!< Minutes Bit Mask */ 5856 /* RTC_C_AMINHR[MINAE] Bits */ 5857 #define RTC_C_AMINHR_MINAE_OFS ( 7) /*!< MINAE Bit Offset */ 5858 #define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /*!< Alarm enable */ 5859 /* RTC_C_AMINHR[HOUR] Bits */ 5860 #define RTC_C_AMINHR_HOUR_OFS ( 8) /*!< Hours Bit Offset */ 5861 #define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /*!< Hours Bit Mask */ 5862 /* RTC_C_AMINHR[HOURAE] Bits */ 5863 #define RTC_C_AMINHR_HOURAE_OFS (15) /*!< HOURAE Bit Offset */ 5864 #define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /*!< Alarm enable */ 5865 /* RTC_C_AMINHR[MIN_LD] Bits */ 5866 #define RTC_C_AMINHR_MIN_LD_OFS ( 0) /*!< MinutesLowDigit Bit Offset */ 5867 #define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /*!< MinutesLowDigit Bit Mask */ 5868 /* RTC_C_AMINHR[MIN_HD] Bits */ 5869 #define RTC_C_AMINHR_MIN_HD_OFS ( 4) /*!< MinutesHighDigit Bit Offset */ 5870 #define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /*!< MinutesHighDigit Bit Mask */ 5871 /* RTC_C_AMINHR[HOUR_LD] Bits */ 5872 #define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /*!< HoursLowDigit Bit Offset */ 5873 #define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /*!< HoursLowDigit Bit Mask */ 5874 /* RTC_C_AMINHR[HOUR_HD] Bits */ 5875 #define RTC_C_AMINHR_HOUR_HD_OFS (12) /*!< HoursHighDigit Bit Offset */ 5876 #define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /*!< HoursHighDigit Bit Mask */ 5877 /* RTC_C_ADOWDAY[DOW] Bits */ 5878 #define RTC_C_ADOWDAY_DOW_OFS ( 0) /*!< DayofWeek Bit Offset */ 5879 #define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /*!< DayofWeek Bit Mask */ 5880 /* RTC_C_ADOWDAY[DOWAE] Bits */ 5881 #define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /*!< DOWAE Bit Offset */ 5882 #define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /*!< Alarm enable */ 5883 /* RTC_C_ADOWDAY[DAY] Bits */ 5884 #define RTC_C_ADOWDAY_DAY_OFS ( 8) /*!< DayofMonth Bit Offset */ 5885 #define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /*!< DayofMonth Bit Mask */ 5886 /* RTC_C_ADOWDAY[DAYAE] Bits */ 5887 #define RTC_C_ADOWDAY_DAYAE_OFS (15) /*!< DAYAE Bit Offset */ 5888 #define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /*!< Alarm enable */ 5889 /* RTC_C_ADOWDAY[DAY_LD] Bits */ 5890 #define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /*!< DayLowDigit Bit Offset */ 5891 #define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /*!< DayLowDigit Bit Mask */ 5892 /* RTC_C_ADOWDAY[DAY_HD] Bits */ 5893 #define RTC_C_ADOWDAY_DAY_HD_OFS (12) /*!< DayHighDigit Bit Offset */ 5894 #define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /*!< DayHighDigit Bit Mask */ 5895 /* Pre-defined bitfield values */ 5896 #define RTC_C_KEY ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ 5897 #define RTC_C_KEY_H ((uint16_t)0x00A5) /*!< RTC_C Key Value for RTC_C write access */ 5898 #define RTC_C_KEY_VAL ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ 5899 5900 5901 /****************************************************************************** 5902 * SCB Bits 5903 ******************************************************************************/ 5904 /* SCB_PFR0[STATE0] Bits */ 5905 #define SCB_PFR0_STATE0_OFS ( 0) /*!< STATE0 Bit Offset */ 5906 #define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /*!< STATE0 Bit Mask */ 5907 #define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /*!< STATE0 Bit 0 */ 5908 #define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /*!< STATE0 Bit 1 */ 5909 #define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /*!< STATE0 Bit 2 */ 5910 #define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /*!< STATE0 Bit 3 */ 5911 #define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /*!< no ARM encoding */ 5912 #define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /*!< N/A */ 5913 /* SCB_PFR0[STATE1] Bits */ 5914 #define SCB_PFR0_STATE1_OFS ( 4) /*!< STATE1 Bit Offset */ 5915 #define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /*!< STATE1 Bit Mask */ 5916 #define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /*!< STATE1 Bit 0 */ 5917 #define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /*!< STATE1 Bit 1 */ 5918 #define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /*!< STATE1 Bit 2 */ 5919 #define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /*!< STATE1 Bit 3 */ 5920 #define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /*!< N/A */ 5921 #define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /*!< N/A */ 5922 #define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL */ 5923 /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */ 5924 /* can be added using the appropriate instruction attribute, but other 32-bit */ 5925 /* basic instructions cannot.) */ 5926 #define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /*!< Thumb-2 encoding with all Thumb-2 basic instructions */ 5927 /* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */ 5928 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */ 5929 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */ 5930 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */ 5931 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */ 5932 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */ 5933 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */ 5934 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ 5935 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /*!< two-stack support */ 5936 /* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */ 5937 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */ 5938 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */ 5939 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */ 5940 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */ 5941 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */ 5942 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */ 5943 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ 5944 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */ 5945 /* SCB_MMFR0[PMSA_SUPPORT] Bits */ 5946 #define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /*!< PMSA_SUPPORT Bit Offset */ 5947 #define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /*!< PMSA_SUPPORT Bit Mask */ 5948 #define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /*!< PMSA_SUPPORT Bit 0 */ 5949 #define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /*!< PMSA_SUPPORT Bit 1 */ 5950 #define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /*!< PMSA_SUPPORT Bit 2 */ 5951 #define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /*!< PMSA_SUPPORT Bit 3 */ 5952 #define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ 5953 #define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /*!< IMPLEMENTATION DEFINED (N/A) */ 5954 #define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /*!< PMSA base (features as defined for ARMv6) (N/A) */ 5955 #define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /*!< PMSAv7 (base plus subregion support) */ 5956 /* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */ 5957 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /*!< CACHE_COHERENCE_SUPPORT Bit Offset */ 5958 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /*!< CACHE_COHERENCE_SUPPORT Bit Mask */ 5959 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /*!< CACHE_COHERENCE_SUPPORT Bit 0 */ 5960 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /*!< CACHE_COHERENCE_SUPPORT Bit 1 */ 5961 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /*!< CACHE_COHERENCE_SUPPORT Bit 2 */ 5962 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /*!< CACHE_COHERENCE_SUPPORT Bit 3 */ 5963 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /*!< no shared support */ 5964 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /*!< partial-inner-shared coherency (coherency amongst some - but not all - of */ 5965 /* the entities within an inner-coherent domain) */ 5966 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /*!< full-inner-shared coherency (coherency amongst all of the entities within an */ 5967 /* inner-coherent domain) */ 5968 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /*!< full coherency (coherency amongst all of the entities) */ 5969 /* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */ 5970 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */ 5971 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */ 5972 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */ 5973 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */ 5974 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */ 5975 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */ 5976 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /*!< Outer non-sharable not supported */ 5977 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /*!< Outer sharable supported */ 5978 /* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */ 5979 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */ 5980 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */ 5981 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */ 5982 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */ 5983 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */ 5984 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */ 5985 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ 5986 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /*!< Auxiliary control register */ 5987 /* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */ 5988 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */ 5989 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */ 5990 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */ 5991 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */ 5992 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */ 5993 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */ 5994 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /*!< not supported */ 5995 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /*!< wait for interrupt supported */ 5996 /* SCB_ISAR0[BITCOUNT_INSTRS] Bits */ 5997 #define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /*!< BITCOUNT_INSTRS Bit Offset */ 5998 #define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< BITCOUNT_INSTRS Bit Mask */ 5999 #define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /*!< BITCOUNT_INSTRS Bit 0 */ 6000 #define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /*!< BITCOUNT_INSTRS Bit 1 */ 6001 #define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /*!< BITCOUNT_INSTRS Bit 2 */ 6002 #define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /*!< BITCOUNT_INSTRS Bit 3 */ 6003 #define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /*!< no bit-counting instructions present */ 6004 #define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds CLZ */ 6005 /* SCB_ISAR0[BITFIELD_INSTRS] Bits */ 6006 #define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /*!< BITFIELD_INSTRS Bit Offset */ 6007 #define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /*!< BITFIELD_INSTRS Bit Mask */ 6008 #define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /*!< BITFIELD_INSTRS Bit 0 */ 6009 #define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /*!< BITFIELD_INSTRS Bit 1 */ 6010 #define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /*!< BITFIELD_INSTRS Bit 2 */ 6011 #define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /*!< BITFIELD_INSTRS Bit 3 */ 6012 #define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /*!< no bitfield instructions present */ 6013 #define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /*!< adds BFC, BFI, SBFX, UBFX */ 6014 /* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */ 6015 #define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /*!< CMPBRANCH_INSTRS Bit Offset */ 6016 #define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /*!< CMPBRANCH_INSTRS Bit Mask */ 6017 #define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /*!< CMPBRANCH_INSTRS Bit 0 */ 6018 #define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /*!< CMPBRANCH_INSTRS Bit 1 */ 6019 #define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /*!< CMPBRANCH_INSTRS Bit 2 */ 6020 #define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /*!< CMPBRANCH_INSTRS Bit 3 */ 6021 #define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no combined compare-and-branch instructions present */ 6022 #define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /*!< adds CB{N}Z */ 6023 /* SCB_ISAR0[COPROC_INSTRS] Bits */ 6024 #define SCB_ISAR0_COPROC_INSTRS_OFS (16) /*!< COPROC_INSTRS Bit Offset */ 6025 #define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /*!< COPROC_INSTRS Bit Mask */ 6026 #define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /*!< COPROC_INSTRS Bit 0 */ 6027 #define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /*!< COPROC_INSTRS Bit 1 */ 6028 #define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /*!< COPROC_INSTRS Bit 2 */ 6029 #define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /*!< COPROC_INSTRS Bit 3 */ 6030 #define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /*!< no coprocessor support, other than for separately attributed architectures */ 6031 /* such as CP15 or VFP */ 6032 #define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /*!< adds generic CDP, LDC, MCR, MRC, STC */ 6033 #define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */ 6034 #define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /*!< adds generic MCRR, MRRC */ 6035 #define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /*!< adds generic MCRR2, MRRC2 */ 6036 /* SCB_ISAR0[DEBUG_INSTRS] Bits */ 6037 #define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /*!< DEBUG_INSTRS Bit Offset */ 6038 #define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /*!< DEBUG_INSTRS Bit Mask */ 6039 #define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /*!< DEBUG_INSTRS Bit 0 */ 6040 #define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /*!< DEBUG_INSTRS Bit 1 */ 6041 #define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /*!< DEBUG_INSTRS Bit 2 */ 6042 #define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /*!< DEBUG_INSTRS Bit 3 */ 6043 #define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /*!< no debug instructions present */ 6044 #define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /*!< adds BKPT */ 6045 /* SCB_ISAR0[DIVIDE_INSTRS] Bits */ 6046 #define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /*!< DIVIDE_INSTRS Bit Offset */ 6047 #define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /*!< DIVIDE_INSTRS Bit Mask */ 6048 #define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /*!< DIVIDE_INSTRS Bit 0 */ 6049 #define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /*!< DIVIDE_INSTRS Bit 1 */ 6050 #define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /*!< DIVIDE_INSTRS Bit 2 */ 6051 #define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /*!< DIVIDE_INSTRS Bit 3 */ 6052 #define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /*!< no divide instructions present */ 6053 #define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /*!< adds SDIV, UDIV (v1 quotient only result) */ 6054 /* SCB_ISAR1[ETEND_INSRS] Bits */ 6055 #define SCB_ISAR1_ETEND_INSRS_OFS (12) /*!< EXTEND_INSRS Bit Offset */ 6056 #define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /*!< EXTEND_INSRS Bit Mask */ 6057 #define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /*!< ETEND_INSRS Bit 0 */ 6058 #define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /*!< ETEND_INSRS Bit 1 */ 6059 #define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /*!< ETEND_INSRS Bit 2 */ 6060 #define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /*!< ETEND_INSRS Bit 3 */ 6061 #define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */ 6062 #define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /*!< adds SXTB, SXTH, UXTB, UXTH */ 6063 #define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /*!< N/A */ 6064 /* SCB_ISAR1[IFTHEN_INSTRS] Bits */ 6065 #define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /*!< IFTHEN_INSTRS Bit Offset */ 6066 #define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /*!< IFTHEN_INSTRS Bit Mask */ 6067 #define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /*!< IFTHEN_INSTRS Bit 0 */ 6068 #define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /*!< IFTHEN_INSTRS Bit 1 */ 6069 #define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /*!< IFTHEN_INSTRS Bit 2 */ 6070 #define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /*!< IFTHEN_INSTRS Bit 3 */ 6071 #define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /*!< IT instructions not present */ 6072 #define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /*!< adds IT instructions (and IT bits in PSRs) */ 6073 /* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */ 6074 #define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /*!< IMMEDIATE_INSTRS Bit Offset */ 6075 #define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /*!< IMMEDIATE_INSTRS Bit Mask */ 6076 #define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /*!< IMMEDIATE_INSTRS Bit 0 */ 6077 #define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /*!< IMMEDIATE_INSTRS Bit 1 */ 6078 #define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /*!< IMMEDIATE_INSTRS Bit 2 */ 6079 #define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /*!< IMMEDIATE_INSTRS Bit 3 */ 6080 #define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no special immediate-generating instructions present */ 6081 #define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /*!< adds ADDW, MOVW, MOVT, SUBW */ 6082 /* SCB_ISAR1[INTERWORK_INSTRS] Bits */ 6083 #define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /*!< INTERWORK_INSTRS Bit Offset */ 6084 #define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /*!< INTERWORK_INSTRS Bit Mask */ 6085 #define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /*!< INTERWORK_INSTRS Bit 0 */ 6086 #define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /*!< INTERWORK_INSTRS Bit 1 */ 6087 #define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /*!< INTERWORK_INSTRS Bit 2 */ 6088 #define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /*!< INTERWORK_INSTRS Bit 3 */ 6089 #define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /*!< no interworking instructions supported */ 6090 #define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /*!< adds BX (and T bit in PSRs) */ 6091 #define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /*!< adds BLX, and PC loads have BX-like behavior */ 6092 #define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /*!< N/A */ 6093 /* SCB_ISAR2[LOADSTORE_INSTRS] Bits */ 6094 #define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /*!< LOADSTORE_INSTRS Bit Offset */ 6095 #define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< LOADSTORE_INSTRS Bit Mask */ 6096 #define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /*!< LOADSTORE_INSTRS Bit 0 */ 6097 #define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /*!< LOADSTORE_INSTRS Bit 1 */ 6098 #define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /*!< LOADSTORE_INSTRS Bit 2 */ 6099 #define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /*!< LOADSTORE_INSTRS Bit 3 */ 6100 #define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /*!< no additional normal load/store instructions present */ 6101 #define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRD/STRD */ 6102 /* SCB_ISAR2[MEMHINT_INSTRS] Bits */ 6103 #define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /*!< MEMHINT_INSTRS Bit Offset */ 6104 #define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< MEMHINT_INSTRS Bit Mask */ 6105 #define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /*!< MEMHINT_INSTRS Bit 0 */ 6106 #define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /*!< MEMHINT_INSTRS Bit 1 */ 6107 #define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /*!< MEMHINT_INSTRS Bit 2 */ 6108 #define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /*!< MEMHINT_INSTRS Bit 3 */ 6109 #define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /*!< no memory hint instructions presen */ 6110 #define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds PLD */ 6111 #define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /*!< adds PLD (ie a repeat on value 1) */ 6112 #define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /*!< adds PLI */ 6113 /* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */ 6114 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /*!< MULTIACCESSINT_INSTRS Bit Offset */ 6115 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /*!< MULTIACCESSINT_INSTRS Bit Mask */ 6116 #define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /*!< MULTIACCESSINT_INSTRS Bit 0 */ 6117 #define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /*!< MULTIACCESSINT_INSTRS Bit 1 */ 6118 #define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /*!< MULTIACCESSINT_INSTRS Bit 2 */ 6119 #define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /*!< MULTIACCESSINT_INSTRS Bit 3 */ 6120 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /*!< the (LDM/STM) instructions are non-interruptible */ 6121 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /*!< the (LDM/STM) instructions are restartable */ 6122 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /*!< the (LDM/STM) instructions are continuable */ 6123 /* SCB_ISAR2[MULT_INSTRS] Bits */ 6124 #define SCB_ISAR2_MULT_INSTRS_OFS (12) /*!< MULT_INSTRS Bit Offset */ 6125 #define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /*!< MULT_INSTRS Bit Mask */ 6126 #define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /*!< MULT_INSTRS Bit 0 */ 6127 #define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /*!< MULT_INSTRS Bit 1 */ 6128 #define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /*!< MULT_INSTRS Bit 2 */ 6129 #define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /*!< MULT_INSTRS Bit 3 */ 6130 #define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /*!< only MUL present */ 6131 #define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /*!< adds MLA */ 6132 #define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /*!< adds MLS */ 6133 /* SCB_ISAR2[MULTS_INSTRS] Bits */ 6134 #define SCB_ISAR2_MULTS_INSTRS_OFS (16) /*!< MULTS_INSTRS Bit Offset */ 6135 #define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /*!< MULTS_INSTRS Bit Mask */ 6136 #define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /*!< MULTS_INSTRS Bit 0 */ 6137 #define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /*!< MULTS_INSTRS Bit 1 */ 6138 #define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /*!< MULTS_INSTRS Bit 2 */ 6139 #define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /*!< MULTS_INSTRS Bit 3 */ 6140 #define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /*!< no signed multiply instructions present */ 6141 #define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /*!< adds SMULL, SMLAL */ 6142 #define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /*!< N/A */ 6143 #define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /*!< N/A */ 6144 /* SCB_ISAR2[MULTU_INSTRS] Bits */ 6145 #define SCB_ISAR2_MULTU_INSTRS_OFS (20) /*!< MULTU_INSTRS Bit Offset */ 6146 #define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /*!< MULTU_INSTRS Bit Mask */ 6147 #define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /*!< MULTU_INSTRS Bit 0 */ 6148 #define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /*!< MULTU_INSTRS Bit 1 */ 6149 #define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /*!< MULTU_INSTRS Bit 2 */ 6150 #define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /*!< MULTU_INSTRS Bit 3 */ 6151 #define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /*!< no unsigned multiply instructions present */ 6152 #define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /*!< adds UMULL, UMLAL */ 6153 #define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /*!< N/A */ 6154 /* SCB_ISAR2[REVERSAL_INSTRS] Bits */ 6155 #define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /*!< REVERSAL_INSTRS Bit Offset */ 6156 #define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /*!< REVERSAL_INSTRS Bit Mask */ 6157 #define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /*!< REVERSAL_INSTRS Bit 0 */ 6158 #define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /*!< REVERSAL_INSTRS Bit 1 */ 6159 #define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /*!< REVERSAL_INSTRS Bit 2 */ 6160 #define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /*!< REVERSAL_INSTRS Bit 3 */ 6161 #define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /*!< no reversal instructions present */ 6162 #define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /*!< adds REV, REV16, REVSH */ 6163 #define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /*!< adds RBIT */ 6164 /* SCB_ISAR3[SATRUATE_INSTRS] Bits */ 6165 #define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /*!< SATRUATE_INSTRS Bit Offset */ 6166 #define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< SATRUATE_INSTRS Bit Mask */ 6167 #define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /*!< SATRUATE_INSTRS Bit 0 */ 6168 #define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /*!< SATRUATE_INSTRS Bit 1 */ 6169 #define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /*!< SATRUATE_INSTRS Bit 2 */ 6170 #define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /*!< SATRUATE_INSTRS Bit 3 */ 6171 #define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no non-SIMD saturate instructions present */ 6172 #define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /*!< N/A */ 6173 /* SCB_ISAR3[SIMD_INSTRS] Bits */ 6174 #define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /*!< SIMD_INSTRS Bit Offset */ 6175 #define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /*!< SIMD_INSTRS Bit Mask */ 6176 #define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /*!< SIMD_INSTRS Bit 0 */ 6177 #define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /*!< SIMD_INSTRS Bit 1 */ 6178 #define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /*!< SIMD_INSTRS Bit 2 */ 6179 #define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /*!< SIMD_INSTRS Bit 3 */ 6180 #define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /*!< no SIMD instructions present */ 6181 #define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /*!< adds SSAT, USAT (and the Q flag in the PSRs) */ 6182 #define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /*!< N/A */ 6183 /* SCB_ISAR3[SVC_INSTRS] Bits */ 6184 #define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /*!< SVC_INSTRS Bit Offset */ 6185 #define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /*!< SVC_INSTRS Bit Mask */ 6186 #define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /*!< SVC_INSTRS Bit 0 */ 6187 #define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /*!< SVC_INSTRS Bit 1 */ 6188 #define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /*!< SVC_INSTRS Bit 2 */ 6189 #define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /*!< SVC_INSTRS Bit 3 */ 6190 #define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /*!< no SVC (SWI) instructions present */ 6191 #define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /*!< adds SVC (SWI) */ 6192 /* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */ 6193 #define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /*!< SYNCPRIM_INSTRS Bit Offset */ 6194 #define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /*!< SYNCPRIM_INSTRS Bit Mask */ 6195 #define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /*!< SYNCPRIM_INSTRS Bit 0 */ 6196 #define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /*!< SYNCPRIM_INSTRS Bit 1 */ 6197 #define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /*!< SYNCPRIM_INSTRS Bit 2 */ 6198 #define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /*!< SYNCPRIM_INSTRS Bit 3 */ 6199 #define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /*!< no synchronization primitives present */ 6200 #define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /*!< adds LDREX, STREX */ 6201 #define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */ 6202 /* SCB_ISAR3[TABBRANCH_INSTRS] Bits */ 6203 #define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /*!< TABBRANCH_INSTRS Bit Offset */ 6204 #define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /*!< TABBRANCH_INSTRS Bit Mask */ 6205 #define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /*!< TABBRANCH_INSTRS Bit 0 */ 6206 #define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /*!< TABBRANCH_INSTRS Bit 1 */ 6207 #define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /*!< TABBRANCH_INSTRS Bit 2 */ 6208 #define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /*!< TABBRANCH_INSTRS Bit 3 */ 6209 #define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no table-branch instructions present */ 6210 #define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /*!< adds TBB, TBH */ 6211 /* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */ 6212 #define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /*!< THUMBCOPY_INSTRS Bit Offset */ 6213 #define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /*!< THUMBCOPY_INSTRS Bit Mask */ 6214 #define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /*!< THUMBCOPY_INSTRS Bit 0 */ 6215 #define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /*!< THUMBCOPY_INSTRS Bit 1 */ 6216 #define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /*!< THUMBCOPY_INSTRS Bit 2 */ 6217 #define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /*!< THUMBCOPY_INSTRS Bit 3 */ 6218 #define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */ 6219 #define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */ 6220 /* SCB_ISAR3[TRUENOP_INSTRS] Bits */ 6221 #define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /*!< TRUENOP_INSTRS Bit Offset */ 6222 #define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /*!< TRUENOP_INSTRS Bit Mask */ 6223 #define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /*!< TRUENOP_INSTRS Bit 0 */ 6224 #define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /*!< TRUENOP_INSTRS Bit 1 */ 6225 #define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /*!< TRUENOP_INSTRS Bit 2 */ 6226 #define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /*!< TRUENOP_INSTRS Bit 3 */ 6227 #define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /*!< true NOP instructions not present - that is, NOP instructions with no */ 6228 /* register dependencies */ 6229 #define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */ 6230 /* SCB_ISAR4[UNPRIV_INSTRS] Bits */ 6231 #define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /*!< UNPRIV_INSTRS Bit Offset */ 6232 #define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /*!< UNPRIV_INSTRS Bit Mask */ 6233 #define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /*!< UNPRIV_INSTRS Bit 0 */ 6234 #define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /*!< UNPRIV_INSTRS Bit 1 */ 6235 #define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /*!< UNPRIV_INSTRS Bit 2 */ 6236 #define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /*!< UNPRIV_INSTRS Bit 3 */ 6237 #define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /*!< no "T variant" instructions exist */ 6238 #define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRBT, LDRT, STRBT, STRT */ 6239 #define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */ 6240 /* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */ 6241 #define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /*!< WITHSHIFTS_INSTRS Bit Offset */ 6242 #define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /*!< WITHSHIFTS_INSTRS Bit Mask */ 6243 #define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /*!< WITHSHIFTS_INSTRS Bit 0 */ 6244 #define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /*!< WITHSHIFTS_INSTRS Bit 1 */ 6245 #define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /*!< WITHSHIFTS_INSTRS Bit 2 */ 6246 #define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /*!< WITHSHIFTS_INSTRS Bit 3 */ 6247 #define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /*!< non-zero shifts only support MOV and shift instructions (see notes) */ 6248 #define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /*!< shifts of loads/stores over the range LSL 0-3 */ 6249 #define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /*!< adds other constant shift options. */ 6250 #define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /*!< adds register-controlled shift options. */ 6251 /* SCB_ISAR4[WRITEBACK_INSTRS] Bits */ 6252 #define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /*!< WRITEBACK_INSTRS Bit Offset */ 6253 #define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /*!< WRITEBACK_INSTRS Bit Mask */ 6254 #define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /*!< WRITEBACK_INSTRS Bit 0 */ 6255 #define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /*!< WRITEBACK_INSTRS Bit 1 */ 6256 #define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /*!< WRITEBACK_INSTRS Bit 2 */ 6257 #define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /*!< WRITEBACK_INSTRS Bit 3 */ 6258 #define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /*!< only non-writeback addressing modes present, except that */ 6259 /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */ 6260 #define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */ 6261 /* SCB_ISAR4[BARRIER_INSTRS] Bits */ 6262 #define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /*!< BARRIER_INSTRS Bit Offset */ 6263 #define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /*!< BARRIER_INSTRS Bit Mask */ 6264 #define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /*!< BARRIER_INSTRS Bit 0 */ 6265 #define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /*!< BARRIER_INSTRS Bit 1 */ 6266 #define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /*!< BARRIER_INSTRS Bit 2 */ 6267 #define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /*!< BARRIER_INSTRS Bit 3 */ 6268 #define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /*!< no barrier instructions supported */ 6269 #define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /*!< adds DMB, DSB, ISB barrier instructions */ 6270 /* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */ 6271 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */ 6272 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */ 6273 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */ 6274 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */ 6275 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */ 6276 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */ 6277 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /*!< no additional support */ 6278 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */ 6279 /* SCB_ISAR4[PSR_M_INSTRS] Bits */ 6280 #define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /*!< PSR_M_INSTRS Bit Offset */ 6281 #define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /*!< PSR_M_INSTRS Bit Mask */ 6282 #define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /*!< PSR_M_INSTRS Bit 0 */ 6283 #define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /*!< PSR_M_INSTRS Bit 1 */ 6284 #define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /*!< PSR_M_INSTRS Bit 2 */ 6285 #define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /*!< PSR_M_INSTRS Bit 3 */ 6286 #define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /*!< instructions not present */ 6287 #define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */ 6288 /* SCB_CPACR[CP11] Bits */ 6289 #define SCB_CPACR_CP11_OFS (22) /*!< CP11 Bit Offset */ 6290 #define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /*!< CP11 Bit Mask */ 6291 /* SCB_CPACR[CP10] Bits */ 6292 #define SCB_CPACR_CP10_OFS (20) /*!< CP10 Bit Offset */ 6293 #define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /*!< CP10 Bit Mask */ 6294 /* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */ 6295 #define SCB_SHPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ 6296 #define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ 6297 /* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */ 6298 #define SCB_SHPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ 6299 #define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ 6300 /* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */ 6301 #define SCB_SHPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ 6302 #define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ 6303 /* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */ 6304 #define SCB_SHPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ 6305 #define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */ 6306 /* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */ 6307 #define SCB_SHPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ 6308 #define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ 6309 /* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */ 6310 #define SCB_SHPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ 6311 #define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ 6312 /* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */ 6313 #define SCB_SHPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ 6314 #define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ 6315 /* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */ 6316 #define SCB_SHPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ 6317 #define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */ 6318 /* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */ 6319 #define SCB_SHPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ 6320 #define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ 6321 /* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */ 6322 #define SCB_SHPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ 6323 #define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ 6324 /* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */ 6325 #define SCB_SHPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ 6326 #define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ 6327 /* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */ 6328 #define SCB_SHPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ 6329 #define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */ 6330 6331 /* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */ 6332 #define SCB_CFSR_IACCVIOL_OFS ( 0) /*!< IACCVIOL Offset */ 6333 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */ 6334 /* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */ 6335 #define SCB_CFSR_DACCVIOL_OFS ( 1) /*!< DACCVIOL Offset */ 6336 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */ 6337 /* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */ 6338 #define SCB_CFSR_MUNSTKERR_OFS ( 3) /*!< MUNSTKERR Offset */ 6339 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */ 6340 /* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */ 6341 #define SCB_CFSR_MSTKERR_OFS ( 4) /*!< MSTKERR Offset */ 6342 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */ 6343 /* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */ 6344 #define SCB_CFSR_MMARVALID_OFS ( 7) /*!< MMARVALID Offset */ 6345 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */ 6346 /* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */ 6347 #define SCB_CFSR_IBUSERR_OFS ( 8) /*!< IBUSERR Offset */ 6348 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */ 6349 /* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */ 6350 #define SCB_CFSR_PRECISERR_OFS ( 9) /*!< PRECISERR Offset */ 6351 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */ 6352 /* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */ 6353 #define SCB_CFSR_IMPRECISERR_OFS (10) /*!< IMPRECISERR Offset */ 6354 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */ 6355 /* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */ 6356 #define SCB_CFSR_UNSTKERR_OFS (11) /*!< UNSTKERR Offset */ 6357 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */ 6358 /* SCB_CFSR[SCB_CFSR_STKERR] Bits */ 6359 #define SCB_CFSR_STKERR_OFS (12) /*!< STKERR Offset */ 6360 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */ 6361 /* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */ 6362 #define SCB_CFSR_BFARVALID_OFS (15) /*!< BFARVALID Offset */ 6363 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */ 6364 /* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */ 6365 #define SCB_CFSR_UNDEFINSTR_OFS (16) /*!< UNDEFINSTR Offset */ 6366 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */ 6367 /* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */ 6368 #define SCB_CFSR_INVSTATE_OFS (17) /*!< INVSTATE Offset */ 6369 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */ 6370 /* SCB_CFSR[SCB_CFSR_INVPC] Bits */ 6371 #define SCB_CFSR_INVPC_OFS (18) /*!< INVPC Offset */ 6372 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */ 6373 /* SCB_CFSR[SCB_CFSR_NOCP] Bits */ 6374 #define SCB_CFSR_NOCP_OFS (19) /*!< NOCP Offset */ 6375 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */ 6376 /* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */ 6377 #define SCB_CFSR_UNALIGNED_OFS (24) /*!< UNALIGNED Offset */ 6378 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */ 6379 /* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */ 6380 #define SCB_CFSR_DIVBYZERO_OFS (25) /*!< DIVBYZERO Offset */ 6381 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */ 6382 /* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */ 6383 #define SCB_CFSR_MLSPERR_OFS ( 5) /*!< MLSPERR Offset */ 6384 #define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */ 6385 /* SCB_CFSR[SCB_CFSR_LSPERR] Bits */ 6386 #define SCB_CFSR_LSPERR_OFS (13) /*!< LSPERR Offset */ 6387 #define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */ 6388 6389 6390 /****************************************************************************** 6391 * SCNSCB Bits 6392 ******************************************************************************/ 6393 6394 6395 /****************************************************************************** 6396 * SYSCTL Bits 6397 ******************************************************************************/ 6398 /* SYSCTL_REBOOT_CTL[REBOOT] Bits */ 6399 #define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ 6400 #define SYSCTL_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ 6401 /* SYSCTL_REBOOT_CTL[WKEY] Bits */ 6402 #define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ 6403 #define SYSCTL_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ 6404 /* SYSCTL_NMI_CTLSTAT[CS_SRC] Bits */ 6405 #define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ 6406 #define SYSCTL_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ 6407 /* SYSCTL_NMI_CTLSTAT[PSS_SRC] Bits */ 6408 #define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ 6409 #define SYSCTL_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ 6410 /* SYSCTL_NMI_CTLSTAT[PCM_SRC] Bits */ 6411 #define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ 6412 #define SYSCTL_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ 6413 /* SYSCTL_NMI_CTLSTAT[PIN_SRC] Bits */ 6414 #define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ 6415 #define SYSCTL_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) 6416 /* SYSCTL_NMI_CTLSTAT[CS_FLG] Bits */ 6417 #define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ 6418 #define SYSCTL_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ 6419 /* SYSCTL_NMI_CTLSTAT[PSS_FLG] Bits */ 6420 #define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ 6421 #define SYSCTL_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ 6422 /* SYSCTL_NMI_CTLSTAT[PCM_FLG] Bits */ 6423 #define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ 6424 #define SYSCTL_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ 6425 /* SYSCTL_NMI_CTLSTAT[PIN_FLG] Bits */ 6426 #define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ 6427 #define SYSCTL_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ 6428 /* SYSCTL_WDTRESET_CTL[TIMEOUT] Bits */ 6429 #define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ 6430 #define SYSCTL_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ 6431 /* SYSCTL_WDTRESET_CTL[VIOLATION] Bits */ 6432 #define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ 6433 #define SYSCTL_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ 6434 /* SYSCTL_PERIHALT_CTL[HALT_T16_0] Bits */ 6435 #define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ 6436 #define SYSCTL_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ 6437 /* SYSCTL_PERIHALT_CTL[HALT_T16_1] Bits */ 6438 #define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ 6439 #define SYSCTL_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ 6440 /* SYSCTL_PERIHALT_CTL[HALT_T16_2] Bits */ 6441 #define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ 6442 #define SYSCTL_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ 6443 /* SYSCTL_PERIHALT_CTL[HALT_T16_3] Bits */ 6444 #define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ 6445 #define SYSCTL_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ 6446 /* SYSCTL_PERIHALT_CTL[HALT_T32_0] Bits */ 6447 #define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ 6448 #define SYSCTL_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ 6449 /* SYSCTL_PERIHALT_CTL[HALT_eUA0] Bits */ 6450 #define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ 6451 #define SYSCTL_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ 6452 /* SYSCTL_PERIHALT_CTL[HALT_eUA1] Bits */ 6453 #define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ 6454 #define SYSCTL_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ 6455 /* SYSCTL_PERIHALT_CTL[HALT_eUA2] Bits */ 6456 #define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ 6457 #define SYSCTL_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ 6458 /* SYSCTL_PERIHALT_CTL[HALT_eUA3] Bits */ 6459 #define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ 6460 #define SYSCTL_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ 6461 /* SYSCTL_PERIHALT_CTL[HALT_eUB0] Bits */ 6462 #define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ 6463 #define SYSCTL_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ 6464 /* SYSCTL_PERIHALT_CTL[HALT_eUB1] Bits */ 6465 #define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ 6466 #define SYSCTL_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ 6467 /* SYSCTL_PERIHALT_CTL[HALT_eUB2] Bits */ 6468 #define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ 6469 #define SYSCTL_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ 6470 /* SYSCTL_PERIHALT_CTL[HALT_eUB3] Bits */ 6471 #define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ 6472 #define SYSCTL_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ 6473 /* SYSCTL_PERIHALT_CTL[HALT_ADC] Bits */ 6474 #define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ 6475 #define SYSCTL_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ 6476 /* SYSCTL_PERIHALT_CTL[HALT_WDT] Bits */ 6477 #define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ 6478 #define SYSCTL_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ 6479 /* SYSCTL_PERIHALT_CTL[HALT_DMA] Bits */ 6480 #define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ 6481 #define SYSCTL_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ 6482 /* SYSCTL_SRAM_BANKEN[BNK0_EN] Bits */ 6483 #define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ 6484 #define SYSCTL_SRAM_BANKEN_BNK0_EN ((uint32_t)0x00000001) /*!< SRAM Bank0 enable */ 6485 /* SYSCTL_SRAM_BANKEN[BNK1_EN] Bits */ 6486 #define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ 6487 #define SYSCTL_SRAM_BANKEN_BNK1_EN ((uint32_t)0x00000002) /*!< SRAM Bank1 enable */ 6488 /* SYSCTL_SRAM_BANKEN[BNK2_EN] Bits */ 6489 #define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ 6490 #define SYSCTL_SRAM_BANKEN_BNK2_EN ((uint32_t)0x00000004) /*!< SRAM Bank1 enable */ 6491 /* SYSCTL_SRAM_BANKEN[BNK3_EN] Bits */ 6492 #define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ 6493 #define SYSCTL_SRAM_BANKEN_BNK3_EN ((uint32_t)0x00000008) /*!< SRAM Bank1 enable */ 6494 /* SYSCTL_SRAM_BANKEN[BNK4_EN] Bits */ 6495 #define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ 6496 #define SYSCTL_SRAM_BANKEN_BNK4_EN ((uint32_t)0x00000010) /*!< SRAM Bank1 enable */ 6497 /* SYSCTL_SRAM_BANKEN[BNK5_EN] Bits */ 6498 #define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ 6499 #define SYSCTL_SRAM_BANKEN_BNK5_EN ((uint32_t)0x00000020) /*!< SRAM Bank1 enable */ 6500 /* SYSCTL_SRAM_BANKEN[BNK6_EN] Bits */ 6501 #define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ 6502 #define SYSCTL_SRAM_BANKEN_BNK6_EN ((uint32_t)0x00000040) /*!< SRAM Bank1 enable */ 6503 /* SYSCTL_SRAM_BANKEN[BNK7_EN] Bits */ 6504 #define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ 6505 #define SYSCTL_SRAM_BANKEN_BNK7_EN ((uint32_t)0x00000080) /*!< SRAM Bank1 enable */ 6506 /* SYSCTL_SRAM_BANKEN[SRAM_RDY] Bits */ 6507 #define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ 6508 #define SYSCTL_SRAM_BANKEN_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ 6509 /* SYSCTL_SRAM_BANKRET[BNK0_RET] Bits */ 6510 #define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /*!< BNK0_RET Bit Offset */ 6511 #define SYSCTL_SRAM_BANKRET_BNK0_RET ((uint32_t)0x00000001) /*!< Bank0 retention */ 6512 /* SYSCTL_SRAM_BANKRET[BNK1_RET] Bits */ 6513 #define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /*!< BNK1_RET Bit Offset */ 6514 #define SYSCTL_SRAM_BANKRET_BNK1_RET ((uint32_t)0x00000002) /*!< Bank1 retention */ 6515 /* SYSCTL_SRAM_BANKRET[BNK2_RET] Bits */ 6516 #define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /*!< BNK2_RET Bit Offset */ 6517 #define SYSCTL_SRAM_BANKRET_BNK2_RET ((uint32_t)0x00000004) /*!< Bank2 retention */ 6518 /* SYSCTL_SRAM_BANKRET[BNK3_RET] Bits */ 6519 #define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /*!< BNK3_RET Bit Offset */ 6520 #define SYSCTL_SRAM_BANKRET_BNK3_RET ((uint32_t)0x00000008) /*!< Bank3 retention */ 6521 /* SYSCTL_SRAM_BANKRET[BNK4_RET] Bits */ 6522 #define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /*!< BNK4_RET Bit Offset */ 6523 #define SYSCTL_SRAM_BANKRET_BNK4_RET ((uint32_t)0x00000010) /*!< Bank4 retention */ 6524 /* SYSCTL_SRAM_BANKRET[BNK5_RET] Bits */ 6525 #define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /*!< BNK5_RET Bit Offset */ 6526 #define SYSCTL_SRAM_BANKRET_BNK5_RET ((uint32_t)0x00000020) /*!< Bank5 retention */ 6527 /* SYSCTL_SRAM_BANKRET[BNK6_RET] Bits */ 6528 #define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /*!< BNK6_RET Bit Offset */ 6529 #define SYSCTL_SRAM_BANKRET_BNK6_RET ((uint32_t)0x00000040) /*!< Bank6 retention */ 6530 /* SYSCTL_SRAM_BANKRET[BNK7_RET] Bits */ 6531 #define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /*!< BNK7_RET Bit Offset */ 6532 #define SYSCTL_SRAM_BANKRET_BNK7_RET ((uint32_t)0x00000080) /*!< Bank7 retention */ 6533 /* SYSCTL_SRAM_BANKRET[SRAM_RDY] Bits */ 6534 #define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ 6535 #define SYSCTL_SRAM_BANKRET_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ 6536 /* SYSCTL_DIO_GLTFLT_CTL[GLTCH_EN] Bits */ 6537 #define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ 6538 #define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ 6539 /* SYSCTL_SECDATA_UNLOCK[UNLKEY] Bits */ 6540 #define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ 6541 #define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ 6542 /* SYSCTL_MASTER_UNLOCK[UNLKEY] Bits */ 6543 #define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ 6544 #define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ 6545 /* SYSCTL_RESET_REQ[POR] Bits */ 6546 #define SYSCTL_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ 6547 #define SYSCTL_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ 6548 /* SYSCTL_RESET_REQ[REBOOT] Bits */ 6549 #define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ 6550 #define SYSCTL_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ 6551 /* SYSCTL_RESET_REQ[WKEY] Bits */ 6552 #define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ 6553 #define SYSCTL_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ 6554 /* SYSCTL_RESET_STATOVER[SOFT] Bits */ 6555 #define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ 6556 #define SYSCTL_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ 6557 /* SYSCTL_RESET_STATOVER[HARD] Bits */ 6558 #define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ 6559 #define SYSCTL_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ 6560 /* SYSCTL_RESET_STATOVER[REBOOT] Bits */ 6561 #define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ 6562 #define SYSCTL_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ 6563 /* SYSCTL_RESET_STATOVER[SOFT_OVER] Bits */ 6564 #define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ 6565 #define SYSCTL_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ 6566 /* SYSCTL_RESET_STATOVER[HARD_OVER] Bits */ 6567 #define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ 6568 #define SYSCTL_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ 6569 /* SYSCTL_RESET_STATOVER[RBT_OVER] Bits */ 6570 #define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ 6571 #define SYSCTL_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ 6572 /* Pre-defined bitfield values */ 6573 #define SYSCTL_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bit 0 */ 6574 /* cleared */ 6575 6576 6577 /****************************************************************************** 6578 * SYSTICK Bits 6579 ******************************************************************************/ 6580 6581 /****************************************************************************** 6582 * Timer32 Bits 6583 ******************************************************************************/ 6584 /* TIMER32_CONTROL[ONESHOT] Bits */ 6585 #define TIMER32_CONTROL_ONESHOT_OFS ( 0) /*!< ONESHOT Bit Offset */ 6586 #define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /*!< Selects one-shot or wrapping counter mode */ 6587 /* TIMER32_CONTROL[SIZE] Bits */ 6588 #define TIMER32_CONTROL_SIZE_OFS ( 1) /*!< SIZE Bit Offset */ 6589 #define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /*!< Selects 16 or 32 bit counter operation */ 6590 /* TIMER32_CONTROL[PRESCALE] Bits */ 6591 #define TIMER32_CONTROL_PRESCALE_OFS ( 2) /*!< PRESCALE Bit Offset */ 6592 #define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /*!< PRESCALE Bit Mask */ 6593 #define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /*!< PRESCALE Bit 0 */ 6594 #define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /*!< PRESCALE Bit 1 */ 6595 #define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /*!< 0 stages of prescale, clock is divided by 1 */ 6596 #define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /*!< 4 stages of prescale, clock is divided by 16 */ 6597 #define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /*!< 8 stages of prescale, clock is divided by 256 */ 6598 /* TIMER32_CONTROL[IE] Bits */ 6599 #define TIMER32_CONTROL_IE_OFS ( 5) /*!< IE Bit Offset */ 6600 #define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /*!< Interrupt enable bit */ 6601 /* TIMER32_CONTROL[MODE] Bits */ 6602 #define TIMER32_CONTROL_MODE_OFS ( 6) /*!< MODE Bit Offset */ 6603 #define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /*!< Mode bit */ 6604 /* TIMER32_CONTROL[ENABLE] Bits */ 6605 #define TIMER32_CONTROL_ENABLE_OFS ( 7) /*!< ENABLE Bit Offset */ 6606 #define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080) 6607 /* TIMER32_RIS[RAW_IFG] Bits */ 6608 #define TIMER32_RIS_RAW_IFG_OFS ( 0) /*!< RAW_IFG Bit Offset */ 6609 #define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /*!< Raw interrupt status */ 6610 /* TIMER32_MIS[IFG] Bits */ 6611 #define TIMER32_MIS_IFG_OFS ( 0) /*!< IFG Bit Offset */ 6612 #define TIMER32_MIS_IFG ((uint32_t)0x00000001) /*!< Enabled interrupt status */ 6613 6614 6615 6616 /****************************************************************************** 6617 * TIMER_A Bits 6618 ******************************************************************************/ 6619 /* TIMER_A_CTL[IFG] Bits */ 6620 #define TIMER_A_CTL_IFG_OFS ( 0) /*!< TAIFG Bit Offset */ 6621 #define TIMER_A_CTL_IFG ((uint16_t)0x0001) /*!< TimerA interrupt flag */ 6622 /* TIMER_A_CTL[IE] Bits */ 6623 #define TIMER_A_CTL_IE_OFS ( 1) /*!< TAIE Bit Offset */ 6624 #define TIMER_A_CTL_IE ((uint16_t)0x0002) /*!< TimerA interrupt enable */ 6625 /* TIMER_A_CTL[CLR] Bits */ 6626 #define TIMER_A_CTL_CLR_OFS ( 2) /*!< TACLR Bit Offset */ 6627 #define TIMER_A_CTL_CLR ((uint16_t)0x0004) /*!< TimerA clear */ 6628 /* TIMER_A_CTL[MC] Bits */ 6629 #define TIMER_A_CTL_MC_OFS ( 4) /*!< MC Bit Offset */ 6630 #define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /*!< MC Bit Mask */ 6631 #define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /*!< MC Bit 0 */ 6632 #define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /*!< MC Bit 1 */ 6633 #define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ 6634 #define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ 6635 #define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ 6636 #define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ 6637 #define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ 6638 #define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ 6639 #define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ 6640 #define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ 6641 /* TIMER_A_CTL[ID] Bits */ 6642 #define TIMER_A_CTL_ID_OFS ( 6) /*!< ID Bit Offset */ 6643 #define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /*!< ID Bit Mask */ 6644 #define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /*!< ID Bit 0 */ 6645 #define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /*!< ID Bit 1 */ 6646 #define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /*!< /1 */ 6647 #define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /*!< /2 */ 6648 #define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /*!< /4 */ 6649 #define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /*!< /8 */ 6650 #define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /*!< /1 */ 6651 #define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /*!< /2 */ 6652 #define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /*!< /4 */ 6653 #define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /*!< /8 */ 6654 /* TIMER_A_CTL[SSEL] Bits */ 6655 #define TIMER_A_CTL_SSEL_OFS ( 8) /*!< TASSEL Bit Offset */ 6656 #define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /*!< TASSEL Bit Mask */ 6657 #define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /*!< SSEL Bit 0 */ 6658 #define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /*!< SSEL Bit 1 */ 6659 #define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /*!< TAxCLK */ 6660 #define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /*!< ACLK */ 6661 #define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /*!< SMCLK */ 6662 #define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /*!< INCLK */ 6663 #define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /*!< TAxCLK */ 6664 #define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /*!< ACLK */ 6665 #define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /*!< SMCLK */ 6666 #define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /*!< INCLK */ 6667 /* TIMER_A_CCTLN[CCIFG] Bits */ 6668 #define TIMER_A_CCTLN_CCIFG_OFS ( 0) /*!< CCIFG Bit Offset */ 6669 #define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /*!< Capture/compare interrupt flag */ 6670 /* TIMER_A_CCTLN[COV] Bits */ 6671 #define TIMER_A_CCTLN_COV_OFS ( 1) /*!< COV Bit Offset */ 6672 #define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /*!< Capture overflow */ 6673 /* TIMER_A_CCTLN[OUT] Bits */ 6674 #define TIMER_A_CCTLN_OUT_OFS ( 2) /*!< OUT Bit Offset */ 6675 #define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /*!< Output */ 6676 /* TIMER_A_CCTLN[CCI] Bits */ 6677 #define TIMER_A_CCTLN_CCI_OFS ( 3) /*!< CCI Bit Offset */ 6678 #define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /*!< Capture/compare input */ 6679 /* TIMER_A_CCTLN[CCIE] Bits */ 6680 #define TIMER_A_CCTLN_CCIE_OFS ( 4) /*!< CCIE Bit Offset */ 6681 #define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /*!< Capture/compare interrupt enable */ 6682 /* TIMER_A_CCTLN[OUTMOD] Bits */ 6683 #define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /*!< OUTMOD Bit Offset */ 6684 #define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /*!< OUTMOD Bit Mask */ 6685 #define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /*!< OUTMOD Bit 0 */ 6686 #define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /*!< OUTMOD Bit 1 */ 6687 #define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /*!< OUTMOD Bit 2 */ 6688 #define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /*!< OUT bit value */ 6689 #define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /*!< Set */ 6690 #define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /*!< Toggle/reset */ 6691 #define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /*!< Set/reset */ 6692 #define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /*!< Toggle */ 6693 #define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /*!< Reset */ 6694 #define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /*!< Toggle/set */ 6695 #define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /*!< Reset/set */ 6696 /* TIMER_A_CCTLN[CAP] Bits */ 6697 #define TIMER_A_CCTLN_CAP_OFS ( 8) /*!< CAP Bit Offset */ 6698 #define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /*!< Capture mode */ 6699 /* TIMER_A_CCTLN[SCCI] Bits */ 6700 #define TIMER_A_CCTLN_SCCI_OFS (10) /*!< SCCI Bit Offset */ 6701 #define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /*!< Synchronized capture/compare input */ 6702 /* TIMER_A_CCTLN[SCS] Bits */ 6703 #define TIMER_A_CCTLN_SCS_OFS (11) /*!< SCS Bit Offset */ 6704 #define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /*!< Synchronize capture source */ 6705 /* TIMER_A_CCTLN[CCIS] Bits */ 6706 #define TIMER_A_CCTLN_CCIS_OFS (12) /*!< CCIS Bit Offset */ 6707 #define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /*!< CCIS Bit Mask */ 6708 #define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /*!< CCIS Bit 0 */ 6709 #define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /*!< CCIS Bit 1 */ 6710 #define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /*!< CCIxA */ 6711 #define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /*!< CCIxB */ 6712 #define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /*!< GND */ 6713 #define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /*!< VCC */ 6714 #define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /*!< CCIxA */ 6715 #define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /*!< CCIxB */ 6716 #define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /*!< GND */ 6717 #define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /*!< VCC */ 6718 /* TIMER_A_CCTLN[CM] Bits */ 6719 #define TIMER_A_CCTLN_CM_OFS (14) /*!< CM Bit Offset */ 6720 #define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /*!< CM Bit Mask */ 6721 #define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /*!< CM Bit 0 */ 6722 #define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /*!< CM Bit 1 */ 6723 #define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /*!< No capture */ 6724 #define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /*!< Capture on rising edge */ 6725 #define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /*!< Capture on falling edge */ 6726 #define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ 6727 #define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /*!< No capture */ 6728 #define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /*!< Capture on rising edge */ 6729 #define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /*!< Capture on falling edge */ 6730 #define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ 6731 /* TIMER_A_EX0[IDEX] Bits */ 6732 #define TIMER_A_EX0_IDEX_OFS ( 0) /*!< TAIDEX Bit Offset */ 6733 #define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /*!< TAIDEX Bit Mask */ 6734 #define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /*!< IDEX Bit 0 */ 6735 #define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /*!< IDEX Bit 1 */ 6736 #define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /*!< IDEX Bit 2 */ 6737 #define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /*!< Divide by 1 */ 6738 #define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /*!< Divide by 2 */ 6739 #define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /*!< Divide by 3 */ 6740 #define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /*!< Divide by 4 */ 6741 #define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /*!< Divide by 5 */ 6742 #define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /*!< Divide by 6 */ 6743 #define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /*!< Divide by 7 */ 6744 #define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /*!< Divide by 8 */ 6745 #define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /*!< Divide by 1 */ 6746 #define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /*!< Divide by 2 */ 6747 #define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /*!< Divide by 3 */ 6748 #define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /*!< Divide by 4 */ 6749 #define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /*!< Divide by 5 */ 6750 #define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /*!< Divide by 6 */ 6751 #define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /*!< Divide by 7 */ 6752 #define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /*!< Divide by 8 */ 6753 6754 /****************************************************************************** 6755 * TLV Bits 6756 ******************************************************************************/ 6757 /****************************************************************************** 6758 * TLV table start and TLV tags * 6759 ******************************************************************************/ 6760 #define TLV_START_ADDR (TLV_BASE + 0x0004) /*!< Start Address of the TLV structure */ 6761 6762 #define TLV_TAG_RESERVED1 1 6763 #define TLV_TAG_RESERVED2 2 6764 #define TLV_TAG_CS 3 6765 #define TLV_TAG_FLASHCTL 4 6766 #define TLV_TAG_ADC14 5 6767 #define TLV_TAG_RESERVED6 6 6768 #define TLV_TAG_RESERVED7 7 6769 #define TLV_TAG_REF 8 6770 #define TLV_TAG_RESERVED9 9 6771 #define TLV_TAG_RESERVED10 10 6772 #define TLV_TAG_DEVINFO 11 6773 #define TLV_TAG_DIEREC 12 6774 #define TLV_TAG_RANDNUM 13 6775 #define TLV_TAG_RESERVED14 14 6776 #define TLV_TAG_BSL 15 6777 #define TLV_TAG_END (0x0BD0E11D) 6778 6779 6780 /****************************************************************************** 6781 * TPIU Bits 6782 ******************************************************************************/ 6783 6784 6785 /****************************************************************************** 6786 * WDT_A Bits 6787 ******************************************************************************/ 6788 /* WDT_A_CTL[IS] Bits */ 6789 #define WDT_A_CTL_IS_OFS ( 0) /*!< WDTIS Bit Offset */ 6790 #define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /*!< WDTIS Bit Mask */ 6791 #define WDT_A_CTL_IS0 ((uint16_t)0x0001) /*!< IS Bit 0 */ 6792 #define WDT_A_CTL_IS1 ((uint16_t)0x0002) /*!< IS Bit 1 */ 6793 #define WDT_A_CTL_IS2 ((uint16_t)0x0004) /*!< IS Bit 2 */ 6794 #define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ 6795 #define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ 6796 #define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ 6797 #define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ 6798 #define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ 6799 #define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ 6800 #define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ 6801 #define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ 6802 /* WDT_A_CTL[CNTCL] Bits */ 6803 #define WDT_A_CTL_CNTCL_OFS ( 3) /*!< WDTCNTCL Bit Offset */ 6804 #define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /*!< Watchdog timer counter clear */ 6805 /* WDT_A_CTL[TMSEL] Bits */ 6806 #define WDT_A_CTL_TMSEL_OFS ( 4) /*!< WDTTMSEL Bit Offset */ 6807 #define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /*!< Watchdog timer mode select */ 6808 /* WDT_A_CTL[SSEL] Bits */ 6809 #define WDT_A_CTL_SSEL_OFS ( 5) /*!< WDTSSEL Bit Offset */ 6810 #define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /*!< WDTSSEL Bit Mask */ 6811 #define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /*!< SSEL Bit 0 */ 6812 #define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /*!< SSEL Bit 1 */ 6813 #define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /*!< SMCLK */ 6814 #define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /*!< ACLK */ 6815 #define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /*!< VLOCLK */ 6816 #define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /*!< BCLK */ 6817 #define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /*!< SMCLK */ 6818 #define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /*!< ACLK */ 6819 #define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /*!< VLOCLK */ 6820 #define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /*!< BCLK */ 6821 /* WDT_A_CTL[HOLD] Bits */ 6822 #define WDT_A_CTL_HOLD_OFS ( 7) /*!< WDTHOLD Bit Offset */ 6823 #define WDT_A_CTL_HOLD ((uint16_t)0x0080) /*!< Watchdog timer hold */ 6824 /* WDT_A_CTL[PW] Bits */ 6825 #define WDT_A_CTL_PW_OFS ( 8) /*!< WDTPW Bit Offset */ 6826 #define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /*!< WDTPW Bit Mask */ 6827 /* Pre-defined bitfield values */ 6828 #define WDT_A_CTL_PW ((uint16_t)0x5A00) /*!< WDT Key Value for WDT write access */ 6829 6830 6831 /****************************************************************************** 6832 * BSL * 6833 ******************************************************************************/ 6834 #define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF) /*!< I2C slave address = 0x48, Interface selection = Auto */ 6835 #define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) /*!< Address of BSL API table */ 6836 #define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) 6837 6838 #define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000) /*!< Auto detect interface */ 6839 #define BSL_UART_INTERFACE ((uint32_t)0x0000C0000) /*!< UART interface */ 6840 #define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000) /*!< SPI interface */ 6841 #define BSL_I2C_INTERFACE ((uint32_t)0x000080000) /*!< I2C interface */ 6842 6843 #define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */ 6844 6845 6846 /****************************************************************************** 6847 * Mailbox struct legacy definition * 6848 ******************************************************************************/ 6849 #define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type 6850 6851 /****************************************************************************** 6852 * Device Unlock Support * 6853 ******************************************************************************/ 6854 /* unlock the device by: 6855 * Load SYSCTL_SECDATA_UNLOCK register address into R0 6856 * Load SYSCTL_SECDATA_UNLOCK unlock key into R1 6857 * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register 6858 */ 6859 #define UNLOCK_DEVICE\ 6860 __asm(" MOVW.W R0, #0x3040");\ 6861 __asm(" MOVT.W R0, #0xE004");\ 6862 __asm(" MOVW.W R1, #0x695A");\ 6863 __asm(" MOVT.W R1, #0x0000");\ 6864 __asm(" STR R1, [R0]"); 6865 6866 /****************************************************************************** 6867 * 6868 * The following are values that can be used to choose the command that will be 6869 * run by the boot code. Perform a logical OR of these settings to create your 6870 * general parameter command. 6871 * 6872 ******************************************************************************/ 6873 #define COMMAND_FACTORY_RESET ((uint32_t)0x00010000) 6874 #define COMMAND_BSL_CONFIG ((uint32_t)0x00020000) 6875 #define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000) 6876 #define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000) 6877 #define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000) 6878 #define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000) 6879 #define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000) 6880 #define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000) 6881 #define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000) 6882 #define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000) 6883 #define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000) 6884 #define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000) 6885 #define COMMAND_NONE ((uint32_t)0xFFFFFFFF) 6886 6887 /****************************************************************************** 6888 * 6889 * The following are values that can be used to configure the BSL. Perform a 6890 * logical OR of these settings to create your BSL parameter. 6891 * 6892 ******************************************************************************/ 6893 #define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000) 6894 6895 #define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000) 6896 #define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001) 6897 #define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002) 6898 6899 #define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000) 6900 #define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010) 6901 #define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020) 6902 #define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030) 6903 #define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040) 6904 #define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050) 6905 #define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060) 6906 #define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070) 6907 6908 #define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000) 6909 #define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000) 6910 6911 #define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000) 6912 #define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000) 6913 #define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000) 6914 #define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000) 6915 6916 #define BSL_CONFIG_I2C_ADD_OFFSET (16) 6917 6918 6919 /****************************************************************************** 6920 * ULP Advisor * 6921 ******************************************************************************/ 6922 #ifdef __TI_ARM__ 6923 #pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8}) 6924 #pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8}) 6925 #pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8}) 6926 #pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8}) 6927 #pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8}) 6928 #pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8}) 6929 #pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8}) 6930 #pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8}) 6931 #pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8}) 6932 #pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8}) 6933 #endif 6934 6935 6936 #ifdef __cplusplus 6937 } 6938 #endif 6939 6940 #endif /* __MSP432P401R_H__ */ 6941 6942
