1 /****************************************************************************** 2 * Filename: ccfg.c 3 4 * Description: Customer Configuration for: 5 * CC13x2x7, CC26x2x7 device family. 6 * 7 * Copyright (c) 2021-2022 Texas Instruments Incorporated. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the copyright holder nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 ******************************************************************************/ 35 36 #ifndef __CCFC_C__ 37 #define __CCFC_C__ 38 39 #include <stdint.h> 40 #include "../inc/hw_types.h" 41 #include "../inc/hw_ccfg.h" 42 #include "../inc/hw_ccfg_simple_struct.h" 43 44 /* Required for Zephyr __ti_ccfg_section macro */ 45 #include <zephyr/linker/sections.h> 46 47 //***************************************************************************** 48 // 49 // Introduction 50 // 51 // This file contains fields used by Boot ROM, startup code, and SW radio 52 // stacks to configure chip behavior. 53 // 54 // Fields are documented in more details in hw_ccfg.h and CCFG.html in 55 // DriverLib documentation (doc_overview.html -> CPU Domain Memory Map -> CCFG). 56 // 57 // PLEASE NOTE: 58 // It is not recommended to do modifications inside the ccfg.c file. 59 // This file is part of the CoreSDK release and future releases may have 60 // important modifications and new fields added without notice. 61 // The recommended method to modify the CCFG settings is to have a separate 62 // <customer_ccfg>.c file that defines the specific CCFG values to be 63 // overridden and then include the TI provided ccfg.c at the very end, 64 // giving default values for non-overriden settings. 65 // 66 // Example: 67 // #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader 68 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC 69 // //---- Use default values for all others ---- 70 // #include "<project-path>/source/ti/devices/<device>/startup_files/ccfg.c" 71 // 72 //***************************************************************************** 73 74 //***************************************************************************** 75 // 76 // Internal settings, forcing several bit-fields to be set to a specific value. 77 // 78 //***************************************************************************** 79 80 //##################################### 81 // Force VDDR high setting (Higher output power but also higher power consumption) 82 // This is also called "boost mode" 83 // WARNING: CCFG_FORCE_VDDR_HH must not be set to 1 if running in external regulator mode. 84 //##################################### 85 86 #ifndef CCFG_FORCE_VDDR_HH 87 #define CCFG_FORCE_VDDR_HH 0x0 // Use default VDDR trim 88 // #define CCFG_FORCE_VDDR_HH 0x1 // Force VDDR voltage to the factory HH setting (FCFG1..VDDR_TRIM_HH) 89 #endif 90 91 //***************************************************************************** 92 // 93 // Set the values of the individual bit fields. 94 // 95 //***************************************************************************** 96 97 //##################################### 98 // Alternative DC/DC settings 99 //##################################### 100 101 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 102 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled 103 // #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x1 // Alternative DC/DC setting disabled 104 #endif 105 106 #if ( CCFG_FORCE_VDDR_HH ) 107 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0xC // Special VMIN level (2.5V) when forced VDDR HH voltage 108 #else 109 #ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 110 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0x8 // 2.25V 111 #endif 112 #endif 113 114 #ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 115 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 // Dithering disabled 116 // #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Dithering enabled 117 #endif 118 119 #ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 120 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x0 // Peak current 121 #endif 122 123 //##################################### 124 // XOSC override settings 125 //##################################### 126 127 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 128 // #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x0 // Enable override 129 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override 130 #endif 131 132 #ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 133 #define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0 134 #endif 135 136 #ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 137 #define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 // Delta = 0 138 #endif 139 140 #ifndef SET_CCFG_MODE_CONF_1_XOSC_MAX_START 141 #define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us 142 #endif 143 144 //##################################### 145 // Power settings 146 //##################################### 147 148 #ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 149 #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation) 150 #endif 151 152 #ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE 153 #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown 154 // #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x1 // Do not use the DC/DC during recharge in powerdown 155 #endif 156 157 #ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE 158 #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode 159 // #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x1 // Do not use the DC/DC during active mode 160 #endif 161 162 #if ( CCFG_FORCE_VDDR_HH ) 163 #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // Special setting to enable forced VDDR HH voltage 164 #else 165 #ifndef SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 166 // #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x0 // VDDS BOD level is 2.0V 167 #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // VDDS BOD level is 1.8V (or 1.65V for external regulator mode) 168 #endif 169 #endif 170 171 #ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 172 #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default) 173 // #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x0 // Temperature compensation on VDDR sleep trim enabled 174 #endif 175 176 //##################################### 177 // Clock settings 178 //##################################### 179 180 #ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION 181 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from HF clock. Note: using this configuration will block the device from entering Standby mode. 182 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock 183 #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC 184 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC 185 #endif 186 187 #ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD 188 // #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta 189 #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta 190 #endif 191 192 #ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 193 #define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value 194 #endif 195 196 #ifndef SET_CCFG_EXT_LF_CLK_DIO 197 #define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock 198 #endif 199 200 #ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 201 #define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency 202 #endif 203 204 //##################################### 205 // Special HF clock source setting 206 //##################################### 207 #ifndef SET_CCFG_MODE_CONF_XOSC_FREQ 208 // #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x0 // HF source is 48 MHz TCXO 209 // #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x1 // HF source is HPOSC (BAW) (only valid for CC2652RB) 210 #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x2 // HF source is a 48 MHz xtal 211 // #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (not supported) 212 #endif 213 214 //##################################### 215 // Bootloader settings 216 //##################################### 217 218 #ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 219 #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader 220 // #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader 221 #endif 222 223 #ifndef SET_CCFG_BL_CONFIG_BL_LEVEL 224 // #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor 225 #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor 226 #endif 227 228 #ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 229 #define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0xFF // DIO number for boot loader backdoor 230 #endif 231 232 #ifndef SET_CCFG_BL_CONFIG_BL_ENABLE 233 // #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor 234 #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor 235 #endif 236 237 //##################################### 238 // Debug access settings 239 //##################################### 240 241 #ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 242 #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option 243 // #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock key 244 #endif 245 246 #ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 247 // #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled 248 #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 249 #endif 250 251 #ifndef SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 252 //#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0x00 // Access disabled 253 #define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 254 #endif 255 256 #ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 257 #define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled 258 //#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 259 #endif 260 261 #ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 262 #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled 263 // #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 264 #endif 265 266 #ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 267 #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled 268 // #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 269 #endif 270 271 #ifndef SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 272 #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0x00 // Access disabled 273 // #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 274 #endif 275 276 //##################################### 277 // Alternative IEEE 802.15.4 MAC address 278 //##################################### 279 #ifndef SET_CCFG_IEEE_MAC_0 280 #define SET_CCFG_IEEE_MAC_0 0xFFFFFFFF // Bits [31:0] 281 #endif 282 283 #ifndef SET_CCFG_IEEE_MAC_1 284 #define SET_CCFG_IEEE_MAC_1 0xFFFFFFFF // Bits [63:32] 285 #endif 286 287 //##################################### 288 // Alternative BLE address 289 //##################################### 290 #ifndef SET_CCFG_IEEE_BLE_0 291 #define SET_CCFG_IEEE_BLE_0 0xFFFFFFFF // Bits [31:0] 292 #endif 293 294 #ifndef SET_CCFG_IEEE_BLE_1 295 #define SET_CCFG_IEEE_BLE_1 0xFFFFFFFF // Bits [63:32] 296 #endif 297 298 //##################################### 299 // Flash erase settings 300 //##################################### 301 302 #ifndef SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 303 // #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x0 // Any chip erase request detected during boot will be ignored 304 #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x1 // Any chip erase request detected during boot will be performed by the boot FW 305 #endif 306 307 #ifndef SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 308 // #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x0 // Disable the boot loader bank erase function 309 #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x1 // Enable the boot loader bank erase function 310 #endif 311 312 //##################################### 313 // Flash image valid 314 //##################################### 315 #ifndef SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 316 #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image vector table is at address 0x00000000 (default) 317 // #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID <valid_vector_table_addr> // Flash image vector table is at address <valid_vector_table_addr> 318 // #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID <invalid_vector_table_addr> // Flash image vector table address is invalid. ROM boot loader is called. 319 #endif 320 321 //##################################### 322 // Flash sector write protection 323 //##################################### 324 #ifndef SET_CCFG_CCFG_PROT_31_0 325 #define SET_CCFG_CCFG_PROT_31_0 0xFFFFFFFF 326 #endif 327 328 #ifndef SET_CCFG_CCFG_PROT_63_32 329 #define SET_CCFG_CCFG_PROT_63_32 0xFFFFFFFF 330 #endif 331 332 #ifndef SET_CCFG_CCFG_PROT_95_64 333 #define SET_CCFG_CCFG_PROT_95_64 0xFFFFFFFF 334 #endif 335 336 #ifndef SET_CCFG_CCFG_PROT_127_96 337 #define SET_CCFG_CCFG_PROT_127_96 0xFFFFFFFF 338 #endif 339 340 //##################################### 341 // Select between cache or GPRAM 342 //##################################### 343 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 344 // #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0 // Cache is disabled and GPRAM is available at 0x11000000-0x11001FFF 345 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 // Cache is enabled and GPRAM is disabled (unavailable) 346 #endif 347 348 //##################################### 349 // TCXO settings 350 //##################################### 351 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 352 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1 // Deprecated. Must be set to 0x1. 353 #endif 354 355 #ifndef SET_CCFG_MODE_CONF_1_TCXO_TYPE 356 #define SET_CCFG_MODE_CONF_1_TCXO_TYPE 0x1 // 1 = Clipped-sine type. 357 //#define SET_CCFG_MODE_CONF_1_TCXO_TYPE 0x0 // 0 = CMOS type. 358 #endif 359 360 #ifndef SET_CCFG_MODE_CONF_1_TCXO_MAX_START 361 #define SET_CCFG_MODE_CONF_1_TCXO_MAX_START 0x7F // Maximum TCXO startup time in units of 100us. 362 #endif 363 364 //***************************************************************************** 365 // 366 // CCFG values that should not be modified. 367 // 368 //***************************************************************************** 369 #define SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058 370 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M >> CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S) 371 372 #if ( CCFG_FORCE_VDDR_HH ) 373 #define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x0 // Special setting to enable forced VDDR HH voltage 374 #else 375 #define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x1 376 #endif 377 378 #define SET_CCFG_MODE_CONF_RTC_COMP 0x1 379 #define SET_CCFG_MODE_CONF_HF_COMP 0x1 380 381 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 0xFF 382 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 0xFF 383 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 0xFF 384 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 0xFF 385 386 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 0xFF 387 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 0xFF 388 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 0xFF 389 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 0xFF 390 391 #define SET_CCFG_RTC_OFFSET_RTC_COMP_P0 0xFFFF 392 #define SET_CCFG_RTC_OFFSET_RTC_COMP_P1 0xFF 393 #define SET_CCFG_RTC_OFFSET_RTC_COMP_P2 0xFF 394 395 #define SET_CCFG_FREQ_OFFSET_HF_COMP_P0 0xFFFF 396 #define SET_CCFG_FREQ_OFFSET_HF_COMP_P1 0xFF 397 #define SET_CCFG_FREQ_OFFSET_HF_COMP_P2 0xFF 398 399 //***************************************************************************** 400 // 401 // Concatenate bit fields to words. 402 // DO NOT EDIT! 403 // 404 //***************************************************************************** 405 #define DEFAULT_CCFG_EXT_LF_CLK ( \ 406 ((((uint32_t)( SET_CCFG_EXT_LF_CLK_DIO )) << CCFG_EXT_LF_CLK_DIO_S ) | ~CCFG_EXT_LF_CLK_DIO_M ) & \ 407 ((((uint32_t)( SET_CCFG_EXT_LF_CLK_RTC_INCREMENT )) << CCFG_EXT_LF_CLK_RTC_INCREMENT_S ) | ~CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) ) 408 409 #define DEFAULT_CCFG_MODE_CONF_1 ( \ 410 ((((uint32_t)( SET_CCFG_MODE_CONF_1_TCXO_TYPE )) << CCFG_MODE_CONF_1_TCXO_TYPE_S ) | ~CCFG_MODE_CONF_1_TCXO_TYPE_M ) & \ 411 ((((uint32_t)( SET_CCFG_MODE_CONF_1_TCXO_MAX_START )) << CCFG_MODE_CONF_1_TCXO_MAX_START_S ) | ~CCFG_MODE_CONF_1_TCXO_MAX_START_M ) & \ 412 ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN )) << CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) & \ 413 ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN )) << CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M ) & \ 414 ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK )) << CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M ) & \ 415 ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT )) << CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M ) & \ 416 ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET )) << CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M ) & \ 417 ((((uint32_t)( SET_CCFG_MODE_CONF_1_XOSC_MAX_START )) << CCFG_MODE_CONF_1_XOSC_MAX_START_S ) | ~CCFG_MODE_CONF_1_XOSC_MAX_START_M ) ) 418 419 #define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \ 420 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG )) << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \ 421 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS )) << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \ 422 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M ) & \ 423 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \ 424 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \ 425 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) ) 426 427 #define DEFAULT_CCFG_MODE_CONF ( \ 428 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M ) & \ 429 ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_RECHARGE )) << CCFG_MODE_CONF_DCDC_RECHARGE_S ) | ~CCFG_MODE_CONF_DCDC_RECHARGE_M ) & \ 430 ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_ACTIVE )) << CCFG_MODE_CONF_DCDC_ACTIVE_S ) | ~CCFG_MODE_CONF_DCDC_ACTIVE_M ) & \ 431 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_EXT_LOAD )) << CCFG_MODE_CONF_VDDR_EXT_LOAD_S ) | ~CCFG_MODE_CONF_VDDR_EXT_LOAD_M ) & \ 432 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL )) << CCFG_MODE_CONF_VDDS_BOD_LEVEL_S ) | ~CCFG_MODE_CONF_VDDS_BOD_LEVEL_M ) & \ 433 ((((uint32_t)( SET_CCFG_MODE_CONF_SCLK_LF_OPTION )) << CCFG_MODE_CONF_SCLK_LF_OPTION_S ) | ~CCFG_MODE_CONF_SCLK_LF_OPTION_M ) & \ 434 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M ) & \ 435 ((((uint32_t)( SET_CCFG_MODE_CONF_RTC_COMP )) << CCFG_MODE_CONF_RTC_COMP_S ) | ~CCFG_MODE_CONF_RTC_COMP_M ) & \ 436 ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_FREQ )) << CCFG_MODE_CONF_XOSC_FREQ_S ) | ~CCFG_MODE_CONF_XOSC_FREQ_M ) & \ 437 ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAP_MOD )) << CCFG_MODE_CONF_XOSC_CAP_MOD_S ) | ~CCFG_MODE_CONF_XOSC_CAP_MOD_M ) & \ 438 ((((uint32_t)( SET_CCFG_MODE_CONF_HF_COMP )) << CCFG_MODE_CONF_HF_COMP_S ) | ~CCFG_MODE_CONF_HF_COMP_M ) & \ 439 ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA )) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) | ~CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ) ) 440 441 #define DEFAULT_CCFG_VOLT_LOAD_0 ( \ 442 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M ) & \ 443 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M ) & \ 444 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M ) & \ 445 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M ) ) 446 447 #define DEFAULT_CCFG_VOLT_LOAD_1 ( \ 448 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M ) & \ 449 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M ) & \ 450 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M ) & \ 451 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M ) ) 452 453 #define DEFAULT_CCFG_RTC_OFFSET ( \ 454 ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P0 )) << CCFG_RTC_OFFSET_RTC_COMP_P0_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P0_M ) & \ 455 ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P1 )) << CCFG_RTC_OFFSET_RTC_COMP_P1_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P1_M ) & \ 456 ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P2 )) << CCFG_RTC_OFFSET_RTC_COMP_P2_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P2_M ) ) 457 458 #define DEFAULT_CCFG_FREQ_OFFSET ( \ 459 ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P0 )) << CCFG_FREQ_OFFSET_HF_COMP_P0_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P0_M ) & \ 460 ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P1 )) << CCFG_FREQ_OFFSET_HF_COMP_P1_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P1_M ) & \ 461 ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P2 )) << CCFG_FREQ_OFFSET_HF_COMP_P2_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P2_M ) ) 462 463 #define DEFAULT_CCFG_IEEE_MAC_0 SET_CCFG_IEEE_MAC_0 464 #define DEFAULT_CCFG_IEEE_MAC_1 SET_CCFG_IEEE_MAC_1 465 #define DEFAULT_CCFG_IEEE_BLE_0 SET_CCFG_IEEE_BLE_0 466 #define DEFAULT_CCFG_IEEE_BLE_1 SET_CCFG_IEEE_BLE_1 467 468 #define DEFAULT_CCFG_BL_CONFIG ( \ 469 ((((uint32_t)( SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE )) << CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S ) | ~CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M ) & \ 470 ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_LEVEL )) << CCFG_BL_CONFIG_BL_LEVEL_S ) | ~CCFG_BL_CONFIG_BL_LEVEL_M ) & \ 471 ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_PIN_NUMBER )) << CCFG_BL_CONFIG_BL_PIN_NUMBER_S ) | ~CCFG_BL_CONFIG_BL_PIN_NUMBER_M ) & \ 472 ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_ENABLE )) << CCFG_BL_CONFIG_BL_ENABLE_S ) | ~CCFG_BL_CONFIG_BL_ENABLE_M ) ) 473 474 #define DEFAULT_CCFG_ERASE_CONF ( \ 475 ((((uint32_t)( SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N )) << CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M ) & \ 476 ((((uint32_t)( SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N )) << CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M ) ) 477 478 #define DEFAULT_CCFG_CCFG_TI_OPTIONS ( \ 479 ((((uint32_t)( SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE )) << CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S ) | ~CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M ) ) 480 481 #define DEFAULT_CCFG_CCFG_TAP_DAP_0 ( \ 482 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M ) & \ 483 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M ) & \ 484 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M ) ) 485 486 #define DEFAULT_CCFG_CCFG_TAP_DAP_1 ( \ 487 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M ) & \ 488 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M ) & \ 489 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M ) ) 490 491 #define DEFAULT_CCFG_IMAGE_VALID_CONF SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 492 493 #define DEFAULT_CCFG_CCFG_PROT_31_0 SET_CCFG_CCFG_PROT_31_0 494 #define DEFAULT_CCFG_CCFG_PROT_63_32 SET_CCFG_CCFG_PROT_63_32 495 #define DEFAULT_CCFG_CCFG_PROT_95_64 SET_CCFG_CCFG_PROT_95_64 496 #define DEFAULT_CCFG_CCFG_PROT_127_96 SET_CCFG_CCFG_PROT_127_96 497 498 //***************************************************************************** 499 // 500 // Customer Configuration Area in Lock Page 501 // 502 //***************************************************************************** 503 #if defined(__IAR_SYSTEMS_ICC__) 504 __root const ccfg_t __ccfg @ ".ccfg" = 505 #elif defined(__TI_COMPILER_VERSION__) 506 #pragma DATA_SECTION(__ccfg, ".ccfg") 507 #pragma RETAIN(__ccfg) 508 const ccfg_t __ccfg = 509 #elif defined(__llvm__) 510 const ccfg_t __ccfg __attribute__((section(".ccfg"), retain)) = 511 #else 512 /* Modified for Zephyr to use __ti_ccfg_section */ 513 const ccfg_t __ti_ccfg_section __ccfg = 514 #endif 515 { // Mapped to address 516 DEFAULT_CCFG_EXT_LF_CLK , // 0x50003FA8 (0x50003xxx maps to last 517 DEFAULT_CCFG_MODE_CONF_1 , // 0x50003FAC sector in FLASH. 518 DEFAULT_CCFG_SIZE_AND_DIS_FLAGS , // 0x50003FB0 Independent of FLASH size) 519 DEFAULT_CCFG_MODE_CONF , // 0x50003FB4 520 DEFAULT_CCFG_VOLT_LOAD_0 , // 0x50003FB8 521 DEFAULT_CCFG_VOLT_LOAD_1 , // 0x50003FBC 522 DEFAULT_CCFG_RTC_OFFSET , // 0x50003FC0 523 DEFAULT_CCFG_FREQ_OFFSET , // 0x50003FC4 524 DEFAULT_CCFG_IEEE_MAC_0 , // 0x50003FC8 525 DEFAULT_CCFG_IEEE_MAC_1 , // 0x50003FCC 526 DEFAULT_CCFG_IEEE_BLE_0 , // 0x50003FD0 527 DEFAULT_CCFG_IEEE_BLE_1 , // 0x50003FD4 528 DEFAULT_CCFG_BL_CONFIG , // 0x50003FD8 529 DEFAULT_CCFG_ERASE_CONF , // 0x50003FDC 530 DEFAULT_CCFG_CCFG_TI_OPTIONS , // 0x50003FE0 531 DEFAULT_CCFG_CCFG_TAP_DAP_0 , // 0x50003FE4 532 DEFAULT_CCFG_CCFG_TAP_DAP_1 , // 0x50003FE8 533 DEFAULT_CCFG_IMAGE_VALID_CONF , // 0x50003FEC 534 DEFAULT_CCFG_CCFG_PROT_31_0 , // 0x50003FF0 535 DEFAULT_CCFG_CCFG_PROT_63_32 , // 0x50003FF4 536 DEFAULT_CCFG_CCFG_PROT_95_64 , // 0x50003FF8 537 DEFAULT_CCFG_CCFG_PROT_127_96 , // 0x50003FFC 538 }; 539 540 #endif // __CCFC_C__ 541
