1 /****************************************************************************** 2 * Filename: hw_gpt_h 3 * Revised: $Date$ 4 * Revision: $Revision$ 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_GPT_H__ 38 #define __HW_GPT_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // GPT component 44 // 45 //***************************************************************************** 46 // Configuration 47 #define GPT_O_CFG 0x00000000 48 49 // Timer A Mode 50 #define GPT_O_TAMR 0x00000004 51 52 // Timer B Mode 53 #define GPT_O_TBMR 0x00000008 54 55 // Control 56 #define GPT_O_CTL 0x0000000C 57 58 // Synch Register 59 #define GPT_O_SYNC 0x00000010 60 61 // Interrupt Mask 62 #define GPT_O_IMR 0x00000018 63 64 // Raw Interrupt Status 65 #define GPT_O_RIS 0x0000001C 66 67 // Masked Interrupt Status 68 #define GPT_O_MIS 0x00000020 69 70 // Interrupt Clear 71 #define GPT_O_ICLR 0x00000024 72 73 // Timer A Interval Load Register 74 #define GPT_O_TAILR 0x00000028 75 76 // Timer B Interval Load Register 77 #define GPT_O_TBILR 0x0000002C 78 79 // Timer A Match Register 80 #define GPT_O_TAMATCHR 0x00000030 81 82 // Timer B Match Register 83 #define GPT_O_TBMATCHR 0x00000034 84 85 // Timer A Pre-scale 86 #define GPT_O_TAPR 0x00000038 87 88 // Timer B Pre-scale 89 #define GPT_O_TBPR 0x0000003C 90 91 // Timer A Pre-scale Match 92 #define GPT_O_TAPMR 0x00000040 93 94 // Timer B Pre-scale Match 95 #define GPT_O_TBPMR 0x00000044 96 97 // Timer A Register 98 #define GPT_O_TAR 0x00000048 99 100 // Timer B Register 101 #define GPT_O_TBR 0x0000004C 102 103 // Timer A Value 104 #define GPT_O_TAV 0x00000050 105 106 // Timer B Value 107 #define GPT_O_TBV 0x00000054 108 109 // Timer A Pre-scale Snap-shot 110 #define GPT_O_TAPS 0x0000005C 111 112 // Timer B Pre-scale Snap-shot 113 #define GPT_O_TBPS 0x00000060 114 115 // Timer A Pre-scale Value 116 #define GPT_O_TAPV 0x00000064 117 118 // Timer B Pre-scale Value 119 #define GPT_O_TBPV 0x00000068 120 121 // DMA Event 122 #define GPT_O_DMAEV 0x0000006C 123 124 // Peripheral Version 125 #define GPT_O_VERSION 0x00000FB0 126 127 // Combined CCP Output 128 #define GPT_O_ANDCCP 0x00000FB4 129 130 //***************************************************************************** 131 // 132 // Register: GPT_O_CFG 133 // 134 //***************************************************************************** 135 // Field: [2:0] CFG 136 // 137 // GPT Configuration 138 // 0x2- 0x3 - Reserved 139 // 0x5- 0x7 - Reserved 140 // ENUMs: 141 // 16BIT_TIMER 16-bit timer configuration. 142 // Configure for two 16-bit 143 // timers. 144 // Also see TAMR.TAMR and 145 // TBMR.TBMR. 146 // 32BIT_TIMER 32-bit timer configuration 147 #define GPT_CFG_CFG_W 3 148 #define GPT_CFG_CFG_M 0x00000007 149 #define GPT_CFG_CFG_S 0 150 #define GPT_CFG_CFG_16BIT_TIMER 0x00000004 151 #define GPT_CFG_CFG_32BIT_TIMER 0x00000000 152 153 //***************************************************************************** 154 // 155 // Register: GPT_O_TAMR 156 // 157 //***************************************************************************** 158 // Field: [15:13] TCACT 159 // 160 // Timer Compare Action Select 161 // ENUMs: 162 // CLRSET_ON_TO Clear CCP output pin immediately and set on 163 // Time-Out 164 // SETCLR_ON_TO Set CCP output pin immediately and clear on 165 // Time-Out 166 // CLRTOG_ON_TO Clear CCP output pin immediately and toggle on 167 // Time-Out 168 // SETTOG_ON_TO Set CCP output pin immediately and toggle on 169 // Time-Out 170 // SET_ON_TO Set CCP output pin on Time-Out 171 // CLR_ON_TO Clear CCP output pin on Time-Out 172 // TOG_ON_TO Toggle State on Time-Out 173 // DIS_CMP Disable compare operations 174 #define GPT_TAMR_TCACT_W 3 175 #define GPT_TAMR_TCACT_M 0x0000E000 176 #define GPT_TAMR_TCACT_S 13 177 #define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 178 #define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 179 #define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 180 #define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 181 #define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 182 #define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 183 #define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 184 #define GPT_TAMR_TCACT_DIS_CMP 0x00000000 185 186 // Field: [12] TACINTD 187 // 188 // One-Shot/Periodic Interrupt Disable 189 // ENUMs: 190 // DIS_TO_INTR Time-out interrupt are disabled 191 // EN_TO_INTR Time-out interrupt function as normal 192 #define GPT_TAMR_TACINTD 0x00001000 193 #define GPT_TAMR_TACINTD_BITN 12 194 #define GPT_TAMR_TACINTD_M 0x00001000 195 #define GPT_TAMR_TACINTD_S 12 196 #define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 197 #define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 198 199 // Field: [11] TAPLO 200 // 201 // GPTM Timer A PWM Legacy Operation 202 // 203 // 0 Legacy operation with CCP pin driven Low when the TAILR 204 // register is reloaded after the timer reaches 0. 205 // 206 // 1 CCP is driven High when the TAILR register is reloaded after the timer 207 // reaches 0. 208 // 209 // This bit is only valid in PWM mode. 210 // ENUMs: 211 // CCP_ON_TO CCP output pin is set to 1 on time-out 212 // LEGACY Legacy operation 213 #define GPT_TAMR_TAPLO 0x00000800 214 #define GPT_TAMR_TAPLO_BITN 11 215 #define GPT_TAMR_TAPLO_M 0x00000800 216 #define GPT_TAMR_TAPLO_S 11 217 #define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 218 #define GPT_TAMR_TAPLO_LEGACY 0x00000000 219 220 // Field: [10] TAMRSU 221 // 222 // Timer A Match Register Update mode 223 // 224 // This bit defines when the TAMATCHR and TAPR registers are updated. 225 // 226 // If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and 227 // TAPR are updated when the timer is enabled. 228 // If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and 229 // TAPR are updated according to the configuration of this bit. 230 // ENUMs: 231 // TOUPDATE Update TAMATCHR and TAPR, if used, on the next 232 // time-out. 233 // CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next 234 // cycle. 235 #define GPT_TAMR_TAMRSU 0x00000400 236 #define GPT_TAMR_TAMRSU_BITN 10 237 #define GPT_TAMR_TAMRSU_M 0x00000400 238 #define GPT_TAMR_TAMRSU_S 10 239 #define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 240 #define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 241 242 // Field: [9] TAPWMIE 243 // 244 // GPTM Timer A PWM Interrupt Enable 245 // This bit enables interrupts in PWM mode on rising, falling, or both edges of 246 // the CCP output, as defined by the CTL.TAEVENT 247 // In addition, when this bit is set and a capture event occurs, Timer A 248 // automatically generates triggers to the DMA if the trigger capability is 249 // enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit 250 // respectively. 251 // 252 // 0 Capture event interrupt is disabled. 253 // 1 Capture event interrupt is enabled. 254 // This bit is only valid in PWM mode. 255 // ENUMs: 256 // EN Interrupt is enabled. This bit is only valid in 257 // PWM mode. 258 // DIS Interrupt is disabled. 259 #define GPT_TAMR_TAPWMIE 0x00000200 260 #define GPT_TAMR_TAPWMIE_BITN 9 261 #define GPT_TAMR_TAPWMIE_M 0x00000200 262 #define GPT_TAMR_TAPWMIE_S 9 263 #define GPT_TAMR_TAPWMIE_EN 0x00000200 264 #define GPT_TAMR_TAPWMIE_DIS 0x00000000 265 266 // Field: [8] TAILD 267 // 268 // GPT Timer A PWM Interval Load Write 269 // ENUMs: 270 // TOUPDATE Update the TAR register with the value in the 271 // TAILR register on the next timeout. If the 272 // prescaler is used, update the TAPS register 273 // with the value in the TAPR register on the next 274 // timeout. 275 // CYCLEUPDATE Update the TAR register with the value in the 276 // TAILR register on the next clock cycle. If the 277 // pre-scaler is used, update the TAPS register 278 // with the value in the TAPR register on the next 279 // clock cycle. 280 #define GPT_TAMR_TAILD 0x00000100 281 #define GPT_TAMR_TAILD_BITN 8 282 #define GPT_TAMR_TAILD_M 0x00000100 283 #define GPT_TAMR_TAILD_S 8 284 #define GPT_TAMR_TAILD_TOUPDATE 0x00000100 285 #define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 286 287 // Field: [7] TASNAPS 288 // 289 // GPT Timer A Snap-Shot Mode 290 // ENUMs: 291 // EN If Timer A is configured in the periodic mode, the 292 // actual free-running value of Timer A is loaded 293 // at the time-out event into the GPT Timer A 294 // (TAR) register. 295 // DIS Snap-shot mode is disabled. 296 #define GPT_TAMR_TASNAPS 0x00000080 297 #define GPT_TAMR_TASNAPS_BITN 7 298 #define GPT_TAMR_TASNAPS_M 0x00000080 299 #define GPT_TAMR_TASNAPS_S 7 300 #define GPT_TAMR_TASNAPS_EN 0x00000080 301 #define GPT_TAMR_TASNAPS_DIS 0x00000000 302 303 // Field: [6] TAWOT 304 // 305 // GPT Timer A Wait-On-Trigger 306 // ENUMs: 307 // WAIT If Timer A is enabled (CTL.TAEN = 1), Timer A does 308 // not begin counting until it receives a trigger 309 // from the timer in the previous position in the 310 // daisy chain. This bit must be clear for GPT 311 // Module 0, Timer A. This function is valid for 312 // one-shot, periodic, and PWM modes 313 // NOWAIT Timer A begins counting as soon as it is enabled. 314 #define GPT_TAMR_TAWOT 0x00000040 315 #define GPT_TAMR_TAWOT_BITN 6 316 #define GPT_TAMR_TAWOT_M 0x00000040 317 #define GPT_TAMR_TAWOT_S 6 318 #define GPT_TAMR_TAWOT_WAIT 0x00000040 319 #define GPT_TAMR_TAWOT_NOWAIT 0x00000000 320 321 // Field: [5] TAMIE 322 // 323 // GPT Timer A Match Interrupt Enable 324 // ENUMs: 325 // EN An interrupt is generated when the match value in 326 // TAMATCHR is reached in the one-shot and 327 // periodic modes. 328 // DIS The match interrupt is disabled for match events. 329 // Additionally, output triggers on match events 330 // are prevented. 331 #define GPT_TAMR_TAMIE 0x00000020 332 #define GPT_TAMR_TAMIE_BITN 5 333 #define GPT_TAMR_TAMIE_M 0x00000020 334 #define GPT_TAMR_TAMIE_S 5 335 #define GPT_TAMR_TAMIE_EN 0x00000020 336 #define GPT_TAMR_TAMIE_DIS 0x00000000 337 338 // Field: [4] TACDIR 339 // 340 // GPT Timer A Count Direction 341 // ENUMs: 342 // UP The timer counts up. When counting up, the timer 343 // starts from a value of 0x0. 344 // DOWN The timer counts down. 345 #define GPT_TAMR_TACDIR 0x00000010 346 #define GPT_TAMR_TACDIR_BITN 4 347 #define GPT_TAMR_TACDIR_M 0x00000010 348 #define GPT_TAMR_TACDIR_S 4 349 #define GPT_TAMR_TACDIR_UP 0x00000010 350 #define GPT_TAMR_TACDIR_DOWN 0x00000000 351 352 // Field: [3] TAAMS 353 // 354 // GPT Timer A Alternate Mode 355 // 356 // Note: To enable PWM mode, you must also clear TACM and then configure TAMR 357 // field to 0x2. 358 // ENUMs: 359 // PWM PWM mode is enabled 360 // CAP_COMP Capture/Compare mode is enabled. 361 #define GPT_TAMR_TAAMS 0x00000008 362 #define GPT_TAMR_TAAMS_BITN 3 363 #define GPT_TAMR_TAAMS_M 0x00000008 364 #define GPT_TAMR_TAAMS_S 3 365 #define GPT_TAMR_TAAMS_PWM 0x00000008 366 #define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 367 368 // Field: [2] TACM 369 // 370 // GPT Timer A Capture Mode 371 // ENUMs: 372 // EDGTIME Edge-Time mode 373 // EDGCNT Edge-Count mode 374 #define GPT_TAMR_TACM 0x00000004 375 #define GPT_TAMR_TACM_BITN 2 376 #define GPT_TAMR_TACM_M 0x00000004 377 #define GPT_TAMR_TACM_S 2 378 #define GPT_TAMR_TACM_EDGTIME 0x00000004 379 #define GPT_TAMR_TACM_EDGCNT 0x00000000 380 381 // Field: [1:0] TAMR 382 // 383 // GPT Timer A Mode 384 // 385 // 0x0 Reserved 386 // 0x1 One-Shot Timer mode 387 // 0x2 Periodic Timer mode 388 // 0x3 Capture mode 389 // The Timer mode is based on the timer configuration defined by bits 2:0 in 390 // the CFG register 391 // ENUMs: 392 // CAPTURE Capture mode 393 // PERIODIC Periodic Timer mode 394 // ONE_SHOT One-Shot Timer mode 395 #define GPT_TAMR_TAMR_W 2 396 #define GPT_TAMR_TAMR_M 0x00000003 397 #define GPT_TAMR_TAMR_S 0 398 #define GPT_TAMR_TAMR_CAPTURE 0x00000003 399 #define GPT_TAMR_TAMR_PERIODIC 0x00000002 400 #define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 401 402 //***************************************************************************** 403 // 404 // Register: GPT_O_TBMR 405 // 406 //***************************************************************************** 407 // Field: [15:13] TCACT 408 // 409 // Timer Compare Action Select 410 // ENUMs: 411 // CLRSET_ON_TO Clear CCP output pin immediately and set on 412 // Time-Out 413 // SETCLR_ON_TO Set CCP output pin immediately and clear on 414 // Time-Out 415 // CLRTOG_ON_TO Clear CCP output pin immediately and toggle on 416 // Time-Out 417 // SETTOG_ON_TO Set CCP output pin immediately and toggle on 418 // Time-Out 419 // SET_ON_TO Set CCP output pin on Time-Out 420 // CLR_ON_TO Clear CCP output pin on Time-Out 421 // TOG_ON_TO Toggle State on Time-Out 422 // DIS_CMP Disable compare operations 423 #define GPT_TBMR_TCACT_W 3 424 #define GPT_TBMR_TCACT_M 0x0000E000 425 #define GPT_TBMR_TCACT_S 13 426 #define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 427 #define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 428 #define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 429 #define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 430 #define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 431 #define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 432 #define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 433 #define GPT_TBMR_TCACT_DIS_CMP 0x00000000 434 435 // Field: [12] TBCINTD 436 // 437 // One-Shot/Periodic Interrupt Mode 438 // ENUMs: 439 // DIS_TO_INTR Mask Time-Out Interrupt 440 // EN_TO_INTR Normal Time-Out Interrupt 441 #define GPT_TBMR_TBCINTD 0x00001000 442 #define GPT_TBMR_TBCINTD_BITN 12 443 #define GPT_TBMR_TBCINTD_M 0x00001000 444 #define GPT_TBMR_TBCINTD_S 12 445 #define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 446 #define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 447 448 // Field: [11] TBPLO 449 // 450 // GPTM Timer B PWM Legacy Operation 451 // 452 // 0 Legacy operation with CCP pin driven Low when the TBILR 453 // register is reloaded after the timer reaches 0. 454 // 455 // 1 CCP is driven High when the TBILR register is reloaded after the timer 456 // reaches 0. 457 // 458 // This bit is only valid in PWM mode. 459 // ENUMs: 460 // CCP_ON_TO CCP output pin is set to 1 on time-out 461 // LEGACY Legacy operation 462 #define GPT_TBMR_TBPLO 0x00000800 463 #define GPT_TBMR_TBPLO_BITN 11 464 #define GPT_TBMR_TBPLO_M 0x00000800 465 #define GPT_TBMR_TBPLO_S 11 466 #define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 467 #define GPT_TBMR_TBPLO_LEGACY 0x00000000 468 469 // Field: [10] TBMRSU 470 // 471 // Timer B Match Register Update mode 472 // 473 // This bit defines when the TBMATCHR and TBPR registers are updated 474 // 475 // If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR 476 // and TBPR are updated when the timer is enabled. 477 // If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR 478 // and TBPR are updated according to the configuration of this bit. 479 // ENUMs: 480 // TOUPDATE Update TBMATCHR and TBPR, if used, on the next 481 // time-out. 482 // CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next 483 // cycle. 484 #define GPT_TBMR_TBMRSU 0x00000400 485 #define GPT_TBMR_TBMRSU_BITN 10 486 #define GPT_TBMR_TBMRSU_M 0x00000400 487 #define GPT_TBMR_TBMRSU_S 10 488 #define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 489 #define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 490 491 // Field: [9] TBPWMIE 492 // 493 // GPTM Timer B PWM Interrupt Enable 494 // This bit enables interrupts in PWM mode on rising, falling, or both edges of 495 // the CCP output, as defined by the CTL.TBEVENT 496 // In addition, when this bit is set and a capture event occurs, Timer A 497 // automatically generates triggers to the DMA if the trigger capability is 498 // enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit 499 // respectively. 500 // 501 // 0 Capture event interrupt is disabled. 502 // 1 Capture event interrupt is enabled. 503 // This bit is only valid in PWM mode. 504 // ENUMs: 505 // EN Interrupt is enabled. This bit is only valid in 506 // PWM mode. 507 // DIS Interrupt is disabled. 508 #define GPT_TBMR_TBPWMIE 0x00000200 509 #define GPT_TBMR_TBPWMIE_BITN 9 510 #define GPT_TBMR_TBPWMIE_M 0x00000200 511 #define GPT_TBMR_TBPWMIE_S 9 512 #define GPT_TBMR_TBPWMIE_EN 0x00000200 513 #define GPT_TBMR_TBPWMIE_DIS 0x00000000 514 515 // Field: [8] TBILD 516 // 517 // GPT Timer B PWM Interval Load Write 518 // ENUMs: 519 // TOUPDATE Update the TBR register with the value in the 520 // TBILR register on the next timeout. If the 521 // prescaler is used, update the TBPS register 522 // with the value in the TBPR register on the next 523 // timeout. 524 // CYCLEUPDATE Update the TBR register with the value in the 525 // TBILR register on the next clock cycle. If the 526 // pre-scaler is used, update the TBPS register 527 // with the value in the TBPR register on the next 528 // clock cycle. 529 #define GPT_TBMR_TBILD 0x00000100 530 #define GPT_TBMR_TBILD_BITN 8 531 #define GPT_TBMR_TBILD_M 0x00000100 532 #define GPT_TBMR_TBILD_S 8 533 #define GPT_TBMR_TBILD_TOUPDATE 0x00000100 534 #define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 535 536 // Field: [7] TBSNAPS 537 // 538 // GPT Timer B Snap-Shot Mode 539 // ENUMs: 540 // EN If Timer B is configured in the periodic mode 541 // DIS Snap-shot mode is disabled. 542 #define GPT_TBMR_TBSNAPS 0x00000080 543 #define GPT_TBMR_TBSNAPS_BITN 7 544 #define GPT_TBMR_TBSNAPS_M 0x00000080 545 #define GPT_TBMR_TBSNAPS_S 7 546 #define GPT_TBMR_TBSNAPS_EN 0x00000080 547 #define GPT_TBMR_TBSNAPS_DIS 0x00000000 548 549 // Field: [6] TBWOT 550 // 551 // GPT Timer B Wait-On-Trigger 552 // ENUMs: 553 // WAIT If Timer B is enabled (CTL.TBEN is set), Timer B 554 // does not begin counting until it receives a 555 // trigger from the timer in the previous position 556 // in the daisy chain. This function is valid for 557 // one-shot, periodic, and PWM modes 558 // NOWAIT Timer B begins counting as soon as it is enabled. 559 #define GPT_TBMR_TBWOT 0x00000040 560 #define GPT_TBMR_TBWOT_BITN 6 561 #define GPT_TBMR_TBWOT_M 0x00000040 562 #define GPT_TBMR_TBWOT_S 6 563 #define GPT_TBMR_TBWOT_WAIT 0x00000040 564 #define GPT_TBMR_TBWOT_NOWAIT 0x00000000 565 566 // Field: [5] TBMIE 567 // 568 // GPT Timer B Match Interrupt Enable. 569 // ENUMs: 570 // EN An interrupt is generated when the match value in 571 // the TBMATCHR register is reached in the 572 // one-shot and periodic modes. 573 // DIS The match interrupt is disabled for match events. 574 // Additionally, output triggers on match events 575 // are prevented. 576 #define GPT_TBMR_TBMIE 0x00000020 577 #define GPT_TBMR_TBMIE_BITN 5 578 #define GPT_TBMR_TBMIE_M 0x00000020 579 #define GPT_TBMR_TBMIE_S 5 580 #define GPT_TBMR_TBMIE_EN 0x00000020 581 #define GPT_TBMR_TBMIE_DIS 0x00000000 582 583 // Field: [4] TBCDIR 584 // 585 // GPT Timer B Count Direction 586 // ENUMs: 587 // UP The timer counts up. When counting up, the timer 588 // starts from a value of 0x0. 589 // DOWN The timer counts down. 590 #define GPT_TBMR_TBCDIR 0x00000010 591 #define GPT_TBMR_TBCDIR_BITN 4 592 #define GPT_TBMR_TBCDIR_M 0x00000010 593 #define GPT_TBMR_TBCDIR_S 4 594 #define GPT_TBMR_TBCDIR_UP 0x00000010 595 #define GPT_TBMR_TBCDIR_DOWN 0x00000000 596 597 // Field: [3] TBAMS 598 // 599 // GPT Timer B Alternate Mode 600 // 601 // Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR 602 // field to 0x2. 603 // ENUMs: 604 // PWM PWM mode is enabled 605 // CAP_COMP Capture/Compare mode is enabled. 606 #define GPT_TBMR_TBAMS 0x00000008 607 #define GPT_TBMR_TBAMS_BITN 3 608 #define GPT_TBMR_TBAMS_M 0x00000008 609 #define GPT_TBMR_TBAMS_S 3 610 #define GPT_TBMR_TBAMS_PWM 0x00000008 611 #define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 612 613 // Field: [2] TBCM 614 // 615 // GPT Timer B Capture Mode 616 // ENUMs: 617 // EDGTIME Edge-Time mode 618 // EDGCNT Edge-Count mode 619 #define GPT_TBMR_TBCM 0x00000004 620 #define GPT_TBMR_TBCM_BITN 2 621 #define GPT_TBMR_TBCM_M 0x00000004 622 #define GPT_TBMR_TBCM_S 2 623 #define GPT_TBMR_TBCM_EDGTIME 0x00000004 624 #define GPT_TBMR_TBCM_EDGCNT 0x00000000 625 626 // Field: [1:0] TBMR 627 // 628 // GPT Timer B Mode 629 // 630 // 0x0 Reserved 631 // 0x1 One-Shot Timer mode 632 // 0x2 Periodic Timer mode 633 // 0x3 Capture mode 634 // The Timer mode is based on the timer configuration defined by bits 2:0 in 635 // the CFG register 636 // ENUMs: 637 // CAPTURE Capture mode 638 // PERIODIC Periodic Timer mode 639 // ONE_SHOT One-Shot Timer mode 640 #define GPT_TBMR_TBMR_W 2 641 #define GPT_TBMR_TBMR_M 0x00000003 642 #define GPT_TBMR_TBMR_S 0 643 #define GPT_TBMR_TBMR_CAPTURE 0x00000003 644 #define GPT_TBMR_TBMR_PERIODIC 0x00000002 645 #define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 646 647 //***************************************************************************** 648 // 649 // Register: GPT_O_CTL 650 // 651 //***************************************************************************** 652 // Field: [14] TBPWML 653 // 654 // GPT Timer B PWM Output Level 655 // 656 // 0: Output is unaffected. 657 // 1: Output is inverted. 658 // ENUMs: 659 // INVERTED Inverted 660 // NORMAL Not inverted 661 #define GPT_CTL_TBPWML 0x00004000 662 #define GPT_CTL_TBPWML_BITN 14 663 #define GPT_CTL_TBPWML_M 0x00004000 664 #define GPT_CTL_TBPWML_S 14 665 #define GPT_CTL_TBPWML_INVERTED 0x00004000 666 #define GPT_CTL_TBPWML_NORMAL 0x00000000 667 668 // Field: [11:10] TBEVENT 669 // 670 // GPT Timer B Event Mode 671 // 672 // The values in this register are defined as follows: 673 // Value Description 674 // 0x0 Positive edge 675 // 0x1 Negative edge 676 // 0x2 Reserved 677 // 0x3 Both edges 678 // Note: If PWM output inversion is enabled, edge detection interrupt 679 // behavior is reversed. Thus, if a positive-edge interrupt trigger 680 // has been set and the PWM inversion generates a postive 681 // edge, no event-trigger interrupt asserts. Instead, the interrupt 682 // is generated on the negative edge of the PWM signal. 683 // ENUMs: 684 // BOTH Both edges 685 // NEG Negative edge 686 // POS Positive edge 687 #define GPT_CTL_TBEVENT_W 2 688 #define GPT_CTL_TBEVENT_M 0x00000C00 689 #define GPT_CTL_TBEVENT_S 10 690 #define GPT_CTL_TBEVENT_BOTH 0x00000C00 691 #define GPT_CTL_TBEVENT_NEG 0x00000400 692 #define GPT_CTL_TBEVENT_POS 0x00000000 693 694 // Field: [9] TBSTALL 695 // 696 // GPT Timer B Stall Enable 697 // ENUMs: 698 // EN Timer B freezes counting while the processor is 699 // halted by the debugger. 700 // DIS Timer B continues counting while the processor is 701 // halted by the debugger. 702 #define GPT_CTL_TBSTALL 0x00000200 703 #define GPT_CTL_TBSTALL_BITN 9 704 #define GPT_CTL_TBSTALL_M 0x00000200 705 #define GPT_CTL_TBSTALL_S 9 706 #define GPT_CTL_TBSTALL_EN 0x00000200 707 #define GPT_CTL_TBSTALL_DIS 0x00000000 708 709 // Field: [8] TBEN 710 // 711 // GPT Timer B Enable 712 // ENUMs: 713 // EN Timer B is enabled and begins counting or the 714 // capture logic is enabled based on CFG register. 715 // DIS Timer B is disabled. 716 #define GPT_CTL_TBEN 0x00000100 717 #define GPT_CTL_TBEN_BITN 8 718 #define GPT_CTL_TBEN_M 0x00000100 719 #define GPT_CTL_TBEN_S 8 720 #define GPT_CTL_TBEN_EN 0x00000100 721 #define GPT_CTL_TBEN_DIS 0x00000000 722 723 // Field: [6] TAPWML 724 // 725 // GPT Timer A PWM Output Level 726 // ENUMs: 727 // INVERTED Inverted 728 // NORMAL Not inverted 729 #define GPT_CTL_TAPWML 0x00000040 730 #define GPT_CTL_TAPWML_BITN 6 731 #define GPT_CTL_TAPWML_M 0x00000040 732 #define GPT_CTL_TAPWML_S 6 733 #define GPT_CTL_TAPWML_INVERTED 0x00000040 734 #define GPT_CTL_TAPWML_NORMAL 0x00000000 735 736 // Field: [3:2] TAEVENT 737 // 738 // GPT Timer A Event Mode 739 // 740 // The values in this register are defined as follows: 741 // Value Description 742 // 0x0 Positive edge 743 // 0x1 Negative edge 744 // 0x2 Reserved 745 // 0x3 Both edges 746 // Note: If PWM output inversion is enabled, edge detection interrupt 747 // behavior is reversed. Thus, if a positive-edge interrupt trigger 748 // has been set and the PWM inversion generates a postive 749 // edge, no event-trigger interrupt asserts. Instead, the interrupt 750 // is generated on the negative edge of the PWM signal. 751 // ENUMs: 752 // BOTH Both edges 753 // NEG Negative edge 754 // POS Positive edge 755 #define GPT_CTL_TAEVENT_W 2 756 #define GPT_CTL_TAEVENT_M 0x0000000C 757 #define GPT_CTL_TAEVENT_S 2 758 #define GPT_CTL_TAEVENT_BOTH 0x0000000C 759 #define GPT_CTL_TAEVENT_NEG 0x00000004 760 #define GPT_CTL_TAEVENT_POS 0x00000000 761 762 // Field: [1] TASTALL 763 // 764 // GPT Timer A Stall Enable 765 // ENUMs: 766 // EN Timer A freezes counting while the processor is 767 // halted by the debugger. 768 // DIS Timer A continues counting while the processor is 769 // halted by the debugger. 770 #define GPT_CTL_TASTALL 0x00000002 771 #define GPT_CTL_TASTALL_BITN 1 772 #define GPT_CTL_TASTALL_M 0x00000002 773 #define GPT_CTL_TASTALL_S 1 774 #define GPT_CTL_TASTALL_EN 0x00000002 775 #define GPT_CTL_TASTALL_DIS 0x00000000 776 777 // Field: [0] TAEN 778 // 779 // GPT Timer A Enable 780 // ENUMs: 781 // EN Timer A is enabled and begins counting or the 782 // capture logic is enabled based on the CFG 783 // register. 784 // DIS Timer A is disabled. 785 #define GPT_CTL_TAEN 0x00000001 786 #define GPT_CTL_TAEN_BITN 0 787 #define GPT_CTL_TAEN_M 0x00000001 788 #define GPT_CTL_TAEN_S 0 789 #define GPT_CTL_TAEN_EN 0x00000001 790 #define GPT_CTL_TAEN_DIS 0x00000000 791 792 //***************************************************************************** 793 // 794 // Register: GPT_O_SYNC 795 // 796 //***************************************************************************** 797 // Field: [7:6] SYNC3 798 // 799 // Synchronize GPT Timer 3. 800 // ENUMs: 801 // BOTH A timeout event for both Timer A and Timer B of 802 // GPT3 is triggered 803 // TIMERB A timeout event for Timer B of GPT3 is triggered 804 // TIMERA A timeout event for Timer A of GPT3 is triggered 805 // NOSYNC No Sync. GPT3 is not affected. 806 #define GPT_SYNC_SYNC3_W 2 807 #define GPT_SYNC_SYNC3_M 0x000000C0 808 #define GPT_SYNC_SYNC3_S 6 809 #define GPT_SYNC_SYNC3_BOTH 0x000000C0 810 #define GPT_SYNC_SYNC3_TIMERB 0x00000080 811 #define GPT_SYNC_SYNC3_TIMERA 0x00000040 812 #define GPT_SYNC_SYNC3_NOSYNC 0x00000000 813 814 // Field: [5:4] SYNC2 815 // 816 // Synchronize GPT Timer 2. 817 // ENUMs: 818 // BOTH A timeout event for both Timer A and Timer B of 819 // GPT2 is triggered 820 // TIMERB A timeout event for Timer B of GPT2 is triggered 821 // TIMERA A timeout event for Timer A of GPT2 is triggered 822 // NOSYNC No Sync. GPT2 is not affected. 823 #define GPT_SYNC_SYNC2_W 2 824 #define GPT_SYNC_SYNC2_M 0x00000030 825 #define GPT_SYNC_SYNC2_S 4 826 #define GPT_SYNC_SYNC2_BOTH 0x00000030 827 #define GPT_SYNC_SYNC2_TIMERB 0x00000020 828 #define GPT_SYNC_SYNC2_TIMERA 0x00000010 829 #define GPT_SYNC_SYNC2_NOSYNC 0x00000000 830 831 // Field: [3:2] SYNC1 832 // 833 // Synchronize GPT Timer 1 834 // ENUMs: 835 // BOTH A timeout event for both Timer A and Timer B of 836 // GPT1 is triggered 837 // TIMERB A timeout event for Timer B of GPT1 is triggered 838 // TIMERA A timeout event for Timer A of GPT1 is triggered 839 // NOSYNC No Sync. GPT1 is not affected. 840 #define GPT_SYNC_SYNC1_W 2 841 #define GPT_SYNC_SYNC1_M 0x0000000C 842 #define GPT_SYNC_SYNC1_S 2 843 #define GPT_SYNC_SYNC1_BOTH 0x0000000C 844 #define GPT_SYNC_SYNC1_TIMERB 0x00000008 845 #define GPT_SYNC_SYNC1_TIMERA 0x00000004 846 #define GPT_SYNC_SYNC1_NOSYNC 0x00000000 847 848 // Field: [1:0] SYNC0 849 // 850 // Synchronize GPT Timer 0 851 // ENUMs: 852 // BOTH A timeout event for both Timer A and Timer B of 853 // GPT0 is triggered 854 // TIMERB A timeout event for Timer B of GPT0 is triggered 855 // TIMERA A timeout event for Timer A of GPT0 is triggered 856 // NOSYNC No Sync. GPT0 is not affected. 857 #define GPT_SYNC_SYNC0_W 2 858 #define GPT_SYNC_SYNC0_M 0x00000003 859 #define GPT_SYNC_SYNC0_S 0 860 #define GPT_SYNC_SYNC0_BOTH 0x00000003 861 #define GPT_SYNC_SYNC0_TIMERB 0x00000002 862 #define GPT_SYNC_SYNC0_TIMERA 0x00000001 863 #define GPT_SYNC_SYNC0_NOSYNC 0x00000000 864 865 //***************************************************************************** 866 // 867 // Register: GPT_O_IMR 868 // 869 //***************************************************************************** 870 // Field: [13] DMABIM 871 // 872 // Enabling this bit will make the RIS.DMABRIS interrupt propagate to 873 // MIS.DMABMIS 874 // ENUMs: 875 // EN Enable Interrupt 876 // DIS Disable Interrupt 877 #define GPT_IMR_DMABIM 0x00002000 878 #define GPT_IMR_DMABIM_BITN 13 879 #define GPT_IMR_DMABIM_M 0x00002000 880 #define GPT_IMR_DMABIM_S 13 881 #define GPT_IMR_DMABIM_EN 0x00002000 882 #define GPT_IMR_DMABIM_DIS 0x00000000 883 884 // Field: [11] TBMIM 885 // 886 // Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS 887 // ENUMs: 888 // EN Enable Interrupt 889 // DIS Disable Interrupt 890 #define GPT_IMR_TBMIM 0x00000800 891 #define GPT_IMR_TBMIM_BITN 11 892 #define GPT_IMR_TBMIM_M 0x00000800 893 #define GPT_IMR_TBMIM_S 11 894 #define GPT_IMR_TBMIM_EN 0x00000800 895 #define GPT_IMR_TBMIM_DIS 0x00000000 896 897 // Field: [10] CBEIM 898 // 899 // Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS 900 // ENUMs: 901 // EN Enable Interrupt 902 // DIS Disable Interrupt 903 #define GPT_IMR_CBEIM 0x00000400 904 #define GPT_IMR_CBEIM_BITN 10 905 #define GPT_IMR_CBEIM_M 0x00000400 906 #define GPT_IMR_CBEIM_S 10 907 #define GPT_IMR_CBEIM_EN 0x00000400 908 #define GPT_IMR_CBEIM_DIS 0x00000000 909 910 // Field: [9] CBMIM 911 // 912 // Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS 913 // ENUMs: 914 // EN Enable Interrupt 915 // DIS Disable Interrupt 916 #define GPT_IMR_CBMIM 0x00000200 917 #define GPT_IMR_CBMIM_BITN 9 918 #define GPT_IMR_CBMIM_M 0x00000200 919 #define GPT_IMR_CBMIM_S 9 920 #define GPT_IMR_CBMIM_EN 0x00000200 921 #define GPT_IMR_CBMIM_DIS 0x00000000 922 923 // Field: [8] TBTOIM 924 // 925 // Enabling this bit will make the RIS.TBTORIS interrupt propagate to 926 // MIS.TBTOMIS 927 // ENUMs: 928 // EN Enable Interrupt 929 // DIS Disable Interrupt 930 #define GPT_IMR_TBTOIM 0x00000100 931 #define GPT_IMR_TBTOIM_BITN 8 932 #define GPT_IMR_TBTOIM_M 0x00000100 933 #define GPT_IMR_TBTOIM_S 8 934 #define GPT_IMR_TBTOIM_EN 0x00000100 935 #define GPT_IMR_TBTOIM_DIS 0x00000000 936 937 // Field: [5] DMAAIM 938 // 939 // Enabling this bit will make the RIS.DMAARIS interrupt propagate to 940 // MIS.DMAAMIS 941 // ENUMs: 942 // EN Enable Interrupt 943 // DIS Disable Interrupt 944 #define GPT_IMR_DMAAIM 0x00000020 945 #define GPT_IMR_DMAAIM_BITN 5 946 #define GPT_IMR_DMAAIM_M 0x00000020 947 #define GPT_IMR_DMAAIM_S 5 948 #define GPT_IMR_DMAAIM_EN 0x00000020 949 #define GPT_IMR_DMAAIM_DIS 0x00000000 950 951 // Field: [4] TAMIM 952 // 953 // Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS 954 // ENUMs: 955 // EN Enable Interrupt 956 // DIS Disable Interrupt 957 #define GPT_IMR_TAMIM 0x00000010 958 #define GPT_IMR_TAMIM_BITN 4 959 #define GPT_IMR_TAMIM_M 0x00000010 960 #define GPT_IMR_TAMIM_S 4 961 #define GPT_IMR_TAMIM_EN 0x00000010 962 #define GPT_IMR_TAMIM_DIS 0x00000000 963 964 // Field: [2] CAEIM 965 // 966 // Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS 967 // ENUMs: 968 // EN Enable Interrupt 969 // DIS Disable Interrupt 970 #define GPT_IMR_CAEIM 0x00000004 971 #define GPT_IMR_CAEIM_BITN 2 972 #define GPT_IMR_CAEIM_M 0x00000004 973 #define GPT_IMR_CAEIM_S 2 974 #define GPT_IMR_CAEIM_EN 0x00000004 975 #define GPT_IMR_CAEIM_DIS 0x00000000 976 977 // Field: [1] CAMIM 978 // 979 // Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS 980 // ENUMs: 981 // EN Enable Interrupt 982 // DIS Disable Interrupt 983 #define GPT_IMR_CAMIM 0x00000002 984 #define GPT_IMR_CAMIM_BITN 1 985 #define GPT_IMR_CAMIM_M 0x00000002 986 #define GPT_IMR_CAMIM_S 1 987 #define GPT_IMR_CAMIM_EN 0x00000002 988 #define GPT_IMR_CAMIM_DIS 0x00000000 989 990 // Field: [0] TATOIM 991 // 992 // Enabling this bit will make the RIS.TATORIS interrupt propagate to 993 // MIS.TATOMIS 994 // ENUMs: 995 // EN Enable Interrupt 996 // DIS Disable Interrupt 997 #define GPT_IMR_TATOIM 0x00000001 998 #define GPT_IMR_TATOIM_BITN 0 999 #define GPT_IMR_TATOIM_M 0x00000001 1000 #define GPT_IMR_TATOIM_S 0 1001 #define GPT_IMR_TATOIM_EN 0x00000001 1002 #define GPT_IMR_TATOIM_DIS 0x00000000 1003 1004 //***************************************************************************** 1005 // 1006 // Register: GPT_O_RIS 1007 // 1008 //***************************************************************************** 1009 // Field: [13] DMABRIS 1010 // 1011 // GPT Timer B DMA Done Raw Interrupt Status 1012 // 1013 // 0: Transfer has not completed 1014 // 1: Transfer has completed 1015 #define GPT_RIS_DMABRIS 0x00002000 1016 #define GPT_RIS_DMABRIS_BITN 13 1017 #define GPT_RIS_DMABRIS_M 0x00002000 1018 #define GPT_RIS_DMABRIS_S 13 1019 1020 // Field: [11] TBMRIS 1021 // 1022 // GPT Timer B Match Raw Interrupt 1023 // 1024 // 0: The match value has not been reached 1025 // 1: The match value is reached. 1026 // 1027 // TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR 1028 // have been reached when configured in one-shot or periodic mode. 1029 #define GPT_RIS_TBMRIS 0x00000800 1030 #define GPT_RIS_TBMRIS_BITN 11 1031 #define GPT_RIS_TBMRIS_M 0x00000800 1032 #define GPT_RIS_TBMRIS_S 11 1033 1034 // Field: [10] CBERIS 1035 // 1036 // GPT Timer B Capture Mode Event Raw Interrupt 1037 // 1038 // 0: The event has not occured. 1039 // 1: The event has occured. 1040 // 1041 // This interrupt asserts when the subtimer is configured in Input Edge-Time 1042 // mode 1043 #define GPT_RIS_CBERIS 0x00000400 1044 #define GPT_RIS_CBERIS_BITN 10 1045 #define GPT_RIS_CBERIS_M 0x00000400 1046 #define GPT_RIS_CBERIS_S 10 1047 1048 // Field: [9] CBMRIS 1049 // 1050 // GPT Timer B Capture Mode Match Raw Interrupt 1051 // 1052 // 0: The capture mode match for Timer B has not occurred. 1053 // 1: A capture mode match has occurred for Timer B. This interrupt 1054 // asserts when the values in the TBR and TBPR 1055 // match the values in the TBMATCHR and TBPMR 1056 // when configured in Input Edge-Time mode. 1057 // 1058 // This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. 1059 #define GPT_RIS_CBMRIS 0x00000200 1060 #define GPT_RIS_CBMRIS_BITN 9 1061 #define GPT_RIS_CBMRIS_M 0x00000200 1062 #define GPT_RIS_CBMRIS_S 9 1063 1064 // Field: [8] TBTORIS 1065 // 1066 // GPT Timer B Time-out Raw Interrupt 1067 // 1068 // 0: Timer B has not timed out 1069 // 1: Timer B has timed out. 1070 // 1071 // This interrupt is asserted when a one-shot or periodic mode timer reaches 1072 // its count limit. The count limit is 0 or the value loaded into TBILR, 1073 // depending on the count direction. 1074 #define GPT_RIS_TBTORIS 0x00000100 1075 #define GPT_RIS_TBTORIS_BITN 8 1076 #define GPT_RIS_TBTORIS_M 0x00000100 1077 #define GPT_RIS_TBTORIS_S 8 1078 1079 // Field: [5] DMAARIS 1080 // 1081 // GPT Timer A DMA Done Raw Interrupt Status 1082 // 1083 // 0: Transfer has not completed 1084 // 1: Transfer has completed 1085 #define GPT_RIS_DMAARIS 0x00000020 1086 #define GPT_RIS_DMAARIS_BITN 5 1087 #define GPT_RIS_DMAARIS_M 0x00000020 1088 #define GPT_RIS_DMAARIS_S 5 1089 1090 // Field: [4] TAMRIS 1091 // 1092 // GPT Timer A Match Raw Interrupt 1093 // 1094 // 0: The match value has not been reached 1095 // 1: The match value is reached. 1096 // 1097 // TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR 1098 // have been reached when configured in one-shot or periodic mode. 1099 #define GPT_RIS_TAMRIS 0x00000010 1100 #define GPT_RIS_TAMRIS_BITN 4 1101 #define GPT_RIS_TAMRIS_M 0x00000010 1102 #define GPT_RIS_TAMRIS_S 4 1103 1104 // Field: [2] CAERIS 1105 // 1106 // GPT Timer A Capture Mode Event Raw Interrupt 1107 // 1108 // 0: The event has not occured. 1109 // 1: The event has occured. 1110 // 1111 // This interrupt asserts when the subtimer is configured in Input Edge-Time 1112 // mode 1113 #define GPT_RIS_CAERIS 0x00000004 1114 #define GPT_RIS_CAERIS_BITN 2 1115 #define GPT_RIS_CAERIS_M 0x00000004 1116 #define GPT_RIS_CAERIS_S 2 1117 1118 // Field: [1] CAMRIS 1119 // 1120 // GPT Timer A Capture Mode Match Raw Interrupt 1121 // 1122 // 0: The capture mode match for Timer A has not occurred. 1123 // 1: A capture mode match has occurred for Timer A. This interrupt 1124 // asserts when the values in the TAR and TAPR 1125 // match the values in the TAMATCHR and TAPMR 1126 // when configured in Input Edge-Time mode. 1127 // 1128 // This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. 1129 #define GPT_RIS_CAMRIS 0x00000002 1130 #define GPT_RIS_CAMRIS_BITN 1 1131 #define GPT_RIS_CAMRIS_M 0x00000002 1132 #define GPT_RIS_CAMRIS_S 1 1133 1134 // Field: [0] TATORIS 1135 // 1136 // GPT Timer A Time-out Raw Interrupt 1137 // 1138 // 0: Timer A has not timed out 1139 // 1: Timer A has timed out. 1140 // 1141 // This interrupt is asserted when a one-shot or periodic mode timer reaches 1142 // its count limit. The count limit is 0 or the value loaded into TAILR, 1143 // depending on the count direction. 1144 #define GPT_RIS_TATORIS 0x00000001 1145 #define GPT_RIS_TATORIS_BITN 0 1146 #define GPT_RIS_TATORIS_M 0x00000001 1147 #define GPT_RIS_TATORIS_S 0 1148 1149 //***************************************************************************** 1150 // 1151 // Register: GPT_O_MIS 1152 // 1153 //***************************************************************************** 1154 // Field: [13] DMABMIS 1155 // 1156 // 0: No interrupt or interrupt not enabled 1157 // 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 1158 #define GPT_MIS_DMABMIS 0x00002000 1159 #define GPT_MIS_DMABMIS_BITN 13 1160 #define GPT_MIS_DMABMIS_M 0x00002000 1161 #define GPT_MIS_DMABMIS_S 13 1162 1163 // Field: [11] TBMMIS 1164 // 1165 // 0: No interrupt or interrupt not enabled 1166 // 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 1167 #define GPT_MIS_TBMMIS 0x00000800 1168 #define GPT_MIS_TBMMIS_BITN 11 1169 #define GPT_MIS_TBMMIS_M 0x00000800 1170 #define GPT_MIS_TBMMIS_S 11 1171 1172 // Field: [10] CBEMIS 1173 // 1174 // 0: No interrupt or interrupt not enabled 1175 // 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 1176 #define GPT_MIS_CBEMIS 0x00000400 1177 #define GPT_MIS_CBEMIS_BITN 10 1178 #define GPT_MIS_CBEMIS_M 0x00000400 1179 #define GPT_MIS_CBEMIS_S 10 1180 1181 // Field: [9] CBMMIS 1182 // 1183 // 0: No interrupt or interrupt not enabled 1184 // 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 1185 #define GPT_MIS_CBMMIS 0x00000200 1186 #define GPT_MIS_CBMMIS_BITN 9 1187 #define GPT_MIS_CBMMIS_M 0x00000200 1188 #define GPT_MIS_CBMMIS_S 9 1189 1190 // Field: [8] TBTOMIS 1191 // 1192 // 0: No interrupt or interrupt not enabled 1193 // 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 1194 #define GPT_MIS_TBTOMIS 0x00000100 1195 #define GPT_MIS_TBTOMIS_BITN 8 1196 #define GPT_MIS_TBTOMIS_M 0x00000100 1197 #define GPT_MIS_TBTOMIS_S 8 1198 1199 // Field: [5] DMAAMIS 1200 // 1201 // 0: No interrupt or interrupt not enabled 1202 // 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 1203 #define GPT_MIS_DMAAMIS 0x00000020 1204 #define GPT_MIS_DMAAMIS_BITN 5 1205 #define GPT_MIS_DMAAMIS_M 0x00000020 1206 #define GPT_MIS_DMAAMIS_S 5 1207 1208 // Field: [4] TAMMIS 1209 // 1210 // 0: No interrupt or interrupt not enabled 1211 // 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 1212 #define GPT_MIS_TAMMIS 0x00000010 1213 #define GPT_MIS_TAMMIS_BITN 4 1214 #define GPT_MIS_TAMMIS_M 0x00000010 1215 #define GPT_MIS_TAMMIS_S 4 1216 1217 // Field: [2] CAEMIS 1218 // 1219 // 0: No interrupt or interrupt not enabled 1220 // 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 1221 #define GPT_MIS_CAEMIS 0x00000004 1222 #define GPT_MIS_CAEMIS_BITN 2 1223 #define GPT_MIS_CAEMIS_M 0x00000004 1224 #define GPT_MIS_CAEMIS_S 2 1225 1226 // Field: [1] CAMMIS 1227 // 1228 // 0: No interrupt or interrupt not enabled 1229 // 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 1230 #define GPT_MIS_CAMMIS 0x00000002 1231 #define GPT_MIS_CAMMIS_BITN 1 1232 #define GPT_MIS_CAMMIS_M 0x00000002 1233 #define GPT_MIS_CAMMIS_S 1 1234 1235 // Field: [0] TATOMIS 1236 // 1237 // 0: No interrupt or interrupt not enabled 1238 // 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 1239 #define GPT_MIS_TATOMIS 0x00000001 1240 #define GPT_MIS_TATOMIS_BITN 0 1241 #define GPT_MIS_TATOMIS_M 0x00000001 1242 #define GPT_MIS_TATOMIS_S 0 1243 1244 //***************************************************************************** 1245 // 1246 // Register: GPT_O_ICLR 1247 // 1248 //***************************************************************************** 1249 // Field: [13] DMABINT 1250 // 1251 // 0: Do nothing. 1252 // 1: Clear RIS.DMABRIS and MIS.DMABMIS 1253 #define GPT_ICLR_DMABINT 0x00002000 1254 #define GPT_ICLR_DMABINT_BITN 13 1255 #define GPT_ICLR_DMABINT_M 0x00002000 1256 #define GPT_ICLR_DMABINT_S 13 1257 1258 // Field: [11] TBMCINT 1259 // 1260 // 0: Do nothing. 1261 // 1: Clear RIS.TBMRIS and MIS.TBMMIS 1262 #define GPT_ICLR_TBMCINT 0x00000800 1263 #define GPT_ICLR_TBMCINT_BITN 11 1264 #define GPT_ICLR_TBMCINT_M 0x00000800 1265 #define GPT_ICLR_TBMCINT_S 11 1266 1267 // Field: [10] CBECINT 1268 // 1269 // 0: Do nothing. 1270 // 1: Clear RIS.CBERIS and MIS.CBEMIS 1271 #define GPT_ICLR_CBECINT 0x00000400 1272 #define GPT_ICLR_CBECINT_BITN 10 1273 #define GPT_ICLR_CBECINT_M 0x00000400 1274 #define GPT_ICLR_CBECINT_S 10 1275 1276 // Field: [9] CBMCINT 1277 // 1278 // 0: Do nothing. 1279 // 1: Clear RIS.CBMRIS and MIS.CBMMIS 1280 #define GPT_ICLR_CBMCINT 0x00000200 1281 #define GPT_ICLR_CBMCINT_BITN 9 1282 #define GPT_ICLR_CBMCINT_M 0x00000200 1283 #define GPT_ICLR_CBMCINT_S 9 1284 1285 // Field: [8] TBTOCINT 1286 // 1287 // 0: Do nothing. 1288 // 1: Clear RIS.TBTORIS and MIS.TBTOMIS 1289 #define GPT_ICLR_TBTOCINT 0x00000100 1290 #define GPT_ICLR_TBTOCINT_BITN 8 1291 #define GPT_ICLR_TBTOCINT_M 0x00000100 1292 #define GPT_ICLR_TBTOCINT_S 8 1293 1294 // Field: [5] DMAAINT 1295 // 1296 // 0: Do nothing. 1297 // 1: Clear RIS.DMAARIS and MIS.DMAAMIS 1298 #define GPT_ICLR_DMAAINT 0x00000020 1299 #define GPT_ICLR_DMAAINT_BITN 5 1300 #define GPT_ICLR_DMAAINT_M 0x00000020 1301 #define GPT_ICLR_DMAAINT_S 5 1302 1303 // Field: [4] TAMCINT 1304 // 1305 // 0: Do nothing. 1306 // 1: Clear RIS.TAMRIS and MIS.TAMMIS 1307 #define GPT_ICLR_TAMCINT 0x00000010 1308 #define GPT_ICLR_TAMCINT_BITN 4 1309 #define GPT_ICLR_TAMCINT_M 0x00000010 1310 #define GPT_ICLR_TAMCINT_S 4 1311 1312 // Field: [2] CAECINT 1313 // 1314 // 0: Do nothing. 1315 // 1: Clear RIS.CAERIS and MIS.CAEMIS 1316 #define GPT_ICLR_CAECINT 0x00000004 1317 #define GPT_ICLR_CAECINT_BITN 2 1318 #define GPT_ICLR_CAECINT_M 0x00000004 1319 #define GPT_ICLR_CAECINT_S 2 1320 1321 // Field: [1] CAMCINT 1322 // 1323 // 0: Do nothing. 1324 // 1: Clear RIS.CAMRIS and MIS.CAMMIS 1325 #define GPT_ICLR_CAMCINT 0x00000002 1326 #define GPT_ICLR_CAMCINT_BITN 1 1327 #define GPT_ICLR_CAMCINT_M 0x00000002 1328 #define GPT_ICLR_CAMCINT_S 1 1329 1330 // Field: [0] TATOCINT 1331 // 1332 // 0: Do nothing. 1333 // 1: Clear RIS.TATORIS and MIS.TATOMIS 1334 #define GPT_ICLR_TATOCINT 0x00000001 1335 #define GPT_ICLR_TATOCINT_BITN 0 1336 #define GPT_ICLR_TATOCINT_M 0x00000001 1337 #define GPT_ICLR_TATOCINT_S 0 1338 1339 //***************************************************************************** 1340 // 1341 // Register: GPT_O_TAILR 1342 // 1343 //***************************************************************************** 1344 // Field: [31:0] TAILR 1345 // 1346 // GPT Timer A Interval Load Register 1347 // 1348 // Writing this field loads the counter for Timer A. A read returns the current 1349 // value of TAILR. 1350 #define GPT_TAILR_TAILR_W 32 1351 #define GPT_TAILR_TAILR_M 0xFFFFFFFF 1352 #define GPT_TAILR_TAILR_S 0 1353 1354 //***************************************************************************** 1355 // 1356 // Register: GPT_O_TBILR 1357 // 1358 //***************************************************************************** 1359 // Field: [31:0] TBILR 1360 // 1361 // GPT Timer B Interval Load Register 1362 // 1363 // Writing this field loads the counter for Timer B. A read returns the current 1364 // value of TBILR. 1365 #define GPT_TBILR_TBILR_W 32 1366 #define GPT_TBILR_TBILR_M 0xFFFFFFFF 1367 #define GPT_TBILR_TBILR_S 0 1368 1369 //***************************************************************************** 1370 // 1371 // Register: GPT_O_TAMATCHR 1372 // 1373 //***************************************************************************** 1374 // Field: [31:0] TAMATCHR 1375 // 1376 // GPT Timer A Match Register 1377 #define GPT_TAMATCHR_TAMATCHR_W 32 1378 #define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF 1379 #define GPT_TAMATCHR_TAMATCHR_S 0 1380 1381 //***************************************************************************** 1382 // 1383 // Register: GPT_O_TBMATCHR 1384 // 1385 //***************************************************************************** 1386 // Field: [15:0] TBMATCHR 1387 // 1388 // GPT Timer B Match Register 1389 #define GPT_TBMATCHR_TBMATCHR_W 16 1390 #define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF 1391 #define GPT_TBMATCHR_TBMATCHR_S 0 1392 1393 //***************************************************************************** 1394 // 1395 // Register: GPT_O_TAPR 1396 // 1397 //***************************************************************************** 1398 // Field: [7:0] TAPSR 1399 // 1400 // Timer A Pre-scale. 1401 // 1402 // Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: 1403 // 1404 // 0: Prescaler ratio = 1 1405 // 1: Prescaler ratio = 2 1406 // 2: Prescaler ratio = 3 1407 // ... 1408 // 255: Prescaler ratio = 256 1409 #define GPT_TAPR_TAPSR_W 8 1410 #define GPT_TAPR_TAPSR_M 0x000000FF 1411 #define GPT_TAPR_TAPSR_S 0 1412 1413 //***************************************************************************** 1414 // 1415 // Register: GPT_O_TBPR 1416 // 1417 //***************************************************************************** 1418 // Field: [7:0] TBPSR 1419 // 1420 // Timer B Pre-scale. 1421 // 1422 // Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: 1423 // 1424 // 0: Prescaler ratio = 1 1425 // 1: Prescaler ratio = 2 1426 // 2: Prescaler ratio = 3 1427 // ... 1428 // 255: Prescaler ratio = 256 1429 #define GPT_TBPR_TBPSR_W 8 1430 #define GPT_TBPR_TBPSR_M 0x000000FF 1431 #define GPT_TBPR_TBPSR_S 0 1432 1433 //***************************************************************************** 1434 // 1435 // Register: GPT_O_TAPMR 1436 // 1437 //***************************************************************************** 1438 // Field: [7:0] TAPSMR 1439 // 1440 // GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. 1441 #define GPT_TAPMR_TAPSMR_W 8 1442 #define GPT_TAPMR_TAPSMR_M 0x000000FF 1443 #define GPT_TAPMR_TAPSMR_S 0 1444 1445 //***************************************************************************** 1446 // 1447 // Register: GPT_O_TBPMR 1448 // 1449 //***************************************************************************** 1450 // Field: [7:0] TBPSMR 1451 // 1452 // GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits 1453 // 23 to 16. 1454 #define GPT_TBPMR_TBPSMR_W 8 1455 #define GPT_TBPMR_TBPSMR_M 0x000000FF 1456 #define GPT_TBPMR_TBPSMR_S 0 1457 1458 //***************************************************************************** 1459 // 1460 // Register: GPT_O_TAR 1461 // 1462 //***************************************************************************** 1463 // Field: [31:0] TAR 1464 // 1465 // GPT Timer A Register 1466 // 1467 // Based on the value in the register field TAMR.TAILD, this register is 1468 // updated with the value from TAILR register either on the next cycle or on 1469 // the next timeout. 1470 // 1471 // A read returns the current value of the Timer A Count Register, in all cases 1472 // except for Input Edge count and Timer modes. 1473 // In the Input Edge Count Mode, this register contains the number of edges 1474 // that have occurred. In the Input Edge Time mode, this register contains the 1475 // time at which the last edge event took place. 1476 #define GPT_TAR_TAR_W 32 1477 #define GPT_TAR_TAR_M 0xFFFFFFFF 1478 #define GPT_TAR_TAR_S 0 1479 1480 //***************************************************************************** 1481 // 1482 // Register: GPT_O_TBR 1483 // 1484 //***************************************************************************** 1485 // Field: [31:0] TBR 1486 // 1487 // GPT Timer B Register 1488 // 1489 // Based on the value in the register field TBMR.TBILD, this register is 1490 // updated with the value from TBILR register either on the next cycle or on 1491 // the next timeout. 1492 // 1493 // A read returns the current value of the Timer B Count Register, in all cases 1494 // except for Input Edge count and Timer modes. 1495 // In the Input Edge Count Mode, this register contains the number of edges 1496 // that have occurred. In the Input Edge Time mode, this register contains the 1497 // time at which the last edge event took place. 1498 #define GPT_TBR_TBR_W 32 1499 #define GPT_TBR_TBR_M 0xFFFFFFFF 1500 #define GPT_TBR_TBR_S 0 1501 1502 //***************************************************************************** 1503 // 1504 // Register: GPT_O_TAV 1505 // 1506 //***************************************************************************** 1507 // Field: [31:0] TAV 1508 // 1509 // GPT Timer A Register 1510 // A read returns the current, free-running value of Timer A in all modes. 1511 // When written, the value written into this register is loaded into the 1512 // TAR register on the next clock cycle. 1513 // Note: In 16-bit mode, only the lower 16-bits of this 1514 // register can be written with a new value. Writes to the prescaler bits have 1515 // no effect 1516 #define GPT_TAV_TAV_W 32 1517 #define GPT_TAV_TAV_M 0xFFFFFFFF 1518 #define GPT_TAV_TAV_S 0 1519 1520 //***************************************************************************** 1521 // 1522 // Register: GPT_O_TBV 1523 // 1524 //***************************************************************************** 1525 // Field: [31:0] TBV 1526 // 1527 // GPT Timer B Register 1528 // A read returns the current, free-running value of Timer B in all modes. 1529 // When written, the value written into this register is loaded into the 1530 // TBR register on the next clock cycle. 1531 // Note: In 16-bit mode, only the lower 16-bits of this 1532 // register can be written with a new value. Writes to the prescaler bits have 1533 // no effect 1534 #define GPT_TBV_TBV_W 32 1535 #define GPT_TBV_TBV_M 0xFFFFFFFF 1536 #define GPT_TBV_TBV_S 0 1537 1538 //***************************************************************************** 1539 // 1540 // Register: GPT_O_TAPS 1541 // 1542 //***************************************************************************** 1543 // Field: [7:0] PSS 1544 // 1545 // GPT Timer A Pre-scaler 1546 #define GPT_TAPS_PSS_W 8 1547 #define GPT_TAPS_PSS_M 0x000000FF 1548 #define GPT_TAPS_PSS_S 0 1549 1550 //***************************************************************************** 1551 // 1552 // Register: GPT_O_TBPS 1553 // 1554 //***************************************************************************** 1555 // Field: [7:0] PSS 1556 // 1557 // GPT Timer B Pre-scaler 1558 #define GPT_TBPS_PSS_W 8 1559 #define GPT_TBPS_PSS_M 0x000000FF 1560 #define GPT_TBPS_PSS_S 0 1561 1562 //***************************************************************************** 1563 // 1564 // Register: GPT_O_TAPV 1565 // 1566 //***************************************************************************** 1567 // Field: [7:0] PSV 1568 // 1569 // GPT Timer A Pre-scaler Value 1570 #define GPT_TAPV_PSV_W 8 1571 #define GPT_TAPV_PSV_M 0x000000FF 1572 #define GPT_TAPV_PSV_S 0 1573 1574 //***************************************************************************** 1575 // 1576 // Register: GPT_O_TBPV 1577 // 1578 //***************************************************************************** 1579 // Field: [7:0] PSV 1580 // 1581 // GPT Timer B Pre-scaler Value 1582 #define GPT_TBPV_PSV_W 8 1583 #define GPT_TBPV_PSV_M 0x000000FF 1584 #define GPT_TBPV_PSV_S 0 1585 1586 //***************************************************************************** 1587 // 1588 // Register: GPT_O_DMAEV 1589 // 1590 //***************************************************************************** 1591 // Field: [11] TBMDMAEN 1592 // 1593 // GPT Timer B Match DMA Trigger Enable 1594 #define GPT_DMAEV_TBMDMAEN 0x00000800 1595 #define GPT_DMAEV_TBMDMAEN_BITN 11 1596 #define GPT_DMAEV_TBMDMAEN_M 0x00000800 1597 #define GPT_DMAEV_TBMDMAEN_S 11 1598 1599 // Field: [10] CBEDMAEN 1600 // 1601 // GPT Timer B Capture Event DMA Trigger Enable 1602 #define GPT_DMAEV_CBEDMAEN 0x00000400 1603 #define GPT_DMAEV_CBEDMAEN_BITN 10 1604 #define GPT_DMAEV_CBEDMAEN_M 0x00000400 1605 #define GPT_DMAEV_CBEDMAEN_S 10 1606 1607 // Field: [9] CBMDMAEN 1608 // 1609 // GPT Timer B Capture Match DMA Trigger Enable 1610 #define GPT_DMAEV_CBMDMAEN 0x00000200 1611 #define GPT_DMAEV_CBMDMAEN_BITN 9 1612 #define GPT_DMAEV_CBMDMAEN_M 0x00000200 1613 #define GPT_DMAEV_CBMDMAEN_S 9 1614 1615 // Field: [8] TBTODMAEN 1616 // 1617 // GPT Timer B Time-Out DMA Trigger Enable 1618 #define GPT_DMAEV_TBTODMAEN 0x00000100 1619 #define GPT_DMAEV_TBTODMAEN_BITN 8 1620 #define GPT_DMAEV_TBTODMAEN_M 0x00000100 1621 #define GPT_DMAEV_TBTODMAEN_S 8 1622 1623 // Field: [4] TAMDMAEN 1624 // 1625 // GPT Timer A Match DMA Trigger Enable 1626 #define GPT_DMAEV_TAMDMAEN 0x00000010 1627 #define GPT_DMAEV_TAMDMAEN_BITN 4 1628 #define GPT_DMAEV_TAMDMAEN_M 0x00000010 1629 #define GPT_DMAEV_TAMDMAEN_S 4 1630 1631 // Field: [2] CAEDMAEN 1632 // 1633 // GPT Timer A Capture Event DMA Trigger Enable 1634 #define GPT_DMAEV_CAEDMAEN 0x00000004 1635 #define GPT_DMAEV_CAEDMAEN_BITN 2 1636 #define GPT_DMAEV_CAEDMAEN_M 0x00000004 1637 #define GPT_DMAEV_CAEDMAEN_S 2 1638 1639 // Field: [1] CAMDMAEN 1640 // 1641 // GPT Timer A Capture Match DMA Trigger Enable 1642 #define GPT_DMAEV_CAMDMAEN 0x00000002 1643 #define GPT_DMAEV_CAMDMAEN_BITN 1 1644 #define GPT_DMAEV_CAMDMAEN_M 0x00000002 1645 #define GPT_DMAEV_CAMDMAEN_S 1 1646 1647 // Field: [0] TATODMAEN 1648 // 1649 // GPT Timer A Time-Out DMA Trigger Enable 1650 #define GPT_DMAEV_TATODMAEN 0x00000001 1651 #define GPT_DMAEV_TATODMAEN_BITN 0 1652 #define GPT_DMAEV_TATODMAEN_M 0x00000001 1653 #define GPT_DMAEV_TATODMAEN_S 0 1654 1655 //***************************************************************************** 1656 // 1657 // Register: GPT_O_VERSION 1658 // 1659 //***************************************************************************** 1660 // Field: [31:0] VERSION 1661 // 1662 // Timer Revision. 1663 #define GPT_VERSION_VERSION_W 32 1664 #define GPT_VERSION_VERSION_M 0xFFFFFFFF 1665 #define GPT_VERSION_VERSION_S 0 1666 1667 //***************************************************************************** 1668 // 1669 // Register: GPT_O_ANDCCP 1670 // 1671 //***************************************************************************** 1672 // Field: [1] LD_TO_EN 1673 // 1674 // PWM assertion would happen at timeout 1675 // 1676 // 0: PWM assertion happens when counter matches load value 1677 // 1: PWM assertion happens at timeout of the counter 1678 #define GPT_ANDCCP_LD_TO_EN 0x00000002 1679 #define GPT_ANDCCP_LD_TO_EN_BITN 1 1680 #define GPT_ANDCCP_LD_TO_EN_M 0x00000002 1681 #define GPT_ANDCCP_LD_TO_EN_S 1 1682 1683 // Field: [0] CCP_AND_EN 1684 // 1685 // Enables AND operation of the CCP outputs for timers A and B. 1686 // 1687 // 0 : PWM outputs of Timer A and Timer B are the internal generated PWM 1688 // signals of the respective timers. 1689 // 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM 1690 // signals and Timer B PWM ouput is Timer B PWM signal only. 1691 #define GPT_ANDCCP_CCP_AND_EN 0x00000001 1692 #define GPT_ANDCCP_CCP_AND_EN_BITN 0 1693 #define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 1694 #define GPT_ANDCCP_CCP_AND_EN_S 0 1695 1696 1697 #endif // __GPT__ 1698
