1 /******************************************************************************
2 *  Filename:       hw_aux_tdc_h
3 *  Revised:        $Date$
4 *  Revision:       $Revision$
5 *
6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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36 
37 #ifndef __HW_AUX_TDC_H__
38 #define __HW_AUX_TDC_H__
39 
40 //*****************************************************************************
41 //
42 // This section defines the register offsets of
43 // AUX_TDC component
44 //
45 //*****************************************************************************
46 // Control
47 #define AUX_TDC_O_CTL                                               0x00000000
48 
49 // Status
50 #define AUX_TDC_O_STAT                                              0x00000004
51 
52 // Result
53 #define AUX_TDC_O_RESULT                                            0x00000008
54 
55 // Saturation Configuration
56 #define AUX_TDC_O_SATCFG                                            0x0000000C
57 
58 // Trigger Source
59 #define AUX_TDC_O_TRIGSRC                                           0x00000010
60 
61 // Trigger Counter
62 #define AUX_TDC_O_TRIGCNT                                           0x00000014
63 
64 // Trigger Counter Load
65 #define AUX_TDC_O_TRIGCNTLOAD                                       0x00000018
66 
67 // Trigger Counter Configuration
68 #define AUX_TDC_O_TRIGCNTCFG                                        0x0000001C
69 
70 // Prescaler Control
71 #define AUX_TDC_O_PRECTL                                            0x00000020
72 
73 // Prescaler Counter
74 #define AUX_TDC_O_PRECNTR                                           0x00000024
75 
76 //*****************************************************************************
77 //
78 // Register: AUX_TDC_O_CTL
79 //
80 //*****************************************************************************
81 // Field:   [1:0] CMD
82 //
83 // TDC commands.
84 // ENUMs:
85 // ABORT                    Force TDC state machine back to IDLE state.
86 //
87 //                          Never write this command
88 //                          while AUX_TDC:STAT.STATE equals CLR_CNT or
89 //                          WAIT_CLR_CNT_DONE.
90 // RUN                      Asynchronous counter start.
91 //
92 //                          The counter starts to
93 //                          count when the start event is high. To achieve
94 //                          precise edge-to-edge measurements you must
95 //                          ensure that the start event is low for at least
96 //                          420 ns after you write this command.
97 // RUN_SYNC_START           Synchronous counter start.
98 //
99 //                          The counter looks for the
100 //                          opposite edge of the selected start event
101 //                          before it starts to count when the selected
102 //                          edge occurs. This guarantees an edge-triggered
103 //                          start and is recommended for frequency
104 //                          measurements.
105 // CLR_RESULT               Clear STAT.SAT, STAT.DONE, and RESULT.VALUE.
106 //
107 //                          This is not needed as
108 //                          prerequisite for a measurement. Reliable clear
109 //                          is only guaranteed from IDLE state.
110 #define AUX_TDC_CTL_CMD_W                                                    2
111 #define AUX_TDC_CTL_CMD_M                                           0x00000003
112 #define AUX_TDC_CTL_CMD_S                                                    0
113 #define AUX_TDC_CTL_CMD_ABORT                                       0x00000003
114 #define AUX_TDC_CTL_CMD_RUN                                         0x00000002
115 #define AUX_TDC_CTL_CMD_RUN_SYNC_START                              0x00000001
116 #define AUX_TDC_CTL_CMD_CLR_RESULT                                  0x00000000
117 
118 //*****************************************************************************
119 //
120 // Register: AUX_TDC_O_STAT
121 //
122 //*****************************************************************************
123 // Field:     [7] SAT
124 //
125 // TDC measurement saturation flag.
126 //
127 // 0: Conversion has not saturated.
128 // 1: Conversion stopped due to saturation.
129 //
130 // This field is cleared when a new measurement is started or when CLR_RESULT
131 // is written to CTL.CMD.
132 #define AUX_TDC_STAT_SAT                                            0x00000080
133 #define AUX_TDC_STAT_SAT_BITN                                                7
134 #define AUX_TDC_STAT_SAT_M                                          0x00000080
135 #define AUX_TDC_STAT_SAT_S                                                   7
136 
137 // Field:     [6] DONE
138 //
139 // TDC measurement complete flag.
140 //
141 // 0: TDC measurement has not yet completed.
142 // 1: TDC measurement has completed.
143 //
144 // This field clears when a new TDC measurement starts or when you write
145 // CLR_RESULT to CTL.CMD.
146 #define AUX_TDC_STAT_DONE                                           0x00000040
147 #define AUX_TDC_STAT_DONE_BITN                                               6
148 #define AUX_TDC_STAT_DONE_M                                         0x00000040
149 #define AUX_TDC_STAT_DONE_S                                                  6
150 
151 // Field:   [5:0] STATE
152 //
153 // TDC state machine status.
154 // ENUMs:
155 // FORCE_STOP               Current state is TDC_FORCESTOP.
156 //                          You wrote ABORT to
157 //                          CTL.CMD to abort the TDC measurement.
158 // START_FALL               Current state is TDC_WAIT_STARTFALL.
159 //                          The fast-counter circuit
160 //                          waits for a falling edge on the start event.
161 // WAIT_CLR_CNT_DONE        Current state is TDC_STATE_WAIT_CLRCNT_DONE.
162 //                          The state machine waits
163 //                          for fast-counter circuit to finish reset.
164 // POR                      Current state is TDC_STATE_POR.
165 //                          This is the reset state.
166 // GET_RESULT               Current state is TDC_STATE_GETRESULTS.
167 //                          The state machine copies
168 //                          the counter value from the fast-counter
169 //                          circuit.
170 // WAIT_STOP_CNTDWN         Current state is TDC_STATE_WAIT_STOPCNTDOWN.
171 //                          The fast-counter circuit
172 //                          looks for the stop condition. It will ignore a
173 //                          number of stop events configured in
174 //                          TRIGCNTLOAD.CNT.
175 // WAIT_STOP                Current state is TDC_STATE_WAIT_STOP.
176 //                          The state machine waits
177 //                          for the fast-counter circuit to stop.
178 // CLR_CNT                  Current state is TDC_STATE_CLRCNT. The
179 //                          fast-counter circuit is reset.
180 // IDLE                     Current state is TDC_STATE_IDLE.
181 //                          This is the default state
182 //                          after reset and abortion. State will change
183 //                          when you write CTL.CMD to either RUN_SYNC_START
184 //                          or RUN.
185 // WAIT_START_STOP_CNT_EN   Current state is TDC_STATE_WAIT_STARTSTOPCNTEN.
186 //                          The fast-counter circuit
187 //                          looks for the start condition. The state
188 //                          machine waits for the fast-counter to
189 //                          increment.
190 // WAIT_START               Current state is TDC_STATE_WAIT_START.
191 //                          The fast-counter circuit
192 //                          looks for the start condition. The state
193 //                          machine waits for the fast-counter to
194 //                          increment.
195 #define AUX_TDC_STAT_STATE_W                                                 6
196 #define AUX_TDC_STAT_STATE_M                                        0x0000003F
197 #define AUX_TDC_STAT_STATE_S                                                 0
198 #define AUX_TDC_STAT_STATE_FORCE_STOP                               0x0000002E
199 #define AUX_TDC_STAT_STATE_START_FALL                               0x0000001E
200 #define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE                        0x00000016
201 #define AUX_TDC_STAT_STATE_POR                                      0x0000000F
202 #define AUX_TDC_STAT_STATE_GET_RESULT                               0x0000000E
203 #define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN                         0x0000000C
204 #define AUX_TDC_STAT_STATE_WAIT_STOP                                0x00000008
205 #define AUX_TDC_STAT_STATE_CLR_CNT                                  0x00000007
206 #define AUX_TDC_STAT_STATE_IDLE                                     0x00000006
207 #define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN                   0x00000004
208 #define AUX_TDC_STAT_STATE_WAIT_START                               0x00000000
209 
210 //*****************************************************************************
211 //
212 // Register: AUX_TDC_O_RESULT
213 //
214 //*****************************************************************************
215 // Field:  [24:0] VALUE
216 //
217 // TDC conversion result.
218 //
219 // The result of the TDC conversion is given in number of clock edges of the
220 // clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and
221 // falling edges are counted.
222 //
223 // If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it
224 // takes a non-zero time to stop the measurement. Hence, the maximum value of
225 // this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT
226 // to R24.
227 #define AUX_TDC_RESULT_VALUE_W                                              25
228 #define AUX_TDC_RESULT_VALUE_M                                      0x01FFFFFF
229 #define AUX_TDC_RESULT_VALUE_S                                               0
230 
231 //*****************************************************************************
232 //
233 // Register: AUX_TDC_O_SATCFG
234 //
235 //*****************************************************************************
236 // Field:   [3:0] LIMIT
237 //
238 // Saturation limit.
239 //
240 // The flag STAT.SAT is set when the TDC counter saturates.
241 //
242 // Values not enumerated are not supported
243 // ENUMs:
244 // R24                      Result bit 24: TDC conversion saturates and stops
245 //                          when RESULT.VALUE[24] is set.
246 // R23                      Result bit 23: TDC conversion saturates and stops
247 //                          when RESULT.VALUE[23] is set.
248 // R22                      Result bit 22: TDC conversion saturates and stops
249 //                          when RESULT.VALUE[22] is set.
250 // R21                      Result bit 21: TDC conversion saturates and stops
251 //                          when RESULT.VALUE[21] is set.
252 // R20                      Result bit 20: TDC conversion saturates and stops
253 //                          when RESULT.VALUE[20] is set.
254 // R19                      Result bit 19: TDC conversion saturates and stops
255 //                          when RESULT.VALUE[19] is set.
256 // R18                      Result bit 18: TDC conversion saturates and stops
257 //                          when RESULT.VALUE[18] is set.
258 // R17                      Result bit 17: TDC conversion saturates and stops
259 //                          when RESULT.VALUE[17] is set.
260 // R16                      Result bit 16: TDC conversion saturates and stops
261 //                          when RESULT.VALUE[16] is set.
262 // R15                      Result bit 15: TDC conversion saturates and stops
263 //                          when RESULT.VALUE[15] is set.
264 // R14                      Result bit 14: TDC conversion saturates and stops
265 //                          when RESULT.VALUE[14] is set.
266 // R13                      Result bit 13: TDC conversion saturates and stops
267 //                          when RESULT.VALUE[13] is set.
268 // R12                      Result bit 12: TDC conversion saturates and stops
269 //                          when RESULT.VALUE[12] is set.
270 #define AUX_TDC_SATCFG_LIMIT_W                                               4
271 #define AUX_TDC_SATCFG_LIMIT_M                                      0x0000000F
272 #define AUX_TDC_SATCFG_LIMIT_S                                               0
273 #define AUX_TDC_SATCFG_LIMIT_R24                                    0x0000000F
274 #define AUX_TDC_SATCFG_LIMIT_R23                                    0x0000000E
275 #define AUX_TDC_SATCFG_LIMIT_R22                                    0x0000000D
276 #define AUX_TDC_SATCFG_LIMIT_R21                                    0x0000000C
277 #define AUX_TDC_SATCFG_LIMIT_R20                                    0x0000000B
278 #define AUX_TDC_SATCFG_LIMIT_R19                                    0x0000000A
279 #define AUX_TDC_SATCFG_LIMIT_R18                                    0x00000009
280 #define AUX_TDC_SATCFG_LIMIT_R17                                    0x00000008
281 #define AUX_TDC_SATCFG_LIMIT_R16                                    0x00000007
282 #define AUX_TDC_SATCFG_LIMIT_R15                                    0x00000006
283 #define AUX_TDC_SATCFG_LIMIT_R14                                    0x00000005
284 #define AUX_TDC_SATCFG_LIMIT_R13                                    0x00000004
285 #define AUX_TDC_SATCFG_LIMIT_R12                                    0x00000003
286 
287 //*****************************************************************************
288 //
289 // Register: AUX_TDC_O_TRIGSRC
290 //
291 //*****************************************************************************
292 // Field:    [14] STOP_POL
293 //
294 // Polarity of stop source.
295 //
296 // Change only while STAT.STATE is IDLE.
297 // ENUMs:
298 // LOW                      TDC conversion stops when low level is detected.
299 // HIGH                     TDC conversion stops when high level is detected.
300 #define AUX_TDC_TRIGSRC_STOP_POL                                    0x00004000
301 #define AUX_TDC_TRIGSRC_STOP_POL_BITN                                       14
302 #define AUX_TDC_TRIGSRC_STOP_POL_M                                  0x00004000
303 #define AUX_TDC_TRIGSRC_STOP_POL_S                                          14
304 #define AUX_TDC_TRIGSRC_STOP_POL_LOW                                0x00004000
305 #define AUX_TDC_TRIGSRC_STOP_POL_HIGH                               0x00000000
306 
307 // Field:  [13:8] STOP_SRC
308 //
309 // Select stop source from the asynchronous AUX event bus.
310 //
311 // Change only while STAT.STATE is IDLE.
312 // ENUMs:
313 // NO_EVENT                 No event.
314 // AUX_TDC_PRE              Select TDC Prescaler event which is generated by
315 //                          configuration of PRECTL.
316 // AUX_SMPH_AUTOTAKE_DONE   AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
317 // AUX_ADC_FIFO_NOT_EMPTY   AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
318 // AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
319 // AUX_ADC_IRQ              AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
320 // AUX_ADC_DONE             AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
321 // AUX_ISRC_RESET_N         AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
322 // AUX_TDC_DONE             AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
323 // AUX_TIMER0_EV            AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
324 // AUX_TIMER1_EV            AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
325 // AUX_TIMER2_PULSE         AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
326 // AUX_TIMER2_EV3           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
327 // AUX_TIMER2_EV2           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
328 // AUX_TIMER2_EV1           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
329 // AUX_TIMER2_EV0           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
330 // AUX_COMPB                AUX_EVCTL:EVSTAT2.AUX_COMPB
331 // AUX_COMPA                AUX_EVCTL:EVSTAT2.AUX_COMPA
332 // MCU_OBSMUX1              AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
333 // MCU_OBSMUX0              AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
334 // MCU_EV                   AUX_EVCTL:EVSTAT2.MCU_EV
335 // ACLK_REF                 AUX_EVCTL:EVSTAT2.ACLK_REF
336 // VDDR_RECHARGE            AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
337 // MCU_ACTIVE               AUX_EVCTL:EVSTAT2.MCU_ACTIVE
338 // PWR_DWN                  AUX_EVCTL:EVSTAT2.PWR_DWN
339 // SCLK_LF                  AUX_EVCTL:EVSTAT2.SCLK_LF
340 // AON_BATMON_TEMP_UPD      AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
341 // AON_BATMON_BAT_UPD       AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
342 // AON_RTC_4KHZ             AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
343 // AON_RTC_CH2_DLY          AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
344 // AON_RTC_CH2              AUX_EVCTL:EVSTAT2.AON_RTC_CH2
345 // MANUAL_EV                AUX_EVCTL:EVSTAT2.MANUAL_EV
346 // AUXIO31                  AUX_EVCTL:EVSTAT1.AUXIO31
347 // AUXIO30                  AUX_EVCTL:EVSTAT1.AUXIO30
348 // AUXIO29                  AUX_EVCTL:EVSTAT1.AUXIO29
349 // AUXIO28                  AUX_EVCTL:EVSTAT1.AUXIO28
350 // AUXIO27                  AUX_EVCTL:EVSTAT1.AUXIO27
351 // AUXIO26                  AUX_EVCTL:EVSTAT1.AUXIO26
352 // AUXIO25                  AUX_EVCTL:EVSTAT1.AUXIO25
353 // AUXIO24                  AUX_EVCTL:EVSTAT1.AUXIO24
354 // AUXIO23                  AUX_EVCTL:EVSTAT1.AUXIO23
355 // AUXIO22                  AUX_EVCTL:EVSTAT1.AUXIO22
356 // AUXIO21                  AUX_EVCTL:EVSTAT1.AUXIO21
357 // AUXIO20                  AUX_EVCTL:EVSTAT1.AUXIO20
358 // AUXIO19                  AUX_EVCTL:EVSTAT1.AUXIO19
359 // AUXIO18                  AUX_EVCTL:EVSTAT1.AUXIO18
360 // AUXIO17                  AUX_EVCTL:EVSTAT1.AUXIO17
361 // AUXIO16                  AUX_EVCTL:EVSTAT1.AUXIO16
362 // AUXIO15                  AUX_EVCTL:EVSTAT0.AUXIO15
363 // AUXIO14                  AUX_EVCTL:EVSTAT0.AUXIO14
364 // AUXIO13                  AUX_EVCTL:EVSTAT0.AUXIO13
365 // AUXIO12                  AUX_EVCTL:EVSTAT0.AUXIO12
366 // AUXIO11                  AUX_EVCTL:EVSTAT0.AUXIO11
367 // AUXIO10                  AUX_EVCTL:EVSTAT0.AUXIO10
368 // AUXIO9                   AUX_EVCTL:EVSTAT0.AUXIO9
369 // AUXIO8                   AUX_EVCTL:EVSTAT0.AUXIO8
370 // AUXIO7                   AUX_EVCTL:EVSTAT0.AUXIO7
371 // AUXIO6                   AUX_EVCTL:EVSTAT0.AUXIO6
372 // AUXIO5                   AUX_EVCTL:EVSTAT0.AUXIO5
373 // AUXIO4                   AUX_EVCTL:EVSTAT0.AUXIO4
374 // AUXIO3                   AUX_EVCTL:EVSTAT0.AUXIO3
375 // AUXIO2                   AUX_EVCTL:EVSTAT0.AUXIO2
376 // AUXIO1                   AUX_EVCTL:EVSTAT0.AUXIO1
377 // AUXIO0                   AUX_EVCTL:EVSTAT0.AUXIO0
378 #define AUX_TDC_TRIGSRC_STOP_SRC_W                                           6
379 #define AUX_TDC_TRIGSRC_STOP_SRC_M                                  0x00003F00
380 #define AUX_TDC_TRIGSRC_STOP_SRC_S                                           8
381 #define AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT                           0x00003F00
382 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE                        0x00003E00
383 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE             0x00003D00
384 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY             0x00003C00
385 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL           0x00003B00
386 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ                        0x00003A00
387 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE                       0x00003900
388 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N                   0x00003800
389 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE                       0x00003700
390 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV                      0x00003600
391 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV                      0x00003500
392 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE                   0x00003400
393 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3                     0x00003300
394 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2                     0x00003200
395 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1                     0x00003100
396 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0                     0x00003000
397 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB                          0x00002F00
398 #define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA                          0x00002E00
399 #define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1                        0x00002D00
400 #define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0                        0x00002C00
401 #define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV                             0x00002B00
402 #define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF                           0x00002A00
403 #define AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE                      0x00002900
404 #define AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE                         0x00002800
405 #define AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN                            0x00002700
406 #define AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF                            0x00002600
407 #define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD                0x00002500
408 #define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD                 0x00002400
409 #define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ                       0x00002300
410 #define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY                    0x00002200
411 #define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2                        0x00002100
412 #define AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV                          0x00002000
413 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31                            0x00001F00
414 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30                            0x00001E00
415 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29                            0x00001D00
416 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28                            0x00001C00
417 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27                            0x00001B00
418 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26                            0x00001A00
419 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25                            0x00001900
420 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24                            0x00001800
421 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23                            0x00001700
422 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22                            0x00001600
423 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21                            0x00001500
424 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20                            0x00001400
425 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19                            0x00001300
426 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18                            0x00001200
427 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17                            0x00001100
428 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16                            0x00001000
429 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15                            0x00000F00
430 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14                            0x00000E00
431 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13                            0x00000D00
432 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12                            0x00000C00
433 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11                            0x00000B00
434 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10                            0x00000A00
435 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9                             0x00000900
436 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8                             0x00000800
437 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7                             0x00000700
438 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6                             0x00000600
439 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5                             0x00000500
440 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4                             0x00000400
441 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3                             0x00000300
442 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2                             0x00000200
443 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1                             0x00000100
444 #define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0                             0x00000000
445 
446 // Field:     [6] START_POL
447 //
448 // Polarity of start source.
449 //
450 // Change only while STAT.STATE is IDLE.
451 // ENUMs:
452 // LOW                      TDC conversion starts when low level is detected.
453 // HIGH                     TDC conversion starts when high level is detected.
454 #define AUX_TDC_TRIGSRC_START_POL                                   0x00000040
455 #define AUX_TDC_TRIGSRC_START_POL_BITN                                       6
456 #define AUX_TDC_TRIGSRC_START_POL_M                                 0x00000040
457 #define AUX_TDC_TRIGSRC_START_POL_S                                          6
458 #define AUX_TDC_TRIGSRC_START_POL_LOW                               0x00000040
459 #define AUX_TDC_TRIGSRC_START_POL_HIGH                              0x00000000
460 
461 // Field:   [5:0] START_SRC
462 //
463 // Select start source from the asynchronous AUX event bus.
464 //
465 // Change only while STAT.STATE is IDLE.
466 // ENUMs:
467 // NO_EVENT                 No event.
468 // AUX_TDC_PRE              Select TDC Prescaler event which is generated by
469 //                          configuration of PRECTL.
470 // AUX_SMPH_AUTOTAKE_DONE   AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
471 // AUX_ADC_FIFO_NOT_EMPTY   AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
472 // AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
473 // AUX_ADC_IRQ              AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
474 // AUX_ADC_DONE             AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
475 // AUX_ISRC_RESET_N         AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
476 // AUX_TDC_DONE             AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
477 // AUX_TIMER0_EV            AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
478 // AUX_TIMER1_EV            AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
479 // AUX_TIMER2_PULSE         AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
480 // AUX_TIMER2_EV3           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
481 // AUX_TIMER2_EV2           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
482 // AUX_TIMER2_EV1           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
483 // AUX_TIMER2_EV0           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
484 // AUX_COMPB                AUX_EVCTL:EVSTAT2.AUX_COMPB
485 // AUX_COMPA                AUX_EVCTL:EVSTAT2.AUX_COMPA
486 // MCU_OBSMUX1              AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
487 // MCU_OBSMUX0              AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
488 // MCU_EV                   AUX_EVCTL:EVSTAT2.MCU_EV
489 // ACLK_REF                 AUX_EVCTL:EVSTAT2.ACLK_REF
490 // VDDR_RECHARGE            AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
491 // MCU_ACTIVE               AUX_EVCTL:EVSTAT2.MCU_ACTIVE
492 // PWR_DWN                  AUX_EVCTL:EVSTAT2.PWR_DWN
493 // SCLK_LF                  AUX_EVCTL:EVSTAT2.SCLK_LF
494 // AON_BATMON_TEMP_UPD      AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
495 // AON_BATMON_BAT_UPD       AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
496 // AON_RTC_4KHZ             AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
497 // AON_RTC_CH2_DLY          AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
498 // AON_RTC_CH2              AUX_EVCTL:EVSTAT2.AON_RTC_CH2
499 // MANUAL_EV                AUX_EVCTL:EVSTAT2.MANUAL_EV
500 // AUXIO31                  AUX_EVCTL:EVSTAT1.AUXIO31
501 // AUXIO30                  AUX_EVCTL:EVSTAT1.AUXIO30
502 // AUXIO29                  AUX_EVCTL:EVSTAT1.AUXIO29
503 // AUXIO28                  AUX_EVCTL:EVSTAT1.AUXIO28
504 // AUXIO27                  AUX_EVCTL:EVSTAT1.AUXIO27
505 // AUXIO26                  AUX_EVCTL:EVSTAT1.AUXIO26
506 // AUXIO25                  AUX_EVCTL:EVSTAT1.AUXIO25
507 // AUXIO24                  AUX_EVCTL:EVSTAT1.AUXIO24
508 // AUXIO23                  AUX_EVCTL:EVSTAT1.AUXIO23
509 // AUXIO22                  AUX_EVCTL:EVSTAT1.AUXIO22
510 // AUXIO21                  AUX_EVCTL:EVSTAT1.AUXIO21
511 // AUXIO20                  AUX_EVCTL:EVSTAT1.AUXIO20
512 // AUXIO19                  AUX_EVCTL:EVSTAT1.AUXIO19
513 // AUXIO18                  AUX_EVCTL:EVSTAT1.AUXIO18
514 // AUXIO17                  AUX_EVCTL:EVSTAT1.AUXIO17
515 // AUXIO16                  AUX_EVCTL:EVSTAT1.AUXIO16
516 // AUXIO15                  AUX_EVCTL:EVSTAT0.AUXIO15
517 // AUXIO14                  AUX_EVCTL:EVSTAT0.AUXIO14
518 // AUXIO13                  AUX_EVCTL:EVSTAT0.AUXIO13
519 // AUXIO12                  AUX_EVCTL:EVSTAT0.AUXIO12
520 // AUXIO11                  AUX_EVCTL:EVSTAT0.AUXIO11
521 // AUXIO10                  AUX_EVCTL:EVSTAT0.AUXIO10
522 // AUXIO9                   AUX_EVCTL:EVSTAT0.AUXIO9
523 // AUXIO8                   AUX_EVCTL:EVSTAT0.AUXIO8
524 // AUXIO7                   AUX_EVCTL:EVSTAT0.AUXIO7
525 // AUXIO6                   AUX_EVCTL:EVSTAT0.AUXIO6
526 // AUXIO5                   AUX_EVCTL:EVSTAT0.AUXIO5
527 // AUXIO4                   AUX_EVCTL:EVSTAT0.AUXIO4
528 // AUXIO3                   AUX_EVCTL:EVSTAT0.AUXIO3
529 // AUXIO2                   AUX_EVCTL:EVSTAT0.AUXIO2
530 // AUXIO1                   AUX_EVCTL:EVSTAT0.AUXIO1
531 // AUXIO0                   AUX_EVCTL:EVSTAT0.AUXIO0
532 #define AUX_TDC_TRIGSRC_START_SRC_W                                          6
533 #define AUX_TDC_TRIGSRC_START_SRC_M                                 0x0000003F
534 #define AUX_TDC_TRIGSRC_START_SRC_S                                          0
535 #define AUX_TDC_TRIGSRC_START_SRC_NO_EVENT                          0x0000003F
536 #define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE                       0x0000003E
537 #define AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE            0x0000003D
538 #define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY            0x0000003C
539 #define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL          0x0000003B
540 #define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ                       0x0000003A
541 #define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE                      0x00000039
542 #define AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N                  0x00000038
543 #define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE                      0x00000037
544 #define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV                     0x00000036
545 #define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV                     0x00000035
546 #define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE                  0x00000034
547 #define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3                    0x00000033
548 #define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2                    0x00000032
549 #define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1                    0x00000031
550 #define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0                    0x00000030
551 #define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB                         0x0000002F
552 #define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA                         0x0000002E
553 #define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1                       0x0000002D
554 #define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0                       0x0000002C
555 #define AUX_TDC_TRIGSRC_START_SRC_MCU_EV                            0x0000002B
556 #define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF                          0x0000002A
557 #define AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE                     0x00000029
558 #define AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE                        0x00000028
559 #define AUX_TDC_TRIGSRC_START_SRC_PWR_DWN                           0x00000027
560 #define AUX_TDC_TRIGSRC_START_SRC_SCLK_LF                           0x00000026
561 #define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD               0x00000025
562 #define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD                0x00000024
563 #define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ                      0x00000023
564 #define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY                   0x00000022
565 #define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2                       0x00000021
566 #define AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV                         0x00000020
567 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO31                           0x0000001F
568 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO30                           0x0000001E
569 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO29                           0x0000001D
570 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO28                           0x0000001C
571 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO27                           0x0000001B
572 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO26                           0x0000001A
573 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO25                           0x00000019
574 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO24                           0x00000018
575 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO23                           0x00000017
576 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO22                           0x00000016
577 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO21                           0x00000015
578 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO20                           0x00000014
579 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO19                           0x00000013
580 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO18                           0x00000012
581 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO17                           0x00000011
582 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO16                           0x00000010
583 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO15                           0x0000000F
584 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO14                           0x0000000E
585 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO13                           0x0000000D
586 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO12                           0x0000000C
587 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO11                           0x0000000B
588 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO10                           0x0000000A
589 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO9                            0x00000009
590 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO8                            0x00000008
591 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO7                            0x00000007
592 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO6                            0x00000006
593 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO5                            0x00000005
594 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO4                            0x00000004
595 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO3                            0x00000003
596 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO2                            0x00000002
597 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO1                            0x00000001
598 #define AUX_TDC_TRIGSRC_START_SRC_AUXIO0                            0x00000000
599 
600 //*****************************************************************************
601 //
602 // Register: AUX_TDC_O_TRIGCNT
603 //
604 //*****************************************************************************
605 // Field:  [15:0] CNT
606 //
607 // Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.
608 //
609 // Read CNT to get the remaining number of stop events to ignore during a TDC
610 // measurement.
611 //
612 // Write CNT to update the remaining number of stop events to ignore during a
613 // TDC measurement. The TDC measurement ignores updates of CNT if there are no
614 // more stop events left to ignore.
615 //
616 // When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the
617 // start of the measurement.
618 #define AUX_TDC_TRIGCNT_CNT_W                                               16
619 #define AUX_TDC_TRIGCNT_CNT_M                                       0x0000FFFF
620 #define AUX_TDC_TRIGCNT_CNT_S                                                0
621 
622 //*****************************************************************************
623 //
624 // Register: AUX_TDC_O_TRIGCNTLOAD
625 //
626 //*****************************************************************************
627 // Field:  [15:0] CNT
628 //
629 // Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.
630 //
631 // To measure frequency of an event source:
632 // - Set start event equal to stop event.
633 // - Set CNT to number of periods to measure. Both 0 and 1 values measures a
634 // single event source period.
635 //
636 // To measure pulse width of an event source:
637 // - Set start event source equal to stop event source.
638 // - Select different polarity for start and stop event.
639 // - Set CNT to 0.
640 //
641 // To measure time from the start event to the Nth stop event when N > 1:
642 // - Select different start and stop event source.
643 // - Set CNT to (N-1).
644 //
645 // See the Technical Reference Manual for event timing requirements.
646 //
647 // When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start
648 // of the measurement.
649 #define AUX_TDC_TRIGCNTLOAD_CNT_W                                           16
650 #define AUX_TDC_TRIGCNTLOAD_CNT_M                                   0x0000FFFF
651 #define AUX_TDC_TRIGCNTLOAD_CNT_S                                            0
652 
653 //*****************************************************************************
654 //
655 // Register: AUX_TDC_O_TRIGCNTCFG
656 //
657 //*****************************************************************************
658 // Field:     [0] EN
659 //
660 // Enable stop-counter.
661 //
662 // 0: Disable stop-counter.
663 // 1: Enable stop-counter.
664 //
665 // Change only while STAT.STATE is IDLE.
666 #define AUX_TDC_TRIGCNTCFG_EN                                       0x00000001
667 #define AUX_TDC_TRIGCNTCFG_EN_BITN                                           0
668 #define AUX_TDC_TRIGCNTCFG_EN_M                                     0x00000001
669 #define AUX_TDC_TRIGCNTCFG_EN_S                                              0
670 
671 //*****************************************************************************
672 //
673 // Register: AUX_TDC_O_PRECTL
674 //
675 //*****************************************************************************
676 // Field:     [7] RESET_N
677 //
678 // Prescaler reset.
679 //
680 // 0: Reset prescaler.
681 // 1: Release reset of prescaler.
682 //
683 // AUX_TDC_PRE event becomes 0 when you reset the prescaler.
684 #define AUX_TDC_PRECTL_RESET_N                                      0x00000080
685 #define AUX_TDC_PRECTL_RESET_N_BITN                                          7
686 #define AUX_TDC_PRECTL_RESET_N_M                                    0x00000080
687 #define AUX_TDC_PRECTL_RESET_N_S                                             7
688 
689 // Field:     [6] RATIO
690 //
691 // Prescaler ratio.
692 //
693 // This controls how often the AUX_TDC_PRE event is generated by the prescaler.
694 // ENUMs:
695 // DIV64                    Prescaler divides input by 64.
696 //
697 //                          AUX_TDC_PRE event has a
698 //                          rising edge for every 64 rising edges of the
699 //                          input. AUX_TDC_PRE event toggles on every 32nd
700 //                          rising edge of the input.
701 // DIV16                    Prescaler divides input by 16.
702 //
703 //                          AUX_TDC_PRE event has a
704 //                          rising edge for every 16 rising edges of the
705 //                          input. AUX_TDC_PRE event toggles on every 8th
706 //                          rising edge of the input.
707 #define AUX_TDC_PRECTL_RATIO                                        0x00000040
708 #define AUX_TDC_PRECTL_RATIO_BITN                                            6
709 #define AUX_TDC_PRECTL_RATIO_M                                      0x00000040
710 #define AUX_TDC_PRECTL_RATIO_S                                               6
711 #define AUX_TDC_PRECTL_RATIO_DIV64                                  0x00000040
712 #define AUX_TDC_PRECTL_RATIO_DIV16                                  0x00000000
713 
714 // Field:   [5:0] SRC
715 //
716 // Prescaler event source.
717 //
718 // Select an event from the asynchronous AUX event bus to connect to the
719 // prescaler input.
720 //
721 // Configure only while RESET_N is 0.
722 // ENUMs:
723 // NO_EVENT                 No event.
724 // AUX_SMPH_AUTOTAKE_DONE   AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
725 // AUX_ADC_FIFO_NOT_EMPTY   AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
726 // AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
727 // AUX_ADC_IRQ              AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
728 // AUX_ADC_DONE             AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
729 // AUX_ISRC_RESET_N         AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
730 // AUX_TDC_DONE             AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
731 // AUX_TIMER0_EV            AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
732 // AUX_TIMER1_EV            AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
733 // AUX_TIMER2_PULSE         AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
734 // AUX_TIMER2_EV3           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
735 // AUX_TIMER2_EV2           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
736 // AUX_TIMER2_EV1           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
737 // AUX_TIMER2_EV0           AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
738 // AUX_COMPB                AUX_EVCTL:EVSTAT2.AUX_COMPB
739 // AUX_COMPA                AUX_EVCTL:EVSTAT2.AUX_COMPA
740 // MCU_OBSMUX1              AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
741 // MCU_OBSMUX0              AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
742 // MCU_EV                   AUX_EVCTL:EVSTAT2.MCU_EV
743 // ACLK_REF                 AUX_EVCTL:EVSTAT2.ACLK_REF
744 // VDDR_RECHARGE            AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
745 // MCU_ACTIVE               AUX_EVCTL:EVSTAT2.MCU_ACTIVE
746 // PWR_DWN                  AUX_EVCTL:EVSTAT2.PWR_DWN
747 // SCLK_LF                  AUX_EVCTL:EVSTAT2.SCLK_LF
748 // AON_BATMON_TEMP_UPD      AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
749 // AON_BATMON_BAT_UPD       AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
750 // AON_RTC_4KHZ             AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
751 // AON_RTC_CH2_DLY          AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
752 // AON_RTC_CH2              AUX_EVCTL:EVSTAT2.AON_RTC_CH2
753 // MANUAL_EV                AUX_EVCTL:EVSTAT2.MANUAL_EV
754 // AUXIO31                  AUX_EVCTL:EVSTAT1.AUXIO31
755 // AUXIO30                  AUX_EVCTL:EVSTAT1.AUXIO30
756 // AUXIO29                  AUX_EVCTL:EVSTAT1.AUXIO29
757 // AUXIO28                  AUX_EVCTL:EVSTAT1.AUXIO28
758 // AUXIO27                  AUX_EVCTL:EVSTAT1.AUXIO27
759 // AUXIO26                  AUX_EVCTL:EVSTAT1.AUXIO26
760 // AUXIO25                  AUX_EVCTL:EVSTAT1.AUXIO25
761 // AUXIO24                  AUX_EVCTL:EVSTAT1.AUXIO24
762 // AUXIO23                  AUX_EVCTL:EVSTAT1.AUXIO23
763 // AUXIO22                  AUX_EVCTL:EVSTAT1.AUXIO22
764 // AUXIO21                  AUX_EVCTL:EVSTAT1.AUXIO21
765 // AUXIO20                  AUX_EVCTL:EVSTAT1.AUXIO20
766 // AUXIO19                  AUX_EVCTL:EVSTAT1.AUXIO19
767 // AUXIO18                  AUX_EVCTL:EVSTAT1.AUXIO18
768 // AUXIO17                  AUX_EVCTL:EVSTAT1.AUXIO17
769 // AUXIO16                  AUX_EVCTL:EVSTAT1.AUXIO16
770 // AUXIO15                  AUX_EVCTL:EVSTAT0.AUXIO15
771 // AUXIO14                  AUX_EVCTL:EVSTAT0.AUXIO14
772 // AUXIO13                  AUX_EVCTL:EVSTAT0.AUXIO13
773 // AUXIO12                  AUX_EVCTL:EVSTAT0.AUXIO12
774 // AUXIO11                  AUX_EVCTL:EVSTAT0.AUXIO11
775 // AUXIO10                  AUX_EVCTL:EVSTAT0.AUXIO10
776 // AUXIO9                   AUX_EVCTL:EVSTAT0.AUXIO9
777 // AUXIO8                   AUX_EVCTL:EVSTAT0.AUXIO8
778 // AUXIO7                   AUX_EVCTL:EVSTAT0.AUXIO7
779 // AUXIO6                   AUX_EVCTL:EVSTAT0.AUXIO6
780 // AUXIO5                   AUX_EVCTL:EVSTAT0.AUXIO5
781 // AUXIO4                   AUX_EVCTL:EVSTAT0.AUXIO4
782 // AUXIO3                   AUX_EVCTL:EVSTAT0.AUXIO3
783 // AUXIO2                   AUX_EVCTL:EVSTAT0.AUXIO2
784 // AUXIO1                   AUX_EVCTL:EVSTAT0.AUXIO1
785 // AUXIO0                   AUX_EVCTL:EVSTAT0.AUXIO0
786 #define AUX_TDC_PRECTL_SRC_W                                                 6
787 #define AUX_TDC_PRECTL_SRC_M                                        0x0000003F
788 #define AUX_TDC_PRECTL_SRC_S                                                 0
789 #define AUX_TDC_PRECTL_SRC_NO_EVENT                                 0x0000003F
790 #define AUX_TDC_PRECTL_SRC_AUX_SMPH_AUTOTAKE_DONE                   0x0000003D
791 #define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_NOT_EMPTY                   0x0000003C
792 #define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_ALMOST_FULL                 0x0000003B
793 #define AUX_TDC_PRECTL_SRC_AUX_ADC_IRQ                              0x0000003A
794 #define AUX_TDC_PRECTL_SRC_AUX_ADC_DONE                             0x00000039
795 #define AUX_TDC_PRECTL_SRC_AUX_ISRC_RESET_N                         0x00000038
796 #define AUX_TDC_PRECTL_SRC_AUX_TDC_DONE                             0x00000037
797 #define AUX_TDC_PRECTL_SRC_AUX_TIMER0_EV                            0x00000036
798 #define AUX_TDC_PRECTL_SRC_AUX_TIMER1_EV                            0x00000035
799 #define AUX_TDC_PRECTL_SRC_AUX_TIMER2_PULSE                         0x00000034
800 #define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV3                           0x00000033
801 #define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV2                           0x00000032
802 #define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV1                           0x00000031
803 #define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV0                           0x00000030
804 #define AUX_TDC_PRECTL_SRC_AUX_COMPB                                0x0000002F
805 #define AUX_TDC_PRECTL_SRC_AUX_COMPA                                0x0000002E
806 #define AUX_TDC_PRECTL_SRC_MCU_OBSMUX1                              0x0000002D
807 #define AUX_TDC_PRECTL_SRC_MCU_OBSMUX0                              0x0000002C
808 #define AUX_TDC_PRECTL_SRC_MCU_EV                                   0x0000002B
809 #define AUX_TDC_PRECTL_SRC_ACLK_REF                                 0x0000002A
810 #define AUX_TDC_PRECTL_SRC_VDDR_RECHARGE                            0x00000029
811 #define AUX_TDC_PRECTL_SRC_MCU_ACTIVE                               0x00000028
812 #define AUX_TDC_PRECTL_SRC_PWR_DWN                                  0x00000027
813 #define AUX_TDC_PRECTL_SRC_SCLK_LF                                  0x00000026
814 #define AUX_TDC_PRECTL_SRC_AON_BATMON_TEMP_UPD                      0x00000025
815 #define AUX_TDC_PRECTL_SRC_AON_BATMON_BAT_UPD                       0x00000024
816 #define AUX_TDC_PRECTL_SRC_AON_RTC_4KHZ                             0x00000023
817 #define AUX_TDC_PRECTL_SRC_AON_RTC_CH2_DLY                          0x00000022
818 #define AUX_TDC_PRECTL_SRC_AON_RTC_CH2                              0x00000021
819 #define AUX_TDC_PRECTL_SRC_MANUAL_EV                                0x00000020
820 #define AUX_TDC_PRECTL_SRC_AUXIO31                                  0x0000001F
821 #define AUX_TDC_PRECTL_SRC_AUXIO30                                  0x0000001E
822 #define AUX_TDC_PRECTL_SRC_AUXIO29                                  0x0000001D
823 #define AUX_TDC_PRECTL_SRC_AUXIO28                                  0x0000001C
824 #define AUX_TDC_PRECTL_SRC_AUXIO27                                  0x0000001B
825 #define AUX_TDC_PRECTL_SRC_AUXIO26                                  0x0000001A
826 #define AUX_TDC_PRECTL_SRC_AUXIO25                                  0x00000019
827 #define AUX_TDC_PRECTL_SRC_AUXIO24                                  0x00000018
828 #define AUX_TDC_PRECTL_SRC_AUXIO23                                  0x00000017
829 #define AUX_TDC_PRECTL_SRC_AUXIO22                                  0x00000016
830 #define AUX_TDC_PRECTL_SRC_AUXIO21                                  0x00000015
831 #define AUX_TDC_PRECTL_SRC_AUXIO20                                  0x00000014
832 #define AUX_TDC_PRECTL_SRC_AUXIO19                                  0x00000013
833 #define AUX_TDC_PRECTL_SRC_AUXIO18                                  0x00000012
834 #define AUX_TDC_PRECTL_SRC_AUXIO17                                  0x00000011
835 #define AUX_TDC_PRECTL_SRC_AUXIO16                                  0x00000010
836 #define AUX_TDC_PRECTL_SRC_AUXIO15                                  0x0000000F
837 #define AUX_TDC_PRECTL_SRC_AUXIO14                                  0x0000000E
838 #define AUX_TDC_PRECTL_SRC_AUXIO13                                  0x0000000D
839 #define AUX_TDC_PRECTL_SRC_AUXIO12                                  0x0000000C
840 #define AUX_TDC_PRECTL_SRC_AUXIO11                                  0x0000000B
841 #define AUX_TDC_PRECTL_SRC_AUXIO10                                  0x0000000A
842 #define AUX_TDC_PRECTL_SRC_AUXIO9                                   0x00000009
843 #define AUX_TDC_PRECTL_SRC_AUXIO8                                   0x00000008
844 #define AUX_TDC_PRECTL_SRC_AUXIO7                                   0x00000007
845 #define AUX_TDC_PRECTL_SRC_AUXIO6                                   0x00000006
846 #define AUX_TDC_PRECTL_SRC_AUXIO5                                   0x00000005
847 #define AUX_TDC_PRECTL_SRC_AUXIO4                                   0x00000004
848 #define AUX_TDC_PRECTL_SRC_AUXIO3                                   0x00000003
849 #define AUX_TDC_PRECTL_SRC_AUXIO2                                   0x00000002
850 #define AUX_TDC_PRECTL_SRC_AUXIO1                                   0x00000001
851 #define AUX_TDC_PRECTL_SRC_AUXIO0                                   0x00000000
852 
853 //*****************************************************************************
854 //
855 // Register: AUX_TDC_O_PRECNTR
856 //
857 //*****************************************************************************
858 // Field:  [15:0] CNT
859 //
860 // Prescaler counter value.
861 //
862 // Write a value to CNT to capture the value of the 16-bit prescaler counter
863 // into CNT. Read CNT to get the captured value.
864 //
865 // The read value gets 1 LSB uncertainty if the event source level rises when
866 // you release the reset.
867 // The read value gets 1 LSB uncertainty if the event source level rises when
868 // you capture the prescaler counter.
869 //
870 // Please note the following:
871 // - The prescaler counter is reset to 2 by PRECTL.RESET_N.
872 // - The captured value is 2 when the number of rising edges on prescaler input
873 // is less than 3. Otherwise, captured value equals number of event pulses - 1.
874 #define AUX_TDC_PRECNTR_CNT_W                                               16
875 #define AUX_TDC_PRECNTR_CNT_M                                       0x0000FFFF
876 #define AUX_TDC_PRECNTR_CNT_S                                                0
877 
878 
879 #endif // __AUX_TDC__
880