1 /******************************************************************************
2 * Filename: udma.h
3 *
4 * Description: Defines and prototypes for the uDMA controller.
5 *
6 * Copyright (c) 2015 - 2022, Texas Instruments Incorporated
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are met:
11 *
12 * 1) Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * 2) Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
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18 *
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20 * be used to endorse or promote products derived from this software without
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22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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35 ******************************************************************************/
36
37 //*****************************************************************************
38 //
39 //! \addtogroup peripheral_group
40 //! @{
41 //! \addtogroup udma_api
42 //! @{
43 //
44 //*****************************************************************************
45
46 #ifndef __UDMA_H__
47 #define __UDMA_H__
48
49 //*****************************************************************************
50 //
51 // If building with a C++ compiler, make all of the definitions in this header
52 // have a C binding.
53 //
54 //*****************************************************************************
55 #ifdef __cplusplus
56 extern "C"
57 {
58 #endif
59
60 #include <stdbool.h>
61 #include <stdint.h>
62 #include "../inc/hw_types.h"
63 #include "../inc/hw_ints.h"
64 #include "../inc/hw_memmap.h"
65 #include "../inc/hw_udma.h"
66 #include "debug.h"
67 #include "interrupt.h"
68
69 //*****************************************************************************
70 //
71 // Support for DriverLib in ROM:
72 // This section renames all functions that are not "static inline", so that
73 // calling these functions will default to implementation in flash. At the end
74 // of this file a second renaming will change the defaults to implementation in
75 // ROM for available functions.
76 //
77 // To force use of the implementation in flash, e.g. for debugging:
78 // - Globally: Define DRIVERLIB_NOROM at project level
79 // - Per function: Use prefix "NOROM_" when calling the function
80 //
81 //*****************************************************************************
82 #if !defined(DOXYGEN)
83 #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable
84 #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable
85 #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet
86 #define uDMAChannelControlSet NOROM_uDMAChannelControlSet
87 #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet
88 #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet
89 #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet
90 #define uDMAChannelModeGet NOROM_uDMAChannelModeGet
91 #endif
92
93 //*****************************************************************************
94 //
95 //! \brief A structure that defines an entry in the channel control table.
96 //!
97 //! These fields are used by the uDMA controller and normally it is not necessary for
98 //! software to directly read or write fields in the table.
99 //
100 //*****************************************************************************
101 typedef struct
102 {
103 volatile void *pvSrcEndAddr; //!< The ending source address of the data transfer.
104 volatile void *pvDstEndAddr; //!< The ending destination address of the data transfer.
105 volatile uint32_t ui32Control; //!< The channel control mode.
106 volatile uint32_t ui32Spare; //!< An unused location.
107 }
108 tDMAControlTable;
109
110 //*****************************************************************************
111 //
112 //! \brief A helper macro for building scatter-gather task table entries.
113 //!
114 //! This macro is intended to be used to help populate a table of uDMA tasks
115 //! for a scatter-gather transfer. This macro will calculate the values for
116 //! the fields of a task structure entry based on the input parameters.
117 //!
118 //! There are specific requirements for the values of each parameter. No
119 //! checking is done so it is up to the caller to ensure that correct values
120 //! are used for the parameters.
121 //!
122 //! This macro is intended to be used to initialize individual entries of
123 //! a structure of tDMAControlTable type, like this:
124 //!
125 /*!
126 \verbatim
127 tDMAControlTable MyTaskList[] =
128 {
129 uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
130 UDMA_SRC_INC_8, MySourceBuf,
131 UDMA_DST_INC_8, MyDestBuf,
132 UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
133 uDMATaskStructEntry(Task2Count, ... ),
134 }
135 \endverbatim
136 */
137 //! \param ui32TransferCount is the count of items to transfer for this task.
138 //! It must be in the range 1-1024.
139 //! \param ui32ItemSize is the bit size of the items to transfer for this task.
140 //! It must be one of:
141 //! - \ref UDMA_SIZE_8
142 //! - \ref UDMA_SIZE_16
143 //! - \ref UDMA_SIZE_32
144 //! \param ui32SrcIncrement is the bit size increment for source data.
145 //! It must be one of:
146 //! - \ref UDMA_SRC_INC_8
147 //! - \ref UDMA_SRC_INC_16
148 //! - \ref UDMA_SRC_INC_32
149 //! - \ref UDMA_SRC_INC_NONE
150 //! \param pvSrcAddr is the starting address of the data to transfer.
151 //! \param ui32DstIncrement is the bit size increment for destination data.
152 //! It must be one of:
153 //! - \ref UDMA_DST_INC_8
154 //! - \ref UDMA_DST_INC_16
155 //! - \ref UDMA_DST_INC_32
156 //! - \ref UDMA_DST_INC_NONE
157 //! \param pvDstAddr is the starting address of the destination data.
158 //! \param ui32ArbSize is the arbitration size to use for the transfer task.
159 //! This is used to select the arbitration size in powers of 2, from 1 to 1024.
160 //! It must be one of:
161 //! - \ref UDMA_ARB_1
162 //! - \ref UDMA_ARB_2
163 //! - \ref UDMA_ARB_4
164 //! - ...
165 //! - \ref UDMA_ARB_1024
166 //! \param ui32Mode is the transfer mode for this task.
167 //! Note that normally all tasks will be one of the scatter-gather modes while the
168 //! last task is a task list will be AUTO or BASIC.
169 //! It must be one of:
170 //! - \ref UDMA_MODE_BASIC
171 //! - \ref UDMA_MODE_AUTO
172 //! - \ref UDMA_MODE_MEM_SCATTER_GATHER
173 //! - \ref UDMA_MODE_PER_SCATTER_GATHER
174 //!
175 //! \return None (this is not a function)
176 //
177 //*****************************************************************************
178 #define uDMATaskStructEntry(ui32TransferCount, \
179 ui32ItemSize, \
180 ui32SrcIncrement, \
181 pvSrcAddr, \
182 ui32DstIncrement, \
183 pvDstAddr, \
184 ui32ArbSize, \
185 ui32Mode) \
186 { \
187 (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \
188 ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \
189 ((ui32SrcIncrement) >> 26)) - 1]))), \
190 (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \
191 ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \
192 ((ui32DstIncrement) >> 30)) - 1]))), \
193 (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \
194 (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \
195 ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
196 ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
197 (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \
198 }
199
200 //*****************************************************************************
201 //
202 // The hardware configured number of uDMA channels.
203 //
204 //*****************************************************************************
205 #define UDMA_NUM_CHANNELS 21
206
207 //*****************************************************************************
208 //
209 // The level of priority for the uDMA channels
210 //
211 //*****************************************************************************
212 #define UDMA_PRIORITY_LOW 0x00000000
213 #define UDMA_PRIORITY_HIGH 0x00000001
214
215 //*****************************************************************************
216 //
217 // Flags that can be passed to uDMAChannelAttributeEnable(),
218 // uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
219 //
220 //*****************************************************************************
221 #define UDMA_ATTR_USEBURST 0x00000001
222 #define UDMA_ATTR_ALTSELECT 0x00000002
223 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004
224 #define UDMA_ATTR_REQMASK 0x00000008
225 #define UDMA_ATTR_ALL 0x0000000F
226
227 //*****************************************************************************
228 //
229 // DMA control modes that can be passed to uDMAChannelModeSet() and returned
230 // uDMAChannelModeGet().
231 //
232 //*****************************************************************************
233 #define UDMA_MODE_STOP 0x00000000
234 #define UDMA_MODE_BASIC 0x00000001
235 #define UDMA_MODE_AUTO 0x00000002
236 #define UDMA_MODE_PINGPONG 0x00000003
237 #define UDMA_MODE_MEM_SCATTER_GATHER \
238 0x00000004
239 #define UDMA_MODE_PER_SCATTER_GATHER \
240 0x00000006
241 #define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode
242 #define UDMA_MODE_ALT_SELECT 0x00000001
243
244 //*****************************************************************************
245 //
246 // Channel configuration values that can be passed to uDMAControlSet().
247 //
248 //*****************************************************************************
249 #define UDMA_DST_INC_8 0x00000000
250 #define UDMA_DST_INC_16 0x40000000
251 #define UDMA_DST_INC_32 0x80000000
252 #define UDMA_DST_INC_NONE 0xC0000000
253 #define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment
254 #define UDMA_DST_INC_S 30
255 #define UDMA_SRC_INC_8 0x00000000
256 #define UDMA_SRC_INC_16 0x04000000
257 #define UDMA_SRC_INC_32 0x08000000
258 #define UDMA_SRC_INC_NONE 0x0c000000
259 #define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment
260 #define UDMA_SRC_INC_S 26
261 #define UDMA_SIZE_8 0x00000000
262 #define UDMA_SIZE_16 0x11000000
263 #define UDMA_SIZE_32 0x22000000
264 #define UDMA_SIZE_M 0x33000000 // Data Size
265 #define UDMA_SIZE_S 24
266 #define UDMA_ARB_1 0x00000000
267 #define UDMA_ARB_2 0x00004000
268 #define UDMA_ARB_4 0x00008000
269 #define UDMA_ARB_8 0x0000c000
270 #define UDMA_ARB_16 0x00010000
271 #define UDMA_ARB_32 0x00014000
272 #define UDMA_ARB_64 0x00018000
273 #define UDMA_ARB_128 0x0001c000
274 #define UDMA_ARB_256 0x00020000
275 #define UDMA_ARB_512 0x00024000
276 #define UDMA_ARB_1024 0x00028000
277 #define UDMA_ARB_M 0x0003C000 // Arbitration Size
278 #define UDMA_ARB_S 14
279 #define UDMA_NEXT_USEBURST 0x00000008
280 #define UDMA_XFER_SIZE_MAX 1024
281 #define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size
282 #define UDMA_XFER_SIZE_S 4
283
284 //*****************************************************************************
285 //
286 // Channel numbers to be passed to API functions that require a channel number
287 // ID.
288 //
289 //*****************************************************************************
290 #define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0
291 #define UDMA_CHAN_UART0_RX 1 // UART0 RX Data
292 #define UDMA_CHAN_UART0_TX 2 // UART0 RX Data
293 #define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data
294 #define UDMA_CHAN_SSI0_TX 4 // SSI0 TX Data
295 #define UDMA_CHAN_UART1_RX 5 // UART1 RX Data
296 #define UDMA_CHAN_UART1_TX 6 // UART1 TX Data
297 #define UDMA_CHAN_AUX_ADC 7 // AUX ADC event
298 #define UDMA_CHAN_AUX_SW 8 // AUX Software event
299 #define UDMA_CHAN_TIMER0_A 9 // Timer0 A event
300 #define UDMA_CHAN_TIMER0_B 10 // Timer0 B event
301 #define UDMA_CHAN_TIMER1_A 11 // Timer1 A event
302 #define UDMA_CHAN_TIMER1_B 12 // Timer1 B event
303 #define UDMA_CHAN_AON_PROG2 13
304 #define UDMA_CHAN_DMA_PROG 14
305 #define UDMA_CHAN_AON_RTC 15
306 #define UDMA_CHAN_SSI1_RX 16 // SSI1 RX Data
307 #define UDMA_CHAN_SSI1_TX 17 // SSI1 TX Data
308 #define UDMA_CHAN_SW_EVT1 18
309 #define UDMA_CHAN_SW_EVT2 19
310 #define UDMA_CHAN_SW_EVT3 20
311
312 //*****************************************************************************
313 //
314 // Flags to be OR'd with the channel ID to indicate if the primary or alternate
315 // control structure should be used.
316 //
317 //*****************************************************************************
318 #define UDMA_PRI_SELECT 0x00000000
319 #define UDMA_ALT_SELECT 0x00000020
320
321 //*****************************************************************************
322 //
323 // API Functions and prototypes
324 //
325 //*****************************************************************************
326
327 #ifdef DRIVERLIB_DEBUG
328 //*****************************************************************************
329 //
330 //! \internal
331 //!
332 //! \brief Checks a uDMA base address.
333 //!
334 //! This function determines if a uDMA module base address is valid.
335 //!
336 //! \param ui32Base specifies the uDMA module base address.
337 //!
338 //! \return Returns \c true if the base address is valid and \c false
339 //! otherwise.
340 //
341 //*****************************************************************************
342 static bool
uDMABaseValid(uint32_t ui32Base)343 uDMABaseValid(uint32_t ui32Base)
344 {
345 return(ui32Base == UDMA0_BASE);
346 }
347 #endif
348
349 //*****************************************************************************
350 //
351 //! \brief Enables the uDMA controller for use.
352 //!
353 //! This function enables the uDMA controller. The uDMA controller must be
354 //! enabled before it can be configured and used.
355 //!
356 //! \param ui32Base is the base address of the uDMA port.
357 //!
358 //! \return None
359 //
360 //*****************************************************************************
361 __STATIC_INLINE void
uDMAEnable(uint32_t ui32Base)362 uDMAEnable(uint32_t ui32Base)
363 {
364 // Check the arguments.
365 ASSERT(uDMABaseValid(ui32Base));
366
367 // Set the master enable bit in the config register.
368 HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE;
369 }
370
371 //*****************************************************************************
372 //
373 //! \brief Disables the uDMA controller for use.
374 //!
375 //! This function disables the uDMA controller. Once disabled, the uDMA
376 //! controller will not operate until re-enabled with \ref uDMAEnable().
377 //!
378 //! \param ui32Base is the base address of the uDMA port.
379 //!
380 //! \return None.
381 //
382 //*****************************************************************************
383 __STATIC_INLINE void
uDMADisable(uint32_t ui32Base)384 uDMADisable(uint32_t ui32Base)
385 {
386 // Check the arguments.
387 ASSERT(uDMABaseValid(ui32Base));
388
389 // Clear the master enable bit in the config register.
390 HWREG(ui32Base + UDMA_O_CFG) = 0;
391 }
392
393 //*****************************************************************************
394 //
395 //! \brief Gets the uDMA error status.
396 //!
397 //! This function returns the uDMA error status. It should be called from
398 //! within the uDMA error interrupt handler to determine if a uDMA error
399 //! occurred.
400 //!
401 //! \param ui32Base is the base address of the uDMA port.
402 //!
403 //! \return Returns non-zero if a uDMA error is pending.
404 //
405 //*****************************************************************************
406 __STATIC_INLINE uint32_t
uDMAErrorStatusGet(uint32_t ui32Base)407 uDMAErrorStatusGet(uint32_t ui32Base)
408 {
409 // Check the arguments.
410 ASSERT(uDMABaseValid(ui32Base));
411
412 // Return the uDMA error status.
413 return(HWREG(ui32Base + UDMA_O_ERROR));
414 }
415
416 //*****************************************************************************
417 //
418 //! \brief Clears the uDMA error interrupt.
419 //!
420 //! This function clears a pending uDMA error interrupt. It should be called
421 //! from within the uDMA error interrupt handler to clear the interrupt.
422 //!
423 //! \param ui32Base is the base address of the uDMA port.
424 //!
425 //! \return None
426 //
427 //*****************************************************************************
428 __STATIC_INLINE void
uDMAErrorStatusClear(uint32_t ui32Base)429 uDMAErrorStatusClear(uint32_t ui32Base)
430 {
431 // Check the arguments.
432 ASSERT(uDMABaseValid(ui32Base));
433
434 // Clear the uDMA error interrupt.
435 HWREG(ui32Base + UDMA_O_ERROR) = UDMA_ERROR_STATUS;
436 }
437
438 //*****************************************************************************
439 //
440 //! \brief Enables a uDMA channel for operation.
441 //!
442 //! This function enables a specific uDMA channel for use. This function must
443 //! be used to enable a channel before it can be used to perform a uDMA
444 //! transfer.
445 //!
446 //! When a uDMA transfer is completed, the channel will be automatically
447 //! disabled by the uDMA controller. Therefore, this function should be called
448 //! prior to starting up any new transfer.
449 //!
450 //! \param ui32Base is the base address of the uDMA port.
451 //! \param ui32ChannelNum is the channel number to enable.
452 //!
453 //! \return None
454 //
455 //*****************************************************************************
456 __STATIC_INLINE void
uDMAChannelEnable(uint32_t ui32Base,uint32_t ui32ChannelNum)457 uDMAChannelEnable(uint32_t ui32Base, uint32_t ui32ChannelNum)
458 {
459 // Check the arguments.
460 ASSERT(uDMABaseValid(ui32Base));
461 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
462
463 // Set the bit for this channel in the enable set register.
464 HWREG(ui32Base + UDMA_O_SETCHANNELEN) = 1 << ui32ChannelNum;
465 }
466
467 //*****************************************************************************
468 //
469 //! \brief Disables a uDMA channel for operation.
470 //!
471 //! This function disables a specific uDMA channel. Once disabled, a channel
472 //! will not respond to uDMA transfer requests until re-enabled via
473 //! \ref uDMAChannelEnable().
474 //!
475 //! \param ui32Base is the base address of the uDMA port.
476 //! \param ui32ChannelNum is the channel number to disable.
477 //!
478 //! \return None.
479 //
480 //*****************************************************************************
481 __STATIC_INLINE void
uDMAChannelDisable(uint32_t ui32Base,uint32_t ui32ChannelNum)482 uDMAChannelDisable(uint32_t ui32Base, uint32_t ui32ChannelNum)
483 {
484 // Check the arguments.
485 ASSERT(uDMABaseValid(ui32Base));
486 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
487
488 // Set the bit for this channel in the enable clear register.
489 HWREG(ui32Base + UDMA_O_CLEARCHANNELEN) = 1 << ui32ChannelNum;
490 }
491
492 //*****************************************************************************
493 //
494 //! \brief Checks if a uDMA channel is enabled for operation.
495 //!
496 //! This function checks to see if a specific uDMA channel is enabled. This
497 //! can be used to check the status of a transfer, since the channel will
498 //! be automatically disabled at the end of a transfer.
499 //!
500 //! \param ui32Base is the base address of the uDMA port.
501 //! \param ui32ChannelNum is the channel number to check.
502 //!
503 //! \return Returns status of uDMA channel.
504 //! - \c true : Channel is enabled.
505 //! - \c false : Disabled.
506 //
507 //*****************************************************************************
508 __STATIC_INLINE bool
uDMAChannelIsEnabled(uint32_t ui32Base,uint32_t ui32ChannelNum)509 uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum)
510 {
511 // Check the arguments.
512 ASSERT(uDMABaseValid(ui32Base));
513 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
514
515 // AND the specified channel bit with the enable register, and return the
516 // result.
517 return((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ?
518 true : false);
519 }
520
521 //*****************************************************************************
522 //
523 //! \brief Sets the base address for the channel control table.
524 //!
525 //! This function sets the base address of the channel control table. This
526 //! table resides in system memory and holds control information for each uDMA
527 //! channel. The table must be aligned on a 1024 byte boundary. The base
528 //! address must be set before any of the channel functions can be used.
529 //! Setting the base address of the primary control table will automatically
530 //! set the address for the alternate control table as the next memory
531 //! location after the primary control table.
532 //!
533 //! The size of the channel control table depends on the number of uDMA
534 //! channels, and which transfer modes are used. Refer to the introductory
535 //! text and the microcontroller datasheet for more information about the
536 //! channel control table.
537 //!
538 //! \note This register cannot be read when the controller is in the reset
539 //! state.
540 //!
541 //! \param ui32Base is the base address of the uDMA port.
542 //! \param pControlTable is a pointer to the 1024 byte aligned base address
543 //! of the uDMA channel control table. The address must be an absolute address
544 //! in system memory space.
545 //!
546 //! \return None
547 //
548 //*****************************************************************************
549 __STATIC_INLINE void
uDMAControlBaseSet(uint32_t ui32Base,void * pControlTable)550 uDMAControlBaseSet(uint32_t ui32Base, void *pControlTable)
551 {
552 // Check the arguments.
553 ASSERT(uDMABaseValid(ui32Base));
554 ASSERT(((uint32_t)pControlTable & ~0x3FF) ==
555 (uint32_t)pControlTable);
556 ASSERT((uint32_t)pControlTable >= SRAM_BASE);
557
558 // Program the base address into the register.
559 HWREG(ui32Base + UDMA_O_CTRL) = (uint32_t)pControlTable;
560 }
561
562 //*****************************************************************************
563 //
564 //! \brief Gets the base address for the channel control table.
565 //!
566 //! This function gets the base address of the channel control table. This
567 //! table resides in system memory and holds control information for each uDMA
568 //! channel.
569 //!
570 //! \param ui32Base is the base address of the uDMA port.
571 //!
572 //! \return Returns a pointer to the base address of the channel control table.
573 //
574 //*****************************************************************************
575 __STATIC_INLINE void *
uDMAControlBaseGet(uint32_t ui32Base)576 uDMAControlBaseGet(uint32_t ui32Base)
577 {
578 // Check the arguments.
579
580 ASSERT(uDMABaseValid(ui32Base));
581 // Read the current value of the control base register, and return it to
582 // the caller.
583 return((void *)HWREG(ui32Base + UDMA_O_CTRL));
584 }
585
586 //*****************************************************************************
587 //
588 //! \brief Gets the base address for the channel control table alternate structures.
589 //!
590 //! This function gets the base address of the second half of the channel
591 //! control table that holds the alternate control structures for each channel.
592 //!
593 //! \param ui32Base is the base address of the uDMA port.
594 //!
595 //! \return Returns a pointer to the base address of the second half of the
596 //! channel control table.
597 //
598 //*****************************************************************************
599 __STATIC_INLINE void *
uDMAControlAlternateBaseGet(uint32_t ui32Base)600 uDMAControlAlternateBaseGet(uint32_t ui32Base)
601 {
602 // Check the arguments.
603 ASSERT(uDMABaseValid(ui32Base));
604
605 // Read the current value of the control base register, and return it to
606 // the caller.
607 return((void *)HWREG(ui32Base + UDMA_O_ALTCTRL));
608 }
609
610 //*****************************************************************************
611 //
612 //! \brief Requests a uDMA channel to start a transfer.
613 //!
614 //! This function allows software to request a uDMA channel to begin a
615 //! transfer. This could be used for performing a memory to memory transfer,
616 //! or if for some reason a transfer needs to be initiated by software instead
617 //! of the peripheral associated with that channel.
618 //!
619 //! \note If the channel is a software channel and interrupts are used, then
620 //! the completion will be signaled on the uDMA dedicated interrupt. If a
621 //! peripheral channel is used, then the completion will be signaled on the
622 //! peripheral's interrupt.
623 //!
624 //! \param ui32Base is the base address of the uDMA port.
625 //! \param ui32ChannelNum is the channel number on which to request a uDMA
626 //! transfer.
627 //!
628 //! \return None.
629 //
630 //*****************************************************************************
631 __STATIC_INLINE void
uDMAChannelRequest(uint32_t ui32Base,uint32_t ui32ChannelNum)632 uDMAChannelRequest(uint32_t ui32Base, uint32_t ui32ChannelNum)
633 {
634 // Check the arguments.
635 ASSERT(uDMABaseValid(ui32Base));
636 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
637
638 // Set the bit for this channel in the software uDMA request register.
639 HWREG(ui32Base + UDMA_O_SOFTREQ) = 1 << ui32ChannelNum;
640 }
641
642 //*****************************************************************************
643 //
644 //! \brief Enables attributes of a uDMA channel.
645 //!
646 //! This function is used to enable attributes of a uDMA channel.
647 //!
648 //! \param ui32Base is the base address of the uDMA port.
649 //! \param ui32ChannelNum is the channel to configure.
650 //! \param ui32Attr is a combination of attributes for the channel.
651 //! The parameter is the bitwise OR of any of the following:
652 //! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode.
653 //! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure
654 //! for this channel (it is very unlikely that this flag should be used).
655 //! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
656 //! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
657 //! peripheral for this channel.
658 //!
659 //! \return None
660 //
661 //*****************************************************************************
662 extern void uDMAChannelAttributeEnable(uint32_t ui32Base,
663 uint32_t ui32ChannelNum,
664 uint32_t ui32Attr);
665
666 //*****************************************************************************
667 //
668 //! \brief Disables attributes of an uDMA channel.
669 //!
670 //! This function is used to disable attributes of a uDMA channel.
671 //!
672 //! \param ui32Base is the base address of the uDMA port.
673 //! \param ui32ChannelNum is the channel to configure.
674 //! \param ui32Attr is a combination of attributes for the channel.
675 //! The parameter is the bitwise OR of any of the following:
676 //! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode.
677 //! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure
678 //! for this channel (it is very unlikely that this flag should be used).
679 //! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
680 //! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
681 //! peripheral for this channel.
682 //!
683 //! \return None
684 //
685 //*****************************************************************************
686 extern void uDMAChannelAttributeDisable(uint32_t ui32Base,
687 uint32_t ui32ChannelNum,
688 uint32_t ui32Attr);
689
690 //*****************************************************************************
691 //
692 //! \brief Gets the enabled attributes of a uDMA channel.
693 //!
694 //! This function returns a combination of flags representing the attributes of
695 //! the uDMA channel.
696 //!
697 //! \param ui32Base is the base address of the uDMA port.
698 //! \param ui32ChannelNum is the channel to configure.
699 //!
700 //! \return Returns the bitwise OR of the attributes of the uDMA channel, which
701 //! can be any of the following:
702 //! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode.
703 //! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure
704 //! for this channel (it is very unlikely that this flag should be used).
705 //! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
706 //! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
707 //! peripheral for this channel.
708 //
709 //*****************************************************************************
710 extern uint32_t uDMAChannelAttributeGet(uint32_t ui32Base,
711 uint32_t ui32ChannelNum);
712
713 //*****************************************************************************
714 //
715 //! \brief Sets the control parameters for a uDMA channel control structure.
716 //!
717 //! This function is used to set control parameters for a uDMA transfer. These
718 //! are typically parameters that are not changed often.
719 //!
720 //! \note The address increment cannot be smaller than the data size.
721 //!
722 //! \param ui32Base is the base address of the uDMA port.
723 //! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
724 //! - \ref UDMA_PRI_SELECT : Use primary data structure.
725 //! - \ref UDMA_ALT_SELECT : Use alternate data structure.
726 //! \param ui32Control is the bitwise OR of five values:
727 //! - Data size
728 //! - \ref UDMA_SIZE_8 : 8 bits.
729 //! - \ref UDMA_SIZE_16 : 16 bits.
730 //! - \ref UDMA_SIZE_32 : 32 bits.
731 //! - Source address increment
732 //! - \ref UDMA_SRC_INC_8 : 8 bits.
733 //! - \ref UDMA_SRC_INC_16 : 16 bits.
734 //! - \ref UDMA_SRC_INC_32 : 32 bits.
735 //! - \ref UDMA_SRC_INC_NONE : Non-incrementing.
736 //! - Destination address increment
737 //! - \ref UDMA_DST_INC_8 : 8 bits.
738 //! - \ref UDMA_DST_INC_16 : 16 bits.
739 //! - \ref UDMA_DST_INC_32 : 32 bits.
740 //! - \ref UDMA_DST_INC_NONE : Non-incrementing.
741 //! - Arbitration size. Determines how many items are transferred before
742 //! the uDMA controller re-arbitrates for the bus. In power of 2.
743 //! - \ref UDMA_ARB_1
744 //! - \ref UDMA_ARB_2
745 //! - \ref UDMA_ARB_4
746 //! - \ref UDMA_ARB_8
747 //! - ...
748 //! - \ref UDMA_ARB_1024
749 //! - Force the channel to only respond to burst requests at the tail end of a scatter-gather transfer.
750 //! - \ref UDMA_NEXT_USEBURST
751 //!
752 //! \return None
753 //
754 //*****************************************************************************
755 extern void uDMAChannelControlSet(uint32_t ui32Base,
756 uint32_t ui32ChannelStructIndex,
757 uint32_t ui32Control);
758
759 //*****************************************************************************
760 //
761 //! \brief Sets the transfer parameters for a uDMA channel control structure.
762 //!
763 //! This function is used to set the parameters for a uDMA transfer. These are
764 //! typically parameters that are changed often. The function
765 //! \ref uDMAChannelControlSet() MUST be called at least once for this channel prior
766 //! to calling this function.
767 //!
768 //! The \c pvSrcAddr and \c pvDstAddr parameters are pointers to the first
769 //! location of the data to be transferred. These addresses should be aligned
770 //! according to the item size. The compiler will take care of this if the
771 //! pointers are pointing to storage of the appropriate data type.
772 //!
773 //! The two scatter/gather modes, MEMORY and PERIPHERAL, are actually different
774 //! depending on whether the primary or alternate control structure is
775 //! selected. This function will look for the \ref UDMA_PRI_SELECT and
776 //! \ref UDMA_ALT_SELECT flag along with the channel number and will set the
777 //! scatter/gather mode as appropriate for the primary or alternate control
778 //! structure.
779 //!
780 //! The channel must also be enabled using \ref uDMAChannelEnable() after calling
781 //! this function. The transfer will not begin until the channel has been set
782 //! up and enabled. Note that the channel is automatically disabled after the
783 //! transfer is completed, meaning that \ref uDMAChannelEnable() must be called
784 //! again after setting up the next transfer.
785 //!
786 //! \note Great care must be taken to not modify a channel control structure
787 //! that is in use or else the results will be unpredictable, including the
788 //! possibility of undesired data transfers to or from memory or peripherals.
789 //! For BASIC and AUTO modes, it is safe to make changes when the channel is
790 //! disabled, or the \ref uDMAChannelModeGet() returns \ref UDMA_MODE_STOP. For
791 //! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the
792 //! primary or alternate control structure only when the other is being used.
793 //! The \ref uDMAChannelModeGet() function will return \ref UDMA_MODE_STOP when a
794 //! channel control structure is inactive and safe to modify.
795 //!
796 //! \param ui32Base is the base address of the uDMA port.
797 //! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
798 //! - \ref UDMA_PRI_SELECT : Use primary data structure.
799 //! - \ref UDMA_ALT_SELECT : Use alternate data structure.
800 //! \param ui32Mode is the type of uDMA transfer.
801 //! The parameter should be one of the following values:
802 //! - \ref UDMA_MODE_STOP : Stops the uDMA transfer. The controller sets the mode
803 //! to this value at the end of a transfer.
804 //! - \ref UDMA_MODE_BASIC : Perform a basic transfer based on request.
805 //! - \ref UDMA_MODE_AUTO to perform a transfer that will always complete once
806 //! started even if request is removed.
807 //! - \ref UDMA_MODE_PINGPONG : Set up a transfer that switches between the
808 //! primary and alternate control structures for the channel. This allows
809 //! use of ping-pong buffering for uDMA transfers.
810 //! - \ref UDMA_MODE_MEM_SCATTER_GATHER : Set up a memory scatter-gather transfer.
811 //! - \ref UDMA_MODE_PER_SCATTER_GATHER : Set up a peripheral scatter-gather transfer.
812 //! \param pvSrcAddr is the source address for the transfer.
813 //! \param pvDstAddr is the destination address for the transfer.
814 //! \param ui32TransferSize is the number of data items to transfer (\b NOT bytes).
815 //!
816 //! \return None
817 //
818 //*****************************************************************************
819 extern void uDMAChannelTransferSet(uint32_t ui32Base,
820 uint32_t ui32ChannelStructIndex,
821 uint32_t ui32Mode, void *pvSrcAddr,
822 void *pvDstAddr, uint32_t ui32TransferSize);
823
824 //*****************************************************************************
825 //
826 //! \brief Configures a uDMA channel for scatter-gather mode.
827 //!
828 //! This function is used to configure a channel for scatter-gather mode.
829 //! The caller must have already set up a task list, and pass a pointer to
830 //! the start of the task list as the \c pvTaskList parameter.
831 //!
832 //! The \c ui32TaskCount parameter is the count of tasks in the task list, not the
833 //! size of the task list.
834 //!
835 //! The flag \c bIsPeriphSG should be used to indicate
836 //! if the scatter-gather should be configured for a peripheral or memory
837 //! scatter-gather operation.
838 //!
839 //! \param ui32Base is the base address of the uDMA port.
840 //! \param ui32ChannelNum is the uDMA channel number.
841 //! \param ui32TaskCount is the number of scatter-gather tasks to execute.
842 //! \param pvTaskList is a pointer to the beginning of the scatter-gather
843 //! task list.
844 //! \param ui32IsPeriphSG is a flag to indicate it is a peripheral
845 //! scatter-gather transfer (else it will be memory scatter-gather transfer)
846 //!
847 //! \return None
848 //!
849 //! \sa \ref uDMATaskStructEntry()
850 //
851 //*****************************************************************************
852 extern void uDMAChannelScatterGatherSet(uint32_t ui32Base,
853 uint32_t ui32ChannelNum,
854 uint32_t ui32TaskCount,
855 void *pvTaskList,
856 uint32_t ui32IsPeriphSG);
857
858 //*****************************************************************************
859 //
860 //! \brief Gets the current transfer size for a uDMA channel control structure.
861 //!
862 //! This function is used to get the uDMA transfer size for a channel. The
863 //! transfer size is the number of items to transfer, where the size of an item
864 //! might be 8, 16, or 32 bits. If a partial transfer has already occurred,
865 //! then the number of remaining items will be returned. If the transfer is
866 //! complete, then 0 will be returned.
867 //!
868 //! \param ui32Base is the base address of the uDMA port.
869 //! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
870 //! - \ref UDMA_PRI_SELECT
871 //! - \ref UDMA_ALT_SELECT
872 //!
873 //! \return Returns the number of items remaining to transfer.
874 //
875 //*****************************************************************************
876 extern uint32_t uDMAChannelSizeGet(uint32_t ui32Base,
877 uint32_t ui32ChannelStructIndex);
878
879 //*****************************************************************************
880 //
881 //! \brief Gets the transfer mode for a uDMA channel control structure.
882 //!
883 //! This function is used to get the transfer mode for the uDMA channel. It
884 //! can be used to query the status of a transfer on a channel. When the
885 //! transfer is complete the mode will be \ref UDMA_MODE_STOP.
886 //!
887 //! \param ui32Base is the base address of the uDMA port.
888 //! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
889 //! - \ref UDMA_PRI_SELECT
890 //! - \ref UDMA_ALT_SELECT
891 //!
892 //! \return Returns the transfer mode of the specified channel and control
893 //! structure, which will be one of the following values:
894 //! - \ref UDMA_MODE_STOP
895 //! - \ref UDMA_MODE_BASIC
896 //! - \ref UDMA_MODE_AUTO
897 //! - \ref UDMA_MODE_PINGPONG
898 //! - \ref UDMA_MODE_MEM_SCATTER_GATHER
899 //! - \ref UDMA_MODE_PER_SCATTER_GATHER
900 //
901 //*****************************************************************************
902 extern uint32_t uDMAChannelModeGet(uint32_t ui32Base,
903 uint32_t ui32ChannelStructIndex);
904
905 //*****************************************************************************
906 //
907 //! \brief Registers an interrupt handler for the uDMA controller in the dynamic interrupt table.
908 //!
909 //! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
910 //!
911 //! This function registers a function as the interrupt handler for a specific
912 //! interrupt and enables the corresponding interrupt in the interrupt controller.
913 //!
914 //! \note The interrupt handler for uDMA is for transfer completion when the
915 //! software channel is used, and for error interrupts. The interrupts for each
916 //! peripheral channel are handled through the individual peripheral interrupt
917 //! handlers.
918 //!
919 //! \param ui32Base is the base address of the uDMA module.
920 //! \param ui32IntChannel specifies which uDMA interrupt is to be registered.
921 //! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts
922 //! from the uDMA software channel.
923 //! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error
924 //! interrupts.
925 //! \param pfnHandler is a pointer to the function to be called when the
926 //! interrupt is activated.
927 //!
928 //! \return None
929 //!
930 //! \sa \ref IntRegister() for important information about registering interrupt
931 //! handlers.
932 //
933 //*****************************************************************************
934 __STATIC_INLINE void
uDMAIntRegister(uint32_t ui32Base,uint32_t ui32IntChannel,void (* pfnHandler)(void))935 uDMAIntRegister(uint32_t ui32Base, uint32_t ui32IntChannel,
936 void (*pfnHandler)(void))
937 {
938 // Check the arguments.
939 ASSERT(uDMABaseValid(ui32Base));
940 ASSERT(pfnHandler);
941 ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR));
942
943 // Register the interrupt handler.
944 IntRegister(ui32IntChannel, pfnHandler);
945
946 // Enable the memory management fault.
947 IntEnable(ui32IntChannel);
948 }
949
950 //*****************************************************************************
951 //
952 //! \brief Unregisters an interrupt handler for the uDMA controller in the dynamic interrupt table.
953 //!
954 //! This function will disable and clear the handler to be called for the
955 //! specified uDMA interrupt.
956 //!
957 //! \param ui32Base is the base address of the uDMA module.
958 //! \param ui32IntChannel specifies which uDMA interrupt to unregister.
959 //! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts
960 //! from the uDMA software channel.
961 //! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error
962 //! interrupts.
963 //!
964 //! \return None
965 //!
966 //! \sa \ref IntRegister() for important information about registering interrupt
967 //! handlers.
968 //
969 //*****************************************************************************
970 __STATIC_INLINE void
uDMAIntUnregister(uint32_t ui32Base,uint32_t ui32IntChannel)971 uDMAIntUnregister(uint32_t ui32Base, uint32_t ui32IntChannel)
972 {
973 // Check the arguments.
974 ASSERT(uDMABaseValid(ui32Base));
975 ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR));
976
977 // Disable the interrupt.
978 IntDisable(ui32IntChannel);
979
980 // Unregister the interrupt handler.
981 IntUnregister(ui32IntChannel);
982 }
983
984 //*****************************************************************************
985 //
986 //! \brief Clears uDMA interrupt done status.
987 //!
988 //! Clears bits in the uDMA interrupt status register according to which bits
989 //! are set in \c ui32ChanMask. There is one bit for each channel. If a a bit
990 //! is set in \c ui32ChanMask, then that corresponding channel's interrupt
991 //! status will be cleared (if it was set).
992 //!
993 //! \param ui32Base is the base address of the uDMA port.
994 //! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel.
995 //!
996 //! \return None
997 //
998 //*****************************************************************************
999 __STATIC_INLINE void
uDMAIntClear(uint32_t ui32Base,uint32_t ui32ChanMask)1000 uDMAIntClear(uint32_t ui32Base, uint32_t ui32ChanMask)
1001 {
1002 // Check the arguments.
1003 ASSERT(uDMABaseValid(ui32Base));
1004
1005 // Clear the requested bits in the uDMA interrupt status register.
1006 HWREG(ui32Base + UDMA_O_REQDONE) = ui32ChanMask;
1007 }
1008
1009 //*****************************************************************************
1010 //
1011 //! \brief Get the uDMA interrupt status.
1012 //!
1013 //! This function returns the interrupt status for the specified UDMA. This
1014 //! function does not differentiate between software or hardware activated
1015 //! interrupts.
1016 //!
1017 //! \param ui32Base is the base address of the uDMA port.
1018 //!
1019 //! \return None
1020 //
1021 //*****************************************************************************
1022 __STATIC_INLINE uint32_t
uDMAIntStatus(uint32_t ui32Base)1023 uDMAIntStatus(uint32_t ui32Base)
1024 {
1025 // Check the arguments.
1026 ASSERT(uDMABaseValid(ui32Base));
1027
1028 // Return the uDMA interrupt status register.
1029 return (HWREG(ui32Base + UDMA_O_REQDONE));
1030 }
1031
1032 //*****************************************************************************
1033 //
1034 //! \brief Enable interrupt on software event driven uDMA transfers.
1035 //!
1036 //! \note The main purpose of this function is to prevent propagation of uDMA
1037 //! status signals to a peripheral, if a peripheral and a software event is
1038 //! sharing the uDMA channel. If it is desired to initiate a transfer by
1039 //! writing to a register inside the uDMA (this means a software driven
1040 //! channel), then the uDMA status signals propagation need to be blocked to
1041 //! the hardware peripherals.
1042 //!
1043 //! \param ui32Base is the base address of the uDMA port.
1044 //! \param ui32IntChannel identifies which uDMA interrupt to enable software
1045 //! interrupts for.
1046 //!
1047 //! \return None
1048 //
1049 //*****************************************************************************
1050 __STATIC_INLINE void
uDMAIntSwEventEnable(uint32_t ui32Base,uint32_t ui32IntChannel)1051 uDMAIntSwEventEnable(uint32_t ui32Base, uint32_t ui32IntChannel)
1052 {
1053 // Check the arguments.
1054 ASSERT(uDMABaseValid(ui32Base));
1055 ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS);
1056
1057 // Enable the channel.
1058 HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 1;
1059 }
1060
1061 //*****************************************************************************
1062 //
1063 //! \brief Disable interrupt on software event driven uDMA transfers.
1064 //!
1065 //! This register disables the blocking of the uDMA status signals propagation
1066 //! to the hardware peripheral connected to the uDMA on the \c ui32IntChannel.
1067 //!
1068 //! \param ui32Base is the base address of the uDMA port.
1069 //! \param ui32IntChannel identifies which uDMA interrupt to disable software
1070 //! interrupts for.
1071 //!
1072 //! \return None
1073 //!
1074 //! \sa \ref uDMAIntSwEventEnable()
1075 //
1076 //*****************************************************************************
1077 __STATIC_INLINE void
uDMAIntSwEventDisable(uint32_t ui32Base,uint32_t ui32IntChannel)1078 uDMAIntSwEventDisable(uint32_t ui32Base, uint32_t ui32IntChannel)
1079 {
1080 // Check the arguments.
1081 ASSERT(uDMABaseValid(ui32Base));
1082 ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS);
1083
1084 // Disable the SW channel.
1085 HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 0;
1086 }
1087
1088 //*****************************************************************************
1089 //
1090 //! \brief Return the status of the uDMA module.
1091 //!
1092 //! \note This status register cannot be read when the controller is in the reset state.
1093 //!
1094 //! \param ui32Base is the base address of the uDMA port.
1095 //!
1096 //! \return Current status of the uDMA module.
1097 //
1098 //*****************************************************************************
1099 __STATIC_INLINE uint32_t
uDMAGetStatus(uint32_t ui32Base)1100 uDMAGetStatus(uint32_t ui32Base)
1101 {
1102 // Check the arguments.
1103 ASSERT(uDMABaseValid(ui32Base));
1104
1105 // Read and return the status register.
1106 return HWREG(ui32Base + UDMA_O_STATUS);
1107 }
1108
1109 //*****************************************************************************
1110 //
1111 //! \brief Set the priority of a uDMA channel.
1112 //!
1113 //! \note Writing 0 to a bit has no effect on the priority. To reset a channel
1114 //! priority to the default value use \ref uDMAChannelPriorityClear().
1115 //!
1116 //! \param ui32Base is the base address of the uDMA port.
1117 //! \param ui32ChannelNum is uDMA channel to set the priority for.
1118 //!
1119 //! \return None
1120 //
1121 //*****************************************************************************
1122 __STATIC_INLINE void
uDMAChannelPrioritySet(uint32_t ui32Base,uint32_t ui32ChannelNum)1123 uDMAChannelPrioritySet(uint32_t ui32Base, uint32_t ui32ChannelNum)
1124 {
1125 // Check the arguments.
1126 ASSERT(uDMABaseValid(ui32Base));
1127 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
1128
1129 // Set the channel priority to high.
1130 HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum;
1131 }
1132
1133 //*****************************************************************************
1134 //
1135 //! \brief Get the priority of a uDMA channel.
1136 //!
1137 //! \param ui32Base is the base address of the uDMA port.
1138 //! \param ui32ChannelNum The uDMA channel to get the priority for.
1139 //!
1140 //! \return Returns one of:
1141 //! - \ref UDMA_PRIORITY_HIGH
1142 //! - \ref UDMA_PRIORITY_LOW
1143 //
1144 //*****************************************************************************
1145 __STATIC_INLINE bool
uDMAChannelPriorityGet(uint32_t ui32Base,uint32_t ui32ChannelNum)1146 uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum)
1147 {
1148 // Check the arguments.
1149 ASSERT(uDMABaseValid(ui32Base));
1150 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
1151
1152 // Return the channel priority.
1153 return(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ?
1154 UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW);
1155 }
1156
1157 //*****************************************************************************
1158 //
1159 //! \brief Clear the priority of a uDMA channel.
1160 //!
1161 //! \note Writing 0 to a bit has no effect on the priority. To set a channel
1162 //! priority to high use \ref uDMAChannelPrioritySet().
1163 //!
1164 //! \param ui32Base is the base address of the uDMA port.
1165 //! \param ui32ChannelNum The uDMA channel to clear the priority for.
1166 //!
1167 //! \return None
1168 //
1169 //*****************************************************************************
1170 __STATIC_INLINE void
uDMAChannelPriorityClear(uint32_t ui32Base,uint32_t ui32ChannelNum)1171 uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum)
1172 {
1173 // Check the arguments.
1174 ASSERT(uDMABaseValid(ui32Base));
1175 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
1176
1177 // Clear the channel priority.
1178 HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum;
1179 }
1180
1181 //*****************************************************************************
1182 //
1183 // Support for DriverLib in ROM:
1184 // Redirect to implementation in ROM when available.
1185 //
1186 //*****************************************************************************
1187 #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
1188 #include "../driverlib/rom.h"
1189 #ifdef ROM_uDMAChannelAttributeEnable
1190 #undef uDMAChannelAttributeEnable
1191 #define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable
1192 #endif
1193 #ifdef ROM_uDMAChannelAttributeDisable
1194 #undef uDMAChannelAttributeDisable
1195 #define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable
1196 #endif
1197 #ifdef ROM_uDMAChannelAttributeGet
1198 #undef uDMAChannelAttributeGet
1199 #define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet
1200 #endif
1201 #ifdef ROM_uDMAChannelControlSet
1202 #undef uDMAChannelControlSet
1203 #define uDMAChannelControlSet ROM_uDMAChannelControlSet
1204 #endif
1205 #ifdef ROM_uDMAChannelTransferSet
1206 #undef uDMAChannelTransferSet
1207 #define uDMAChannelTransferSet ROM_uDMAChannelTransferSet
1208 #endif
1209 #ifdef ROM_uDMAChannelScatterGatherSet
1210 #undef uDMAChannelScatterGatherSet
1211 #define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet
1212 #endif
1213 #ifdef ROM_uDMAChannelSizeGet
1214 #undef uDMAChannelSizeGet
1215 #define uDMAChannelSizeGet ROM_uDMAChannelSizeGet
1216 #endif
1217 #ifdef ROM_uDMAChannelModeGet
1218 #undef uDMAChannelModeGet
1219 #define uDMAChannelModeGet ROM_uDMAChannelModeGet
1220 #endif
1221 #endif
1222
1223 //*****************************************************************************
1224 //
1225 // Mark the end of the C bindings section for C++ compilers.
1226 //
1227 //*****************************************************************************
1228 #ifdef __cplusplus
1229 }
1230 #endif
1231
1232 #endif // __UDMA_H__
1233
1234 //*****************************************************************************
1235 //
1236 //! Close the Doxygen group.
1237 //! @}
1238 //! @}
1239 //
1240 //*****************************************************************************
1241