1 /****************************************************************************** 2 * Filename: hw_rfc_pwr_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_RFC_PWR_H__ 38 #define __HW_RFC_PWR_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // RFC_PWR component 44 // 45 //***************************************************************************** 46 // RF Core Power Management and Clock Enable 47 #define RFC_PWR_O_PWMCLKEN 0x00000000 48 49 //***************************************************************************** 50 // 51 // Register: RFC_PWR_O_PWMCLKEN 52 // 53 //***************************************************************************** 54 // Field: [10] RFCTRC 55 // 56 // Enable clock to the RF Core Tracer (RFCTRC) module. 57 #define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 58 #define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 59 #define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 60 #define RFC_PWR_PWMCLKEN_RFCTRC_S 10 61 62 // Field: [9] FSCA 63 // 64 // Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) 65 // module. 66 #define RFC_PWR_PWMCLKEN_FSCA 0x00000200 67 #define RFC_PWR_PWMCLKEN_FSCA_BITN 9 68 #define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 69 #define RFC_PWR_PWMCLKEN_FSCA_S 9 70 71 // Field: [8] PHA 72 // 73 // Enable clock to the Packet Handling Accelerator (PHA) module. 74 #define RFC_PWR_PWMCLKEN_PHA 0x00000100 75 #define RFC_PWR_PWMCLKEN_PHA_BITN 8 76 #define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 77 #define RFC_PWR_PWMCLKEN_PHA_S 8 78 79 // Field: [7] RAT 80 // 81 // Enable clock to the Radio Timer (RAT) module. 82 #define RFC_PWR_PWMCLKEN_RAT 0x00000080 83 #define RFC_PWR_PWMCLKEN_RAT_BITN 7 84 #define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 85 #define RFC_PWR_PWMCLKEN_RAT_S 7 86 87 // Field: [6] RFERAM 88 // 89 // Enable clock to the RF Engine RAM module. 90 #define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 91 #define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 92 #define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 93 #define RFC_PWR_PWMCLKEN_RFERAM_S 6 94 95 // Field: [5] RFE 96 // 97 // Enable clock to the RF Engine (RFE) module. 98 #define RFC_PWR_PWMCLKEN_RFE 0x00000020 99 #define RFC_PWR_PWMCLKEN_RFE_BITN 5 100 #define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 101 #define RFC_PWR_PWMCLKEN_RFE_S 5 102 103 // Field: [4] MDMRAM 104 // 105 // Enable clock to the Modem RAM module. 106 #define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 107 #define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 108 #define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 109 #define RFC_PWR_PWMCLKEN_MDMRAM_S 4 110 111 // Field: [3] MDM 112 // 113 // Enable clock to the Modem (MDM) module. 114 #define RFC_PWR_PWMCLKEN_MDM 0x00000008 115 #define RFC_PWR_PWMCLKEN_MDM_BITN 3 116 #define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 117 #define RFC_PWR_PWMCLKEN_MDM_S 3 118 119 // Field: [2] CPERAM 120 // 121 // Enable clock to the Command and Packet Engine (CPE) RAM module. As part of 122 // RF Core initialization, set this bit together with CPE bit to enable CPE to 123 // boot. 124 #define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 125 #define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 126 #define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 127 #define RFC_PWR_PWMCLKEN_CPERAM_S 2 128 129 // Field: [1] CPE 130 // 131 // Enable processor clock (hclk) to the Command and Packet Engine (CPE). As 132 // part of RF Core initialization, set this bit together with CPERAM bit to 133 // enable CPE to boot. 134 #define RFC_PWR_PWMCLKEN_CPE 0x00000002 135 #define RFC_PWR_PWMCLKEN_CPE_BITN 1 136 #define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 137 #define RFC_PWR_PWMCLKEN_CPE_S 1 138 139 // Field: [0] RFC 140 // 141 // Enable essential clocks for the RF Core interface. This includes the 142 // interconnect, the radio doorbell DBELL command interface, the power 143 // management (PWR) clock control module, and bus clock (sclk) for the CPE. To 144 // remove possibility of locking yourself out from the RF Core, this bit can 145 // not be cleared. If you need to disable all clocks to the RF Core, see the 146 // PRCM:RFCCLKG.CLK_EN register. 147 #define RFC_PWR_PWMCLKEN_RFC 0x00000001 148 #define RFC_PWR_PWMCLKEN_RFC_BITN 0 149 #define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 150 #define RFC_PWR_PWMCLKEN_RFC_S 0 151 152 153 #endif // __RFC_PWR__ 154
