1 /******************************************************************************
2 *  Filename:       udma.h
3 *  Revised:        2020-08-19 12:18:33 +0200 (Wed, 19 Aug 2020)
4 *  Revision:       58172
5 *
6 *  Description:    Defines and prototypes for the uDMA controller.
7 *
8 *  Copyright (c) 2015 - 2020, Texas Instruments Incorporated
9 *  All rights reserved.
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11 *  Redistribution and use in source and binary forms, with or without
12 *  modification, are permitted provided that the following conditions are met:
13 *
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15 *     this list of conditions and the following disclaimer.
16 *
17 *  2) Redistributions in binary form must reproduce the above copyright notice,
18 *     this list of conditions and the following disclaimer in the documentation
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21 *  3) Neither the name of the ORGANIZATION nor the names of its contributors may
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24 *
25 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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37 ******************************************************************************/
38 
39 //*****************************************************************************
40 //
41 //! \addtogroup peripheral_group
42 //! @{
43 //! \addtogroup udma_api
44 //! @{
45 //
46 //*****************************************************************************
47 
48 #ifndef __UDMA_H__
49 #define __UDMA_H__
50 
51 //*****************************************************************************
52 //
53 // If building with a C++ compiler, make all of the definitions in this header
54 // have a C binding.
55 //
56 //*****************************************************************************
57 #ifdef __cplusplus
58 extern "C"
59 {
60 #endif
61 
62 #include <stdbool.h>
63 #include <stdint.h>
64 #include "../inc/hw_types.h"
65 #include "../inc/hw_ints.h"
66 #include "../inc/hw_memmap.h"
67 #include "../inc/hw_udma.h"
68 #include "debug.h"
69 #include "interrupt.h"
70 
71 //*****************************************************************************
72 //
73 // Support for DriverLib in ROM:
74 // This section renames all functions that are not "static inline", so that
75 // calling these functions will default to implementation in flash. At the end
76 // of this file a second renaming will change the defaults to implementation in
77 // ROM for available functions.
78 //
79 // To force use of the implementation in flash, e.g. for debugging:
80 // - Globally: Define DRIVERLIB_NOROM at project level
81 // - Per function: Use prefix "NOROM_" when calling the function
82 //
83 //*****************************************************************************
84 #if !defined(DOXYGEN)
85     #define uDMAChannelAttributeEnable      NOROM_uDMAChannelAttributeEnable
86     #define uDMAChannelAttributeDisable     NOROM_uDMAChannelAttributeDisable
87     #define uDMAChannelAttributeGet         NOROM_uDMAChannelAttributeGet
88     #define uDMAChannelControlSet           NOROM_uDMAChannelControlSet
89     #define uDMAChannelTransferSet          NOROM_uDMAChannelTransferSet
90     #define uDMAChannelScatterGatherSet     NOROM_uDMAChannelScatterGatherSet
91     #define uDMAChannelSizeGet              NOROM_uDMAChannelSizeGet
92     #define uDMAChannelModeGet              NOROM_uDMAChannelModeGet
93 #endif
94 
95 //*****************************************************************************
96 //
97 //! \brief A structure that defines an entry in the channel control table.
98 //!
99 //! These fields are used by the uDMA controller and normally it is not necessary for
100 //! software to directly read or write fields in the table.
101 //
102 //*****************************************************************************
103 typedef struct
104 {
105     volatile void *pvSrcEndAddr;   //!< The ending source address of the data transfer.
106     volatile void *pvDstEndAddr;   //!< The ending destination address of the data transfer.
107     volatile uint32_t ui32Control; //!< The channel control mode.
108     volatile uint32_t ui32Spare;   //!< An unused location.
109 }
110 tDMAControlTable;
111 
112 //*****************************************************************************
113 //
114 //! \brief A helper macro for building scatter-gather task table entries.
115 //!
116 //! This macro is intended to be used to help populate a table of uDMA tasks
117 //! for a scatter-gather transfer. This macro will calculate the values for
118 //! the fields of a task structure entry based on the input parameters.
119 //!
120 //! There are specific requirements for the values of each parameter.  No
121 //! checking is done so it is up to the caller to ensure that correct values
122 //! are used for the parameters.
123 //!
124 //! This macro is intended to be used to initialize individual entries of
125 //! a structure of tDMAControlTable type, like this:
126 //!
127 /*!
128 \verbatim
129   tDMAControlTable MyTaskList[] =
130   {
131       uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
132                           UDMA_SRC_INC_8, MySourceBuf,
133                           UDMA_DST_INC_8, MyDestBuf,
134                           UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
135       uDMATaskStructEntry(Task2Count, ... ),
136   }
137 \endverbatim
138 */
139 //! \param ui32TransferCount is the count of items to transfer for this task.
140 //! It must be in the range 1-1024.
141 //! \param ui32ItemSize is the bit size of the items to transfer for this task.
142 //! It must be one of:
143 //! - \ref UDMA_SIZE_8
144 //! - \ref UDMA_SIZE_16
145 //! - \ref UDMA_SIZE_32
146 //! \param ui32SrcIncrement is the bit size increment for source data.
147 //! It must be one of:
148 //! - \ref UDMA_SRC_INC_8
149 //! - \ref UDMA_SRC_INC_16
150 //! - \ref UDMA_SRC_INC_32
151 //! - \ref UDMA_SRC_INC_NONE
152 //! \param pvSrcAddr is the starting address of the data to transfer.
153 //! \param ui32DstIncrement is the bit size increment for destination data.
154 //! It must be one of:
155 //! - \ref UDMA_DST_INC_8
156 //! - \ref UDMA_DST_INC_16
157 //! - \ref UDMA_DST_INC_32
158 //! - \ref UDMA_DST_INC_NONE
159 //! \param pvDstAddr is the starting address of the destination data.
160 //! \param ui32ArbSize is the arbitration size to use for the transfer task.
161 //! This is used to select the arbitration size in powers of 2, from 1 to 1024.
162 //! It must be one of:
163 //! - \ref UDMA_ARB_1
164 //! - \ref UDMA_ARB_2
165 //! - \ref UDMA_ARB_4
166 //! - ...
167 //! - \ref UDMA_ARB_1024
168 //! \param ui32Mode is the transfer mode for this task.
169 //! Note that normally all tasks will be one of the scatter-gather modes while the
170 //! last task is a task list will be AUTO or BASIC.
171 //! It must be one of:
172 //! - \ref UDMA_MODE_BASIC
173 //! - \ref UDMA_MODE_AUTO
174 //! - \ref UDMA_MODE_MEM_SCATTER_GATHER
175 //! - \ref UDMA_MODE_PER_SCATTER_GATHER
176 //!
177 //! \return None (this is not a function)
178 //
179 //*****************************************************************************
180 #define uDMATaskStructEntry(ui32TransferCount,                                \
181                             ui32ItemSize,                                     \
182                             ui32SrcIncrement,                                 \
183                             pvSrcAddr,                                        \
184                             ui32DstIncrement,                                 \
185                             pvDstAddr,                                        \
186                             ui32ArbSize,                                      \
187                             ui32Mode)                                         \
188     {                                                                         \
189         (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) :            \
190             ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) <<       \
191                                          ((ui32SrcIncrement) >> 26)) - 1]))), \
192         (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) :            \
193             ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) <<       \
194                                          ((ui32DstIncrement) >> 30)) - 1]))), \
195         (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) |            \
196         (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) |                    \
197         ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) ||                     \
198           ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ?                     \
199                 (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0            \
200     }
201 
202 //*****************************************************************************
203 //
204 // The hardware configured number of uDMA channels.
205 //
206 //*****************************************************************************
207 #define UDMA_NUM_CHANNELS       21
208 
209 //*****************************************************************************
210 //
211 // The level of priority for the uDMA channels
212 //
213 //*****************************************************************************
214 #define UDMA_PRIORITY_LOW       0x00000000
215 #define UDMA_PRIORITY_HIGH      0x00000001
216 
217 //*****************************************************************************
218 //
219 // Flags that can be passed to uDMAChannelAttributeEnable(),
220 // uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
221 //
222 //*****************************************************************************
223 #define UDMA_ATTR_USEBURST      0x00000001
224 #define UDMA_ATTR_ALTSELECT     0x00000002
225 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004
226 #define UDMA_ATTR_REQMASK       0x00000008
227 #define UDMA_ATTR_ALL           0x0000000F
228 
229 //*****************************************************************************
230 //
231 // DMA control modes that can be passed to uDMAChannelModeSet() and returned
232 // uDMAChannelModeGet().
233 //
234 //*****************************************************************************
235 #define UDMA_MODE_STOP          0x00000000
236 #define UDMA_MODE_BASIC         0x00000001
237 #define UDMA_MODE_AUTO          0x00000002
238 #define UDMA_MODE_PINGPONG      0x00000003
239 #define UDMA_MODE_MEM_SCATTER_GATHER                                          \
240                                 0x00000004
241 #define UDMA_MODE_PER_SCATTER_GATHER                                          \
242                                 0x00000006
243 #define UDMA_MODE_M             0x00000007  // uDMA Transfer Mode
244 #define UDMA_MODE_ALT_SELECT    0x00000001
245 
246 //*****************************************************************************
247 //
248 // Channel configuration values that can be passed to uDMAControlSet().
249 //
250 //*****************************************************************************
251 #define UDMA_DST_INC_8          0x00000000
252 #define UDMA_DST_INC_16         0x40000000
253 #define UDMA_DST_INC_32         0x80000000
254 #define UDMA_DST_INC_NONE       0xC0000000
255 #define UDMA_DST_INC_M          0xC0000000  // Destination Address Increment
256 #define UDMA_DST_INC_S          30
257 #define UDMA_SRC_INC_8          0x00000000
258 #define UDMA_SRC_INC_16         0x04000000
259 #define UDMA_SRC_INC_32         0x08000000
260 #define UDMA_SRC_INC_NONE       0x0c000000
261 #define UDMA_SRC_INC_M          0x0C000000  // Source Address Increment
262 #define UDMA_SRC_INC_S          26
263 #define UDMA_SIZE_8             0x00000000
264 #define UDMA_SIZE_16            0x11000000
265 #define UDMA_SIZE_32            0x22000000
266 #define UDMA_SIZE_M             0x33000000  // Data Size
267 #define UDMA_SIZE_S             24
268 #define UDMA_ARB_1              0x00000000
269 #define UDMA_ARB_2              0x00004000
270 #define UDMA_ARB_4              0x00008000
271 #define UDMA_ARB_8              0x0000c000
272 #define UDMA_ARB_16             0x00010000
273 #define UDMA_ARB_32             0x00014000
274 #define UDMA_ARB_64             0x00018000
275 #define UDMA_ARB_128            0x0001c000
276 #define UDMA_ARB_256            0x00020000
277 #define UDMA_ARB_512            0x00024000
278 #define UDMA_ARB_1024           0x00028000
279 #define UDMA_ARB_M              0x0003C000  // Arbitration Size
280 #define UDMA_ARB_S              14
281 #define UDMA_NEXT_USEBURST      0x00000008
282 #define UDMA_XFER_SIZE_MAX      1024
283 #define UDMA_XFER_SIZE_M        0x00003FF0  // Transfer size
284 #define UDMA_XFER_SIZE_S        4
285 
286 //*****************************************************************************
287 //
288 // Channel numbers to be passed to API functions that require a channel number
289 // ID.
290 //
291 //*****************************************************************************
292 #define UDMA_CHAN_SW_EVT0       0   // Software Event Channel 0
293 #define UDMA_CHAN_UART0_RX      1   // UART0 RX Data
294 #define UDMA_CHAN_UART0_TX      2   // UART0 RX Data
295 #define UDMA_CHAN_SSI0_RX       3   // SSI0 RX Data
296 #define UDMA_CHAN_SSI0_TX       4   // SSI0 RX Data
297 #define UDMA_CHAN_UART1_RX      5   // UART1 RX Data
298 #define UDMA_CHAN_UART1_TX      6   // UART1 Tx Data
299 #define UDMA_CHAN_AUX_ADC       7   // AUX ADC event
300 #define UDMA_CHAN_AUX_SW        8   // AUX Software event
301 #define UDMA_CHAN_TIMER0_A      9   // Timer0 A event
302 #define UDMA_CHAN_TIMER0_B      10  // Timer0 B event
303 #define UDMA_CHAN_TIMER1_A      11
304 #define UDMA_CHAN_TIMER1_B      12
305 #define UDMA_CHAN_AON_PROG2     13
306 #define UDMA_CHAN_DMA_PROG      14
307 #define UDMA_CHAN_AON_RTC       15
308 #define UDMA_CHAN_SSI1_RX       16
309 #define UDMA_CHAN_SSI1_TX       17
310 #define UDMA_CHAN_SW_EVT1       18
311 #define UDMA_CHAN_SW_EVT2       19
312 #define UDMA_CHAN_SW_EVT3       20
313 
314 //*****************************************************************************
315 //
316 // Flags to be OR'd with the channel ID to indicate if the primary or alternate
317 // control structure should be used.
318 //
319 //*****************************************************************************
320 #define UDMA_PRI_SELECT         0x00000000
321 #define UDMA_ALT_SELECT         0x00000020
322 
323 //*****************************************************************************
324 //
325 // API Functions and prototypes
326 //
327 //*****************************************************************************
328 
329 #ifdef DRIVERLIB_DEBUG
330 //*****************************************************************************
331 //
332 //! \internal
333 //!
334 //! \brief Checks a uDMA base address.
335 //!
336 //! This function determines if a uDMA module base address is valid.
337 //!
338 //! \param ui32Base specifies the uDMA module base address.
339 //!
340 //! \return Returns \c true if the base address is valid and \c false
341 //! otherwise.
342 //
343 //*****************************************************************************
344 static bool
uDMABaseValid(uint32_t ui32Base)345 uDMABaseValid(uint32_t ui32Base)
346 {
347     return(ui32Base == UDMA0_BASE);
348 }
349 #endif
350 
351 //*****************************************************************************
352 //
353 //! \brief Enables the uDMA controller for use.
354 //!
355 //! This function enables the uDMA controller. The uDMA controller must be
356 //! enabled before it can be configured and used.
357 //!
358 //! \param ui32Base is the base address of the uDMA port.
359 //!
360 //! \return None
361 //
362 //*****************************************************************************
363 __STATIC_INLINE void
uDMAEnable(uint32_t ui32Base)364 uDMAEnable(uint32_t ui32Base)
365 {
366     // Check the arguments.
367     ASSERT(uDMABaseValid(ui32Base));
368 
369     // Set the master enable bit in the config register.
370     HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE;
371 }
372 
373 //*****************************************************************************
374 //
375 //! \brief Disables the uDMA controller for use.
376 //!
377 //! This function disables the uDMA controller.  Once disabled, the uDMA
378 //! controller will not operate until re-enabled with \ref uDMAEnable().
379 //!
380 //! \param ui32Base is the base address of the uDMA port.
381 //!
382 //! \return None.
383 //
384 //*****************************************************************************
385 __STATIC_INLINE void
uDMADisable(uint32_t ui32Base)386 uDMADisable(uint32_t ui32Base)
387 {
388     // Check the arguments.
389     ASSERT(uDMABaseValid(ui32Base));
390 
391     // Clear the master enable bit in the config register.
392     HWREG(ui32Base + UDMA_O_CFG) = 0;
393 }
394 
395 //*****************************************************************************
396 //
397 //! \brief Gets the uDMA error status.
398 //!
399 //! This function returns the uDMA error status. It should be called from
400 //! within the uDMA error interrupt handler to determine if a uDMA error
401 //! occurred.
402 //!
403 //! \param ui32Base is the base address of the uDMA port.
404 //!
405 //! \return Returns non-zero if a uDMA error is pending.
406 //
407 //*****************************************************************************
408 __STATIC_INLINE uint32_t
uDMAErrorStatusGet(uint32_t ui32Base)409 uDMAErrorStatusGet(uint32_t ui32Base)
410 {
411     // Check the arguments.
412     ASSERT(uDMABaseValid(ui32Base));
413 
414     // Return the uDMA error status.
415     return(HWREG(ui32Base + UDMA_O_ERROR));
416 }
417 
418 //*****************************************************************************
419 //
420 //! \brief Clears the uDMA error interrupt.
421 //!
422 //! This function clears a pending uDMA error interrupt. It should be called
423 //! from within the uDMA error interrupt handler to clear the interrupt.
424 //!
425 //! \param ui32Base is the base address of the uDMA port.
426 //!
427 //! \return None
428 //
429 //*****************************************************************************
430 __STATIC_INLINE void
uDMAErrorStatusClear(uint32_t ui32Base)431 uDMAErrorStatusClear(uint32_t ui32Base)
432 {
433     // Check the arguments.
434     ASSERT(uDMABaseValid(ui32Base));
435 
436     // Clear the uDMA error interrupt.
437     HWREG(ui32Base + UDMA_O_ERROR) = UDMA_ERROR_STATUS;
438 }
439 
440 //*****************************************************************************
441 //
442 //! \brief Enables a uDMA channel for operation.
443 //!
444 //! This function enables a specific uDMA channel for use. This function must
445 //! be used to enable a channel before it can be used to perform a uDMA
446 //! transfer.
447 //!
448 //! When a uDMA transfer is completed, the channel will be automatically
449 //! disabled by the uDMA controller. Therefore, this function should be called
450 //! prior to starting up any new transfer.
451 //!
452 //! \param ui32Base is the base address of the uDMA port.
453 //! \param ui32ChannelNum is the channel number to enable.
454 //!
455 //! \return None
456 //
457 //*****************************************************************************
458 __STATIC_INLINE void
uDMAChannelEnable(uint32_t ui32Base,uint32_t ui32ChannelNum)459 uDMAChannelEnable(uint32_t ui32Base, uint32_t ui32ChannelNum)
460 {
461     // Check the arguments.
462     ASSERT(uDMABaseValid(ui32Base));
463     ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
464 
465     // Set the bit for this channel in the enable set register.
466     HWREG(ui32Base + UDMA_O_SETCHANNELEN) = 1 << ui32ChannelNum;
467 }
468 
469 //*****************************************************************************
470 //
471 //! \brief Disables a uDMA channel for operation.
472 //!
473 //! This function disables a specific uDMA channel. Once disabled, a channel
474 //! will not respond to uDMA transfer requests until re-enabled via
475 //! \ref uDMAChannelEnable().
476 //!
477 //! \param ui32Base is the base address of the uDMA port.
478 //! \param ui32ChannelNum is the channel number to disable.
479 //!
480 //! \return None.
481 //
482 //*****************************************************************************
483 __STATIC_INLINE void
uDMAChannelDisable(uint32_t ui32Base,uint32_t ui32ChannelNum)484 uDMAChannelDisable(uint32_t ui32Base, uint32_t ui32ChannelNum)
485 {
486     // Check the arguments.
487     ASSERT(uDMABaseValid(ui32Base));
488     ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
489 
490     // Set the bit for this channel in the enable clear register.
491     HWREG(ui32Base + UDMA_O_CLEARCHANNELEN) = 1 << ui32ChannelNum;
492 }
493 
494 //*****************************************************************************
495 //
496 //! \brief Checks if a uDMA channel is enabled for operation.
497 //!
498 //! This function checks to see if a specific uDMA channel is enabled.  This
499 //! can be used to check the status of a transfer, since the channel will
500 //! be automatically disabled at the end of a transfer.
501 //!
502 //! \param ui32Base is the base address of the uDMA port.
503 //! \param ui32ChannelNum is the channel number to check.
504 //!
505 //! \return Returns status of uDMA channel.
506 //! - \c true  : Channel is enabled.
507 //! - \c false : Disabled.
508 //
509 //*****************************************************************************
510 __STATIC_INLINE bool
uDMAChannelIsEnabled(uint32_t ui32Base,uint32_t ui32ChannelNum)511 uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum)
512 {
513     // Check the arguments.
514     ASSERT(uDMABaseValid(ui32Base));
515     ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
516 
517     // AND the specified channel bit with the enable register, and return the
518     // result.
519     return((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ?
520            true : false);
521 }
522 
523 //*****************************************************************************
524 //
525 //! \brief Sets the base address for the channel control table.
526 //!
527 //! This function sets the base address of the channel control table. This
528 //! table resides in system memory and holds control information for each uDMA
529 //! channel.  The table must be aligned on a 1024 byte boundary. The base
530 //! address must be set before any of the channel functions can be used.
531 //! Setting the base address of the primary control table will automatically
532 //! set the address for the alternate control table as the next memory
533 //! location after the primary control table.
534 //!
535 //! The size of the channel control table depends on the number of uDMA
536 //! channels, and which transfer modes are used.  Refer to the introductory
537 //! text and the microcontroller datasheet for more information about the
538 //! channel control table.
539 //!
540 //! \note This register cannot be read when the controller is in the reset
541 //! state.
542 //!
543 //! \param ui32Base is the base address of the uDMA port.
544 //! \param pControlTable is a pointer to the 1024 byte aligned base address
545 //! of the uDMA channel control table. The address must be an absolute address
546 //! in system memory space.
547 //!
548 //! \return None
549 //
550 //*****************************************************************************
551 __STATIC_INLINE void
uDMAControlBaseSet(uint32_t ui32Base,void * pControlTable)552 uDMAControlBaseSet(uint32_t ui32Base, void *pControlTable)
553 {
554     // Check the arguments.
555     ASSERT(uDMABaseValid(ui32Base));
556     ASSERT(((uint32_t)pControlTable & ~0x3FF) ==
557            (uint32_t)pControlTable);
558     ASSERT((uint32_t)pControlTable >= SRAM_BASE);
559 
560     // Program the base address into the register.
561     HWREG(ui32Base + UDMA_O_CTRL) = (uint32_t)pControlTable;
562 }
563 
564 //*****************************************************************************
565 //
566 //! \brief Gets the base address for the channel control table.
567 //!
568 //! This function gets the base address of the channel control table.  This
569 //! table resides in system memory and holds control information for each uDMA
570 //! channel.
571 //!
572 //! \param ui32Base is the base address of the uDMA port.
573 //!
574 //! \return Returns a pointer to the base address of the channel control table.
575 //
576 //*****************************************************************************
577 __STATIC_INLINE void *
uDMAControlBaseGet(uint32_t ui32Base)578 uDMAControlBaseGet(uint32_t ui32Base)
579 {
580     // Check the arguments.
581 
582     ASSERT(uDMABaseValid(ui32Base));
583     // Read the current value of the control base register, and return it to
584     // the caller.
585     return((void *)HWREG(ui32Base + UDMA_O_CTRL));
586 }
587 
588 //*****************************************************************************
589 //
590 //! \brief Gets the base address for the channel control table alternate structures.
591 //!
592 //! This function gets the base address of the second half of the channel
593 //! control table that holds the alternate control structures for each channel.
594 //!
595 //! \param ui32Base is the base address of the uDMA port.
596 //!
597 //! \return Returns a pointer to the base address of the second half of the
598 //! channel control table.
599 //
600 //*****************************************************************************
601 __STATIC_INLINE void *
uDMAControlAlternateBaseGet(uint32_t ui32Base)602 uDMAControlAlternateBaseGet(uint32_t ui32Base)
603 {
604     // Check the arguments.
605     ASSERT(uDMABaseValid(ui32Base));
606 
607     // Read the current value of the control base register, and return it to
608     // the caller.
609     return((void *)HWREG(ui32Base + UDMA_O_ALTCTRL));
610 }
611 
612 //*****************************************************************************
613 //
614 //! \brief Requests a uDMA channel to start a transfer.
615 //!
616 //! This function allows software to request a uDMA channel to begin a
617 //! transfer. This could be used for performing a memory to memory transfer,
618 //! or if for some reason a transfer needs to be initiated by software instead
619 //! of the peripheral associated with that channel.
620 //!
621 //! \note If the channel is a software channel and interrupts are used, then
622 //! the completion will be signaled on the uDMA dedicated interrupt. If a
623 //! peripheral channel is used, then the completion will be signaled on the
624 //! peripheral's interrupt.
625 //!
626 //! \param ui32Base is the base address of the uDMA port.
627 //! \param ui32ChannelNum is the channel number on which to request a uDMA
628 //! transfer.
629 //!
630 //! \return None.
631 //
632 //*****************************************************************************
633 __STATIC_INLINE void
uDMAChannelRequest(uint32_t ui32Base,uint32_t ui32ChannelNum)634 uDMAChannelRequest(uint32_t ui32Base, uint32_t ui32ChannelNum)
635 {
636     // Check the arguments.
637     ASSERT(uDMABaseValid(ui32Base));
638     ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
639 
640     // Set the bit for this channel in the software uDMA request register.
641     HWREG(ui32Base + UDMA_O_SOFTREQ) = 1 << ui32ChannelNum;
642 }
643 
644 //*****************************************************************************
645 //
646 //! \brief Enables attributes of a uDMA channel.
647 //!
648 //! This function is used to enable attributes of a uDMA channel.
649 //!
650 //! \param ui32Base is the base address of the uDMA port.
651 //! \param ui32ChannelNum is the channel to configure.
652 //! \param ui32Attr is a combination of attributes for the channel.
653 //! The parameter is the bitwise OR of any of the following:
654 //! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode.
655 //! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure
656 //! for this channel (it is very unlikely that this flag should be used).
657 //! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
658 //! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
659 //! peripheral for this channel.
660 //!
661 //! \return None
662 //
663 //*****************************************************************************
664 extern void uDMAChannelAttributeEnable(uint32_t ui32Base,
665                                        uint32_t ui32ChannelNum,
666                                        uint32_t ui32Attr);
667 
668 //*****************************************************************************
669 //
670 //! \brief Disables attributes of an uDMA channel.
671 //!
672 //! This function is used to disable attributes of a uDMA channel.
673 //!
674 //! \param ui32Base is the base address of the uDMA port.
675 //! \param ui32ChannelNum is the channel to configure.
676 //! \param ui32Attr is a combination of attributes for the channel.
677 //! The parameter is the bitwise OR of any of the following:
678 //! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode.
679 //! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure
680 //! for this channel (it is very unlikely that this flag should be used).
681 //! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
682 //! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
683 //! peripheral for this channel.
684 //!
685 //! \return None
686 //
687 //*****************************************************************************
688 extern void uDMAChannelAttributeDisable(uint32_t ui32Base,
689                                         uint32_t ui32ChannelNum,
690                                         uint32_t ui32Attr);
691 
692 //*****************************************************************************
693 //
694 //! \brief Gets the enabled attributes of a uDMA channel.
695 //!
696 //! This function returns a combination of flags representing the attributes of
697 //! the uDMA channel.
698 //!
699 //! \param ui32Base is the base address of the uDMA port.
700 //! \param ui32ChannelNum is the channel to configure.
701 //!
702 //! \return Returns the bitwise OR of the attributes of the uDMA channel, which
703 //! can be any of the following:
704 //! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode.
705 //! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure
706 //! for this channel (it is very unlikely that this flag should be used).
707 //! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
708 //! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
709 //! peripheral for this channel.
710 //
711 //*****************************************************************************
712 extern uint32_t uDMAChannelAttributeGet(uint32_t ui32Base,
713                                         uint32_t ui32ChannelNum);
714 
715 //*****************************************************************************
716 //
717 //! \brief Sets the control parameters for a uDMA channel control structure.
718 //!
719 //! This function is used to set control parameters for a uDMA transfer.  These
720 //! are typically parameters that are not changed often.
721 //!
722 //! \note The address increment cannot be smaller than the data size.
723 //!
724 //! \param ui32Base is the base address of the uDMA port.
725 //! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
726 //! - \ref UDMA_PRI_SELECT : Use primary data structure.
727 //! - \ref UDMA_ALT_SELECT : Use alternate data structure.
728 //! \param ui32Control is the bitwise OR of five values:
729 //! - Data size
730 //!   - \ref UDMA_SIZE_8  : 8 bits.
731 //!   - \ref UDMA_SIZE_16 : 16 bits.
732 //!   - \ref UDMA_SIZE_32 : 32 bits.
733 //! - Source address increment
734 //!   - \ref UDMA_SRC_INC_8    : 8 bits.
735 //!   - \ref UDMA_SRC_INC_16   : 16 bits.
736 //!   - \ref UDMA_SRC_INC_32   : 32 bits.
737 //!   - \ref UDMA_SRC_INC_NONE : Non-incrementing.
738 //! - Destination address increment
739 //!   - \ref UDMA_DST_INC_8    : 8 bits.
740 //!   - \ref UDMA_DST_INC_16   : 16 bits.
741 //!   - \ref UDMA_DST_INC_32   : 32 bits.
742 //!   - \ref UDMA_DST_INC_NONE : Non-incrementing.
743 //! - Arbitration size. Determines how many items are transferred before
744 //! the uDMA controller re-arbitrates for the bus. In power of 2.
745 //!   - \ref UDMA_ARB_1
746 //!   - \ref UDMA_ARB_2
747 //!   - \ref UDMA_ARB_4
748 //!   - \ref UDMA_ARB_8
749 //!   - ...
750 //!   - \ref UDMA_ARB_1024
751 //! - Force the channel to only respond to burst requests at the tail end of a scatter-gather transfer.
752 //!   - \ref UDMA_NEXT_USEBURST
753 //!
754 //! \return None
755 //
756 //*****************************************************************************
757 extern void uDMAChannelControlSet(uint32_t ui32Base,
758                                   uint32_t ui32ChannelStructIndex,
759                                   uint32_t ui32Control);
760 
761 //*****************************************************************************
762 //
763 //! \brief Sets the transfer parameters for a uDMA channel control structure.
764 //!
765 //! This function is used to set the parameters for a uDMA transfer.  These are
766 //! typically parameters that are changed often. The function
767 //! \ref uDMAChannelControlSet() MUST be called at least once for this channel prior
768 //! to calling this function.
769 //!
770 //! The \c pvSrcAddr and \c pvDstAddr parameters are pointers to the first
771 //! location of the data to be transferred. These addresses should be aligned
772 //! according to the item size. The compiler will take care of this if the
773 //! pointers are pointing to storage of the appropriate data type.
774 //!
775 //! The two scatter/gather modes, MEMORY and PERIPHERAL, are actually different
776 //! depending on whether the primary or alternate control structure is
777 //! selected. This function will look for the \ref UDMA_PRI_SELECT and
778 //! \ref UDMA_ALT_SELECT flag along with the channel number and will set the
779 //! scatter/gather mode as appropriate for the primary or alternate control
780 //! structure.
781 //!
782 //! The channel must also be enabled using \ref uDMAChannelEnable() after calling
783 //! this function. The transfer will not begin until the channel has been set
784 //! up and enabled. Note that the channel is automatically disabled after the
785 //! transfer is completed, meaning that \ref uDMAChannelEnable() must be called
786 //! again after setting up the next transfer.
787 //!
788 //! \note Great care must be taken to not modify a channel control structure
789 //! that is in use or else the results will be unpredictable, including the
790 //! possibility of undesired data transfers to or from memory or peripherals.
791 //! For BASIC and AUTO modes, it is safe to make changes when the channel is
792 //! disabled, or the \ref uDMAChannelModeGet() returns \ref UDMA_MODE_STOP. For
793 //! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the
794 //! primary or alternate control structure only when the other is being used.
795 //! The \ref uDMAChannelModeGet() function will return \ref UDMA_MODE_STOP when a
796 //! channel control structure is inactive and safe to modify.
797 //!
798 //! \param ui32Base is the base address of the uDMA port.
799 //! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
800 //! - \ref UDMA_PRI_SELECT : Use primary data structure.
801 //! - \ref UDMA_ALT_SELECT : Use alternate data structure.
802 //! \param ui32Mode is the type of uDMA transfer.
803 //! The parameter should be one of the following values:
804 //! - \ref UDMA_MODE_STOP     : Stops the uDMA transfer. The controller sets the mode
805 //! to this value at the end of a transfer.
806 //! - \ref UDMA_MODE_BASIC    : Perform a basic transfer based on request.
807 //! - \ref UDMA_MODE_AUTO to perform a transfer that will always complete once
808 //! started even if request is removed.
809 //! - \ref UDMA_MODE_PINGPONG : Set up a transfer that switches between the
810 //! primary and alternate control structures for the channel. This allows
811 //! use of ping-pong buffering for uDMA transfers.
812 //! - \ref UDMA_MODE_MEM_SCATTER_GATHER : Set up a memory scatter-gather transfer.
813 //! - \ref UDMA_MODE_PER_SCATTER_GATHER : Set up a peripheral scatter-gather transfer.
814 //! \param pvSrcAddr is the source address for the transfer.
815 //! \param pvDstAddr is the destination address for the transfer.
816 //! \param ui32TransferSize is the number of data items to transfer (\b NOT bytes).
817 //!
818 //! \return None
819 //
820 //*****************************************************************************
821 extern void uDMAChannelTransferSet(uint32_t ui32Base,
822                                    uint32_t ui32ChannelStructIndex,
823                                    uint32_t ui32Mode, void *pvSrcAddr,
824                                    void *pvDstAddr, uint32_t ui32TransferSize);
825 
826 //*****************************************************************************
827 //
828 //! \brief Configures a uDMA channel for scatter-gather mode.
829 //!
830 //! This function is used to configure a channel for scatter-gather mode.
831 //! The caller must have already set up a task list, and pass a pointer to
832 //! the start of the task list as the \c pvTaskList parameter.
833 //!
834 //! The \c ui32TaskCount parameter is the count of tasks in the task list, not the
835 //! size of the task list.
836 //!
837 //! The flag \c bIsPeriphSG should be used to indicate
838 //! if the scatter-gather should be configured for a peripheral or memory
839 //! scatter-gather operation.
840 //!
841 //! \param ui32Base is the base address of the uDMA port.
842 //! \param ui32ChannelNum is the uDMA channel number.
843 //! \param ui32TaskCount is the number of scatter-gather tasks to execute.
844 //! \param pvTaskList is a pointer to the beginning of the scatter-gather
845 //! task list.
846 //! \param ui32IsPeriphSG is a flag to indicate it is a peripheral
847 //! scatter-gather transfer (else it will be memory scatter-gather transfer)
848 //!
849 //! \return None
850 //!
851 //! \sa \ref uDMATaskStructEntry()
852 //
853 //*****************************************************************************
854 extern void uDMAChannelScatterGatherSet(uint32_t ui32Base,
855                                         uint32_t ui32ChannelNum,
856                                         uint32_t ui32TaskCount,
857                                         void *pvTaskList,
858                                         uint32_t ui32IsPeriphSG);
859 
860 //*****************************************************************************
861 //
862 //! \brief Gets the current transfer size for a uDMA channel control structure.
863 //!
864 //! This function is used to get the uDMA transfer size for a channel. The
865 //! transfer size is the number of items to transfer, where the size of an item
866 //! might be 8, 16, or 32 bits. If a partial transfer has already occurred,
867 //! then the number of remaining items will be returned. If the transfer is
868 //! complete, then 0 will be returned.
869 //!
870 //! \param ui32Base is the base address of the uDMA port.
871 //! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
872 //! - \ref UDMA_PRI_SELECT
873 //! - \ref UDMA_ALT_SELECT
874 //!
875 //! \return Returns the number of items remaining to transfer.
876 //
877 //*****************************************************************************
878 extern uint32_t uDMAChannelSizeGet(uint32_t ui32Base,
879                                    uint32_t ui32ChannelStructIndex);
880 
881 //*****************************************************************************
882 //
883 //! \brief Gets the transfer mode for a uDMA channel control structure.
884 //!
885 //! This function is used to get the transfer mode for the uDMA channel. It
886 //! can be used to query the status of a transfer on a channel. When the
887 //! transfer is complete the mode will be \ref UDMA_MODE_STOP.
888 //!
889 //! \param ui32Base is the base address of the uDMA port.
890 //! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
891 //! - \ref UDMA_PRI_SELECT
892 //! - \ref UDMA_ALT_SELECT
893 //!
894 //! \return Returns the transfer mode of the specified channel and control
895 //! structure, which will be one of the following values:
896 //! - \ref UDMA_MODE_STOP
897 //! - \ref UDMA_MODE_BASIC
898 //! - \ref UDMA_MODE_AUTO
899 //! - \ref UDMA_MODE_PINGPONG
900 //! - \ref UDMA_MODE_MEM_SCATTER_GATHER
901 //! - \ref UDMA_MODE_PER_SCATTER_GATHER
902 //
903 //*****************************************************************************
904 extern uint32_t uDMAChannelModeGet(uint32_t ui32Base,
905                                    uint32_t ui32ChannelStructIndex);
906 
907 //*****************************************************************************
908 //
909 //! \brief Registers an interrupt handler for the uDMA controller in the dynamic interrupt table.
910 //!
911 //! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
912 //!
913 //! This function registers a function as the interrupt handler for a specific
914 //! interrupt and enables the corresponding interrupt in the interrupt controller.
915 //!
916 //! \note The interrupt handler for uDMA is for transfer completion when the
917 //! software channel is used, and for error interrupts. The interrupts for each
918 //! peripheral channel are handled through the individual peripheral interrupt
919 //! handlers.
920 //!
921 //! \param ui32Base is the base address of the uDMA module.
922 //! \param ui32IntChannel specifies which uDMA interrupt is to be registered.
923 //! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts
924 //!   from the uDMA software channel.
925 //! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error
926 //!   interrupts.
927 //! \param pfnHandler is a pointer to the function to be called when the
928 //! interrupt is activated.
929 //!
930 //! \return None
931 //!
932 //! \sa \ref IntRegister() for important information about registering interrupt
933 //! handlers.
934 //
935 //*****************************************************************************
936 __STATIC_INLINE void
uDMAIntRegister(uint32_t ui32Base,uint32_t ui32IntChannel,void (* pfnHandler)(void))937 uDMAIntRegister(uint32_t ui32Base, uint32_t ui32IntChannel,
938                 void (*pfnHandler)(void))
939 {
940     // Check the arguments.
941     ASSERT(uDMABaseValid(ui32Base));
942     ASSERT(pfnHandler);
943     ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR));
944 
945     // Register the interrupt handler.
946     IntRegister(ui32IntChannel, pfnHandler);
947 
948     // Enable the memory management fault.
949     IntEnable(ui32IntChannel);
950 }
951 
952 //*****************************************************************************
953 //
954 //! \brief Unregisters an interrupt handler for the uDMA controller in the dynamic interrupt table.
955 //!
956 //! This function will disable and clear the handler to be called for the
957 //! specified uDMA interrupt.
958 //!
959 //! \param ui32Base is the base address of the uDMA module.
960 //! \param ui32IntChannel specifies which uDMA interrupt to unregister.
961 //! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts
962 //!   from the uDMA software channel.
963 //! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error
964 //!   interrupts.
965 //!
966 //! \return None
967 //!
968 //! \sa \ref IntRegister() for important information about registering interrupt
969 //! handlers.
970 //
971 //*****************************************************************************
972 __STATIC_INLINE void
uDMAIntUnregister(uint32_t ui32Base,uint32_t ui32IntChannel)973 uDMAIntUnregister(uint32_t ui32Base, uint32_t ui32IntChannel)
974 {
975     // Check the arguments.
976     ASSERT(uDMABaseValid(ui32Base));
977     ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR));
978 
979     // Disable the interrupt.
980     IntDisable(ui32IntChannel);
981 
982     // Unregister the interrupt handler.
983     IntUnregister(ui32IntChannel);
984 }
985 
986 //*****************************************************************************
987 //
988 //! \brief Clears uDMA interrupt done status.
989 //!
990 //! Clears bits in the uDMA interrupt status register according to which bits
991 //! are set in \c ui32ChanMask. There is one bit for each channel. If a a bit
992 //! is set in \c ui32ChanMask, then that corresponding channel's interrupt
993 //! status will be cleared (if it was set).
994 //!
995 //! \param ui32Base is the base address of the uDMA port.
996 //! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel.
997 //!
998 //! \return None
999 //
1000 //*****************************************************************************
1001 __STATIC_INLINE void
uDMAIntClear(uint32_t ui32Base,uint32_t ui32ChanMask)1002 uDMAIntClear(uint32_t ui32Base, uint32_t ui32ChanMask)
1003 {
1004     // Check the arguments.
1005     ASSERT(uDMABaseValid(ui32Base));
1006 
1007     // Clear the requested bits in the uDMA interrupt status register.
1008     HWREG(ui32Base + UDMA_O_REQDONE) = ui32ChanMask;
1009 }
1010 
1011 //*****************************************************************************
1012 //
1013 //! \brief Get the uDMA interrupt status.
1014 //!
1015 //! This function returns the interrupt status for the specified UDMA. This
1016 //! function does not differentiate between software or hardware activated
1017 //! interrupts.
1018 //!
1019 //! \param ui32Base is the base address of the uDMA port.
1020 //!
1021 //! \return None
1022 //
1023 //*****************************************************************************
1024 __STATIC_INLINE uint32_t
uDMAIntStatus(uint32_t ui32Base)1025 uDMAIntStatus(uint32_t ui32Base)
1026 {
1027     // Check the arguments.
1028     ASSERT(uDMABaseValid(ui32Base));
1029 
1030     // Return the uDMA interrupt status register.
1031     return (HWREG(ui32Base + UDMA_O_REQDONE));
1032 }
1033 
1034 //*****************************************************************************
1035 //
1036 //! \brief Enable interrupt on software event driven uDMA transfers.
1037 //!
1038 //! \note The main purpose of this function is to prevent propagation of uDMA
1039 //! status signals to a peripheral, if a peripheral and a software event is
1040 //! sharing the uDMA channel. If it is desired to initiate a transfer by
1041 //! writing to a register inside the uDMA (this means a software driven
1042 //! channel), then the uDMA status signals propagation need to be blocked to
1043 //! the hardware peripherals.
1044 //!
1045 //! \param ui32Base is the base address of the uDMA port.
1046 //! \param ui32IntChannel identifies which uDMA interrupt to enable software
1047 //!        interrupts for.
1048 //!
1049 //! \return None
1050 //
1051 //*****************************************************************************
1052 __STATIC_INLINE void
uDMAIntSwEventEnable(uint32_t ui32Base,uint32_t ui32IntChannel)1053 uDMAIntSwEventEnable(uint32_t ui32Base, uint32_t ui32IntChannel)
1054 {
1055     // Check the arguments.
1056     ASSERT(uDMABaseValid(ui32Base));
1057     ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS);
1058 
1059     // Enable the channel.
1060     HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 1;
1061 }
1062 
1063 //*****************************************************************************
1064 //
1065 //! \brief Disable interrupt on software event driven uDMA transfers.
1066 //!
1067 //! This register disables the blocking of the uDMA status signals propagation
1068 //! to the hardware peripheral connected to the uDMA on the \c ui32IntChannel.
1069 //!
1070 //! \param ui32Base is the base address of the uDMA port.
1071 //! \param ui32IntChannel identifies which uDMA interrupt to disable software
1072 //!        interrupts for.
1073 //!
1074 //! \return None
1075 //!
1076 //! \sa \ref uDMAIntSwEventEnable()
1077 //
1078 //*****************************************************************************
1079 __STATIC_INLINE void
uDMAIntSwEventDisable(uint32_t ui32Base,uint32_t ui32IntChannel)1080 uDMAIntSwEventDisable(uint32_t ui32Base, uint32_t ui32IntChannel)
1081 {
1082     // Check the arguments.
1083     ASSERT(uDMABaseValid(ui32Base));
1084     ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS);
1085 
1086     // Disable the SW channel.
1087     HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 0;
1088 }
1089 
1090 //*****************************************************************************
1091 //
1092 //! \brief Return the status of the uDMA module.
1093 //!
1094 //! \note This status register cannot be read when the controller is in the reset state.
1095 //!
1096 //! \param ui32Base is the base address of the uDMA port.
1097 //!
1098 //! \return Current status of the uDMA module.
1099 //
1100 //*****************************************************************************
1101 __STATIC_INLINE uint32_t
uDMAGetStatus(uint32_t ui32Base)1102 uDMAGetStatus(uint32_t ui32Base)
1103 {
1104     // Check the arguments.
1105     ASSERT(uDMABaseValid(ui32Base));
1106 
1107     // Read and return the status register.
1108     return HWREG(ui32Base + UDMA_O_STATUS);
1109 }
1110 
1111 //*****************************************************************************
1112 //
1113 //! \brief Set the priority of a uDMA channel.
1114 //!
1115 //! \note Writing 0 to a bit has no effect on the priority. To reset a channel
1116 //! priority to the default value use \ref uDMAChannelPriorityClear().
1117 //!
1118 //! \param ui32Base is the base address of the uDMA port.
1119 //! \param ui32ChannelNum is uDMA channel to set the priority for.
1120 //!
1121 //! \return None
1122 //
1123 //*****************************************************************************
1124 __STATIC_INLINE void
uDMAChannelPrioritySet(uint32_t ui32Base,uint32_t ui32ChannelNum)1125 uDMAChannelPrioritySet(uint32_t ui32Base, uint32_t ui32ChannelNum)
1126 {
1127     // Check the arguments.
1128     ASSERT(uDMABaseValid(ui32Base));
1129     ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
1130 
1131     // Set the channel priority to high.
1132     HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum;
1133 }
1134 
1135 //*****************************************************************************
1136 //
1137 //! \brief Get the priority of a uDMA channel.
1138 //!
1139 //! \param ui32Base is the base address of the uDMA port.
1140 //! \param ui32ChannelNum The uDMA channel to get the priority for.
1141 //!
1142 //! \return Returns one of:
1143 //! - \ref UDMA_PRIORITY_HIGH
1144 //! - \ref UDMA_PRIORITY_LOW
1145 //
1146 //*****************************************************************************
1147 __STATIC_INLINE bool
uDMAChannelPriorityGet(uint32_t ui32Base,uint32_t ui32ChannelNum)1148 uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum)
1149 {
1150     // Check the arguments.
1151     ASSERT(uDMABaseValid(ui32Base));
1152     ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
1153 
1154     // Return the channel priority.
1155     return(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ?
1156            UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW);
1157 }
1158 
1159 //*****************************************************************************
1160 //
1161 //! \brief Clear the priority of a uDMA channel.
1162 //!
1163 //! \note Writing 0 to a bit has no effect on the priority. To set a channel
1164 //! priority to high use \ref uDMAChannelPrioritySet().
1165 //!
1166 //! \param ui32Base is the base address of the uDMA port.
1167 //! \param ui32ChannelNum The uDMA channel to clear the priority for.
1168 //!
1169 //! \return None
1170 //
1171 //*****************************************************************************
1172 __STATIC_INLINE void
uDMAChannelPriorityClear(uint32_t ui32Base,uint32_t ui32ChannelNum)1173 uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum)
1174 {
1175     // Check the arguments.
1176     ASSERT(uDMABaseValid(ui32Base));
1177     ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
1178 
1179     // Clear the channel priority.
1180     HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum;
1181 }
1182 
1183 //*****************************************************************************
1184 //
1185 // Support for DriverLib in ROM:
1186 // Redirect to implementation in ROM when available.
1187 //
1188 //*****************************************************************************
1189 #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
1190     #include "../driverlib/rom.h"
1191     #ifdef ROM_uDMAChannelAttributeEnable
1192         #undef  uDMAChannelAttributeEnable
1193         #define uDMAChannelAttributeEnable      ROM_uDMAChannelAttributeEnable
1194     #endif
1195     #ifdef ROM_uDMAChannelAttributeDisable
1196         #undef  uDMAChannelAttributeDisable
1197         #define uDMAChannelAttributeDisable     ROM_uDMAChannelAttributeDisable
1198     #endif
1199     #ifdef ROM_uDMAChannelAttributeGet
1200         #undef  uDMAChannelAttributeGet
1201         #define uDMAChannelAttributeGet         ROM_uDMAChannelAttributeGet
1202     #endif
1203     #ifdef ROM_uDMAChannelControlSet
1204         #undef  uDMAChannelControlSet
1205         #define uDMAChannelControlSet           ROM_uDMAChannelControlSet
1206     #endif
1207     #ifdef ROM_uDMAChannelTransferSet
1208         #undef  uDMAChannelTransferSet
1209         #define uDMAChannelTransferSet          ROM_uDMAChannelTransferSet
1210     #endif
1211     #ifdef ROM_uDMAChannelScatterGatherSet
1212         #undef  uDMAChannelScatterGatherSet
1213         #define uDMAChannelScatterGatherSet     ROM_uDMAChannelScatterGatherSet
1214     #endif
1215     #ifdef ROM_uDMAChannelSizeGet
1216         #undef  uDMAChannelSizeGet
1217         #define uDMAChannelSizeGet              ROM_uDMAChannelSizeGet
1218     #endif
1219     #ifdef ROM_uDMAChannelModeGet
1220         #undef  uDMAChannelModeGet
1221         #define uDMAChannelModeGet              ROM_uDMAChannelModeGet
1222     #endif
1223 #endif
1224 
1225 //*****************************************************************************
1226 //
1227 // Mark the end of the C bindings section for C++ compilers.
1228 //
1229 //*****************************************************************************
1230 #ifdef __cplusplus
1231 }
1232 #endif
1233 
1234 #endif //  __UDMA_H__
1235 
1236 //*****************************************************************************
1237 //
1238 //! Close the Doxygen group.
1239 //! @}
1240 //! @}
1241 //
1242 //*****************************************************************************
1243