1 /******************************************************************************
2 * Filename: prcm.h
3 * Revised: 2020-08-19 12:18:33 +0200 (Wed, 19 Aug 2020)
4 * Revision: 58172
5 *
6 * Description: Defines and prototypes for the PRCM
7 *
8 * Copyright (c) 2015 - 2020, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 ******************************************************************************/
38
39 //*****************************************************************************
40 //
41 //! \addtogroup system_control_group
42 //! @{
43 //! \addtogroup prcm_api
44 //! @{
45 //
46 //*****************************************************************************
47
48 #ifndef __PRCM_H__
49 #define __PRCM_H__
50
51 //*****************************************************************************
52 //
53 // If building with a C++ compiler, make all of the definitions in this header
54 // have a C binding.
55 //
56 //*****************************************************************************
57 #ifdef __cplusplus
58 extern "C"
59 {
60 #endif
61
62 #include <stdbool.h>
63 #include <stdint.h>
64 #include "../inc/hw_types.h"
65 #include "../inc/hw_memmap.h"
66 #include "../inc/hw_ints.h"
67 #include "../inc/hw_prcm.h"
68 #include "../inc/hw_nvic.h"
69 #include "../inc/hw_aon_rtc.h"
70 #include "interrupt.h"
71 #include "debug.h"
72 #include "cpu.h"
73
74
75 //*****************************************************************************
76 //
77 // Support for DriverLib in ROM:
78 // This section renames all functions that are not "static inline", so that
79 // calling these functions will default to implementation in flash. At the end
80 // of this file a second renaming will change the defaults to implementation in
81 // ROM for available functions.
82 //
83 // To force use of the implementation in flash, e.g. for debugging:
84 // - Globally: Define DRIVERLIB_NOROM at project level
85 // - Per function: Use prefix "NOROM_" when calling the function
86 //
87 //*****************************************************************************
88 #if !defined(DOXYGEN)
89 #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet
90 #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet
91 #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet
92 #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride
93 #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource
94 #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource
95 #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn
96 #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff
97 #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable
98 #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable
99 #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable
100 #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable
101 #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable
102 #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable
103 #define PRCMPowerDomainsAllOff NOROM_PRCMPowerDomainsAllOff
104 #define PRCMPowerDomainsAllOn NOROM_PRCMPowerDomainsAllOn
105 #define PRCMDeepSleep NOROM_PRCMDeepSleep
106 #endif
107
108 //*****************************************************************************
109 //
110 // Defines for the different System CPU power modes.
111 //
112 //*****************************************************************************
113 #define PRCM_RUN_MODE 0x00000001
114 #define PRCM_SLEEP_MODE 0x00000002
115 #define PRCM_DEEP_SLEEP_MODE 0x00000004
116
117 //*****************************************************************************
118 //
119 // Defines used for setting the clock division factors
120 //
121 //*****************************************************************************
122 #define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1
123 #define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2
124 #define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4
125 #define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8
126 #define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16
127 #define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32
128 #define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64
129 #define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128
130 #define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256
131
132 //*****************************************************************************
133 //
134 // Defines used for enabling and disabling domains and memories in the MCU
135 // domain
136 //
137 //*****************************************************************************
138 #define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for
139 // clock/power control.
140 #define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for
141 // clock/power control.
142 #define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for
143 // clock/power control.
144 #define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power
145 // control.
146 #define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power
147 // control.
148 #define PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP \
149 0x00020010 // For function PRCMPowerDomainOff() it is an option to
150 // select that VIMS power domain shall not power up
151 // during the next wake up from uLDO (VIMS_MODE=0b10).
152 #define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power
153 // control.
154 #define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock
155 // control.
156 #define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for
157 // clock/power control.
158 #define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU
159 // domain.
160 #define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off
161 #define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on
162 #define PRCM_DOMAIN_POWER_DOWN_READY \
163 0x00000000 // The domain is ready to be
164 // powered down.
165
166 //*****************************************************************************
167 //
168 // Defines for setting up the audio interface in the I2S module.
169 //
170 //*****************************************************************************
171 #define PRCM_WCLK_NEG_EDGE 0x00000008
172 #define PRCM_WCLK_POS_EDGE 0x00000000
173 #define PRCM_WCLK_SINGLE_PHASE 0x00000000
174 #define PRCM_WCLK_DUAL_PHASE 0x00000002
175 #define PRCM_WCLK_USER_DEF 0x00000004
176 #define PRCM_I2S_WCLK_NEG_EDGE 0
177 #define PRCM_I2S_WCLK_POS_EDGE 1
178 #define PRCM_I2S_WCLK_SINGLE_PHASE 0
179 #define PRCM_I2S_WCLK_DUAL_PHASE 1
180 #define PRCM_I2S_WCLK_USER_DEF 2
181
182 #define I2S_SAMPLE_RATE_16K 0x00000001
183 #define I2S_SAMPLE_RATE_24K 0x00000002
184 #define I2S_SAMPLE_RATE_32K 0x00000004
185 #define I2S_SAMPLE_RATE_48K 0x00000008
186
187 //*****************************************************************************
188 //
189 // Defines used for enabling and disabling peripheral modules in the MCU domain
190 // bits[11:8] Defines the index into the register offset constant tables:
191 // g_pui32RCGCRegs, g_pui32SCGCRegs and g_pui32DCGCRegs
192 // bits[4:0] Defines the bit position within the register pointet on in [11:8]
193 //
194 //*****************************************************************************
195 #define PRCM_PERIPH_TIMER0 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S )) // Peripheral ID for GPT module 0
196 #define PRCM_PERIPH_TIMER1 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for GPT module 1
197 #define PRCM_PERIPH_TIMER2 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 2 )) // Peripheral ID for GPT module 2
198 #define PRCM_PERIPH_TIMER3 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 3 )) // Peripheral ID for GPT module 3
199 #define PRCM_PERIPH_SSI0 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S )) // Peripheral ID for SSI module 0
200 #define PRCM_PERIPH_SSI1 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S + 1 )) // Peripheral ID for SSI module 1
201 #define PRCM_PERIPH_UART0 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S )) // Peripheral ID for UART module 0
202 #define PRCM_PERIPH_UART1 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for UART module 1
203 #define PRCM_PERIPH_I2C0 ( 0x00000300 | ( PRCM_I2CCLKGR_CLK_EN_S )) // Peripheral ID for I2C module 0
204 #define PRCM_PERIPH_CRYPTO ( 0x00000400 | ( PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S )) // Peripheral ID for CRYPTO module
205 #define PRCM_PERIPH_TRNG ( 0x00000400 | ( PRCM_SECDMACLKGR_TRNG_CLK_EN_S )) // Peripheral ID for TRNG module
206 #define PRCM_PERIPH_PKA ( 0x00000400 | ( PRCM_SECDMACLKGR_PKA_CLK_EN_S )) // Peripheral ID for PKA module
207 #define PRCM_PERIPH_UDMA ( 0x00000400 | ( PRCM_SECDMACLKGR_DMA_CLK_EN_S )) // Peripheral ID for UDMA module
208 #define PRCM_PERIPH_GPIO ( 0x00000500 | ( PRCM_GPIOCLKGR_CLK_EN_S )) // Peripheral ID for GPIO module
209 #define PRCM_PERIPH_I2S ( 0x00000600 | ( PRCM_I2SCLKGR_CLK_EN_S )) // Peripheral ID for I2S module
210
211 //*****************************************************************************
212 //
213 // API Functions and prototypes
214 //
215 //*****************************************************************************
216
217 #ifdef DRIVERLIB_DEBUG
218 //*****************************************************************************
219 //
220 //! \brief Checks a peripheral identifier.
221 //!
222 //! This function determines if a peripheral identifier is valid.
223 //!
224 //! \param ui32Peripheral is the peripheral identifier.
225 //!
226 //! \return Returns status of peripheral identifier:
227 //! - \b true : Peripheral identifier is valid.
228 //! - \b false : Peripheral identifier is invalid.
229 //
230 //*****************************************************************************
231 static bool
PRCMPeripheralValid(uint32_t ui32Peripheral)232 PRCMPeripheralValid(uint32_t ui32Peripheral)
233 {
234 return((ui32Peripheral == PRCM_PERIPH_TIMER0) ||
235 (ui32Peripheral == PRCM_PERIPH_TIMER1) ||
236 (ui32Peripheral == PRCM_PERIPH_TIMER2) ||
237 (ui32Peripheral == PRCM_PERIPH_TIMER3) ||
238 (ui32Peripheral == PRCM_PERIPH_SSI0) ||
239 (ui32Peripheral == PRCM_PERIPH_SSI1) ||
240 (ui32Peripheral == PRCM_PERIPH_UART0) ||
241 (ui32Peripheral == PRCM_PERIPH_UART1) ||
242 (ui32Peripheral == PRCM_PERIPH_I2C0) ||
243 (ui32Peripheral == PRCM_PERIPH_CRYPTO) ||
244 (ui32Peripheral == PRCM_PERIPH_TRNG) ||
245 (ui32Peripheral == PRCM_PERIPH_PKA) ||
246 (ui32Peripheral == PRCM_PERIPH_UDMA) ||
247 (ui32Peripheral == PRCM_PERIPH_GPIO) ||
248 (ui32Peripheral == PRCM_PERIPH_I2S));
249 }
250 #endif
251
252 //*****************************************************************************
253 //
254 //! \brief Configure the infrastructure clock.
255 //!
256 //! Each System CPU power mode has its own infrastructure clock division factor. This
257 //! function can be used for setting up the division factor for the
258 //! infrastructure clock in the available power modes for the System CPU. The
259 //! infrastructure clock is used for all internal logic in the PRCM, and is
260 //! always running as long as power is on in the MCU voltage domain.
261 //! This can be enabled and disabled from the AON Wake Up Controller.
262 //!
263 //! \note If source clock is 48 MHz, minimum clock divider is \ref PRCM_CLOCK_DIV_2.
264 //!
265 //! \param ui32ClkDiv determines the division ratio for the infrastructure
266 //! clock when the device is in the specified mode.
267 //! Allowed division factors for all three System CPU power modes are:
268 //! - \ref PRCM_CLOCK_DIV_1
269 //! - \ref PRCM_CLOCK_DIV_2
270 //! - \ref PRCM_CLOCK_DIV_8
271 //! - \ref PRCM_CLOCK_DIV_32
272 //! \param ui32PowerMode determines the System CPU operation mode for which to
273 //! modify the clock division factor.
274 //! The three allowed power modes are:
275 //! - \ref PRCM_RUN_MODE
276 //! - \ref PRCM_SLEEP_MODE
277 //! - \ref PRCM_DEEP_SLEEP_MODE
278 //!
279 //! \return None
280 //
281 //*****************************************************************************
282 extern void PRCMInfClockConfigureSet(uint32_t ui32ClkDiv,
283 uint32_t ui32PowerMode);
284
285 //*****************************************************************************
286 //
287 //! \brief Use this function to get the infrastructure clock configuration.
288 //!
289 //! \param ui32PowerMode determines which System CPU power mode to return the
290 //! infrastructure clock division ratio for.
291 //! The three allowed power modes are:
292 //! - \ref PRCM_RUN_MODE
293 //! - \ref PRCM_SLEEP_MODE
294 //! - \ref PRCM_DEEP_SLEEP_MODE
295 //!
296 //! \return Returns the infrastructure clock division factor for the specified
297 //! power mode.
298 //! - \ref PRCM_CLOCK_DIV_1
299 //! - \ref PRCM_CLOCK_DIV_2
300 //! - \ref PRCM_CLOCK_DIV_8
301 //! - \ref PRCM_CLOCK_DIV_32
302 //!
303 //! \sa \ref PRCMInfClockConfigureSet().
304 //
305 //*****************************************************************************
306 extern uint32_t PRCMInfClockConfigureGet(uint32_t ui32PowerMode);
307
308 //*****************************************************************************
309 //
310 //! \brief Assert or de-assert a request for the uLDO.
311 //!
312 //! Use this function to request to switch to the micro Low Voltage Dropout
313 //! regulator (uLDO). The uLDO has a much lower capacity for supplying power
314 //! to the system. It is therefore imperative and solely the programmers
315 //! responsibility to ensure that a sufficient amount of peripheral modules
316 //! have been turned of before requesting a switch to the uLDO.
317 //!
318 //! \note Asserting this bit has no effect until:
319 //! 1. FLASH has accepted to be powered down
320 //! 2. Deepsleep must be asserted
321 //!
322 //! \param ui32Enable
323 //! - 0 : Disable uLDO request
324 //! - 1 : Enable uLDO request
325 //!
326 //! \return None
327 //!
328 //! \sa \ref PRCMDeepSleep()
329 //
330 //*****************************************************************************
331 __STATIC_INLINE void
PRCMMcuUldoConfigure(uint32_t ui32Enable)332 PRCMMcuUldoConfigure(uint32_t ui32Enable)
333 {
334 // Enable or disable the uLDO request signal.
335 HWREG(PRCM_BASE + PRCM_O_VDCTL) = ui32Enable;
336 }
337
338 //*****************************************************************************
339 //
340 //! \brief Setup the clock division factor for the GP-Timer domain.
341 //!
342 //! Use this function to set up the clock division factor on the GP-Timer.
343 //!
344 //! The division rate will be constant and ungated for Run / Sleep / DeepSleep mode when
345 //! it is slower than PRCM_GPTCLKDIV_RATIO setting.
346 //! When set faster than PRCM_GPTCLKDIV_RATIO setting PRCM_GPTCLKDIV_RATIO will be used.
347 //! Note that the register will contain the written content even though the setting is
348 //! faster than PRCM_GPTCLKDIV_RATIO setting.
349 //!
350 //! \note For change to take effect, \ref PRCMLoadSet() needs to be called
351 //!
352 //! \param clkDiv is the division factor to set.
353 //! The argument must be only one of the following values:
354 //! - \ref PRCM_CLOCK_DIV_1
355 //! - \ref PRCM_CLOCK_DIV_2
356 //! - \ref PRCM_CLOCK_DIV_4
357 //! - \ref PRCM_CLOCK_DIV_8
358 //! - \ref PRCM_CLOCK_DIV_16
359 //! - \ref PRCM_CLOCK_DIV_32
360 //! - \ref PRCM_CLOCK_DIV_64
361 //! - \ref PRCM_CLOCK_DIV_128
362 //! - \ref PRCM_CLOCK_DIV_256
363 //!
364 //! \return None
365 //!
366 //! \sa \ref PRCMGPTimerClockDivisionGet()
367 //
368 //*****************************************************************************
369 __STATIC_INLINE void
PRCMGPTimerClockDivisionSet(uint32_t clkDiv)370 PRCMGPTimerClockDivisionSet( uint32_t clkDiv )
371 {
372 ASSERT( clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256 );
373
374 HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ) = clkDiv;
375 }
376
377 //*****************************************************************************
378 //
379 //! \brief Get the clock division factor for the GP-Timer domain.
380 //!
381 //! Use this function to get the clock division factor set for the GP-Timer.
382 //!
383 //! \return Returns one of the following values:
384 //! - \ref PRCM_CLOCK_DIV_1
385 //! - \ref PRCM_CLOCK_DIV_2
386 //! - \ref PRCM_CLOCK_DIV_4
387 //! - \ref PRCM_CLOCK_DIV_8
388 //! - \ref PRCM_CLOCK_DIV_16
389 //! - \ref PRCM_CLOCK_DIV_32
390 //! - \ref PRCM_CLOCK_DIV_64
391 //! - \ref PRCM_CLOCK_DIV_128
392 //! - \ref PRCM_CLOCK_DIV_256
393 //!
394 //! \sa \ref PRCMGPTimerClockDivisionSet()
395 //
396 //*****************************************************************************
397 __STATIC_INLINE uint32_t
PRCMGPTimerClockDivisionGet(void)398 PRCMGPTimerClockDivisionGet( void )
399 {
400 return ( HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ));
401 }
402
403
404 //*****************************************************************************
405 //
406 //! \brief Enable the audio clock generation.
407 //!
408 //! Use this function to enable the audio clock generation.
409 //!
410 //! \return None
411 //
412 //*****************************************************************************
413 __STATIC_INLINE void
PRCMAudioClockEnable(void)414 PRCMAudioClockEnable(void)
415 {
416 // Enable the audio clock generation.
417 HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 1;
418 }
419
420 //*****************************************************************************
421 //
422 //! \brief Disable the audio clock generation.
423 //!
424 //! Use this function to disable the audio clock generation.
425 //!
426 //! \return None
427 //
428 //*****************************************************************************
429 __STATIC_INLINE void
PRCMAudioClockDisable(void)430 PRCMAudioClockDisable(void)
431 {
432 // Disable the audio clock generation
433 HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 0;
434 }
435
436 //*****************************************************************************
437 //
438 //! \brief Configure the audio clock generation.
439 //!
440 //! \deprecated This function will be removed in a future release.
441 //!
442 //! Use this function to set the sample rate when using internal audio clock
443 //! generation for the I2S module.
444 //!
445 //! \note While other clocks are possible, the stability of the four sample
446 //! rates defined here are only guaranteed if the clock input to the I2S module
447 //! is 48MHz.
448 //!
449 //! \param ui32ClkConfig is the audio clock configuration.
450 //! The parameter is a bitwise OR'ed value consisting of:
451 //! - Phase
452 //! - \ref PRCM_WCLK_SINGLE_PHASE
453 //! - \ref PRCM_WCLK_DUAL_PHASE
454 //! - Clock polarity
455 //! - \ref PRCM_WCLK_NEG_EDGE
456 //! - \ref PRCM_WCLK_POS_EDGE
457 //! \param ui32SampleRate is the desired audio clock sample rate.
458 //! The supported sample rate configurations are:
459 //! - \ref I2S_SAMPLE_RATE_16K
460 //! - \ref I2S_SAMPLE_RATE_24K
461 //! - \ref I2S_SAMPLE_RATE_32K
462 //! - \ref I2S_SAMPLE_RATE_48K
463 //!
464 //! \return None
465 //!
466 //! \sa \ref PRCMAudioClockConfigSetOverride()
467 //
468 //*****************************************************************************
469 #ifndef DEPRECATED
470 extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig,
471 uint32_t ui32SampleRate);
472 #endif
473
474 //*****************************************************************************
475 //
476 //! \brief Configure the audio clock generation with manual setting of clock divider.
477 //!
478 //! \deprecated This function will be removed in a future release.
479 //!
480 //! Use this function to set the audio clock divider values manually.
481 //!
482 //! \note See hardware documentation before setting audio clock dividers manually.
483 //!
484 //! \param ui32ClkConfig is the audio clock configuration.
485 //! The parameter is a bitwise OR'ed value consisting of:
486 //! - Phase
487 //! - \ref PRCM_WCLK_SINGLE_PHASE
488 //! - \ref PRCM_WCLK_DUAL_PHASE
489 //! - Clock polarity
490 //! - \ref PRCM_WCLK_NEG_EDGE
491 //! - \ref PRCM_WCLK_POS_EDGE
492 //! \param ui32MstDiv is the desired master clock divider.
493 //! \param ui32WordDiv is the desired word clock divider.
494 //! \param ui32BitDiv is the desired bit clock divider.
495 //!
496 //! \return None
497 //!
498 //! \sa \ref PRCMAudioClockConfigSet()
499 //
500 //*****************************************************************************
501 #ifndef DEPRECATED
502 extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv,
503 uint32_t ui32BitDiv, uint32_t ui32WordDiv);
504 #endif
505
506 //*****************************************************************************
507 //
508 //! \brief Configure the audio clocks for I2S module.
509 //!
510 //! \note See hardware documentation before setting audio clock dividers.
511 //! This is user's responsability to provide valid clock dividers.
512 //!
513 //! \param ui8SamplingEdge Define the clock polarity:
514 //! - \ref PRCM_I2S_WCLK_NEG_EDGE
515 //! - \ref PRCM_I2S_WCLK_POS_EDGE
516 //! \param ui8WCLKPhase Define I2S phase used
517 //! - PRCM_I2S_WCLK_SINGLE_PHASE
518 //! - PRCM_I2S_WCLK_DUAL_PHASE
519 //! - PRCM_I2S_WCLK_USER_DEF
520 //! \param ui32MstDiv is the desired master clock divider.
521 //! \param ui32BitDiv is the desired bit clock divider.
522 //! \param ui32WordDiv is the desired word clock divider.
523 //!
524 //! \return None
525 //!
526 //*****************************************************************************
527 extern void PRCMAudioClockConfigOverride
528 (uint8_t ui8SamplingEdge,
529 uint8_t ui8WCLKPhase,
530 uint32_t ui32MstDiv,
531 uint32_t ui32BitDiv,
532 uint32_t ui32WordDiv);
533
534 //*****************************************************************************
535 //
536 //! \brief Configure the audio clocks to be internally generated.
537 //!
538 //! Use this function to set the audio clocks as internal.
539 //!
540 //! \return None
541 //!
542 //! \sa \ref PRCMAudioClockExternalSource()
543 //
544 //*****************************************************************************
545 extern void PRCMAudioClockInternalSource(void);
546
547 //*****************************************************************************
548 //
549 //! \brief Configure the audio clocks to be externally generated.
550 //!
551 //! Use this function to set the audio clocks as external.
552 //!
553 //! \return None
554 //!
555 //! \sa \ref PRCMAudioClockInternalSource()
556 //
557 //*****************************************************************************
558 extern void PRCMAudioClockExternalSource(void);
559
560 //*****************************************************************************
561 //
562 //! \brief Use this function to synchronize the load settings.
563 //!
564 //! Most of the clock settings in the PRCM module should be updated
565 //! synchronously. This is ensured by the implementation of a load registers
566 //! that, when written to, will let the previous written update values for all
567 //! the relevant registers propagate through to hardware.
568 //!
569 //! The functions that require a synchronization of the clock settings are:
570 //! - \ref PRCMAudioClockConfigSet()
571 //! - \ref PRCMAudioClockConfigSetOverride()
572 //! - \ref PRCMAudioClockDisable()
573 //! - \ref PRCMDomainEnable()
574 //! - \ref PRCMDomainDisable()
575 //! - \ref PRCMPeripheralRunEnable()
576 //! - \ref PRCMPeripheralRunDisable()
577 //! - \ref PRCMPeripheralSleepEnable()
578 //! - \ref PRCMPeripheralSleepDisable()
579 //! - \ref PRCMPeripheralDeepSleepEnable()
580 //! - \ref PRCMPeripheralDeepSleepDisable()
581 //!
582 //! \return None
583 //!
584 //! \sa \ref PRCMLoadGet()
585 //
586 //*****************************************************************************
587 __STATIC_INLINE void
PRCMLoadSet(void)588 PRCMLoadSet(void)
589 {
590 // Enable the update of all load related registers.
591 HWREG(PRCM_NONBUF_BASE + PRCM_O_CLKLOADCTL) = PRCM_CLKLOADCTL_LOAD;
592 }
593
594 //*****************************************************************************
595 //
596 //! \brief Check if any of the load sensitive register has been updated.
597 //!
598 //! \return Returns status of the load sensitive register:
599 //! - \c true : No registers have changed since the last load.
600 //! - \c false : Any register has changed.
601 //!
602 //! \sa \ref PRCMLoadSet()
603 //
604 //*****************************************************************************
605 __STATIC_INLINE bool
PRCMLoadGet(void)606 PRCMLoadGet(void)
607 {
608 // Return the load status.
609 return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ?
610 true : false);
611 }
612
613 //*****************************************************************************
614 //
615 //! \brief Enable clock domains in the MCU voltage domain.
616 //!
617 //! \note A call to this function will only setup the shadow registers in the
618 //! MCU domain for the PRCM module. For the changes to propagate to the system
619 //! controller in the AON domain a call to this function should always be
620 //! followed by a call to \ref PRCMLoadSet().
621 //!
622 //! \note Clocks will only be running if the domain is powered.
623 //!
624 //! \param ui32Domains is a bit mask containing the clock domains to enable.
625 //! The independent clock domains inside the MCU voltage domain which can be
626 //! configured are:
627 //! - \ref PRCM_DOMAIN_RFCORE
628 //! - \ref PRCM_DOMAIN_VIMS
629 //!
630 //! \return None
631 //
632 //*****************************************************************************
633 __STATIC_INLINE void
PRCMDomainEnable(uint32_t ui32Domains)634 PRCMDomainEnable(uint32_t ui32Domains)
635 {
636 // Check the arguments.
637 ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
638 (ui32Domains & PRCM_DOMAIN_VIMS));
639
640 // Enable the clock domain(s).
641 if(ui32Domains & PRCM_DOMAIN_RFCORE)
642 {
643 HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = PRCM_RFCCLKG_CLK_EN;
644 }
645 if(ui32Domains & PRCM_DOMAIN_VIMS)
646 {
647 HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = PRCM_VIMSCLKG_CLK_EN_M;
648 }
649 }
650
651 //*****************************************************************************
652 //
653 //! \brief Disable clock domains in the MCU voltage domain.
654 //!
655 //! \note A call to this function will only setup the shadow registers in the
656 //! MCU domain for the PRCM module. For the changes to propagate to the system
657 //! controller in the AON domain a call to this function should always be
658 //! followed by a call to \ref PRCMLoadSet().
659 //!
660 //! \note Clocks will only be running if the domain is powered.
661 //!
662 //! \param ui32Domains is a bit mask containing the clock domains to disable.
663 //! The independent clock domains inside the MCU voltage domain are:
664 //! - \ref PRCM_DOMAIN_RFCORE
665 //! - \ref PRCM_DOMAIN_VIMS
666 //!
667 //! \return None
668 //!
669 //! \sa PRCMDomainEnable()
670 //
671 //*****************************************************************************
672 __STATIC_INLINE void
PRCMDomainDisable(uint32_t ui32Domains)673 PRCMDomainDisable(uint32_t ui32Domains)
674 {
675 // Check the arguments.
676 ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
677 (ui32Domains & PRCM_DOMAIN_VIMS));
678
679 // Disable the power domains.
680 if(ui32Domains & PRCM_DOMAIN_RFCORE)
681 {
682 HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = 0x0;
683 }
684 if(ui32Domains & PRCM_DOMAIN_VIMS)
685 {
686 HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = 0x0;
687 }
688 }
689
690 //*****************************************************************************
691 //
692 //! \brief Turn power on in power domains in the MCU domain.
693 //!
694 //! Use this function to turn on power domains inside the MCU voltage domain.
695 //!
696 //! Power on and power off request has different implications for the
697 //! different power domains.
698 //! - RF Core power domain:
699 //! - Power On : Domain is on or in the process of turning on.
700 //! - Power Off : Domain is powered down when System CPU is in deep sleep. The third
701 //! option for the RF Core is to power down when the it is idle.
702 //! This can be set using \b PRCMRfPowerDownWhenIdle()
703 //! - SERIAL power domain:
704 //! - Power on : Domain is powered on.
705 //! - Power off : Domain is powered off.
706 //! - PERIPHERIAL power domain:
707 //! - Power on : Domain is powered on.
708 //! - Power off : Domain is powered off.
709 //! - VIMS power domain:
710 //! - Power On : Domain is powered if Bus domain is powered.
711 //! - Power Off : Domain is only powered when CPU domain is on.
712 //! - BUS power domain:
713 //! - Power On : Domain is on.
714 //! - Power Off : Domain is on if requested by RF Core or if CPU domain is on.
715 //! - CPU power domain:
716 //! - Power On : Domain is on.
717 //! - Power Off : Domain is powering down if System CPU is idle. This will also
718 //! initiate a power down of the SRAM and BUS power domains, unless
719 //! RF Core is requesting them to be on.
720 //!
721 //! \note After a call to this function the status of the power domain should be checked
722 //! using either \ref PRCMPowerDomainsAllOff() or \ref PRCMPowerDomainsAllOn().
723 //! Any write operation to a power domain which is still not operational can
724 //! result in unexpected behavior.
725 //!
726 //! \param ui32Domains determines which power domains to turn on.
727 //! The domains that can be turned on/off are:
728 //! - \b PRCM_DOMAIN_RFCORE : RF Core
729 //! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
730 //! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1
731 //! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM
732 //! - \b PRCM_DOMAIN_SYSBUS
733 //! - \b PRCM_DOMAIN_CPU
734 //!
735 //! \return None
736 //
737 //*****************************************************************************
738 extern void PRCMPowerDomainOn(uint32_t ui32Domains);
739
740 //*****************************************************************************
741 //
742 //! \brief Turn off a specific power domain.
743 //!
744 //! Use this function to power down domains inside the MCU voltage domain.
745 //!
746 //! \note For specifics regarding on/off configuration please see
747 //! \ref PRCMPowerDomainOn().
748 //!
749 //! \param ui32Domains determines which domain to request a power down for.
750 //! The domains that can be turned on/off are:
751 //! - \b PRCM_DOMAIN_RFCORE : RF Core
752 //! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
753 //! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1
754 //! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM
755 //! - \b PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP : SRAM, FLASH, ROM
756 //! - \b PRCM_DOMAIN_SYSBUS
757 //! - \b PRCM_DOMAIN_CPU
758 //!
759 //! \return None
760 //
761 //*****************************************************************************
762 extern void PRCMPowerDomainOff(uint32_t ui32Domains);
763
764 //*****************************************************************************
765 //
766 //! \brief Configure RF core to power down when idle.
767 //!
768 //! Use this function to configure the RF core to power down when Idle. This
769 //! is handled automatically in hardware if the RF Core reports that it is
770 //! idle.
771 //!
772 //! \return None
773 //
774 //*****************************************************************************
775 __STATIC_INLINE void
PRCMRfPowerDownWhenIdle(void)776 PRCMRfPowerDownWhenIdle(void)
777 {
778 // Configure the RF power domain.
779 HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC) = 0;
780 }
781
782 //*****************************************************************************
783 //
784 //! \brief Enables a peripheral in Run mode.
785 //!
786 //! Peripherals are enabled with this function. At power-up, some peripherals
787 //! are disabled; they must be enabled in order to operate or respond to
788 //! register reads/writes.
789 //!
790 //! \note The actual enabling of the peripheral may be delayed until some
791 //! time after this function returns. Care should be taken to ensure that the
792 //! peripheral is not accessed until it is enabled.
793 //! When enabling Timers always make sure that the division factor for the
794 //! \b PERBUSCPUCLK is set. This will guarantee that the timers run at a
795 //! continuous rate even if the \b SYSBUSCLK is gated.
796 //!
797 //! \note A call to this function will only setup the shadow registers in the
798 //! MCU domain for the PRCM module. For the changes to propagate to the system
799 //! controller in the AON domain a call to this function should always be
800 //! followed by a call to \ref PRCMLoadSet().
801 //!
802 //! \param ui32Peripheral is the peripheral to enable.
803 //! The parameter must be one of the following:
804 //! - \ref PRCM_PERIPH_TIMER0
805 //! - \ref PRCM_PERIPH_TIMER1
806 //! - \ref PRCM_PERIPH_TIMER2
807 //! - \ref PRCM_PERIPH_TIMER3
808 //! - \ref PRCM_PERIPH_SSI0
809 //! - \ref PRCM_PERIPH_SSI1
810 //! - \ref PRCM_PERIPH_UART0
811 //! - \ref PRCM_PERIPH_UART1
812 //! - \ref PRCM_PERIPH_I2C0
813 //! - \ref PRCM_PERIPH_CRYPTO
814 //! - \ref PRCM_PERIPH_TRNG
815 //! - \ref PRCM_PERIPH_PKA
816 //! - \ref PRCM_PERIPH_UDMA
817 //! - \ref PRCM_PERIPH_GPIO
818 //! - \ref PRCM_PERIPH_I2S
819 //!
820 //! \return None
821 //!
822 //! \sa \ref PRCMLoadSet()
823 //
824 //*****************************************************************************
825 extern void PRCMPeripheralRunEnable(uint32_t ui32Peripheral);
826
827 //*****************************************************************************
828 //
829 //! \brief Disables a peripheral in Run mode
830 //!
831 //! Peripherals are disabled with this function. Once disabled, they will not
832 //! operate or respond to register reads/writes.
833 //!
834 //! \note A call to this function will only setup the shadow registers in the
835 //! MCU domain for the PRCM module. For the changes to propagate to the system
836 //! controller in the AON domain a call to this function should always be
837 //! followed by a call to \ref PRCMLoadSet().
838 //!
839 //! \note The actual disabling of the peripheral may be delayed until some
840 //! time after this function returns. Care should be taken by the user to
841 //! ensure that the peripheral is not accessed in this interval as this might
842 //! cause the system to hang.
843 //!
844 //! \param ui32Peripheral is the peripheral to disable.
845 //! The parameter must be one of the following:
846 //! - \ref PRCM_PERIPH_TIMER0
847 //! - \ref PRCM_PERIPH_TIMER1
848 //! - \ref PRCM_PERIPH_TIMER2
849 //! - \ref PRCM_PERIPH_TIMER3
850 //! - \ref PRCM_PERIPH_SSI0
851 //! - \ref PRCM_PERIPH_SSI1
852 //! - \ref PRCM_PERIPH_UART0
853 //! - \ref PRCM_PERIPH_UART1
854 //! - \ref PRCM_PERIPH_I2C0
855 //! - \ref PRCM_PERIPH_CRYPTO
856 //! - \ref PRCM_PERIPH_TRNG
857 //! - \ref PRCM_PERIPH_PKA
858 //! - \ref PRCM_PERIPH_UDMA
859 //! - \ref PRCM_PERIPH_GPIO
860 //! - \ref PRCM_PERIPH_I2S
861 //!
862 //! \return None
863 //!
864 //! \sa \ref PRCMLoadSet()
865 //
866 //*****************************************************************************
867 extern void PRCMPeripheralRunDisable(uint32_t ui32Peripheral);
868
869 //*****************************************************************************
870 //
871 //! \brief Enables a peripheral in sleep mode.
872 //!
873 //! This function allows a peripheral to continue operating when the processor
874 //! goes into sleep mode. Since the clocking configuration of the device does
875 //! not change, any peripheral can safely continue operating while the
876 //! processor is in sleep mode, and can therefore wake the processor from sleep
877 //! mode.
878 //!
879 //! \note A call to this function will only setup the shadow registers in the
880 //! MCU domain for the PRCM module. For the changes to propagate to the system
881 //! controller in the AON domain a call to this function should always be
882 //! followed by a call to \ref PRCMLoadSet().
883 //!
884 //! \param ui32Peripheral is the peripheral to enable in sleep mode.
885 //! The parameter must be one of the following:
886 //! - \ref PRCM_PERIPH_TIMER0
887 //! - \ref PRCM_PERIPH_TIMER1
888 //! - \ref PRCM_PERIPH_TIMER2
889 //! - \ref PRCM_PERIPH_TIMER3
890 //! - \ref PRCM_PERIPH_SSI0
891 //! - \ref PRCM_PERIPH_SSI1
892 //! - \ref PRCM_PERIPH_UART0
893 //! - \ref PRCM_PERIPH_UART1
894 //! - \ref PRCM_PERIPH_I2C0
895 //! - \ref PRCM_PERIPH_CRYPTO
896 //! - \ref PRCM_PERIPH_TRNG
897 //! - \ref PRCM_PERIPH_PKA
898 //! - \ref PRCM_PERIPH_UDMA
899 //! - \ref PRCM_PERIPH_GPIO
900 //! - \ref PRCM_PERIPH_I2S
901 //!
902 //! \return None
903 //!
904 //! \sa \ref PRCMLoadSet()
905 //
906 //*****************************************************************************
907 extern void PRCMPeripheralSleepEnable(uint32_t ui32Peripheral);
908
909 //*****************************************************************************
910 //
911 //! \brief Disables a peripheral in sleep mode.
912 //!
913 //! This function causes a peripheral to stop operating when the processor goes
914 //! into sleep mode. Disabling peripherals while in sleep mode helps to lower
915 //! the current draw of the device. If enabled (via \ref PRCMPeripheralRunEnable()),
916 //! the peripheral will automatically resume operation when the processor
917 //! leaves sleep mode, maintaining its entire state from before sleep mode was
918 //! entered.
919 //!
920 //! \note A call to this function will only setup the shadow registers in the
921 //! MCU domain for the PRCM module. For the changes to propagate to the system
922 //! controller in the AON domain a call to this function should always be
923 //! followed by a call to \ref PRCMLoadSet().
924 //!
925 //! \param ui32Peripheral is the peripheral to disable in sleep mode.
926 //! The parameter must be one of the following:
927 //! - \ref PRCM_PERIPH_TIMER0
928 //! - \ref PRCM_PERIPH_TIMER1
929 //! - \ref PRCM_PERIPH_TIMER2
930 //! - \ref PRCM_PERIPH_TIMER3
931 //! - \ref PRCM_PERIPH_SSI0
932 //! - \ref PRCM_PERIPH_SSI1
933 //! - \ref PRCM_PERIPH_UART0
934 //! - \ref PRCM_PERIPH_UART1
935 //! - \ref PRCM_PERIPH_I2C0
936 //! - \ref PRCM_PERIPH_CRYPTO
937 //! - \ref PRCM_PERIPH_TRNG
938 //! - \ref PRCM_PERIPH_PKA
939 //! - \ref PRCM_PERIPH_UDMA
940 //! - \ref PRCM_PERIPH_GPIO
941 //! - \ref PRCM_PERIPH_I2S
942 //!
943 //! \return None
944 //!
945 //! \sa \ref PRCMLoadSet()
946 //
947 //*****************************************************************************
948 extern void PRCMPeripheralSleepDisable(uint32_t ui32Peripheral);
949
950 //*****************************************************************************
951 //
952 //! \brief Enables a peripheral in deep-sleep mode.
953 //!
954 //! This function allows a peripheral to continue operating when the processor
955 //! goes into deep-sleep mode. Since the clocking configuration of the device
956 //! may change, not all peripherals can safely continue operating while the
957 //! processor is in sleep mode. This in turn depends on the chosen power mode.
958 //! It is the responsibility of the caller to make sensible choices.
959 //!
960 //! \note A call to this function will only setup the shadow registers in the
961 //! MCU domain for the PRCM module. For the changes to propagate to the system
962 //! controller in the AON domain a call to this function should always be
963 //! followed by a call to \ref PRCMLoadSet().
964 //!
965 //! \param ui32Peripheral is the peripheral to enable in deep-sleep mode.
966 //! The parameter must be one of the following:
967 //! - \ref PRCM_PERIPH_TIMER0
968 //! - \ref PRCM_PERIPH_TIMER1
969 //! - \ref PRCM_PERIPH_TIMER2
970 //! - \ref PRCM_PERIPH_TIMER3
971 //! - \ref PRCM_PERIPH_SSI0
972 //! - \ref PRCM_PERIPH_SSI1
973 //! - \ref PRCM_PERIPH_UART0
974 //! - \ref PRCM_PERIPH_UART1
975 //! - \ref PRCM_PERIPH_I2C0
976 //! - \ref PRCM_PERIPH_CRYPTO
977 //! - \ref PRCM_PERIPH_TRNG
978 //! - \ref PRCM_PERIPH_PKA
979 //! - \ref PRCM_PERIPH_UDMA
980 //! - \ref PRCM_PERIPH_GPIO
981 //! - \ref PRCM_PERIPH_I2S
982 //!
983 //! \return None
984 //!
985 //! \sa \ref PRCMLoadSet()
986 //
987 //*****************************************************************************
988 extern void PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral);
989
990 //*****************************************************************************
991 //
992 //! \brief Disables a peripheral in deep-sleep mode.
993 //!
994 //! This function causes a peripheral to stop operating when the processor goes
995 //! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps
996 //! to lower the current draw of the device, and can keep peripherals that
997 //! require a particular clock frequency from operating when the clock changes
998 //! as a result of entering deep-sleep mode. If enabled (via
999 //! \ref PRCMPeripheralRunEnable()), the peripheral will automatically resume
1000 //! operation when the processor leaves deep-sleep mode, maintaining its entire
1001 //! state from before deep-sleep mode was entered.
1002 //!
1003 //! \note A call to this function will only setup the shadow registers in the
1004 //! MCU domain for the PRCM module. For the changes to propagate to the system
1005 //! controller in the AON domain a call to this function should always be
1006 //! followed by a call to \ref PRCMLoadSet().
1007 //!
1008 //! \param ui32Peripheral is the peripheral to disable in deep-sleep mode.
1009 //! The parameter must be one of the following:
1010 //! - \ref PRCM_PERIPH_TIMER0
1011 //! - \ref PRCM_PERIPH_TIMER1
1012 //! - \ref PRCM_PERIPH_TIMER2
1013 //! - \ref PRCM_PERIPH_TIMER3
1014 //! - \ref PRCM_PERIPH_SSI0
1015 //! - \ref PRCM_PERIPH_SSI1
1016 //! - \ref PRCM_PERIPH_UART0
1017 //! - \ref PRCM_PERIPH_UART1
1018 //! - \ref PRCM_PERIPH_I2C0
1019 //! - \ref PRCM_PERIPH_CRYPTO
1020 //! - \ref PRCM_PERIPH_TRNG
1021 //! - \ref PRCM_PERIPH_PKA
1022 //! - \ref PRCM_PERIPH_UDMA
1023 //! - \ref PRCM_PERIPH_GPIO
1024 //! - \ref PRCM_PERIPH_I2S
1025 //!
1026 //! \return None
1027 //!
1028 //! \sa \ref PRCMLoadSet()
1029 //
1030 //*****************************************************************************
1031 extern void PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral);
1032
1033 //*****************************************************************************
1034 //
1035 //! \brief Get the status for a specific power domain.
1036 //!
1037 //! Use this function to retrieve the current power status of one or more
1038 //! power domains.
1039 //!
1040 //! \param ui32Domains determines which domain to get the power status for.
1041 //! The parameter must be an OR'ed combination of one or several of:
1042 //! - \ref PRCM_DOMAIN_RFCORE : RF Core.
1043 //! - \ref PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
1044 //! - \ref PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1
1045 //!
1046 //! \return Returns status of the requested domains:
1047 //! - \ref PRCM_DOMAIN_POWER_OFF : The specified domains are \b all powered down.
1048 //! This status is unconditional and the powered down status is guaranteed.
1049 //! - \ref PRCM_DOMAIN_POWER_OFF : Any of the domains are still powered up.
1050 //
1051 //*****************************************************************************
1052 extern uint32_t PRCMPowerDomainsAllOff(uint32_t ui32Domains);
1053
1054 //*****************************************************************************
1055 //
1056 //! \brief Get the status for a specific power domain.
1057 //!
1058 //! Use this function to retrieve the current power status of one or more
1059 //! power domains.
1060 //!
1061 //! \param ui32Domains determines which domain to get the power status for.
1062 //! The parameter must be an OR'ed combination of one or several of:
1063 //! - \ref PRCM_DOMAIN_RFCORE : RF Core.
1064 //! - \ref PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
1065 //! - \ref PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1
1066 //!
1067 //! \return Returns status of the requested domains:
1068 //! - \ref PRCM_DOMAIN_POWER_ON : The specified domains are \b all powered up.
1069 //! This status is unconditional and the powered up status is guaranteed.
1070 //! - \ref PRCM_DOMAIN_POWER_OFF : Any of the domains are still powered down.
1071 //
1072 //*****************************************************************************
1073 extern uint32_t PRCMPowerDomainsAllOn(uint32_t ui32Domains);
1074
1075 //*****************************************************************************
1076 //
1077 //! \brief Return the access status of the RF Core.
1078 //!
1079 //! Use this function to check if the RF Core is on and ready to be accessed.
1080 //! Accessing register or memories that are not powered and clocked will
1081 //! cause a bus fault.
1082 //!
1083 //! \return Returns access status of the RF Core.
1084 //! - \c true : RF Core can be accessed.
1085 //! - \c false : RF Core domain is not ready for access.
1086 //
1087 //*****************************************************************************
1088 __STATIC_INLINE bool
PRCMRfReady(void)1089 PRCMRfReady(void)
1090 {
1091 // Return the ready status of the RF Core.
1092 return ((HWREG(PRCM_BASE + PRCM_O_PDSTAT1RFC) &
1093 PRCM_PDSTAT1RFC_ON) ? true : false);
1094 }
1095
1096
1097 //*****************************************************************************
1098 //
1099 //! \brief Put the processor into sleep mode.
1100 //!
1101 //! This function places the processor into sleep mode; it does not return
1102 //! until the processor returns to run mode. The peripherals that are enabled
1103 //! via PRCMPeripheralSleepEnable() continue to operate and can wake up the
1104 //! processor.
1105 //!
1106 //! \return None
1107 //!
1108 //! \sa \ref PRCMPeripheralSleepEnable()
1109 //
1110 //*****************************************************************************
1111 __STATIC_INLINE void
PRCMSleep(void)1112 PRCMSleep(void)
1113 {
1114 // Wait for an interrupt.
1115 CPUwfi();
1116 }
1117
1118 //*****************************************************************************
1119 //
1120 //! \brief Put the processor into deep-sleep mode.
1121 //!
1122 //! This function places the processor into deep-sleep mode; it does not return
1123 //! until the processor returns to run mode. The peripherals that are enabled
1124 //! via \ref PRCMPeripheralDeepSleepEnable() continue to operate and can wake up
1125 //! the processor.
1126 //!
1127 //! \return None
1128 //!
1129 //! \sa \ref PRCMPeripheralDeepSleepEnable()
1130 //
1131 //*****************************************************************************
1132 extern void PRCMDeepSleep(void);
1133
1134 //*****************************************************************************
1135 //
1136 //! \brief Enable CACHE RAM retention
1137 //!
1138 //! Enables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM
1139 //!
1140 //! \return None
1141 //
1142 //*****************************************************************************
1143 __STATIC_INLINE void
PRCMCacheRetentionEnable(void)1144 PRCMCacheRetentionEnable( void )
1145 {
1146 HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) |= PRCM_RAMRETEN_VIMS_M;
1147 }
1148
1149 //*****************************************************************************
1150 //
1151 //! \brief Disable CACHE RAM retention
1152 //!
1153 //! Disables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM
1154 //!
1155 //! \return None
1156 //
1157 //*****************************************************************************
1158 __STATIC_INLINE void
PRCMCacheRetentionDisable(void)1159 PRCMCacheRetentionDisable( void )
1160 {
1161 HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) &= ~PRCM_RAMRETEN_VIMS_M;
1162 }
1163
1164
1165 //*****************************************************************************
1166 //
1167 // Support for DriverLib in ROM:
1168 // Redirect to implementation in ROM when available.
1169 //
1170 //*****************************************************************************
1171 #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
1172 #include "../driverlib/rom.h"
1173 #ifdef ROM_PRCMInfClockConfigureSet
1174 #undef PRCMInfClockConfigureSet
1175 #define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet
1176 #endif
1177 #ifdef ROM_PRCMInfClockConfigureGet
1178 #undef PRCMInfClockConfigureGet
1179 #define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet
1180 #endif
1181 #ifdef ROM_PRCMAudioClockConfigSet
1182 #undef PRCMAudioClockConfigSet
1183 #define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet
1184 #endif
1185 #ifdef ROM_PRCMAudioClockConfigSetOverride
1186 #undef PRCMAudioClockConfigSetOverride
1187 #define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride
1188 #endif
1189 #ifdef ROM_PRCMAudioClockInternalSource
1190 #undef PRCMAudioClockInternalSource
1191 #define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource
1192 #endif
1193 #ifdef ROM_PRCMAudioClockExternalSource
1194 #undef PRCMAudioClockExternalSource
1195 #define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource
1196 #endif
1197 #ifdef ROM_PRCMPowerDomainOn
1198 #undef PRCMPowerDomainOn
1199 #define PRCMPowerDomainOn ROM_PRCMPowerDomainOn
1200 #endif
1201 #ifdef ROM_PRCMPowerDomainOff
1202 #undef PRCMPowerDomainOff
1203 #define PRCMPowerDomainOff ROM_PRCMPowerDomainOff
1204 #endif
1205 #ifdef ROM_PRCMPeripheralRunEnable
1206 #undef PRCMPeripheralRunEnable
1207 #define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable
1208 #endif
1209 #ifdef ROM_PRCMPeripheralRunDisable
1210 #undef PRCMPeripheralRunDisable
1211 #define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable
1212 #endif
1213 #ifdef ROM_PRCMPeripheralSleepEnable
1214 #undef PRCMPeripheralSleepEnable
1215 #define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable
1216 #endif
1217 #ifdef ROM_PRCMPeripheralSleepDisable
1218 #undef PRCMPeripheralSleepDisable
1219 #define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable
1220 #endif
1221 #ifdef ROM_PRCMPeripheralDeepSleepEnable
1222 #undef PRCMPeripheralDeepSleepEnable
1223 #define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable
1224 #endif
1225 #ifdef ROM_PRCMPeripheralDeepSleepDisable
1226 #undef PRCMPeripheralDeepSleepDisable
1227 #define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable
1228 #endif
1229 #ifdef ROM_PRCMPowerDomainsAllOff
1230 #undef PRCMPowerDomainsAllOff
1231 #define PRCMPowerDomainsAllOff ROM_PRCMPowerDomainsAllOff
1232 #endif
1233 #ifdef ROM_PRCMPowerDomainsAllOn
1234 #undef PRCMPowerDomainsAllOn
1235 #define PRCMPowerDomainsAllOn ROM_PRCMPowerDomainsAllOn
1236 #endif
1237 #ifdef ROM_PRCMDeepSleep
1238 #undef PRCMDeepSleep
1239 #define PRCMDeepSleep ROM_PRCMDeepSleep
1240 #endif
1241 #endif
1242
1243 //*****************************************************************************
1244 //
1245 // Mark the end of the C bindings section for C++ compilers.
1246 //
1247 //*****************************************************************************
1248 #ifdef __cplusplus
1249 }
1250 #endif
1251
1252 #endif // __PRCM_H__
1253
1254 //*****************************************************************************
1255 //
1256 //! Close the Doxygen group.
1257 //! @}
1258 //! @}
1259 //
1260 //*****************************************************************************
1261