1 /****************************************************************************** 2 * Filename: hw_nvic.h 3 * Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) 4 * Revision: 42365 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_NVIC_H__ 38 #define __HW_NVIC_H__ 39 40 //***************************************************************************** 41 // 42 // The following are defines for the NVIC register addresses. 43 // 44 //***************************************************************************** 45 #define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg 46 #define NVIC_ACTLR 0xE000E008 // Auxiliary Control 47 #define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status 48 // Register 49 #define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register 50 #define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register 51 #define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg 52 #define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable 53 #define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable 54 #define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable 55 #define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable 56 #define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending 57 #define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending 58 #define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending 59 #define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending 60 #define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit 61 #define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit 62 #define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority 63 #define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority 64 #define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority 65 #define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority 66 #define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority 67 #define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority 68 #define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority 69 #define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority 70 #define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority 71 #define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority 72 #define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority 73 #define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority 74 #define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority 75 #define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority 76 #define NVIC_CPUID 0xE000ED00 // CPU ID Base 77 #define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State 78 #define NVIC_VTABLE 0xE000ED08 // Vector Table Offset 79 #define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset 80 // Control 81 #define NVIC_SYS_CTRL 0xE000ED10 // System Control 82 #define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control 83 #define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 84 #define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 85 #define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 86 #define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State 87 #define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status 88 #define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status 89 #define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register 90 #define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address 91 #define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address 92 #define NVIC_MPU_TYPE 0xE000ED90 // MPU Type 93 #define NVIC_MPU_CTRL 0xE000ED94 // MPU Control 94 #define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number 95 #define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address 96 #define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size 97 #define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 98 #define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size 99 // Alias 1 100 #define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 101 #define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size 102 // Alias 2 103 #define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 104 #define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size 105 // Alias 3 106 #define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg 107 #define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select 108 #define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data 109 #define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control 110 #define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt 111 112 //***************************************************************************** 113 // 114 // The following are defines for the bit fields in the NVIC_INT_TYPE register. 115 // 116 //***************************************************************************** 117 #define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) 118 #define NVIC_INT_TYPE_LINES_S 0 119 120 //***************************************************************************** 121 // 122 // The following are defines for the bit fields in the NVIC_ACTLR register. 123 // 124 //***************************************************************************** 125 #define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding 126 #define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer 127 #define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple 128 // Cycle Instructions 129 130 //***************************************************************************** 131 // 132 // The following are defines for the bit fields in the NVIC_ST_CTRL register. 133 // 134 //***************************************************************************** 135 #define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag 136 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source 137 #define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable 138 #define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable 139 140 //***************************************************************************** 141 // 142 // The following are defines for the bit fields in the NVIC_ST_RELOAD register. 143 // 144 //***************************************************************************** 145 #define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value 146 #define NVIC_ST_RELOAD_S 0 147 148 //***************************************************************************** 149 // 150 // The following are defines for the bit fields in the NVIC_ST_CURRENT 151 // register. 152 // 153 //***************************************************************************** 154 #define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value 155 #define NVIC_ST_CURRENT_S 0 156 157 //***************************************************************************** 158 // 159 // The following are defines for the bit fields in the NVIC_ST_CAL register. 160 // 161 //***************************************************************************** 162 #define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock 163 #define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew 164 #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value 165 #define NVIC_ST_CAL_ONEMS_S 0 166 167 //***************************************************************************** 168 // 169 // The following are defines for the bit fields in the NVIC_EN0 register. 170 // 171 //***************************************************************************** 172 #define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable 173 #define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable 174 #define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable 175 #define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable 176 #define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable 177 #define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable 178 #define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable 179 #define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable 180 #define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable 181 #define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable 182 #define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable 183 #define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable 184 #define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable 185 #define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable 186 #define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable 187 #define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable 188 #define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable 189 #define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable 190 #define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable 191 #define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable 192 #define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable 193 #define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable 194 #define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable 195 #define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable 196 #define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable 197 #define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable 198 #define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable 199 #define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable 200 #define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable 201 #define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable 202 #define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable 203 #define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable 204 #define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable 205 206 //***************************************************************************** 207 // 208 // The following are defines for the bit fields in the NVIC_EN1 register. 209 // 210 //***************************************************************************** 211 #define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable 212 #define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable 213 #define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable 214 #define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable 215 #define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable 216 #define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable 217 #define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable 218 #define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable 219 #define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable 220 #define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable 221 #define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable 222 #define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable 223 #define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable 224 #define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable 225 #define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable 226 #define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable 227 #define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable 228 #define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable 229 #define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable 230 #define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable 231 #define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable 232 #define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable 233 #define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable 234 #define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable 235 236 //***************************************************************************** 237 // 238 // The following are defines for the bit fields in the NVIC_DIS0 register. 239 // 240 //***************************************************************************** 241 #define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable 242 #define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable 243 #define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable 244 #define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable 245 #define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable 246 #define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable 247 #define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable 248 #define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable 249 #define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable 250 #define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable 251 #define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable 252 #define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable 253 #define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable 254 #define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable 255 #define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable 256 #define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable 257 #define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable 258 #define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable 259 #define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable 260 #define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable 261 #define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable 262 #define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable 263 #define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable 264 #define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable 265 #define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable 266 #define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable 267 #define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable 268 #define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable 269 #define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable 270 #define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable 271 #define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable 272 #define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable 273 #define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable 274 275 //***************************************************************************** 276 // 277 // The following are defines for the bit fields in the NVIC_DIS1 register. 278 // 279 //***************************************************************************** 280 #define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable 281 #define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable 282 #define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable 283 #define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable 284 #define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable 285 #define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable 286 #define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable 287 #define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable 288 #define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable 289 #define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable 290 #define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable 291 #define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable 292 #define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable 293 #define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable 294 #define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable 295 #define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable 296 #define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable 297 #define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable 298 #define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable 299 #define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable 300 #define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable 301 #define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable 302 #define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable 303 #define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable 304 305 //***************************************************************************** 306 // 307 // The following are defines for the bit fields in the NVIC_PEND0 register. 308 // 309 //***************************************************************************** 310 #define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending 311 #define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend 312 #define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend 313 #define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend 314 #define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend 315 #define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend 316 #define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend 317 #define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend 318 #define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend 319 #define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend 320 #define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend 321 #define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend 322 #define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend 323 #define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend 324 #define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend 325 #define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend 326 #define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend 327 #define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend 328 #define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend 329 #define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend 330 #define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend 331 #define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend 332 #define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend 333 #define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend 334 #define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend 335 #define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend 336 #define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend 337 #define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend 338 #define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend 339 #define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend 340 #define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend 341 #define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend 342 #define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend 343 344 //***************************************************************************** 345 // 346 // The following are defines for the bit fields in the NVIC_PEND1 register. 347 // 348 //***************************************************************************** 349 #define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending 350 #define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend 351 #define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend 352 #define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend 353 #define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend 354 #define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend 355 #define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend 356 #define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend 357 #define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend 358 #define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend 359 #define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend 360 #define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend 361 #define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend 362 #define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend 363 #define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend 364 #define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend 365 #define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend 366 #define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend 367 #define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend 368 #define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend 369 #define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend 370 #define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend 371 #define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend 372 #define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend 373 374 //***************************************************************************** 375 // 376 // The following are defines for the bit fields in the NVIC_UNPEND0 register. 377 // 378 //***************************************************************************** 379 #define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending 380 #define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend 381 #define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend 382 #define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend 383 #define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend 384 #define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend 385 #define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend 386 #define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend 387 #define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend 388 #define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend 389 #define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend 390 #define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend 391 #define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend 392 #define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend 393 #define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend 394 #define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend 395 #define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend 396 #define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend 397 #define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend 398 #define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend 399 #define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend 400 #define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend 401 #define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend 402 #define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend 403 #define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend 404 #define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend 405 #define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend 406 #define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend 407 #define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend 408 #define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend 409 #define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend 410 #define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend 411 #define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend 412 413 //***************************************************************************** 414 // 415 // The following are defines for the bit fields in the NVIC_UNPEND1 register. 416 // 417 //***************************************************************************** 418 #define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending 419 #define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend 420 #define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend 421 #define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend 422 #define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend 423 #define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend 424 #define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend 425 #define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend 426 #define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend 427 #define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend 428 #define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend 429 #define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend 430 #define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend 431 #define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend 432 #define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend 433 #define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend 434 #define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend 435 #define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend 436 #define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend 437 #define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend 438 #define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend 439 #define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend 440 #define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend 441 #define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend 442 443 //***************************************************************************** 444 // 445 // The following are defines for the bit fields in the NVIC_ACTIVE0 register. 446 // 447 //***************************************************************************** 448 #define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active 449 #define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active 450 #define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active 451 #define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active 452 #define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active 453 #define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active 454 #define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active 455 #define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active 456 #define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active 457 #define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active 458 #define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active 459 #define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active 460 #define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active 461 #define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active 462 #define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active 463 #define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active 464 #define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active 465 #define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active 466 #define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active 467 #define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active 468 #define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active 469 #define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active 470 #define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active 471 #define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active 472 #define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active 473 #define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active 474 #define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active 475 #define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active 476 #define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active 477 #define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active 478 #define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active 479 #define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active 480 #define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active 481 482 //***************************************************************************** 483 // 484 // The following are defines for the bit fields in the NVIC_ACTIVE1 register. 485 // 486 //***************************************************************************** 487 #define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active 488 #define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active 489 #define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active 490 #define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active 491 #define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active 492 #define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active 493 #define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active 494 #define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active 495 #define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active 496 #define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active 497 #define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active 498 #define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active 499 #define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active 500 #define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active 501 #define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active 502 #define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active 503 #define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active 504 #define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active 505 #define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active 506 #define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active 507 #define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active 508 #define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active 509 #define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active 510 #define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active 511 512 //***************************************************************************** 513 // 514 // The following are defines for the bit fields in the NVIC_PRI0 register. 515 // 516 //***************************************************************************** 517 #define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask 518 #define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask 519 #define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask 520 #define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask 521 #define NVIC_PRI0_INT3_S 29 522 #define NVIC_PRI0_INT2_S 21 523 #define NVIC_PRI0_INT1_S 13 524 #define NVIC_PRI0_INT0_S 5 525 526 //***************************************************************************** 527 // 528 // The following are defines for the bit fields in the NVIC_PRI1 register. 529 // 530 //***************************************************************************** 531 #define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask 532 #define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask 533 #define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask 534 #define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask 535 #define NVIC_PRI1_INT7_S 29 536 #define NVIC_PRI1_INT6_S 21 537 #define NVIC_PRI1_INT5_S 13 538 #define NVIC_PRI1_INT4_S 5 539 540 //***************************************************************************** 541 // 542 // The following are defines for the bit fields in the NVIC_PRI2 register. 543 // 544 //***************************************************************************** 545 #define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask 546 #define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask 547 #define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask 548 #define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask 549 #define NVIC_PRI2_INT11_S 29 550 #define NVIC_PRI2_INT10_S 21 551 #define NVIC_PRI2_INT9_S 13 552 #define NVIC_PRI2_INT8_S 5 553 554 //***************************************************************************** 555 // 556 // The following are defines for the bit fields in the NVIC_PRI3 register. 557 // 558 //***************************************************************************** 559 #define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask 560 #define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask 561 #define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask 562 #define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask 563 #define NVIC_PRI3_INT15_S 29 564 #define NVIC_PRI3_INT14_S 21 565 #define NVIC_PRI3_INT13_S 13 566 #define NVIC_PRI3_INT12_S 5 567 568 //***************************************************************************** 569 // 570 // The following are defines for the bit fields in the NVIC_PRI4 register. 571 // 572 //***************************************************************************** 573 #define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask 574 #define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask 575 #define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask 576 #define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask 577 #define NVIC_PRI4_INT19_S 29 578 #define NVIC_PRI4_INT18_S 21 579 #define NVIC_PRI4_INT17_S 13 580 #define NVIC_PRI4_INT16_S 5 581 582 //***************************************************************************** 583 // 584 // The following are defines for the bit fields in the NVIC_PRI5 register. 585 // 586 //***************************************************************************** 587 #define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask 588 #define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask 589 #define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask 590 #define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask 591 #define NVIC_PRI5_INT23_S 29 592 #define NVIC_PRI5_INT22_S 21 593 #define NVIC_PRI5_INT21_S 13 594 #define NVIC_PRI5_INT20_S 5 595 596 //***************************************************************************** 597 // 598 // The following are defines for the bit fields in the NVIC_PRI6 register. 599 // 600 //***************************************************************************** 601 #define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask 602 #define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask 603 #define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask 604 #define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask 605 #define NVIC_PRI6_INT27_S 29 606 #define NVIC_PRI6_INT26_S 21 607 #define NVIC_PRI6_INT25_S 13 608 #define NVIC_PRI6_INT24_S 5 609 610 //***************************************************************************** 611 // 612 // The following are defines for the bit fields in the NVIC_PRI7 register. 613 // 614 //***************************************************************************** 615 #define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask 616 #define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask 617 #define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask 618 #define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask 619 #define NVIC_PRI7_INT31_S 29 620 #define NVIC_PRI7_INT30_S 21 621 #define NVIC_PRI7_INT29_S 13 622 #define NVIC_PRI7_INT28_S 5 623 624 //***************************************************************************** 625 // 626 // The following are defines for the bit fields in the NVIC_PRI8 register. 627 // 628 //***************************************************************************** 629 #define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask 630 #define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask 631 #define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask 632 #define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask 633 #define NVIC_PRI8_INT35_S 29 634 #define NVIC_PRI8_INT34_S 21 635 #define NVIC_PRI8_INT33_S 13 636 #define NVIC_PRI8_INT32_S 5 637 638 //***************************************************************************** 639 // 640 // The following are defines for the bit fields in the NVIC_PRI9 register. 641 // 642 //***************************************************************************** 643 #define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask 644 #define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask 645 #define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask 646 #define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask 647 #define NVIC_PRI9_INT39_S 29 648 #define NVIC_PRI9_INT38_S 21 649 #define NVIC_PRI9_INT37_S 13 650 #define NVIC_PRI9_INT36_S 5 651 652 //***************************************************************************** 653 // 654 // The following are defines for the bit fields in the NVIC_PRI10 register. 655 // 656 //***************************************************************************** 657 #define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask 658 #define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask 659 #define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask 660 #define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask 661 #define NVIC_PRI10_INT43_S 29 662 #define NVIC_PRI10_INT42_S 21 663 #define NVIC_PRI10_INT41_S 13 664 #define NVIC_PRI10_INT40_S 5 665 666 //***************************************************************************** 667 // 668 // The following are defines for the bit fields in the NVIC_PRI11 register. 669 // 670 //***************************************************************************** 671 #define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask 672 #define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask 673 #define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask 674 #define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask 675 #define NVIC_PRI11_INT47_S 29 676 #define NVIC_PRI11_INT46_S 21 677 #define NVIC_PRI11_INT45_S 13 678 #define NVIC_PRI11_INT44_S 5 679 680 //***************************************************************************** 681 // 682 // The following are defines for the bit fields in the NVIC_PRI12 register. 683 // 684 //***************************************************************************** 685 #define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask 686 #define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask 687 #define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask 688 #define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask 689 #define NVIC_PRI12_INT51_S 29 690 #define NVIC_PRI12_INT50_S 21 691 #define NVIC_PRI12_INT49_S 13 692 #define NVIC_PRI12_INT48_S 5 693 694 //***************************************************************************** 695 // 696 // The following are defines for the bit fields in the NVIC_PRI13 register. 697 // 698 //***************************************************************************** 699 #define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask 700 #define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask 701 #define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask 702 #define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask 703 #define NVIC_PRI13_INT55_S 29 704 #define NVIC_PRI13_INT54_S 21 705 #define NVIC_PRI13_INT53_S 13 706 #define NVIC_PRI13_INT52_S 5 707 708 //***************************************************************************** 709 // 710 // The following are defines for the bit fields in the NVIC_CPUID register. 711 // 712 //***************************************************************************** 713 #define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code 714 #define NVIC_CPUID_IMP_ARM 0x41000000 // ARM 715 #define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number 716 #define NVIC_CPUID_CON_M 0x000F0000 // Constant 717 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number 718 #define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor 719 #define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor 720 #define NVIC_CPUID_REV_M 0x0000000F // Revision Number 721 722 //***************************************************************************** 723 // 724 // The following are defines for the bit fields in the NVIC_INT_CTRL register. 725 // 726 //***************************************************************************** 727 #define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending 728 #define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending 729 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending 730 #define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending 731 #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending 732 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling 733 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending 734 #define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number 735 #undef NVIC_INT_CTRL_VEC_PEN_M 736 #define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number 737 #define NVIC_INT_CTRL_VEC_PEN_NMI \ 738 0x00002000 // NMI 739 #define NVIC_INT_CTRL_VEC_PEN_HARD \ 740 0x00003000 // Hard fault 741 #define NVIC_INT_CTRL_VEC_PEN_MEM \ 742 0x00004000 // Memory management fault 743 #define NVIC_INT_CTRL_VEC_PEN_BUS \ 744 0x00005000 // Bus fault 745 #define NVIC_INT_CTRL_VEC_PEN_USG \ 746 0x00006000 // Usage fault 747 #define NVIC_INT_CTRL_VEC_PEN_SVC \ 748 0x0000B000 // SVCall 749 #define NVIC_INT_CTRL_VEC_PEN_PNDSV \ 750 0x0000E000 // PendSV 751 #define NVIC_INT_CTRL_VEC_PEN_TICK \ 752 0x0000F000 // SysTick 753 #define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base 754 #define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number 755 #undef NVIC_INT_CTRL_VEC_ACT_M 756 #define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number 757 #define NVIC_INT_CTRL_VEC_PEN_S 12 758 #define NVIC_INT_CTRL_VEC_ACT_S 0 759 760 //***************************************************************************** 761 // 762 // The following are defines for the bit fields in the NVIC_VTABLE register. 763 // 764 //***************************************************************************** 765 #define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base 766 #define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset 767 #undef NVIC_VTABLE_OFFSET_M 768 #define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset 769 #define NVIC_VTABLE_OFFSET_S 9 770 #undef NVIC_VTABLE_OFFSET_S 771 #define NVIC_VTABLE_OFFSET_S 10 772 773 //***************************************************************************** 774 // 775 // The following are defines for the bit fields in the NVIC_APINT register. 776 // 777 //***************************************************************************** 778 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key 779 #define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key 780 #define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess 781 #define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping 782 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split 783 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split 784 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split 785 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split 786 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split 787 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split 788 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split 789 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split 790 #define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request 791 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault 792 #define NVIC_APINT_VECT_RESET 0x00000001 // System Reset 793 794 //***************************************************************************** 795 // 796 // The following are defines for the bit fields in the NVIC_SYS_CTRL register. 797 // 798 //***************************************************************************** 799 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending 800 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable 801 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit 802 803 //***************************************************************************** 804 // 805 // The following are defines for the bit fields in the NVIC_CFG_CTRL register. 806 // 807 //***************************************************************************** 808 #define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception 809 // Entry 810 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and 811 // Fault 812 #define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 813 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access 814 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger 815 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control 816 817 //***************************************************************************** 818 // 819 // The following are defines for the bit fields in the NVIC_SYS_PRI1 register. 820 // 821 //***************************************************************************** 822 #define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority 823 #define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority 824 #define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority 825 #define NVIC_SYS_PRI1_USAGE_S 21 826 #define NVIC_SYS_PRI1_BUS_S 13 827 #define NVIC_SYS_PRI1_MEM_S 5 828 829 //***************************************************************************** 830 // 831 // The following are defines for the bit fields in the NVIC_SYS_PRI2 register. 832 // 833 //***************************************************************************** 834 #define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority 835 #define NVIC_SYS_PRI2_SVC_S 29 836 837 //***************************************************************************** 838 // 839 // The following are defines for the bit fields in the NVIC_SYS_PRI3 register. 840 // 841 //***************************************************************************** 842 #define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority 843 #define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority 844 #define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority 845 #define NVIC_SYS_PRI3_TICK_S 29 846 #define NVIC_SYS_PRI3_PENDSV_S 21 847 #define NVIC_SYS_PRI3_DEBUG_S 5 848 849 //***************************************************************************** 850 // 851 // The following are defines for the bit fields in the NVIC_SYS_HND_CTRL 852 // register. 853 // 854 //***************************************************************************** 855 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable 856 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable 857 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable 858 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending 859 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending 860 #define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending 861 #define NVIC_SYS_HND_CTRL_USAGEP \ 862 0x00001000 // Usage Fault Pending 863 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active 864 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active 865 #define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active 866 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active 867 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active 868 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active 869 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active 870 871 //***************************************************************************** 872 // 873 // The following are defines for the bit fields in the NVIC_FAULT_STAT 874 // register. 875 // 876 //***************************************************************************** 877 #define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault 878 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault 879 #define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault 880 #define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault 881 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault 882 #define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage 883 // Fault 884 #define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid 885 #define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy 886 // State Preservation 887 #define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault 888 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault 889 #define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error 890 #define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error 891 #define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error 892 #define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address 893 // Register Valid 894 #define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on 895 // Floating-Point Lazy State 896 // Preservation 897 #define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation 898 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation 899 #define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation 900 #define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation 901 902 //***************************************************************************** 903 // 904 // The following are defines for the bit fields in the NVIC_HFAULT_STAT 905 // register. 906 // 907 //***************************************************************************** 908 #define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event 909 #define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault 910 #define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault 911 912 //***************************************************************************** 913 // 914 // The following are defines for the bit fields in the NVIC_DEBUG_STAT 915 // register. 916 // 917 //***************************************************************************** 918 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted 919 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch 920 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match 921 #define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction 922 #define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request 923 924 //***************************************************************************** 925 // 926 // The following are defines for the bit fields in the NVIC_MM_ADDR register. 927 // 928 //***************************************************************************** 929 #define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address 930 #define NVIC_MM_ADDR_S 0 931 932 //***************************************************************************** 933 // 934 // The following are defines for the bit fields in the NVIC_FAULT_ADDR 935 // register. 936 // 937 //***************************************************************************** 938 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address 939 #define NVIC_FAULT_ADDR_S 0 940 941 //***************************************************************************** 942 // 943 // The following are defines for the bit fields in the NVIC_DBG_CTRL register. 944 // 945 //***************************************************************************** 946 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask 947 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key 948 #define NVIC_DBG_CTRL_S_RESET_ST \ 949 0x02000000 // Core has reset since last read 950 #define NVIC_DBG_CTRL_S_RETIRE_ST \ 951 0x01000000 // Core has executed insruction 952 // since last read 953 #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up 954 #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping 955 #define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt 956 #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available 957 #define NVIC_DBG_CTRL_C_SNAPSTALL \ 958 0x00000020 // Breaks a stalled load/store 959 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping 960 #define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core 961 #define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core 962 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug 963 964 //***************************************************************************** 965 // 966 // The following are defines for the bit fields in the NVIC_DBG_XFER register. 967 // 968 //***************************************************************************** 969 #define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read 970 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register 971 #define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 972 #define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 973 #define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 974 #define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 975 #define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 976 #define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 977 #define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 978 #define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 979 #define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 980 #define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 981 #define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 982 #define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 983 #define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 984 #define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 985 #define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 986 #define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 987 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register 988 #define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP 989 #define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP 990 #define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP 991 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask 992 993 //***************************************************************************** 994 // 995 // The following are defines for the bit fields in the NVIC_DBG_DATA register. 996 // 997 //***************************************************************************** 998 #define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache 999 #define NVIC_DBG_DATA_S 0 1000 1001 //***************************************************************************** 1002 // 1003 // The following are defines for the bit fields in the NVIC_DBG_INT register. 1004 // 1005 //***************************************************************************** 1006 #define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault 1007 #define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors 1008 #define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error 1009 #define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state 1010 #define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check 1011 #define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error 1012 #define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault 1013 #define NVIC_DBG_INT_RESET 0x00000008 // Core reset status 1014 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset 1015 #define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending 1016 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch 1017 1018 //***************************************************************************** 1019 // 1020 // The following are defines for the bit fields in the NVIC_SW_TRIG register. 1021 // 1022 //***************************************************************************** 1023 #define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID 1024 #define NVIC_SW_TRIG_INTID_S 0 1025 1026 #endif // __HW_NVIC_H__ 1027
