1 /******************************************************************************
2 * Filename: setup_rom.c
3 * Revised: 2020-02-14 11:30:20 +0100 (Fri, 14 Feb 2020)
4 * Revision: 56760
5 *
6 * Description: Setup file for CC13xx/CC26xx devices.
7 *
8 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 ******************************************************************************/
38
39 // Hardware headers
40 #include "../inc/hw_types.h"
41 #include "../inc/hw_memmap.h"
42 #include "../inc/hw_adi.h"
43 #include "../inc/hw_adi_2_refsys.h"
44 #include "../inc/hw_adi_3_refsys.h"
45 #include "../inc/hw_adi_4_aux.h"
46 #include "../inc/hw_aon_batmon.h"
47 #include "../inc/hw_aux_sysif.h"
48 #include "../inc/hw_ccfg.h"
49 #include "../inc/hw_ddi_0_osc.h"
50 #include "../inc/hw_fcfg1.h"
51 // Driverlib headers
52 #include "ddi.h"
53 #include "ioc.h"
54 #include "osc.h"
55 #include "sys_ctrl.h"
56 #include "setup_rom.h"
57
58 //*****************************************************************************
59 //
60 // Handle support for DriverLib in ROM:
61 // This section will undo prototype renaming made in the header file
62 //
63 //*****************************************************************************
64 #if !defined(DOXYGEN)
65 #undef SetupAfterColdResetWakeupFromShutDownCfg1
66 #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1
67 #undef SetupAfterColdResetWakeupFromShutDownCfg2
68 #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2
69 #undef SetupAfterColdResetWakeupFromShutDownCfg3
70 #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3
71 #undef SetupGetTrimForAdcShModeEn
72 #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn
73 #undef SetupGetTrimForAdcShVbufEn
74 #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn
75 #undef SetupGetTrimForAmpcompCtrl
76 #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl
77 #undef SetupGetTrimForAmpcompTh1
78 #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1
79 #undef SetupGetTrimForAmpcompTh2
80 #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2
81 #undef SetupGetTrimForAnabypassValue1
82 #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1
83 #undef SetupGetTrimForDblrLoopFilterResetVoltage
84 #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage
85 #undef SetupGetTrimForRadcExtCfg
86 #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg
87 #undef SetupGetTrimForRcOscLfIBiasTrim
88 #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim
89 #undef SetupGetTrimForRcOscLfRtuneCtuneTrim
90 #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim
91 #undef SetupGetTrimForXoscHfCtl
92 #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl
93 #undef SetupGetTrimForXoscHfFastStart
94 #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart
95 #undef SetupGetTrimForXoscHfIbiastherm
96 #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm
97 #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
98 #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
99 #undef SetupSetCacheModeAccordingToCcfgSetting
100 #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting
101 #undef SetupSetAonRtcSubSecInc
102 #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc
103 #undef SetupStepVddrTrimTo
104 #define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo
105 #endif
106
107 //*****************************************************************************
108 //
109 // Function declarations
110 //
111 //*****************************************************************************
112
113 //*****************************************************************************
114 //
115 // SetupStepVddrTrimTo
116 //
117 //*****************************************************************************
118 void
SetupStepVddrTrimTo(uint32_t toCode)119 SetupStepVddrTrimTo( uint32_t toCode )
120 {
121 uint32_t pmctlResetctl_reg ;
122 int32_t targetTrim ;
123 int32_t currentTrim ;
124
125 targetTrim = SetupSignExtendVddrTrimValue( toCode & ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M >> ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ));
126 currentTrim = SetupSignExtendVddrTrimValue((
127 HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) &
128 ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >>
129 ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ;
130
131 if ( targetTrim != currentTrim ) {
132 pmctlResetctl_reg = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M );
133 if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) {
134 HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ( pmctlResetctl_reg & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M );
135 HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for VDDR_LOSS_EN setting to propagate
136 }
137
138 while ( targetTrim != currentTrim ) {
139 HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
140
141 if ( targetTrim > currentTrim ) currentTrim++;
142 else currentTrim--;
143
144 HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) = (
145 ( HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & ~ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) |
146 ((((uint32_t)currentTrim) << ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) &
147 ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) );
148 }
149
150 HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
151
152 if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) {
153 HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
154 HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
155 HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = pmctlResetctl_reg;
156 HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate
157 }
158 }
159 }
160
161 //*****************************************************************************
162 //
163 // SetupAfterColdResetWakeupFromShutDownCfg1
164 //
165 //*****************************************************************************
166 void
SetupAfterColdResetWakeupFromShutDownCfg1(uint32_t ccfg_ModeConfReg)167 SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg )
168 {
169 // Check for CC1352 boost mode
170 // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode
171 if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) &&
172 (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) )
173 {
174 // Set VDDS_BOD trim - using masked write {MASK8:DATA8}
175 // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1
176 // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to
177 // latch new VDDS BOD. Set to 0 first to guarantee a positive transition.
178 HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
179 //
180 // VDDS_BOD_LEVEL = 1 means that boost mode is selected
181 // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31)
182 HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) =
183 ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) |
184 ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ;
185 HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
186
187 SetupStepVddrTrimTo(( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) &
188 FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >>
189 FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ;
190 }
191
192 // 1.
193 // Do not allow DCDC to be enabled if in external regulator mode.
194 // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg).
195 //
196 // 2.
197 // Adjusted battery monitor low limit in internal regulator mode.
198 // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode.
199 if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) {
200 ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M );
201 } else {
202 HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0;
203 }
204
205 // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE
206 // Note: Inverse polarity
207 HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_EN_BITN ) =
208 ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 );
209
210 // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE
211 // Note: Inverse polarity
212 HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN ) =
213 ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 );
214 }
215
216 //*****************************************************************************
217 //
218 // SetupAfterColdResetWakeupFromShutDownCfg2
219 //
220 //*****************************************************************************
221 void
SetupAfterColdResetWakeupFromShutDownCfg2(uint32_t ui32Fcfg1Revision,uint32_t ccfg_ModeConfReg)222 SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg )
223 {
224 uint32_t ui32Trim;
225
226 // Following sequence is required for using XOSCHF, if not included
227 // devices crashes when trying to switch to XOSCHF.
228 //
229 // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1
230 // register
231 ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg );
232 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim);
233
234 // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and
235 // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register.
236 ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim();
237 DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL,
238 (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M |
239 DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M),
240 DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S,
241 ui32Trim);
242
243 // Trim XOSCHF IBIAS THERM. Get and set trim value for the
244 // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other
245 // register bit fields are set to 0.
246 ui32Trim = SetupGetTrimForXoscHfIbiastherm();
247 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2,
248 ui32Trim<<DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S);
249
250 // Trim AMPCOMP settings required before switch to XOSCHF
251 ui32Trim = SetupGetTrimForAmpcompTh2();
252 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH2, ui32Trim);
253 ui32Trim = SetupGetTrimForAmpcompTh1();
254 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH1, ui32Trim);
255 #if ( CCFG_BASE == CCFG_BASE_DEFAULT )
256 ui32Trim = SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision );
257 #else
258 ui32Trim = NOROM_SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision );
259 #endif
260 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPCTL, ui32Trim);
261
262 // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN in accordance to FCFG1 setting
263 // This is bit[5] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
264 // Using MASK4 write + 1 => writing to bits[7:4]
265 ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision );
266 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
267 ( 0x20 | ( ui32Trim << 1 ));
268
269 // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting
270 // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
271 // Using MASK4 write + 1 => writing to bits[7:4]
272 ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision );
273 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
274 ( 0x10 | ( ui32Trim ));
275
276 // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields
277 // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting.
278 // Remaining register bit fields are set to their reset values of 0.
279 ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision);
280 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim);
281
282 // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting
283 // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL)
284 // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4))
285 // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and
286 // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000)
287 ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision );
288 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) =
289 ( 0x60 | ( ui32Trim << 1 ));
290
291 // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from
292 // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM
293 // This is DDI_0_OSC_O_ATESTCTL bit[7]
294 // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020))
295 // Using MASK4 write + 1 => writing to bits[7:4]
296 ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision );
297 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) =
298 ( 0x80 | ( ui32Trim << 3 ));
299
300 // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and
301 // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write
302 // This can be simplified since the registers are packed together in the same
303 // order both in FCFG1 and in the HW register.
304 // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18]
305 // Using MASK8 write + 4 => writing to bits[23:16]
306 ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision );
307 HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) =
308 ( 0xFC00 | ( ui32Trim << 2 ));
309
310 // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit
311 // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting.
312 // Remaining register bit fields are set to their reset values of 0.
313 ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision);
314 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim);
315
316 }
317
318 //*****************************************************************************
319 //
320 // SetupAfterColdResetWakeupFromShutDownCfg3
321 //
322 //*****************************************************************************
323 void
SetupAfterColdResetWakeupFromShutDownCfg3(uint32_t ccfg_ModeConfReg)324 SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg )
325 {
326 uint32_t fcfg1OscConf;
327 uint32_t ui32Trim;
328 uint32_t currentHfClock;
329 uint32_t ccfgExtLfClk;
330
331 // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC
332 switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) {
333 case 2 :
334 // XOSC source is a 48 MHz crystal
335 // Do nothing (since this is the reset setting)
336 break;
337 case 1 :
338 // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC)
339
340 fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF );
341
342 if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) {
343 // This is a HPOSC chip, apply HPOSC settings
344 // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0)
345 HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN;
346
347 // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit)
348 // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits)
349 // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits)
350 // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit)
351 // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits)
352 // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits)
353 // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit)
354
355 HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) &
356 ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) |
357 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) |
358 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) );
359 HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) |
360 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) );
361 HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) &
362 ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) |
363 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) |
364 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) |
365 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) |
366 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) );
367 break;
368 }
369 // Not a HPOSC chip - fall through to default
370 default :
371 // XOSC source is a 24 MHz crystal (default)
372 // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0)
373 HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M;
374 break;
375 }
376
377 // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO
378 // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used.
379 if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) {
380 HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS;
381 }
382
383 // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0.
384 // This is typically already 0 except on Lizard where it is set in ROM-boot
385 HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN;
386
387 // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1
388 ui32Trim = SetupGetTrimForXoscHfFastStart();
389 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim );
390
391 // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION
392 switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) {
393 case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz)
394 OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF );
395 SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency
396 break;
397 case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT)
398 // Set SCLK_LF to use the same source as SCLK_HF
399 // Can be simplified a bit since possible return values for HF matches LF settings
400 currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF );
401 OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock );
402 while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) {
403 // Wait until switched
404 }
405 ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK );
406 SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S );
407 IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S,
408 IOC_PORT_AON_CLK32K,
409 IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis
410 // Set XOSC_LF in bypass mode to allow external 32 kHz clock
411 HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS;
412 // Fall through to set XOSC_LF as SCLK_LF source
413 case 2 : // XOSC_LF -> SLCK_LF (32768 Hz)
414 OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF );
415 break;
416 default : // (=3) RCOSC_LF
417 OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF );
418 break;
419 }
420
421 // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1
422 HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) =
423 ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >>
424 FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) <<
425 ADI_4_AUX_ADCREF1_VTRIM_S ) &
426 ADI_4_AUX_ADCREF1_VTRIM_M );
427
428 // Sync with AON
429 SysCtrlAonSync();
430 }
431
432 //*****************************************************************************
433 //
434 // SetupGetTrimForAnabypassValue1
435 //
436 //*****************************************************************************
437 uint32_t
SetupGetTrimForAnabypassValue1(uint32_t ccfg_ModeConfReg)438 SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg )
439 {
440 uint32_t ui32Fcfg1Value ;
441 uint32_t ui32XoscHfRow ;
442 uint32_t ui32XoscHfCol ;
443 uint32_t ui32TrimValue ;
444
445 // Use device specific trim values located in factory configuration
446 // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in
447 // the ANABYPASS_VALUE1 register. Value for the other bit fields
448 // are set to 0.
449
450 ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP);
451 ui32XoscHfRow = (( ui32Fcfg1Value &
452 FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >>
453 FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S );
454 ui32XoscHfCol = (( ui32Fcfg1Value &
455 FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >>
456 FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S );
457
458 if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) {
459 // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation
460 // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg
461 // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by
462 // a define and sign extension must therefore be hard coded.
463 // ( A small test program is created verifying the code lines below:
464 // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c)
465 int32_t i32CustomerDeltaAdjust =
466 (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S )))
467 >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W ));
468
469 while ( i32CustomerDeltaAdjust < 0 ) {
470 ui32XoscHfCol >>= 1; // COL 1 step down
471 if ( ui32XoscHfCol == 0 ) { // if COL below minimum
472 ui32XoscHfCol = 0xFFFF; // Set COL to maximum
473 ui32XoscHfRow >>= 1; // ROW 1 step down
474 if ( ui32XoscHfRow == 0 ) { // if ROW below minimum
475 ui32XoscHfRow = 1; // Set both ROW and COL
476 ui32XoscHfCol = 1; // to minimum
477 }
478 }
479 i32CustomerDeltaAdjust++;
480 }
481 while ( i32CustomerDeltaAdjust > 0 ) {
482 ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up
483 if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum
484 ui32XoscHfCol = 1; // Set COL to minimum
485 ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up
486 if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum
487 ui32XoscHfRow = 0xF; // Set both ROW and COL
488 ui32XoscHfCol = 0xFFFF; // to maximum
489 }
490 }
491 i32CustomerDeltaAdjust--;
492 }
493 }
494
495 ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) |
496 ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) );
497
498 return (ui32TrimValue);
499 }
500
501 //*****************************************************************************
502 //
503 // SetupGetTrimForRcOscLfRtuneCtuneTrim
504 //
505 //*****************************************************************************
506 uint32_t
SetupGetTrimForRcOscLfRtuneCtuneTrim(void)507 SetupGetTrimForRcOscLfRtuneCtuneTrim( void )
508 {
509 uint32_t ui32TrimValue;
510
511 // Use device specific trim values located in factory configuration
512 // area
513 ui32TrimValue =
514 ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
515 FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>>
516 FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<<
517 DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S;
518
519 ui32TrimValue |=
520 ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
521 FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>>
522 FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<<
523 DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S;
524
525 return(ui32TrimValue);
526 }
527
528 //*****************************************************************************
529 //
530 // SetupGetTrimForXoscHfIbiastherm
531 //
532 //*****************************************************************************
533 uint32_t
SetupGetTrimForXoscHfIbiastherm(void)534 SetupGetTrimForXoscHfIbiastherm( void )
535 {
536 uint32_t ui32TrimValue;
537
538 // Use device specific trim value located in factory configuration
539 // area
540 ui32TrimValue =
541 (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) &
542 FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>>
543 FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S;
544
545 return(ui32TrimValue);
546 }
547
548 //*****************************************************************************
549 //
550 // SetupGetTrimForAmpcompTh2
551 //
552 //*****************************************************************************
553 uint32_t
SetupGetTrimForAmpcompTh2(void)554 SetupGetTrimForAmpcompTh2( void )
555 {
556 uint32_t ui32TrimValue;
557 uint32_t ui32Fcfg1Value;
558
559 // Use device specific trim value located in factory configuration
560 // area. All defined register bit fields have corresponding trim
561 // value in the factory configuration area
562 ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2);
563 ui32TrimValue = ((ui32Fcfg1Value &
564 FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>>
565 FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<<
566 DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S;
567 ui32TrimValue |= (((ui32Fcfg1Value &
568 FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>>
569 FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<<
570 DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S);
571 ui32TrimValue |= (((ui32Fcfg1Value &
572 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>>
573 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<<
574 DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S);
575 ui32TrimValue |= (((ui32Fcfg1Value &
576 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>>
577 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<<
578 DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S);
579
580 return(ui32TrimValue);
581 }
582
583 //*****************************************************************************
584 //
585 // SetupGetTrimForAmpcompTh1
586 //
587 //*****************************************************************************
588 uint32_t
SetupGetTrimForAmpcompTh1(void)589 SetupGetTrimForAmpcompTh1( void )
590 {
591 uint32_t ui32TrimValue;
592 uint32_t ui32Fcfg1Value;
593
594 // Use device specific trim values located in factory configuration
595 // area. All defined register bit fields have a corresponding trim
596 // value in the factory configuration area
597 ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1);
598 ui32TrimValue = (((ui32Fcfg1Value &
599 FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>>
600 FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<<
601 DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S);
602 ui32TrimValue |= (((ui32Fcfg1Value &
603 FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>>
604 FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<<
605 DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S);
606 ui32TrimValue |= (((ui32Fcfg1Value &
607 FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>>
608 FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<<
609 DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S);
610 ui32TrimValue |= (((ui32Fcfg1Value &
611 FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>>
612 FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<<
613 DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S);
614
615 return(ui32TrimValue);
616 }
617
618 //*****************************************************************************
619 //
620 // SetupGetTrimForAmpcompCtrl
621 //
622 //*****************************************************************************
623 uint32_t
SetupGetTrimForAmpcompCtrl(uint32_t ui32Fcfg1Revision)624 SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision )
625 {
626 uint32_t ui32TrimValue ;
627 uint32_t ui32Fcfg1Value ;
628 uint32_t ibiasOffset ;
629 uint32_t ibiasInit ;
630 uint32_t modeConf1 ;
631 int32_t deltaAdjust ;
632
633 // Use device specific trim values located in factory configuration
634 // area. Register bit fields without trim values in the factory
635 // configuration area will be set to the value of 0.
636 ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 );
637
638 ibiasOffset = ( ui32Fcfg1Value &
639 FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >>
640 FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ;
641 ibiasInit = ( ui32Fcfg1Value &
642 FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >>
643 FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ;
644
645 if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) {
646 // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG
647 modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 );
648
649 // Both fields are signed 4-bit values. This is an assumption when doing the sign extension.
650 deltaAdjust =
651 (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S )))
652 >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W ));
653 deltaAdjust += (int32_t)ibiasOffset;
654 if ( deltaAdjust < 0 ) {
655 deltaAdjust = 0;
656 }
657 if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) {
658 deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S );
659 }
660 ibiasOffset = (uint32_t)deltaAdjust;
661
662 deltaAdjust =
663 (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S )))
664 >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W ));
665 deltaAdjust += (int32_t)ibiasInit;
666 if ( deltaAdjust < 0 ) {
667 deltaAdjust = 0;
668 }
669 if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) {
670 deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S );
671 }
672 ibiasInit = (uint32_t)deltaAdjust;
673 }
674 ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) |
675 ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ;
676
677 ui32TrimValue |= (((ui32Fcfg1Value &
678 FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>>
679 FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<<
680 DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S);
681 ui32TrimValue |= (((ui32Fcfg1Value &
682 FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>>
683 FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<<
684 DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S);
685 ui32TrimValue |= (((ui32Fcfg1Value &
686 FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>>
687 FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<<
688 DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S);
689
690 if ( ui32Fcfg1Revision >= 0x00000022 ) {
691 ui32TrimValue |= ((( ui32Fcfg1Value &
692 FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >>
693 FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) <<
694 DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S );
695 }
696
697 return(ui32TrimValue);
698 }
699
700 //*****************************************************************************
701 //
702 // SetupGetTrimForDblrLoopFilterResetVoltage
703 //
704 //*****************************************************************************
705 uint32_t
SetupGetTrimForDblrLoopFilterResetVoltage(uint32_t ui32Fcfg1Revision)706 SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision )
707 {
708 uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value
709
710 if ( ui32Fcfg1Revision >= 0x00000020 ) {
711 dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) &
712 FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >>
713 FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S;
714 }
715
716 return ( dblrLoopFilterResetVoltageValue );
717 }
718
719 //*****************************************************************************
720 //
721 // SetupGetTrimForAdcShModeEn
722 //
723 //*****************************************************************************
724 uint32_t
SetupGetTrimForAdcShModeEn(uint32_t ui32Fcfg1Revision)725 SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision )
726 {
727 uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting
728
729 if ( ui32Fcfg1Revision >= 0x00000022 ) {
730 getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
731 FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >>
732 FCFG1_OSC_CONF_ADC_SH_MODE_EN_S;
733 }
734
735 return ( getTrimForAdcShModeEnValue );
736 }
737
738 //*****************************************************************************
739 //
740 // SetupGetTrimForAdcShVbufEn
741 //
742 //*****************************************************************************
743 uint32_t
SetupGetTrimForAdcShVbufEn(uint32_t ui32Fcfg1Revision)744 SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision )
745 {
746 uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting
747
748 if ( ui32Fcfg1Revision >= 0x00000022 ) {
749 getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
750 FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >>
751 FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S;
752 }
753
754 return ( getTrimForAdcShVbufEnValue );
755 }
756
757 //*****************************************************************************
758 //
759 // SetupGetTrimForXoscHfCtl
760 //
761 //*****************************************************************************
762 uint32_t
SetupGetTrimForXoscHfCtl(uint32_t ui32Fcfg1Revision)763 SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision )
764 {
765 uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting
766 uint32_t fcfg1Data;
767
768 if ( ui32Fcfg1Revision >= 0x00000020 ) {
769 fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
770 getTrimForXoschfCtlValue =
771 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >>
772 FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) <<
773 DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S);
774
775 getTrimForXoschfCtlValue |=
776 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >>
777 FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) <<
778 DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S);
779
780 getTrimForXoschfCtlValue |=
781 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >>
782 FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) <<
783 DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S);
784 }
785
786 return ( getTrimForXoschfCtlValue );
787 }
788
789 //*****************************************************************************
790 //
791 // SetupGetTrimForXoscHfFastStart
792 //
793 //*****************************************************************************
794 uint32_t
SetupGetTrimForXoscHfFastStart(void)795 SetupGetTrimForXoscHfFastStart( void )
796 {
797 uint32_t ui32XoscHfFastStartValue ;
798
799 // Get value from FCFG1
800 ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
801 FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >>
802 FCFG1_OSC_CONF_XOSC_HF_FAST_START_S;
803
804 return ( ui32XoscHfFastStartValue );
805 }
806
807 //*****************************************************************************
808 //
809 // SetupGetTrimForRadcExtCfg
810 //
811 //*****************************************************************************
812 uint32_t
SetupGetTrimForRadcExtCfg(uint32_t ui32Fcfg1Revision)813 SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision )
814 {
815 uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting
816 uint32_t fcfg1Data;
817
818 if ( ui32Fcfg1Revision >= 0x00000020 ) {
819 fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
820 getTrimForRadcExtCfgValue =
821 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >>
822 FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) <<
823 DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S);
824
825 getTrimForRadcExtCfgValue |=
826 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >>
827 FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) <<
828 DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S);
829
830 getTrimForRadcExtCfgValue |=
831 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >>
832 FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) <<
833 DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S);
834 }
835
836 return ( getTrimForRadcExtCfgValue );
837 }
838
839 //*****************************************************************************
840 //
841 // SetupGetTrimForRcOscLfIBiasTrim
842 //
843 //*****************************************************************************
844 uint32_t
SetupGetTrimForRcOscLfIBiasTrim(uint32_t ui32Fcfg1Revision)845 SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision )
846 {
847 uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value
848
849 if ( ui32Fcfg1Revision >= 0x00000022 ) {
850 trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
851 FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >>
852 FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ;
853 }
854
855 return ( trimForRcOscLfIBiasTrimValue );
856 }
857
858 //*****************************************************************************
859 //
860 // SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
861 //
862 //*****************************************************************************
863 uint32_t
SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio(uint32_t ui32Fcfg1Revision)864 SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision )
865 {
866 uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields
867
868 if ( ui32Fcfg1Revision >= 0x00000022 ) {
869 trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
870 ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M |
871 FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >>
872 FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ;
873 }
874
875 return ( trimForXoscLfRegulatorAndCmirrwrRatioValue );
876 }
877
878 //*****************************************************************************
879 //
880 // SetupSetCacheModeAccordingToCcfgSetting
881 //
882 //*****************************************************************************
883 void
SetupSetCacheModeAccordingToCcfgSetting(void)884 SetupSetCacheModeAccordingToCcfgSetting( void )
885 {
886 // - Make sure to enable aggressive VIMS clock gating for power optimization
887 // Only for PG2 devices.
888 // - Enable cache prefetch enable as default setting
889 // (Slightly higher power consumption, but higher CPU performance)
890 // - IF ( CCFG_..._DIS_GPRAM == 1 )
891 // then: Enable cache (set cache mode = 1), even if set by ROM boot code
892 // (This is done because it's not set by boot code when running inside
893 // a debugger supporting the Halt In Boot (HIB) functionality).
894 // else: Set MODE_GPRAM if not already set (see inline comments as well)
895 uint32_t vimsCtlMode0 ;
896
897 while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) {
898 // Do nothing - wait for an eventual ongoing mode change to complete.
899 // (There should typically be no wait time here, but need to be sure)
900 }
901
902 // Note that Mode=0 is equal to MODE_GPRAM
903 vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M );
904
905
906 if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) {
907 // Enable cache (and hence disable GPRAM)
908 HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE );
909 } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) {
910 // GPRAM is enabled in CCFG but not selected
911 // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM
912 HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF );
913 while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) {
914 // Do nothing - wait for an eventual mode change to complete (This goes fast).
915 }
916 HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0;
917 } else {
918 // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set
919 HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0;
920 }
921 }
922
923 //*****************************************************************************
924 //
925 // SetupSetAonRtcSubSecInc
926 //
927 //*****************************************************************************
928 void
SetupSetAonRtcSubSecInc(uint32_t subSecInc)929 SetupSetAonRtcSubSecInc( uint32_t subSecInc )
930 {
931 // Loading a new RTCSUBSECINC value is done in 5 steps:
932 // 1. Write bit[15:0] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC0
933 // 2. Write bit[23:16] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC1
934 // 3. Set AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ
935 // 4. Wait for AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK
936 // 5. Clear AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ
937 HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_SYSIF_RTCSUBSECINC0_INC15_0_M );
938 HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_SYSIF_RTCSUBSECINC1_INC23_16_M );
939
940 HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ;
941 while( ! ( HWREGBITW( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL, AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN )));
942 HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = 0;
943 }
944
