1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18
19 /********************************************************************************************************
20 * @file rf.c
21 *
22 * @brief This is the source file for B91
23 *
24 * @author Driver Group
25 *
26 *******************************************************************************************************/
27 #include "rf.h"
28 #include "compiler.h"
29 #include "dma.h"
30
31
32 /**********************************************************************************************************************
33 * RF global constants *
34 *********************************************************************************************************************/
35 /**
36 * @brief The table of rf power level.
37 */
38 const rf_power_level_e rf_power_Level_list[30] =
39 {
40 /*VBAT*/
41 RF_POWER_P9p11dBm,
42 RF_POWER_P8p57dBm,
43 RF_POWER_P8p05dBm,
44 RF_POWER_P7p45dBm,
45 RF_POWER_P6p98dBm,
46 RF_POWER_P5p68dBm,
47 /*VANT*/
48 RF_POWER_P4p35dBm,
49 RF_POWER_P3p83dBm,
50 RF_POWER_P3p25dBm,
51 RF_POWER_P2p79dBm,
52 RF_POWER_P2p32dBm,
53 RF_POWER_P1p72dBm,
54 RF_POWER_P0p80dBm,
55 RF_POWER_P0p01dBm,
56 RF_POWER_N0p53dBm,
57 RF_POWER_N1p37dBm,
58 RF_POWER_N2p01dBm,
59 RF_POWER_N3p37dBm,
60 RF_POWER_N4p77dBm,
61 RF_POWER_N6p54dBm,
62 RF_POWER_N8p78dBm,
63 RF_POWER_N12p06dBm,
64 RF_POWER_N17p83dBm,
65 RF_POWER_N23p54dBm,
66 };
67
68 rf_mode_e g_rfmode;
69
70 /**********************************************************************************************************************
71 * global function implementation *
72 *********************************************************************************************************************/
73
74 /**
75 * @brief This function serves to initiate information of RF.
76 * @return none.
77 */
rf_mode_init(void)78 void rf_mode_init(void)
79 {
80 write_reg8(0x140ed2,0x9b);//DCOC_SFIIP DCOC_SFQQP
81 write_reg8(0x140ed3,0x19);//DCOC_SFQQ
82 #if RF_RX_SHORT_MODE_EN
83 write_reg8(0x140c7b,0x0e);//BLANK_WINDOW
84 #else
85 write_reg8(0x140c7b,0xfe);//BLANK_WINDOW
86 #endif
87
88 write_reg8(0x140e4a,0x0e);//POW_000_001
89 write_reg8(0x140e4b,0x09);//POW_001_010_H
90 write_reg8(0x140e4e,0x09);//POW_100_101 //POW_101_100_L
91 write_reg8(0x140e4f,0x0f);//POW_101_100_H
92 write_reg8(0x140e54,0x0e);//POW_001_010_L
93 write_reg8(0x140e55,0x09);//POW_001_010_H
94 write_reg8(0x140e56,0x0c);//POW_011_100_L
95 write_reg8(0x140e57,0x08);//POW_011_100_H
96 write_reg8(0x140e58,0x09);//POW_101_100_L
97 write_reg8(0x140e59,0x0f);//POW_101_100_H
98
99 write_reg8(0x140c76,0x50);//FREQ_CORR_CFG2_0
100 write_reg8(0x140c77,0x73);//FREQ_CORR_CFG2_1
101 #if RF_RX_SHORT_MODE_EN
102 write_reg8(0x14083a,0x86);//rx_ant_offset rx_dly(0x140c7b,0x140c79,0x14083a,0x14083b)
103 write_reg8(0x14083b,0x65);//samp_offset
104 #endif
105 analog_write_reg8(0x8b,0x04);//FREQ_CORR_CFG2_1
106 }
107
108 /**
109 * @brief This function serves to set zigbee_250K mode of RF.
110 * @return none.
111 */
rf_set_zigbee_250K_mode(void)112 void rf_set_zigbee_250K_mode(void)
113 {
114 write_reg8(0x140e3d,0x41);//ble:bw_code.
115 write_reg8(0x140e20,0x06);//sc_code.
116 write_reg8(0x140e21,0x2a);//if_freq,IF = 1Mhz,BW = 1Mhz.
117 write_reg8(0x140e22,0x43);//HPMC_EXP_DIFF_COUNT_L.
118 write_reg8(0x140e23,0x26);//HPMC_EXP_DIFF_COUNT_H.
119 write_reg8(0x140e3f,0x00);//250k modulation index:telink add rx for 250k/500k.
120 write_reg8(0x140c3f,0x00);//LOW_RATE_EN bit<1>:1 enable bit<2>:0 250k.
121 write_reg8(0x140c20,0x84);// script cc.
122
123 write_reg8(0x140c22,0x01);//modem:BLE_MODE_TX,2MBPS.
124 write_reg8(0x140c4e,0x18);//ble sync thre:To modem.
125 write_reg8(0x140c4d,0x0f);//r_rxchn_en_i:To modem.
126 write_reg8(0x140c21,0x01);//modem:ZIGBEE_MODE:01.
127 write_reg8(0x140c23,0x80);//modem:ZIGBEE_MODE_TX.
128 write_reg8(0x140c26,0x02);//modem:sync rst sel,for zigbee access code sync.
129 write_reg8(0x140c2a,0x10);//modem:disable MSK.
130 write_reg8(0x140c3d,0x01);//modem:zb_sfd_frm_ll.
131 write_reg8(0x140c2c,0x39);//modem:zb_dis_rst_pdet_isfd.
132 write_reg8(0x140c36,0xb7);//LR_NUM_GEAR_L.
133 write_reg8(0x140c37,0x0e);//LR_NUM_GEAR_H.
134 write_reg8(0x140c38,0xc4);//LR_TIM_EDGE_DEV.
135 write_reg8(0x140c39,0x71);//LR_TIM_REC_CFG_1.
136 write_reg8(0x140c73,0x01);//TOT_DEV_RST.
137
138 #if RF_RX_SHORT_MODE_EN
139 write_reg8(0x140c79,0x30);//RX_DIS_PDET_BLANK.
140 #else
141 write_reg8(0x140c79,0x00);//RX_DIS_PDET_BLANK.
142 #endif
143 write_reg8(0x140c9a,0x00);//tx_tp_align.
144 write_reg8(0x140cc2,0x36);//grx_0.
145 write_reg8(0x140cc3,0x48);//grx_1.
146 write_reg8(0x140cc4,0x54);//grx_2.
147 write_reg8(0x140cc5,0x62);//grx_3.
148 write_reg8(0x140cc6,0x6e);//grx_4.
149 write_reg8(0x140cc7,0x79);//grx_5.
150
151 write_reg8(0x140800,0x13);//tx_mode.
152 write_reg8(0x140801,0x00);//PN.
153 write_reg8(0x140802,0x42);//preamble len.
154 write_reg8(0x140803,0x44);//bit<0:1>private mode control. bit<2:3> tx mode.
155 write_reg8(0x140804,0xe0);//bit<4>mode:1->1m;bit<0:3>:ble head.
156 write_reg8(0x140805,0x04);//lr mode bit<4:5> 0:off,3:125k,2:500k.
157
158 write_reg32(0x140808,0x000000a7);//access code for zigbee 250K.
159 write_reg32(0x140810,0x000000d1);//access code for hybee 1m.
160 write_reg8(0x140818,0x95);//access code for hybee 2m.
161 write_reg8(0x140819,0x0c);//access code for hybee 500K.
162
163 write_reg8(0x140821,0x23);//rx packet len 0 enable.
164 write_reg8(0x140822,0x00);//rxchn_man_en.
165 write_reg8(0x140c4c,0x4c);//RX:acc_len modem.
166
167 g_rfmode = RF_MODE_ZIGBEE_250K;
168 }
169
170 /**
171 * @brief This function serves to set ble_1M mode of RF.
172 * @return none.
173 */
rf_set_ble_1M_mode(void)174 void rf_set_ble_1M_mode(void)
175 {
176 write_reg8(0x140e3d,0x61);//ble:bw_code.
177 write_reg8(0x140e20,0x16);//sc_code.
178 write_reg8(0x140e21,0x0a);//if_freq,IF = 1Mhz,BW = 1Mhz.
179 write_reg8(0x140e22,0x20);//HPMC_EXP_DIFF_COUNT_L.
180 write_reg8(0x140e23,0x23);//HPMC_EXP_DIFF_COUNT_H.
181 write_reg8(0x140e3f,0x00);//250k modulation index:telink add rx for 250k/500k.
182 write_reg8(0x140c3f,0x00);//LOW_RATE_EN bit<1>:1 enable bit<2>:0 250k.
183 write_reg8(0x140c20,0x84);// script cc.
184
185 write_reg8(0x140c22,0x00);//modem:BLE_MODE_TX,2MBPS.
186 write_reg8(0x140c4e,0x1e);//ble sync thre:To modem.
187 write_reg8(0x140c4d,0x01);//r_rxchn_en_i:To modem.
188 write_reg8(0x140c21,0x00);//modem:ZIGBEE_MODE:01.
189 write_reg8(0x140c23,0x00);//modem:ZIGBEE_MODE_TX.
190 write_reg8(0x140c26,0x00);//modem:sync rst sel,for zigbee access code sync.
191 write_reg8(0x140c2a,0x10);//modem:disable MSK.
192 write_reg8(0x140c3d,0x00);//modem:zb_sfd_frm_ll.
193 write_reg8(0x140c2c,0x38);//modem:zb_dis_rst_pdet_isfd.
194 write_reg8(0x140c36,0xb7);//LR_NUM_GEAR_L.
195 write_reg8(0x140c37,0x0e);//LR_NUM_GEAR_H.
196 write_reg8(0x140c38,0xc4);//LR_TIM_EDGE_DEV.
197 write_reg8(0x140c39,0x71);//LR_TIM_REC_CFG_1.
198 write_reg8(0x140c73,0x01);//TOT_DEV_RST.
199
200 #if RF_RX_SHORT_MODE_EN
201 write_reg8(0x140c79,0x38);//RX_DIS_PDET_BLANK.
202 #else
203 write_reg8(0x140c79,0x08);//RX_DIS_PDET_BLANK.
204 #endif
205 write_reg8(0x140c9a,0x00);//tx_tp_align.
206 write_reg8(0x140cc2,0x39);//grx_0.
207 write_reg8(0x140cc3,0x4b);//grx_1.
208 write_reg8(0x140cc4,0x56);//grx_2.
209 write_reg8(0x140cc5,0x62);//grx_3.
210 write_reg8(0x140cc6,0x6e);//grx_4.
211 write_reg8(0x140cc7,0x79);//grx_5.
212
213 write_reg8(0x140800,0x1f);//tx_mode.
214 write_reg8(0x140801,0x08);//PN.
215 write_reg8(0x140802,0x46);//preamble len 0x46 for ble confirmed by biao.li.20200828.
216 write_reg8(0x140803,0x44);//bit<0:1>private mode control. bit<2:3> tx mode.
217 write_reg8(0x140804,0xf5);//bit<4>mode:1->1m;bit<0:3>:ble head.
218 write_reg8(0x140805,0x04);//lr mode bit<4:5> 0:off,3:125k,2:500k.
219
220 write_reg8(0x140821,0xa1);//rx packet len 0 enable.
221 write_reg8(0x140822,0x00);//rxchn_man_en.
222 write_reg8(0x140c4c,0x4c);//RX:acc_len modem.
223
224 write_reg32(0x140808,0x00000000);
225 write_reg8(0x140830,0x36);
226 write_reg8(0x140a06,0x00);
227 write_reg8(0x140a0c,0x50);
228 write_reg8(0x140a0e,0x00);
229 write_reg8(0x140a10,0x00);
230
231 g_rfmode = RF_MODE_BLE_1M;
232 }
233
234 /**
235 * @brief This setting serve to set the configuration of Tx DMA.
236 */
237 dma_config_t rf_tx_dma_config={
238 .dst_req_sel= DMA_REQ_ZB_TX,//tx req.
239 .src_req_sel=0,
240 .dst_addr_ctrl=DMA_ADDR_FIX,
241 .src_addr_ctrl=DMA_ADDR_INCREMENT,//increment.
242 .dstmode=DMA_HANDSHAKE_MODE,//handshake.
243 .srcmode=DMA_NORMAL_MODE,
244 .dstwidth=DMA_CTR_WORD_WIDTH,//must word.
245 .srcwidth=DMA_CTR_WORD_WIDTH,//must word.
246 .src_burst_size=0,//must 0.
247 .vacant_bit=0,
248 .read_num_en=1,
249 .priority=0,
250 .write_num_en=0,
251 .auto_en=1,//must 1.
252 };
253
254 /**
255 * @brief This function serves to set RF tx DMA setting.
256 * @param[in] none
257 * @return none.
258 */
rf_set_tx_dma_config(void)259 void rf_set_tx_dma_config(void)
260 {
261 reg_rf_bb_auto_ctrl |= (FLD_RF_TX_MULTI_EN|FLD_RF_CH_0_RNUM_EN_BK);//u_pd_mcu.u_dmac.atcdmac100_ahbslv.tx_multi_en,rx_multi_en,ch_0_rnum_en_bk.
262 dma_config(DMA0,&rf_tx_dma_config);
263 dma_set_dst_address(DMA0,reg_rf_txdma_adr);
264 }
265
266 /**
267 * @brief This function serves to set RF tx DMA setting.
268 * @param[in] fifo_depth - tx chn deep.
269 * @param[in] fifo_byte_size - tx_idx_addr = {tx_chn_adr*bb_tx_size,4'b0}.
270 * @return none.
271 */
rf_set_tx_dma(unsigned char fifo_dep,unsigned short fifo_byte_size)272 void rf_set_tx_dma(unsigned char fifo_dep,unsigned short fifo_byte_size)
273 {
274 rf_set_tx_dma_config();
275 rf_set_tx_dma_fifo_num(fifo_dep);
276 rf_set_tx_dma_fifo_size(fifo_byte_size);
277
278 }
279
280 /**
281 * @brief This setting serve to set the configuration of Rx DMA.
282 * @note In this struct write_num_en must be 0;This seeting will cause the conflict of DMA.
283 */
284 dma_config_t rf_rx_dma_config={
285 .dst_req_sel= 0,//tx req.
286 .src_req_sel=DMA_REQ_ZB_RX,
287 .dst_addr_ctrl=0,
288 .src_addr_ctrl=DMA_ADDR_FIX,//increment.
289 .dstmode=DMA_NORMAL_MODE,
290 .srcmode=DMA_HANDSHAKE_MODE,//handshake.
291 .dstwidth=DMA_CTR_WORD_WIDTH,//must word.
292 .srcwidth=DMA_CTR_WORD_WIDTH,//must word.
293 .src_burst_size=0,//must 0.
294 .vacant_bit=0,
295 .read_num_en=0,
296 .priority=0,
297 .write_num_en=0,//must 0.
298 .auto_en=1,//must 1.
299 };
300
301 /**
302 * @brief This function serve to rx dma config
303 * @param[in] none
304 * @return none
305 */
rf_set_rx_dma_config(void)306 void rf_set_rx_dma_config(void)
307 {
308 reg_rf_bb_auto_ctrl |= (FLD_RF_RX_MULTI_EN|FLD_RF_CH_0_RNUM_EN_BK);//ch0_rnum_en_bk,tx_multi_en,rx_multi_en.
309 dma_config(DMA1,&rf_rx_dma_config);
310 dma_set_src_address(DMA1,reg_rf_rxdma_adr);
311 reg_dma_size(1)=0xffffffff;
312 }
313
314 /**
315 * @brief This function serves to rx dma setting.
316 * @param[in] buff - The buffer that store received packet.
317 * @param[in] wptr_mask - DMA fifo mask value (0~fif0_num-1).
318 * @param[in] fifo_byte_size - The length of one dma fifo.
319 * @return none.
320 */
rf_set_rx_dma(unsigned char * buff,unsigned char wptr_mask,unsigned short fifo_byte_size)321 void rf_set_rx_dma(unsigned char *buff,unsigned char wptr_mask,unsigned short fifo_byte_size)
322 {
323 rf_set_rx_dma_config();
324 rf_set_rx_buffer(buff);
325 rf_set_rx_dma_fifo_num(wptr_mask);
326 rf_set_rx_dma_fifo_size(fifo_byte_size);
327 }
328
329 volatile unsigned char g_single_tong_freqoffset = 0;//for eliminate single carrier frequency offset.
330
331 /**
332 * @brief This function serves to set RF baseband channel.This function is suitable for ble open PN mode.
333 * @param[in] chn_num - Bluetooth channel set according to Bluetooth protocol standard.
334 * @return none.
335 */
336
337
338 _attribute_ram_code_
rf_set_ble_chn(signed char chn_num)339 void rf_set_ble_chn (signed char chn_num)
340 {
341 write_reg8 (0x14080d, chn_num);
342 if (chn_num < 11)
343 chn_num += 2;
344 else if (chn_num < 37)
345 chn_num += 3;
346 else if (chn_num == 37)
347 chn_num = 1;
348 else if (chn_num == 38)
349 chn_num = 13;
350 else if (chn_num == 39)
351 chn_num = 40;
352 else if (chn_num < 51)
353 chn_num = chn_num;
354 else if(chn_num <= 61)
355 chn_num = -61 + chn_num;
356
357 chn_num = chn_num << 1;
358 rf_set_chn(chn_num);
359
360 }
361
362 /**
363 * @brief This function serves to set rf channel for all mode.The actual channel set by this function is 2400+chn.
364 * @param[in] chn - That you want to set the channel as 2400+chn.
365 * @return none.
366 */
367 _attribute_ram_code_
rf_set_chn(signed char chn)368 void rf_set_chn(signed char chn)
369 {
370 unsigned int freq_low;
371 unsigned int freq_high;
372 unsigned int chnl_freq;
373 unsigned char ctrim;
374 unsigned int freq;
375
376 freq = 2400+chn;
377 if(freq >= 2550){
378 ctrim = 0;
379 }
380 else if(freq >= 2520){
381 ctrim = 1;
382 }
383 else if(freq >= 2495){
384 ctrim = 2;
385 }
386 else if(freq >= 2465){
387 ctrim = 3;
388 }
389 else if(freq >= 2435){
390 ctrim = 4;
391 }
392 else if(freq >= 2405){
393 ctrim = 5;
394 }
395 else if(freq >= 2380){
396 ctrim = 6;
397 }
398 else{
399 ctrim = 7;
400 }
401
402 chnl_freq = freq*2 + g_single_tong_freqoffset;
403 freq_low = (chnl_freq & 0x7f);
404 freq_high = ((chnl_freq>>7)&0x3f);
405
406 write_reg8(0x140e44, (read_reg8(0x140e44) | 0x01 ));
407 write_reg8(0x140e44, (read_reg8(0x140e44) & 0x01) | freq_low << 1);
408 write_reg8(0x140e45, (read_reg8(0x140e45) & 0xc0) | freq_high);
409 write_reg8(0x140e29, (read_reg8(0x140e29) & 0x1f) | (ctrim<<5) ); //FE_CTRIM
410 }
411
412 /**
413 * @brief This function serves to get rssi.
414 * @return rssi value.
415 */
rf_get_rssi(void)416 signed char rf_get_rssi(void)
417 {
418 return (((signed char)(read_reg8(REG_TL_MODEM_BASE_ADDR+0x5d))) - 110);//this function can not tested on fpga
419 }
420
421 /**
422 * @brief This function serves to set RF Rx manual on.
423 * @return none.
424 */
rf_set_rxmode(void)425 void rf_set_rxmode(void)
426 {
427 reg_rf_ll_ctrl0 = 0x45;// reset tx/rx state machine.
428 reg_rf_modem_mode_cfg_rx1_0 |= FLD_RF_CONT_MODE;//set continue mode.
429 reg_rf_ll_ctrl0 |= FLD_RF_R_RX_EN_MAN;//rx enable.
430 reg_rf_rxmode |= FLD_RF_RX_ENABLE;//bb rx enable.
431
432
433 }
434
435 /**
436 * @brief This function serves to set RF Tx mode.
437 * @return none.
438 */
rf_set_txmode(void)439 void rf_set_txmode(void)
440 {
441 reg_rf_ll_ctrl0 = 0x45;// reset tx/rx state machine.
442 reg_rf_ll_ctrl0 |= FLD_RF_R_TX_EN_MAN;
443 reg_rf_rxmode &= (~FLD_RF_RX_ENABLE);
444 }
445
446 /**
447 * @brief This function serves to set RF Tx packet address to DMA src_addr.
448 * @param[in] addr - The packet address which to send.
449 * @return none.
450 */
rf_tx_pkt(void * addr)451 void rf_tx_pkt(void* addr)
452 {
453 dma_set_src_address(DMA0,convert_ram_addr_cpu2bus(addr));
454 reg_dma_ctr0(0) |= 0x01;
455 }
456
457 /**
458 * @brief This function serves to set RF power level.
459 * @param[in] level - The power level to set.
460 * @return none.
461 */
rf_set_power_level(rf_power_level_e level)462 void rf_set_power_level(rf_power_level_e level)
463 {
464 unsigned char value;
465 if(level&BIT(7))
466 {
467 reg_rf_mode_cfg_tx3_0 |= FLD_RF_MODE_VANT_TX_BLE;
468 }
469 else
470 {
471 reg_rf_mode_cfg_tx3_0 &= ~FLD_RF_MODE_VANT_TX_BLE;
472 }
473
474 value = (unsigned char)(level & 0x3F);
475 reg_rf_mode_cfg_txrx_0 = ((reg_rf_mode_cfg_txrx_0 & 0x7f) | ((value&0x01)<<7));
476 reg_rf_mode_cfg_txrx_1 = ((reg_rf_mode_cfg_txrx_1 & 0xe0) | ((value>>1)&0x1f));
477 }
478
479 /**
480 * @brief This function serves to start tx of auto mode. In this mode,
481 * RF module stays in tx status until a packet is sent or it fails to sent packet when timeout expires.
482 * Timeout duration is set by the parameter "tick".
483 * The address to store send data is set by the function "addr".
484 * @param[in] addr - The address to store send data.
485 * @param[in] tick - It indicates timeout duration in Rx status.Max value: 0xffffff (16777215).
486 * @return none.
487 */
rf_start_btx(void * addr,unsigned int tick)488 void rf_start_btx (void* addr, unsigned int tick)
489 {
490 write_reg32(0x80140a18, tick);
491 reg_rf_ll_ctrl3 |= FLD_RF_R_CMD_SCHDULE_EN; // Enable cmd_schedule mode.
492 dma_set_src_address(DMA0,convert_ram_addr_cpu2bus(addr));
493 write_reg8 (0x80140a00, 0x81); // ble tx.
494 }
495
496 /**
497 * @brief This function serves to start Rx of auto mode. In this mode,
498 * RF module stays in Rx status until a packet is received or it fails to receive packet when timeout expires.
499 * Timeout duration is set by the parameter "tick".
500 * The address to store received data is set by the function "addr".
501 * @param[in] addr - The address to store received data.
502 * @param[in] tick - It indicates timeout duration in Rx status.Max value: 0xffffff (16777215).
503 * @return none
504 */
rf_start_brx(void * addr,unsigned int tick)505 void rf_start_brx (void* addr, unsigned int tick)
506 {
507 write_reg32 (0x80140a28, 0x0fffffff);
508 write_reg32(0x80140a18, tick);
509 reg_rf_ll_ctrl3 |= FLD_RF_R_CMD_SCHDULE_EN; // Enable cmd_schedule mode.
510 dma_set_src_address(DMA0,convert_ram_addr_cpu2bus(addr));
511 write_reg8 (0x80140a00, 0x82);// ble rx.
512 }
513
514 /**
515 * @brief This function serves to RF trigger stx2rx.
516 * @param[in] addr - DMA tx buffer.
517 * @param[in] tick - Trigger tx send packet after tick delay.
518 * @return none.
519 */
rf_start_stx2rx(void * addr,unsigned int tick)520 void rf_start_stx2rx (void* addr, unsigned int tick)
521 {
522 dma_set_src_address(DMA0,convert_ram_addr_cpu2bus(addr));
523 write_reg32(0x80140a18, tick);
524 reg_rf_ll_ctrl3 |= FLD_RF_R_CMD_SCHDULE_EN; // Enable cmd_schedule mode.
525 write_reg8 (0x80140a00, 0x87); // single tx2rx.
526 }
527
528 /**
529 * @brief This function serves to RF trigger stx.
530 * @param[in] addr - DMA tx buffer.
531 * @param[in] tick - Trigger tx after tick delay.
532 * @return none.
533 */
rf_start_stx(void * addr,unsigned int tick)534 void rf_start_stx (void* addr, unsigned int tick)
535 {
536 dma_set_src_address(DMA0,convert_ram_addr_cpu2bus(addr));
537 reg_rf_ll_cmd_schedule = tick;
538 reg_rf_ll_ctrl3 |= FLD_RF_R_CMD_SCHDULE_EN; // Enable cmd_schedule mode.
539 reg_rf_ll_cmd = 0x85;
540 }
541
542 /**
543 * @brief This function serves to reset baseband
544 * @return none
545 */
rf_baseband_reset(void)546 void rf_baseband_reset(void)
547 {
548 reg_rst3 &= (~FLD_RST3_ZB); // reset baseband
549 reg_rst3 |= (FLD_RST3_ZB); // clr baseband
550 }
551
552 /**
553 * @brief This function serves to set RF power through select the level index.
554 * @param[in] idx - The index of power level which you want to set.
555 * @return none.
556 */
rf_set_power_level_index(rf_power_level_index_e idx)557 void rf_set_power_level_index(rf_power_level_index_e idx)
558 {
559 unsigned char value;
560 unsigned char level = 0;
561
562 if(idx < sizeof(rf_power_Level_list)/sizeof(rf_power_Level_list[0]))
563 {
564 level = rf_power_Level_list[idx];
565 }
566
567 if(level&BIT(7))
568 {
569 reg_rf_mode_cfg_tx3_0 |= FLD_RF_MODE_VANT_TX_BLE;
570 }
571 else
572 {
573 reg_rf_mode_cfg_tx3_0 &= ~FLD_RF_MODE_VANT_TX_BLE;
574 }
575
576 value = (unsigned char)(level & 0x3F);
577
578 reg_rf_mode_cfg_txrx_0 = ((reg_rf_mode_cfg_txrx_0 & 0x7f) | ((value&0x01)<<7));
579 reg_rf_mode_cfg_txrx_1 = ((reg_rf_mode_cfg_txrx_1 & 0xe0) | ((value>>1)&0x1f));
580
581 }
582
