1 /******************************************************************************
2  * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3  * All rights reserved.
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *   http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  *****************************************************************************/
18 
19 /********************************************************************************************************
20  * @file	analog_reg.h
21  *
22  * @brief	This is the header file for B91
23  *
24  * @author	Driver Group
25  *
26  *******************************************************************************************************/
27 #ifndef ANALOG_REG_H
28 #define ANALOG_REG_H
29 #include "../sys.h"
30 /*******************************      alg  registers: 140180      ******************************/
31 #define ALG_BASE_ADDR			   0x140180
32 #define reg_ana_addr			REG_ADDR8(ALG_BASE_ADDR)
33 #define reg_ana_ctrl			REG_ADDR8(ALG_BASE_ADDR+0x02)
34 enum
35 {
36 	//FLD_ANA_TX_EN         = BIT(0),
37 	FLD_ANA_RX_EN         = BIT(1),
38 	FLD_ANA_MASKX_TX_DONE = BIT(2),
39 	FLD_ANA_MASKX_RX_DONE = BIT(3),
40 	FLD_ANA_CONTIU_ACC    = BIT(4),
41 	FLD_ANA_RW            = BIT(5),   /**< 1:write,0:read */
42 	FLD_ANA_CYC           = BIT(6),
43 	FLD_ANA_BUSY          = BIT(7),
44 };
45 #define reg_ana_len             REG_ADDR8(ALG_BASE_ADDR+0x03)
46 #define reg_ana_data(n)			REG_ADDR8(ALG_BASE_ADDR+0x04+(n))
47 #define reg_ana_addr_data16		REG_ADDR16(ALG_BASE_ADDR+0x04)
48 #define reg_ana_addr_data32		REG_ADDR32(ALG_BASE_ADDR+0x04)
49 
50 #define reg_ana_sta             REG_ADDR8(ALG_BASE_ADDR+0x09)
51 enum
52 {
53 	FLD_ANA_RX_DONE    = BIT(7),
54 };
55 #define reg_ana_irq_sta         REG_ADDR8(ALG_BASE_ADDR+0x0a)
56 enum
57 {
58 	FLD_ANA_TXBUFF_IRQ    = BIT(0),
59 	FLD_ANA_RXBUFF_IRQ    = BIT(1),
60 };
61 #define reg_ana_dma_ctl         REG_ADDR8(ALG_BASE_ADDR+0x0b)
62 enum
63 {
64 	FLD_ANA_CYC1           = BIT(0),
65 	FLD_ANA_DMA_EN         = BIT(1),
66 
67 };
68 
69 #endif
70