1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBxx_HAL_PWR_EX_H 21 #define STM32WBxx_HAL_PWR_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbxx_hal_def.h" 29 30 /** @addtogroup STM32WBxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup PWREx PWREx 35 * @brief PWR Extended HAL module driver 36 * @{ 37 */ 38 39 40 /* Exported types ------------------------------------------------------------*/ 41 42 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief PWR PVM configuration structure definition 48 */ 49 typedef struct 50 { 51 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. 52 This parameter can be a value of @ref PWREx_PVM_Type. 53 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 54 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 55 */ 56 57 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 58 This parameter can be a value of @ref PWREx_PVM_Mode. */ 59 uint32_t WakeupTarget; /*!< Specifies the Wakeup Target 60 This parameter can be a value of @ref PWREx_WakeUpTarget_Definition */ 61 } PWR_PVMTypeDef; 62 63 #if defined(PWR_CR5_SMPSEN) 64 /** 65 * @brief PWR SMPS step down configuration structure definition 66 */ 67 typedef struct 68 { 69 uint32_t StartupCurrent; /*!< SMPS step down converter supply startup current selection. 70 This parameter can be a value of @ref PWREx_SMPS_STARTUP_CURRENT. */ 71 72 uint32_t OutputVoltage; /*!< SMPS step down converter output voltage scaling voltage level. 73 This parameter can be a value of @ref PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL */ 74 } PWR_SMPSTypeDef; 75 #endif /* PWR_CR5_SMPSEN */ 76 77 /** 78 * @} 79 */ 80 81 /* Exported constants --------------------------------------------------------*/ 82 83 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 84 * @{ 85 */ 86 87 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants 88 * @{ 89 */ 90 #define PWR_WUP_POLARITY_SHIFT 0x05U /*!< Internal constant used to retrieve wakeup pin polarity */ 91 /** 92 * @} 93 */ 94 95 96 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins 97 * @{ 98 */ 99 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 100 #if defined(PWR_CR3_EWUP2) 101 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 102 #endif /* PWR_CR3_EWUP2 */ 103 #if defined(PWR_CR3_EWUP3) 104 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 105 #endif /* PWR_CR3_EWUP3 */ 106 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 107 #if defined(PWR_CR3_EWUP5) 108 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 109 #endif /* PWR_CR3_EWUP5 */ 110 111 #define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ 112 #if defined(PWR_CR3_EWUP2) 113 #define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ 114 #endif /* PWR_CR3_EWUP2 */ 115 #if defined(PWR_CR3_EWUP3) 116 #define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ 117 #endif /* PWR_CR3_EWUP3 */ 118 #define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ 119 #if defined(PWR_CR3_EWUP5) 120 #define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ 121 #endif /* PWR_CR3_EWUP5 */ 122 /** 123 * @} 124 */ 125 126 /* Literals kept for legacy purpose */ 127 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 128 #if defined(PWR_CR3_EWUP2) 129 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 130 #endif /* PWR_CR3_EWUP2 */ 131 #if defined(PWR_CR3_EWUP3) 132 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 133 #endif /* PWR_CR3_EWUP3 */ 134 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 135 #if defined(PWR_CR3_EWUP5) 136 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 137 #endif /* PWR_CR3_EWUP5 */ 138 139 /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration 140 * @{ 141 */ 142 #define PWR_PIN_POLARITY_HIGH 0x00000000U 143 #define PWR_PIN_POLARITY_LOW 0x00000001U 144 /** 145 * @} 146 */ 147 148 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type 149 * @{ 150 */ 151 #if defined(PWR_CR2_PVME1) 152 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ 153 #endif /* PWR_CR2_PVME1 */ 154 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ 155 /** 156 * @} 157 */ 158 159 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode 160 * @{ 161 */ 162 #define PWR_PVM_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ 163 164 #define PWR_PVM_MODE_IT_RISING (PVM_MODE_IT | PVM_RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */ 165 #define PWR_PVM_MODE_IT_FALLING (PVM_MODE_IT | PVM_FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */ 166 #define PWR_PVM_MODE_IT_RISING_FALLING (PVM_MODE_IT | PVM_RISING_FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 167 168 #define PWR_PVM_MODE_EVENT_RISING (PVM_MODE_EVT | PVM_RISING_EDGE) /*!< Event Mode with Rising edge trigger detection */ 169 #define PWR_PVM_MODE_EVENT_FALLING (PVM_MODE_EVT | PVM_FALLING_EDGE) /*!< Event Mode with Falling edge trigger detection */ 170 #define PWR_PVM_MODE_EVENT_RISING_FALLING (PVM_MODE_EVT | PVM_RISING_FALLING_EDGE) /*!< Event Mode with Rising/Falling edge trigger detection */ 171 /** 172 * @} 173 */ 174 175 /** @defgroup PWREx_Flash_PowerDown Flash Power Down modes 176 * @{ 177 */ 178 #define PWR_FLASHPD_LPRUN PWR_CR1_FPDR /*!< Enable Flash power down in low power run mode */ 179 #define PWR_FLASHPD_LPSLEEP PWR_CR1_FPDS /*!< Enable Flash power down in low power sleep mode */ 180 /** 181 * @} 182 */ 183 184 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale 185 * @{ 186 */ 187 #if defined(PWR_CR1_VOS) 188 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */ 189 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz */ 190 #else 191 #define PWR_REGULATOR_VOLTAGE_SCALE1 (0x00000200UL) /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */ 192 #endif /* PWR_CR1_VOS */ 193 /** 194 * @} 195 */ 196 197 198 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection 199 * @{ 200 */ 201 #define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */ 202 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 203 /** 204 * @} 205 */ 206 207 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging 208 * @{ 209 */ 210 #define PWR_BATTERY_CHARGING_DISABLE (0x00000000U) 211 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE 212 /** 213 * @} 214 */ 215 216 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode 217 * @{ 218 */ 219 #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */ 220 #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */ 221 #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */ 222 #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */ 223 #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */ 224 #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */ 225 #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */ 226 #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */ 227 #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */ 228 #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */ 229 #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */ 230 #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */ 231 #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */ 232 #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 14 */ 233 #define PWR_GPIO_BIT_14 PWR_PDCRC_PC14 /*!< GPIO port I/O pin 14 */ 234 #define PWR_GPIO_BIT_15 PWR_PUCRC_PC15 /*!< GPIO port I/O pin 15 */ 235 /** 236 * @} 237 */ 238 239 /** @defgroup PWREx_GPIO GPIO port 240 * @{ 241 */ 242 #define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ 243 #define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ 244 #define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ 245 #if defined(GPIOD) 246 #define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ 247 #endif /* GPIOD */ 248 #define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ 249 #define PWR_GPIO_H 0x00000007U /*!< GPIO port H */ 250 /** 251 * @} 252 */ 253 254 #if defined(PWR_CR5_SMPSEN) 255 /** @defgroup PWREx_BOR_CONFIGURATION BOR configuration 256 * @{ 257 */ 258 #define PWR_BOR_SYSTEM_RESET (LL_PWR_BOR_SYSTEM_RESET) /*!< BOR will generate a system reset */ 259 #define PWR_BOR_SMPS_FORCE_BYPASS (LL_PWR_BOR_SMPS_FORCE_BYPASS) /*!< BOR will for SMPS step down converter in bypass mode */ 260 /** 261 * @} 262 */ 263 264 /** @defgroup PWREx_SMPS_OPERATING_MODES SMPS step down converter operating modes 265 * @{ 266 */ 267 /* Note: Literals values are defined from register SR2 bits SMPSF and SMPSBF */ 268 /* but they are also used as register CR5 bits SMPSEN and SMPSBEN, */ 269 /* as used by all SMPS operating mode functions targeting different */ 270 /* registers: */ 271 /* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */ 272 /* and "LL_PWR_SMPS_GetEffectiveMode()". */ 273 #define PWR_SMPS_BYPASS (PWR_SR2_SMPSBF) /*!< SMPS step down in bypass mode */ 274 #define PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF) /*!< SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. */ 275 /** 276 * @} 277 */ 278 279 /** @defgroup PWREx_SMPS_STARTUP_CURRENT SMPS step down converter supply startup current selection 280 * @{ 281 */ 282 #define PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U) /*!< SMPS step down converter supply startup current 80mA */ 283 #define PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 100mA */ 284 #define PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 120mA */ 285 #define PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 140mA */ 286 #define PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 ) /*!< SMPS step down converter supply startup current 160mA */ 287 #define PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 180mA */ 288 #define PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 200mA */ 289 #define PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 220mA */ 290 /** 291 * @} 292 */ 293 294 /** @defgroup PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL SMPS step down converter output voltage scaling voltage level 295 * @{ 296 */ 297 /* Note: SMPS voltage is trimmed during device production to control 298 the actual voltage level variation from device to device. */ 299 #define PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U) /*!< SMPS step down converter supply output voltage 1.20V */ 300 #define PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.25V */ 301 #define PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.30V */ 302 #define PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.35V */ 303 #define PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.40V */ 304 #define PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.45V */ 305 #define PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.50V */ 306 #define PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.55V */ 307 #define PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 ) /*!< SMPS step down converter supply output voltage 1.60V */ 308 #define PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.65V */ 309 #define PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.70V */ 310 #define PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.75V */ 311 #define PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.80V */ 312 #define PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.85V */ 313 #define PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.90V */ 314 /** 315 * @} 316 */ 317 #endif /* PWR_CR5_SMPSEN */ 318 319 /** @defgroup PWREx_Flag PWR Status Flags 320 * Elements values convention: 0000 0000 0XXY YYYYb 321 * - Y YYYY : Flag position in the XX register (5 bits) 322 * - XX : Status register (2 bits) 323 * - 01: SR1 register 324 * - 10: SR2 register 325 * - 11: EXTSCR register 326 * The only exception is PWR_FLAG_WUF, encompassing all 327 * wake-up flags and set to PWR_SR1_WUF. 328 * @{ 329 */ 330 /*--------------------------------SR1-------------------------------*/ 331 #define PWR_FLAG_WUF1 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF1_Pos) /*!< Wakeup event on wakeup pin 1 */ 332 #if defined(PWR_CR3_EWUP2) 333 #define PWR_FLAG_WUF2 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF2_Pos) /*!< Wakeup event on wakeup pin 2 */ 334 #endif /* PWR_CR3_EWUP2 */ 335 #if defined(PWR_CR3_EWUP3) 336 #define PWR_FLAG_WUF3 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF3_Pos) /*!< Wakeup event on wakeup pin 3 */ 337 #endif /* PWR_CR3_EWUP3 */ 338 #define PWR_FLAG_WUF4 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF4_Pos) /*!< Wakeup event on wakeup pin 4 */ 339 #if defined(PWR_CR3_EWUP5) 340 #define PWR_FLAG_WUF5 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF5_Pos) /*!< Wakeup event on wakeup pin 5 */ 341 #endif /* PWR_CR3_EWUP5 */ 342 #define PWR_FLAG_WU (PWR_FLAG_REG_SR1 | PWR_SR1_WUF) /*!< Encompass wakeup event on all wakeup pins */ 343 344 #if defined(PWR_CR5_SMPSEN) 345 #define PWR_FLAG_FRCBYPI (PWR_FLAG_REG_SR1 | PWR_SR1_SMPSFBF_Pos) /*!< SMPS Forced in Bypass Interrupt Flag */ 346 #endif /* PWR_CR5_SMPSEN */ 347 #define PWR_FLAG_BHWF (PWR_FLAG_REG_SR1 | PWR_SR1_BLEWUF_Pos) /*!< BLE_Host WakeUp Flag */ 348 #define PWR_FLAG_RFPHASEI (PWR_FLAG_REG_SR1 | PWR_SR1_CRPEF_Pos) /*!< Radio Phase Interrupt Flag */ 349 #define PWR_FLAG_BLEACTI (PWR_FLAG_REG_SR1 | PWR_SR1_BLEAF_Pos) /*!< BLE Activity Interrupt Flag */ 350 #define PWR_FLAG_802ACTI (PWR_FLAG_REG_SR1 | PWR_SR1_802AF_Pos) /*!< 802.15.4 Activity Interrupt Flag */ 351 #define PWR_FLAG_HOLDC2I (PWR_FLAG_REG_SR1 | PWR_SR1_C2HF_Pos) /*!< CPU2 on-Hold Interrupt Flag */ 352 #define PWR_FLAG_WUFI (PWR_FLAG_REG_SR1 | PWR_SR1_WUFI_Pos) /*!< Wakeup on internal wakeup line */ 353 354 /*--------------------------------SR2-------------------------------*/ 355 #if defined(PWR_CR5_SMPSEN) 356 #define PWR_FLAG_SMPSRDYF (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSBF_Pos) /*!< SMPS Ready Flag */ 357 #define PWR_FLAG_SMPSBYPF (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSF_Pos) /*!< SMPS Bypass Flag */ 358 #endif /* PWR_CR5_SMPSEN */ 359 360 #define PWR_FLAG_REGLPS (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPS_Pos) /*!< Low-power regulator start flag */ 361 #define PWR_FLAG_REGLPF (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPF_Pos) /*!< Low-power regulator flag */ 362 363 #if defined(PWR_CR1_VOS) 364 #define PWR_FLAG_VOSF (PWR_FLAG_REG_SR2 | PWR_SR2_VOSF_Pos) /*!< Voltage scaling flag */ 365 #endif /* PWR_CR1_VOS */ 366 #define PWR_FLAG_PVDO (PWR_FLAG_REG_SR2 | PWR_SR2_PVDO_Pos) /*!< Power Voltage Detector output flag */ 367 368 #if defined(PWR_CR2_PVME1) 369 #define PWR_FLAG_PVMO1 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO1_Pos) /*!< Power Voltage Monitoring 1 output flag */ 370 #endif /* PWR_CR2_PVME1 */ 371 #define PWR_FLAG_PVMO3 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO3_Pos) /*!< Power Voltage Monitoring 3 output flag */ 372 373 /*------------------------------EXTSCR---------------------------*/ 374 #define PWR_FLAG_SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1SBF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU1 */ 375 #define PWR_FLAG_STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1STOPF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop flag for CPU1 */ 376 377 #define PWR_FLAG_C2SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2SBF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU2 */ 378 #define PWR_FLAG_C2STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOPF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop flag for CPU2 */ 379 380 #define PWR_FLAG_CRITICAL_RF_PHASE (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_CRPF_Pos | (PWR_EXTSCR_CCRPF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< Critical radio system phase flag */ 381 #define PWR_FLAG_C1DEEPSLEEP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1DS_Pos) /*!< CPU1 DeepSleep Flag */ 382 #define PWR_FLAG_C2DEEPSLEEP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2DS_Pos) /*!< CPU2 DeepSleep Flag */ 383 /** 384 * @} 385 */ 386 387 /** @defgroup PWREx_WakeUpTarget_Definition PWR Wakeup Target Definition 388 * @{ 389 */ 390 #define PWR_WAKEUPTARGET_CPU1 (0x00000001U) 391 #define PWR_WAKEUPTARGET_CPU2 (0x00000002U) 392 #define PWR_WAKEUPTARGET_ALL_CPU (PWR_WAKEUPTARGET_CPU1 | PWR_WAKEUPTARGET_CPU2) 393 #define PWR_WAKEUPTARGET_RF (0x00000004U) 394 /** 395 * @} 396 */ 397 398 /** @defgroup PWREx_Core_Select PWREx Core definition 399 * @{ 400 */ 401 #define PWR_CORE_CPU1 (0x00000000U) 402 #define PWR_CORE_CPU2 (0x00000001U) 403 /** 404 * @} 405 */ 406 407 /** 408 * @} 409 */ 410 /* Private define ------------------------------------------------------------*/ 411 /** @defgroup PWR_Private_Defines PWR Private Defines 412 * @{ 413 */ 414 415 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines 416 * @{ 417 */ 418 #if defined(PWR_CR2_PVME1) 419 #define PWR_EXTI_LINE_PVM1 (LL_EXTI_LINE_31) /*!< External interrupt line 31 Connected to PVM1 */ 420 #endif /* PWR_CR2_PVME1 */ 421 #define PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_33) /*!< External interrupt line 33 Connected to PVM3 */ 422 /** 423 * @} 424 */ 425 426 /** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask 427 * @{ 428 */ 429 /* Note: On STM32WB series, power PVD event is not available on AIEC lines */ 430 /* (only interruption is available through AIEC line 16). */ 431 #define PVM_MODE_IT (0x00010000U) /*!< Mask for interruption yielded by PVM threshold crossing */ 432 #define PVM_MODE_EVT (0x00020000U) /*!< Mask for event yielded by PVM threshold crossing */ 433 #define PVM_RISING_EDGE (0x00000001U) /*!< Mask for rising edge set as PVM trigger */ 434 #define PVM_FALLING_EDGE (0x00000002U) /*!< Mask for falling edge set as PVM trigger */ 435 #define PVM_RISING_FALLING_EDGE (0x00000003U) /*!< Mask for rising and falling edges set as PVM trigger */ 436 /** 437 * @} 438 */ 439 440 /** @defgroup PWR_FLAG_REG PWR flag register 441 * @{ 442 */ 443 #define PWR_FLAG_REG_SR1 (0x20UL) /* Bitfield to indicate PWR flag located in register PWR_SR1 */ 444 #define PWR_FLAG_REG_SR2 (0x40UL) /* Bitfield to indicate PWR flag located in register PWR_SR2 */ 445 #define PWR_FLAG_REG_EXTSCR (0x60UL) /* Bitfield to indicate PWR flag located in register PWR_EXTSCR */ 446 #define PWR_FLAG_REG_MASK (PWR_FLAG_REG_SR1 | PWR_FLAG_REG_SR2 | PWR_FLAG_REG_EXTSCR) /* Bitfield mask to indicate PWR flag location in PWR register */ 447 #define PWR_FLAG_EXTSCR_CLR_POS (16UL) /* Bitfield for register PWR_EXTSCR clearable bits positions: position of bitfield in flag literals */ 448 #define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos | PWR_EXTSCR_C2CSSF_Pos | PWR_EXTSCR_CCRPF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */ 449 /** 450 * @} 451 */ 452 453 /** 454 * @} 455 */ 456 457 /* Exported macros -----------------------------------------------------------*/ 458 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 459 * @{ 460 */ 461 462 #if defined(PWR_CR2_PVME1) 463 /** 464 * @brief Enable the PVM1 Extended Interrupt C1 Line. 465 * @retval None 466 */ 467 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1) 468 469 /** 470 * @brief Enable the PVM1 Extended Interrupt C2 Line. 471 * @retval None 472 */ 473 #define __HAL_PWR_PVM1_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1) 474 475 /** 476 * @brief Disable the PVM1 Extended Interrupt C1 Line. 477 * @retval None 478 */ 479 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1) 480 481 /** 482 * @brief Disable the PVM1 Extended Interrupt C2 Line. 483 * @retval None 484 */ 485 #define __HAL_PWR_PVM1_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1) 486 487 /** 488 * @brief Enable the PVM1 Event C1 Line. 489 * @retval None 490 */ 491 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1) 492 493 /** 494 * @brief Enable the PVM1 Event C2 Line. 495 * @retval None 496 */ 497 #define __HAL_PWR_PVM1_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1) 498 499 /** 500 * @brief Disable the PVM1 Event C1 Line. 501 * @retval None 502 */ 503 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1) 504 505 /** 506 * @brief Disable the PVM1 Event C2 Line. 507 * @retval None 508 */ 509 #define __HAL_PWR_PVM1_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1) 510 511 /** 512 * @brief Enable the PVM1 Extended Interrupt Rising Trigger. 513 * @note PVM1 flag polarity is inverted compared to EXTI line, therefore 514 * EXTI rising and falling logic edges are inverted versus PVM1 voltage edges. 515 * @retval None 516 */ 517 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVM1) 518 519 /** 520 * @brief Disable the PVM1 Extended Interrupt Rising Trigger. 521 * @note PVM1 flag polarity is inverted compared to EXTI line, therefore 522 * EXTI rising and falling logic edges are inverted versus PVM1 voltage edges. 523 * @retval None 524 */ 525 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVM1) 526 527 /** 528 * @brief Enable the PVM1 Extended Interrupt Falling Trigger. 529 * @note PVM1 flag polarity is inverted compared to EXTI line, therefore 530 * EXTI rising and falling logic edges are inverted versus PVM1 voltage edges. 531 * @retval None 532 */ 533 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVM1) 534 535 536 /** 537 * @brief Disable the PVM1 Extended Interrupt Falling Trigger. 538 * @note PVM1 flag polarity is inverted compared to EXTI line, therefore 539 * EXTI rising and falling logic edges are inverted versus PVM1 voltage edges. 540 * @retval None 541 */ 542 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVM1) 543 544 /** 545 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. 546 * @retval None 547 */ 548 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 549 do { \ 550 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ 551 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ 552 } while(0) 553 554 /** 555 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. 556 * @retval None 557 */ 558 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 559 do { \ 560 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ 561 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ 562 } while(0) 563 564 /** 565 * @brief Generate a Software interrupt on selected EXTI line. 566 * @retval None 567 */ 568 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVM1) 569 570 /** 571 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. 572 * @retval EXTI PVM1 Line Status. 573 */ 574 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVM1) 575 576 /** 577 * @brief Clear the PVM1 EXTI flag. 578 * @retval None 579 */ 580 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVM1) 581 582 #endif /* PWR_CR2_PVME1 */ 583 584 /** 585 * @brief Enable the PVM3 Extended Interrupt C1 Line. 586 * @retval None 587 */ 588 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3) 589 590 /** 591 * @brief Enable the PVM3 Extended Interrupt C2 Line. 592 * @retval None 593 */ 594 #define __HAL_PWR_PVM3_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3) 595 596 /** 597 * @brief Disable the PVM3 Extended Interrupt C1 Line. 598 * @retval None 599 */ 600 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3) 601 602 /** 603 * @brief Disable the PVM3 Extended Interrupt C2 Line. 604 * @retval None 605 */ 606 #define __HAL_PWR_PVM3_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3) 607 608 /** 609 * @brief Enable the PVM3 Event C1 Line. 610 * @retval None 611 */ 612 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3) 613 614 /** 615 * @brief Enable the PVM3 Event C2 Line. 616 * @retval None 617 */ 618 #define __HAL_PWR_PVM3_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3) 619 620 /** 621 * @brief Disable the PVM3 Event C1 Line. 622 * @retval None 623 */ 624 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3) 625 626 /** 627 * @brief Disable the PVM3 Event C2 Line. 628 * @retval None 629 */ 630 #define __HAL_PWR_PVM3_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3) 631 632 /** 633 * @brief Enable the PVM3 Extended Interrupt Rising Trigger. 634 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 635 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 636 * @retval None 637 */ 638 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_32_63(PWR_EXTI_LINE_PVM3) 639 640 /** 641 * @brief Disable the PVM3 Extended Interrupt Rising Trigger. 642 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 643 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 644 * @retval None 645 */ 646 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_32_63(PWR_EXTI_LINE_PVM3) 647 648 /** 649 * @brief Enable the PVM3 Extended Interrupt Falling Trigger. 650 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 651 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 652 * @retval None 653 */ 654 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_32_63(PWR_EXTI_LINE_PVM3) 655 656 657 /** 658 * @brief Disable the PVM3 Extended Interrupt Falling Trigger. 659 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 660 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 661 * @retval None 662 */ 663 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_32_63(PWR_EXTI_LINE_PVM3) 664 665 /** 666 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. 667 * @retval None 668 */ 669 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ 670 do { \ 671 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ 672 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ 673 } while(0) 674 675 /** 676 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. 677 * @retval None 678 */ 679 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ 680 do { \ 681 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ 682 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ 683 } while(0) 684 685 /** 686 * @brief Generate a Software interrupt on selected EXTI line. 687 * @retval None 688 */ 689 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(PWR_EXTI_LINE_PVM3) 690 691 /** 692 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. 693 * @retval EXTI PVM3 Line Status. 694 */ 695 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() LL_EXTI_ReadFlag_32_63(PWR_EXTI_LINE_PVM3) 696 697 /** 698 * @brief Clear the PVM3 EXTI flag. 699 * @retval None 700 */ 701 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3) 702 703 #if defined(PWR_CR1_VOS) 704 /** 705 * @brief Configure the main internal regulator output voltage. 706 * @param __REGULATOR__ specifies the regulator output voltage to achieve 707 * a tradeoff between performance and power consumption. 708 * This parameter can be one of the following values: 709 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 710 * typical output voltage at 1.2 V, 711 * system frequency up to 64 MHz. 712 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 713 * typical output voltage at 1.0 V, 714 * system frequency up to 16 MHz. 715 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check 716 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User 717 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. 718 * @retval None 719 */ 720 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ 721 __IO uint32_t tmpreg; \ 722 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ 723 /* Delay after an RCC peripheral clock enabling */ \ 724 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ 725 UNUSED(tmpreg); \ 726 } while(0) 727 #endif /* PWR_CR1_VOS */ 728 729 /** 730 * @brief Wakeup BLE controller from its sleep mode 731 * @note This bit is automatically reset when 802.15.4 controller 732 * exit its sleep mode. 733 * @retval None 734 */ 735 #define __HAL_C2_PWR_WAKEUP_BLE() LL_C2_PWR_WakeUp_BLE() 736 737 /** 738 * @brief Wakeup 802.15.4 controller from its sleep mode 739 * @note This bit is automatically reset when 802.15.4 controller 740 * exit its sleep mode. 741 * @retval None 742 */ 743 #define __HAL_C2_PWR_WAKEUP_802_15_4() LL_C2_PWR_WakeUp_802_15_4() 744 745 /** 746 * @} 747 */ 748 749 /* Private macros --------------------------------------------------------*/ 750 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 751 * @{ 752 */ 753 #if defined(PWR_CR3_EWUP2) 754 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 755 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ 756 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ 757 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 758 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ 759 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 760 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ 761 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ 762 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ 763 ((PIN) == PWR_WAKEUP_PIN5_LOW)) 764 #else 765 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 766 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 767 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 768 ((PIN) == PWR_WAKEUP_PIN4_LOW)) 769 #endif /* PWR_CR3_EWUP2 */ 770 771 #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \ 772 ((POLARITY) == PWR_PIN_POLARITY_LOW)) 773 774 #if defined(PWR_CR2_PVME1) 775 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 776 ((TYPE) == PWR_PVM_3)) 777 #else 778 #define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_3) 779 #endif /* PWR_CR2_PVME1 */ 780 781 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 782 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 783 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 784 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 785 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 786 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 787 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 788 789 #define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00u) && \ 790 (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00u)) 791 792 #if defined(PWR_CR1_VOS) 793 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 794 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 795 #endif /* PWR_CR1_VOS */ 796 797 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 798 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 799 800 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ 801 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 802 803 804 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) 805 806 #if defined(GPIOD) 807 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 808 ((GPIO) == PWR_GPIO_B) ||\ 809 ((GPIO) == PWR_GPIO_C) ||\ 810 ((GPIO) == PWR_GPIO_D) ||\ 811 ((GPIO) == PWR_GPIO_E) ||\ 812 ((GPIO) == PWR_GPIO_H)) 813 #else 814 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 815 ((GPIO) == PWR_GPIO_B) ||\ 816 ((GPIO) == PWR_GPIO_C) ||\ 817 ((GPIO) == PWR_GPIO_E) ||\ 818 ((GPIO) == PWR_GPIO_H)) 819 #endif /* GPIOD */ 820 821 #if defined(PWR_CR5_SMPSEN) 822 #define IS_PWR_SMPS_MODE(SMPS_MODE) (((SMPS_MODE) == PWR_SMPS_BYPASS) ||\ 823 ((SMPS_MODE) == PWR_SMPS_STEP_DOWN)) 824 825 #define IS_PWR_SMPS_STARTUP_CURRENT(SMPS_STARTUP_CURRENT) (((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_80MA) ||\ 826 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_100MA) ||\ 827 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_120MA) ||\ 828 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_140MA) ||\ 829 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_160MA) ||\ 830 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_180MA) ||\ 831 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_200MA) ||\ 832 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_220MA)) 833 834 #define IS_PWR_SMPS_OUTPUT_VOLTAGE(SMPS_OUTPUT_VOLTAGE) (((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V20) ||\ 835 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V25) ||\ 836 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V30) ||\ 837 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V35) ||\ 838 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V40) ||\ 839 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V45) ||\ 840 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V50) ||\ 841 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V55) ||\ 842 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V60) ||\ 843 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V65) ||\ 844 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V70) ||\ 845 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V75) ||\ 846 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V80) ||\ 847 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V85) ||\ 848 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V90)) 849 #endif /* PWR_CR5_SMPSEN */ 850 851 #define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) 852 853 #define IS_PWR_CORE_HOLD_RELEASE(CPU) ((CPU) == PWR_CORE_CPU2) 854 855 /** 856 * @} 857 */ 858 859 860 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 861 * @{ 862 */ 863 864 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 865 * @{ 866 */ 867 868 /* Peripheral Control functions **********************************************/ 869 uint32_t HAL_PWREx_GetVoltageRange(void); 870 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 871 872 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); 873 void HAL_PWREx_DisableBatteryCharging(void); 874 875 void HAL_PWREx_EnableVddUSB(void); 876 void HAL_PWREx_DisableVddUSB(void); 877 878 void HAL_PWREx_EnableInternalWakeUpLine(void); 879 void HAL_PWREx_DisableInternalWakeUpLine(void); 880 881 #if defined(PWR_CR5_SMPSEN) 882 void HAL_PWREx_EnableBORH_SMPSBypassIT(void); 883 void HAL_PWREx_DisableBORH_SMPSBypassIT(void); 884 #endif /* PWR_CR5_SMPSEN */ 885 void HAL_PWREx_EnableRFPhaseIT(void); 886 void HAL_PWREx_DisableRFPhaseIT(void); 887 void HAL_PWREx_EnableBLEActivityIT(void); 888 void HAL_PWREx_DisableBLEActivityIT(void); 889 void HAL_PWREx_Enable802ActivityIT(void); 890 void HAL_PWREx_Disable802ActivityIT(void); 891 void HAL_PWREx_EnableHOLDC2IT(void); 892 void HAL_PWREx_DisableHOLDC2IT(void); 893 894 void HAL_PWREx_HoldCore(uint32_t CPU); 895 void HAL_PWREx_ReleaseCore(uint32_t CPU); 896 897 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 898 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 899 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 900 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 901 void HAL_PWREx_EnablePullUpPullDownConfig(void); 902 void HAL_PWREx_DisablePullUpPullDownConfig(void); 903 904 #if defined(PWR_CR5_SMPSEN) 905 void HAL_PWREx_SetBORConfig(uint32_t BORConfiguration); 906 uint32_t HAL_PWREx_GetBORConfig(void); 907 #endif /* PWR_CR5_SMPSEN */ 908 909 void HAL_PWREx_EnableSRAMRetention(void); 910 void HAL_PWREx_DisableSRAMRetention(void); 911 912 void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode); 913 void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); 914 915 #if defined(PWR_CR2_PVME1) 916 void HAL_PWREx_EnablePVM1(void); 917 void HAL_PWREx_DisablePVM1(void); 918 #endif /* PWR_CR2_PVME1 */ 919 920 void HAL_PWREx_EnablePVM3(void); 921 void HAL_PWREx_DisablePVM3(void); 922 923 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); 924 925 #if defined(PWR_CR5_SMPSEN) 926 HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS); 927 void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode); 928 uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void); 929 #endif /* PWR_CR5_SMPSEN */ 930 931 /* WakeUp pins configuration functions ****************************************/ 932 void HAL_PWREx_EnableWakeUpPin(uint32_t WakeUpPinPolarity, uint32_t wakeupTarget); 933 uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag); 934 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag); 935 936 /* Low Power modes configuration functions ************************************/ 937 void HAL_PWREx_EnableLowPowerRunMode(void); 938 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); 939 940 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); 941 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 942 #if defined(PWR_SUPPORT_STOP2) 943 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 944 #endif /* PWR_SUPPORT_STOP2 */ 945 void HAL_PWREx_EnterSHUTDOWNMode(void); 946 947 void HAL_PWREx_PVD_PVM_IRQHandler(void); 948 949 #if defined(PWR_CR2_PVME1) 950 void HAL_PWREx_PVM1Callback(void); 951 #endif /* PWR_CR2_PVME1 */ 952 void HAL_PWREx_PVM3Callback(void); 953 954 /** 955 * @} 956 */ 957 958 /** 959 * @} 960 */ 961 962 /** 963 * @} 964 */ 965 966 /** 967 * @} 968 */ 969 970 #ifdef __cplusplus 971 } 972 #endif 973 974 975 #endif /* STM32WBxx_HAL_PWR_EX_H */ 976 977
