1 /**
2   ******************************************************************************
3   * @file    stm32wbaxx_hal_cortex.c
4   * @author  MCD Application Team
5   * @brief   CORTEX HAL module driver.
6   *          This file provides firmware functions to manage the following
7   *          functionalities of the CORTEX:
8   *           + Initialization and Configuration functions
9   *           + Peripheral Control functions
10   ******************************************************************************
11   * @attention
12   *
13   * Copyright (c) 2022 STMicroelectronics.
14   * All rights reserved.
15   *
16   * This software is licensed under terms that can be found in the LICENSE file
17   * in the root directory of this software component.
18   * If no LICENSE file comes with this software, it is provided AS-IS.
19   *
20   ******************************************************************************
21   @verbatim
22   ==============================================================================
23                         ##### How to use this driver #####
24   ==============================================================================
25 
26     [..]
27     *** How to configure Interrupts using CORTEX HAL driver ***
28     ===========================================================
29     [..]
30     This section provides functions allowing to configure the NVIC interrupts (IRQ).
31     The Cortex-M33 exceptions are managed by CMSIS functions.
32 
33     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
34     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
35     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
36 
37      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
38          The pending IRQ priority will be managed only by the sub priority.
39 
40      -@- IRQ priority order (sorted by highest to lowest priority):
41         (+@) Lowest pre-emption priority
42         (+@) Lowest sub priority
43         (+@) Lowest hardware priority (IRQ number)
44 
45     [..]
46     *** How to configure SysTick using CORTEX HAL driver ***
47     ========================================================
48     [..]
49     Setup SysTick Timer for time base.
50 
51     (+) The SysTick clock source shall be configured with HAL_SYSTICK_CLKSourceConfig().
52 
53     (+) The SysTick IRQ priority shall be configured with HAL_NVIC_SetPriority(SysTick_IRQn,...).
54         The HAL_NVIC_SetPriority() calls the CMSIS NVIC_SetPriority() function.
55 
56     (+) The HAL_SYSTICK_Config() function:
57         (++) Configures the SysTick Reload register with the value passed as function parameter.
58         (++) Resets the SysTick Counter register.
59         (++) Enables the SysTick Interrupt.
60         (++) Starts the SysTick Counter.
61 
62     (+) To adjust the SysTick time base, use the following formula:
63 
64         Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
65         (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
66         (++) Reload Value should not exceed 0xFFFFFF
67 
68     (+) In case the HAL time base is the SysTick Timer, the HAL time base configuration must be completed
69         by calling the HAL_InitTick() function.
70 
71     [..]
72     *** How to configure MPU regions using CORTEX HAL driver ***
73     ============================================================
74     [..]
75     This section provides functions allowing to configure the Memory Protection Unit (MPU).
76 
77     (#) Disable the MPU using HAL_MPU_Disable().
78     (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes().
79     (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to
80         the right MPU attributes number.
81     (#) Enable the MPU using HAL_MPU_Enable() function.
82 
83      -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory
84          management fault handler MemManage_Handler() when an illegal memory access is performed.
85      -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration
86          from affecting the new MPU configuration.
87      -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context
88          and the same sequence as above applies to configure the non-secure MPU.
89 
90   @endverbatim
91   ******************************************************************************
92 
93   The table below gives the allowed values of the pre-emption priority and subpriority according
94   to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
95 
96     ==========================================================================================================================
97       NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
98     ==========================================================================================================================
99      NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bit for pre-emption priority
100                            |                                   |                             | 4 bits for subpriority
101     --------------------------------------------------------------------------------------------------------------------------
102      NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bit for pre-emption priority
103                            |                                   |                             | 3 bits for subpriority
104     --------------------------------------------------------------------------------------------------------------------------
105      NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
106                            |                                   |                             | 2 bits for subpriority
107     --------------------------------------------------------------------------------------------------------------------------
108      NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
109                            |                                   |                             | 1 bit for subpriority
110     --------------------------------------------------------------------------------------------------------------------------
111      NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
112                            |                                   |                             | 0 bit for subpriority
113     ==========================================================================================================================
114 
115   ******************************************************************************
116   */
117 
118 /* Includes ------------------------------------------------------------------*/
119 #include "stm32wbaxx_hal.h"
120 
121 /** @addtogroup STM32WBAxx_HAL_Driver
122   * @{
123   */
124 
125 /** @addtogroup CORTEX
126   * @{
127   */
128 
129 #ifdef HAL_CORTEX_MODULE_ENABLED
130 
131 /* Private types -------------------------------------------------------------*/
132 /* Private variables ---------------------------------------------------------*/
133 /* Private constants ---------------------------------------------------------*/
134 /* Private macros ------------------------------------------------------------*/
135 /* Private functions ---------------------------------------------------------*/
136 static void MPU_ConfigRegion(MPU_Type *MPUx, MPU_Region_InitTypeDef *MPU_RegionInit);
137 static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, MPU_Attributes_InitTypeDef *MPU_AttributesInit);
138 /* Exported functions --------------------------------------------------------*/
139 
140 /** @addtogroup CORTEX_Exported_Functions
141   * @{
142   */
143 
144 
145 /** @addtogroup CORTEX_Exported_Functions_Group1
146   *  @brief    Initialization and Configuration functions
147   *
148 @verbatim
149   ==============================================================================
150               ##### Initialization and Configuration functions #####
151   ==============================================================================
152     [..]
153       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
154       SysTick functionalities
155 
156 @endverbatim
157   * @{
158   */
159 
160 
161 /**
162   * @brief  Set the priority grouping field (pre-emption priority and subpriority)
163   *         using the required unlock sequence.
164   * @param  PriorityGroup: The priority grouping bits length.
165   *         This parameter can be one of the following values:
166   *         @arg NVIC_PRIORITYGROUP_0: 0 bit  for pre-emption priority,
167   *                                    4 bits for subpriority
168   *         @arg NVIC_PRIORITYGROUP_1: 1 bit  for pre-emption priority,
169   *                                    3 bits for subpriority
170   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
171   *                                    2 bits for subpriority
172   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
173   *                                    1 bit  for subpriority
174   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
175   *                                    0 bit  for subpriority
176   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
177   *         The pending IRQ priority will be managed only by the subpriority.
178   * @retval None
179   */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)180 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
181 {
182   /* Check the parameters */
183   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
184 
185   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
186   NVIC_SetPriorityGrouping(PriorityGroup);
187 }
188 
189 /**
190   * @brief  Set the priority of an interrupt.
191   * @param  IRQn: External interrupt number.
192   *         This parameter can be an enumerator of IRQn_Type enumeration
193   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h))
194   * @param  PreemptPriority: The pre-emption priority for the IRQn channel.
195   *         This parameter can be a value between 0 and 15
196   *         A lower priority value indicates a higher priority
197   * @param  SubPriority: the subpriority level for the IRQ channel.
198   *         This parameter can be a value between 0 and 15
199   *         A lower priority value indicates a higher priority.
200   * @retval None
201   */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)202 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
203 {
204   uint32_t prioritygroup;
205 
206   prioritygroup = (NVIC_GetPriorityGrouping() & 0x7U);
207 
208   /* Check the parameters */
209   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority, prioritygroup));
210   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority, prioritygroup));
211 
212   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
213 }
214 
215 /**
216   * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
217   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
218   *         function should be called before.
219   * @param  IRQn External interrupt number.
220   *         This parameter can be an enumerator of IRQn_Type enumeration
221   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h))
222   * @retval None
223   */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)224 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
225 {
226   /* Check the parameters */
227   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
228 
229   /* Enable interrupt */
230   NVIC_EnableIRQ(IRQn);
231 }
232 
233 /**
234   * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
235   * @param  IRQn External interrupt number.
236   *         This parameter can be an enumerator of IRQn_Type enumeration
237   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h))
238   * @retval None
239   */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)240 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
241 {
242   /* Check the parameters */
243   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
244 
245   /* Disable interrupt */
246   NVIC_DisableIRQ(IRQn);
247 }
248 
249 /**
250   * @brief  Initiate a system reset request to reset the MCU.
251   * @retval None
252   */
HAL_NVIC_SystemReset(void)253 void HAL_NVIC_SystemReset(void)
254 {
255   /* System Reset */
256   NVIC_SystemReset();
257 }
258 
259 /**
260   * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
261   *         Counter is in free running mode to generate periodic interrupts.
262   * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
263   * @retval status:  - 0  Function succeeded.
264   *                  - 1  Function failed.
265   */
HAL_SYSTICK_Config(uint32_t TicksNumb)266 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
267 {
268   if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk)
269   {
270     /* Reload value impossible */
271     return (1UL);
272   }
273 
274   /* Set reload register */
275   WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL));
276 
277   /* Load the SysTick Counter Value */
278   WRITE_REG(SysTick->VAL, 0UL);
279 
280   /* Enable SysTick IRQ and SysTick Timer */
281   SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk));
282 
283   /* Function successful */
284   return (0UL);
285 }
286 /**
287   * @}
288   */
289 
290 /** @addtogroup CORTEX_Exported_Functions_Group2
291   *  @brief   Cortex control functions
292   *
293 @verbatim
294   ==============================================================================
295                       ##### Peripheral Control functions #####
296   ==============================================================================
297     [..]
298       This subsection provides a set of functions allowing to control the CORTEX
299       (NVIC, SYSTICK, MPU) functionalities.
300 
301 
302 @endverbatim
303   * @{
304   */
305 
306 /**
307   * @brief  Get the priority grouping field from the NVIC Interrupt Controller.
308   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
309   */
HAL_NVIC_GetPriorityGrouping(void)310 uint32_t HAL_NVIC_GetPriorityGrouping(void)
311 {
312   /* Get the PRIGROUP[10:8] field value */
313   return NVIC_GetPriorityGrouping();
314 }
315 
316 /**
317   * @brief  Get the priority of an interrupt.
318   * @param  IRQn: External interrupt number.
319   *         This parameter can be an enumerator of IRQn_Type enumeration
320   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h))
321   * @param   PriorityGroup: the priority grouping bits length.
322   *         This parameter can be one of the following values:
323   *           @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
324   *                                      4 bits for subpriority
325   *           @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
326   *                                      3 bits for subpriority
327   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
328   *                                      2 bits for subpriority
329   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
330   *                                      1 bit for subpriority
331   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
332   *                                      0 bit for subpriority
333   * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
334   * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
335   * @retval None
336   */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)337 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
338 {
339   /* Check the parameters */
340   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
341   /* Get priority for Cortex-M system or device specific interrupts */
342   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
343 }
344 
345 /**
346   * @brief  Set Pending bit of an external interrupt.
347   * @param  IRQn External interrupt number
348   *         This parameter can be an enumerator of IRQn_Type enumeration
349   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h))
350   * @retval None
351   */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)352 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
353 {
354   /* Set interrupt pending */
355   NVIC_SetPendingIRQ(IRQn);
356 }
357 
358 /**
359   * @brief  Get Pending Interrupt (read the pending register in the NVIC
360   *         and return the pending bit for the specified interrupt).
361   * @param  IRQn External interrupt number.
362   *          This parameter can be an enumerator of IRQn_Type enumeration
363   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h))
364   * @retval status: - 0  Interrupt status is not pending.
365   *                 - 1  Interrupt status is pending.
366   */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)367 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
368 {
369   /* Return 1 if pending else 0 */
370   return NVIC_GetPendingIRQ(IRQn);
371 }
372 
373 /**
374   * @brief  Clear the pending bit of an external interrupt.
375   * @param  IRQn External interrupt number.
376   *         This parameter can be an enumerator of IRQn_Type enumeration
377   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h))
378   * @retval None
379   */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)380 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
381 {
382   /* Clear pending interrupt */
383   NVIC_ClearPendingIRQ(IRQn);
384 }
385 
386 /**
387   * @brief Get active interrupt (read the active register in NVIC and return the active bit).
388   * @param IRQn External interrupt number
389   *         This parameter can be an enumerator of IRQn_Type enumeration
390   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h))
391   * @retval status: - 0  Interrupt status is not pending.
392   *                 - 1  Interrupt status is pending.
393   */
HAL_NVIC_GetActive(IRQn_Type IRQn)394 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
395 {
396   /* Return 1 if active else 0 */
397   return NVIC_GetActive(IRQn);
398 }
399 
400 /**
401   * @brief  Configure the SysTick clock source.
402   * @param  CLKSource: specifies the SysTick clock source.
403   *          This parameter can be one of the following values:
404   *             @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source.
405   *             @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source.
406   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
407   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
408   * @retval None
409   */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)410 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
411 {
412   /* Check the parameters */
413   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
414   switch (CLKSource)
415   {
416     /* Select HCLK as Systick clock source */
417     case SYSTICK_CLKSOURCE_HCLK:
418       SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
419       break;
420     /* Select HCLK_DIV8 as Systick clock source */
421     case SYSTICK_CLKSOURCE_HCLK_DIV8:
422       CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
423       MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (0x00000000U));
424       break;
425     /* Select LSI as Systick clock source */
426     case SYSTICK_CLKSOURCE_LSI:
427       CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
428       MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_0);
429       break;
430     /* Select LSE as Systick clock source */
431     case SYSTICK_CLKSOURCE_LSE:
432       CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
433       MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1);
434       break;
435     default:
436       /* Nothing to do */
437       break;
438   }
439 }
440 
441 /**
442   * @brief  Get the SysTick clock source configuration.
443   * @retval  SysTick clock source that can be one of the following values:
444   *             @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source.
445   *             @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source.
446   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
447   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
448   */
HAL_SYSTICK_GetCLKSourceConfig(void)449 uint32_t HAL_SYSTICK_GetCLKSourceConfig(void)
450 {
451   uint32_t systick_source;
452 
453   /* Read SysTick->CTRL register for internal or external clock source */
454   if(READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U)
455   {
456     /* Internal clock source */
457     systick_source = SYSTICK_CLKSOURCE_HCLK;
458   }
459   else
460   {
461     /* External clock source, check the selected one in RCC */
462     switch (__HAL_RCC_GET_SYSTICK_SOURCE())
463     {
464       case RCC_SYSTICKCLKSOURCE_LSI:
465         systick_source = SYSTICK_CLKSOURCE_LSI;
466         break;
467 
468       case RCC_SYSTICKCLKSOURCE_LSE:
469         systick_source = SYSTICK_CLKSOURCE_LSE;
470         break;
471 
472       default: /* RCC_SYSTICKCLKSOURCE_HCLK_DIV8 */
473         systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8;
474         break;
475     }
476   }
477   return systick_source;
478 }
479 
480 /**
481   * @brief  Handle SYSTICK interrupt request.
482   * @retval None
483   */
HAL_SYSTICK_IRQHandler(void)484 void HAL_SYSTICK_IRQHandler(void)
485 {
486   HAL_SYSTICK_Callback();
487 }
488 
489 /**
490   * @brief  SYSTICK callback.
491   * @retval None
492   */
HAL_SYSTICK_Callback(void)493 __weak void HAL_SYSTICK_Callback(void)
494 {
495   /* NOTE : This function should not be modified, when the callback is needed,
496             the HAL_SYSTICK_Callback could be implemented in the user file
497    */
498 }
499 
500 /**
501   * @brief  Enable the MPU.
502   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
503   *          NMI, FAULTMASK and privileged accessto the default memory
504   *          This parameter can be one of the following values:
505   *            @arg MPU_HFNMI_PRIVDEF_NONE
506   *            @arg MPU_HARDFAULT_NMI
507   *            @arg MPU_PRIVILEGED_DEFAULT
508   *            @arg MPU_HFNMI_PRIVDEF
509   * @retval None
510   */
HAL_MPU_Enable(uint32_t MPU_Control)511 void HAL_MPU_Enable(uint32_t MPU_Control)
512 {
513   __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
514 
515   /* Enable the MPU */
516   MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
517 
518   /* Enable fault exceptions */
519   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
520 
521   /* Follow ARM recommendation with */
522   /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
523   __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
524   __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
525 }
526 
527 /**
528   * @brief  Enable the MPU Region.
529   * @retval None
530   */
HAL_MPU_EnableRegion(uint32_t RegionNumber)531 void HAL_MPU_EnableRegion(uint32_t RegionNumber)
532 {
533   /* Check the parameters */
534   assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
535 
536   /* Set the Region number */
537   MPU->RNR = RegionNumber;
538 
539   /* Enable the Region */
540   SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
541 }
542 
543 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
544 /**
545   * @brief  Enable the non-secure MPU.
546   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
547   *          NMI, FAULTMASK and privileged accessto the default memory
548   *          This parameter can be one of the following values:
549   *            @arg MPU_HFNMI_PRIVDEF_NONE
550   *            @arg MPU_HARDFAULT_NMI
551   *            @arg MPU_PRIVILEGED_DEFAULT
552   *            @arg MPU_HFNMI_PRIVDEF
553   * @retval None
554   */
HAL_MPU_Enable_NS(uint32_t MPU_Control)555 void HAL_MPU_Enable_NS(uint32_t MPU_Control)
556 {
557   __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
558 
559   /* Enable the MPU */
560   MPU_NS->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
561 
562   /* Enable fault exceptions */
563   SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
564 
565   /* Follow ARM recommendation with */
566   /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
567   __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
568   __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
569 }
570 
571 /**
572   * @brief  Enable the non-secure MPU Region.
573   * @retval None
574   */
HAL_MPU_EnableRegion_NS(uint32_t RegionNumber)575 void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber)
576 {
577   assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
578 
579   /* Set the Region number */
580   MPU_NS->RNR = RegionNumber;
581 
582   /* Enable the Region */
583   SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
584 }
585 #endif /* __ARM_FEATURE_CMSE */
586 
587 /**
588   * @brief  Disable the MPU.
589   * @retval None
590   */
HAL_MPU_Disable(void)591 void HAL_MPU_Disable(void)
592 {
593   __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
594 
595   /* Disable fault exceptions */
596   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
597 
598   /* Disable the MPU */
599   MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
600 
601   /* Follow ARM recommendation with */
602   /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
603   __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
604   __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
605 }
606 
607 /**
608   * @brief  Disable the MPU Region.
609   * @retval None
610   */
HAL_MPU_DisableRegion(uint32_t RegionNumber)611 void HAL_MPU_DisableRegion(uint32_t RegionNumber)
612 {
613   /* Check the parameters */
614   assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
615 
616   /* Set the Region number */
617   MPU->RNR = RegionNumber;
618 
619   /* Disable the Region */
620   CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
621 }
622 
623 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
HAL_MPU_Disable_NS(void)624 void HAL_MPU_Disable_NS(void)
625 {
626   __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
627 
628   /* Disable fault exceptions */
629   SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
630 
631   /* Disable the MPU */
632   MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
633 
634   /* Follow ARM recommendation with */
635   /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
636   __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
637   __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
638 }
639 
640 /**
641   * @brief  Disable the non-secure MPU Region.
642   * @retval None
643   */
HAL_MPU_DisableRegion_NS(uint32_t RegionNumber)644 void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber)
645 {
646   /* Check the parameters */
647   assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
648 
649   /* Set the Region number */
650   MPU_NS->RNR = RegionNumber;
651 
652   /* Disable the Region */
653   CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
654 }
655 #endif /* __ARM_FEATURE_CMSE */
656 
657 /**
658   * @brief  Initialize and configure the Region and the memory to be protected.
659   * @param  MPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
660   *                the initialization and configuration information.
661   * @retval None
662   */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_RegionInit)663 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit)
664 {
665   MPU_ConfigRegion(MPU, MPU_RegionInit);
666 }
667 
668 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
669 /**
670   * @brief  Initialize and configure the Region and the memory to be protected for non-secure MPU.
671   * @param  MPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
672   *                the initialization and configuration information.
673   * @retval None
674   */
HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef * MPU_RegionInit)675 void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit)
676 {
677   MPU_ConfigRegion(MPU_NS, MPU_RegionInit);
678 }
679 #endif /* __ARM_FEATURE_CMSE */
680 
MPU_ConfigRegion(MPU_Type * MPUx,MPU_Region_InitTypeDef * MPU_RegionInit)681 static void MPU_ConfigRegion(MPU_Type *MPUx, MPU_Region_InitTypeDef *MPU_RegionInit)
682 {
683   /* Check the parameters */
684   assert_param(IS_MPU_REGION_NUMBER(MPU_RegionInit->Number));
685   assert_param(IS_MPU_REGION_ENABLE(MPU_RegionInit->Enable));
686   assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_RegionInit->DisableExec));
687   assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_RegionInit->AccessPermission));
688   assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_RegionInit->IsShareable));
689   assert_param(IS_MPU_ATTRIBUTES_NUMBER(MPU_RegionInit->AttributesIndex));
690 
691   /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */
692   __DMB();
693 
694   /* Set the Region number */
695   MPUx->RNR = MPU_RegionInit->Number;
696 
697    /* Disable the Region */
698   CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk);
699 
700   MPUx->RBAR = (((uint32_t)MPU_RegionInit->BaseAddress & 0xFFFFFFE0U)  |
701                 ((uint32_t)MPU_RegionInit->IsShareable      << MPU_RBAR_SH_Pos)  |
702                 ((uint32_t)MPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos)  |
703                 ((uint32_t)MPU_RegionInit->DisableExec      << MPU_RBAR_XN_Pos));
704 
705   MPUx->RLAR = (((uint32_t)MPU_RegionInit->LimitAddress & 0xFFFFFFE0U) |
706                 ((uint32_t)MPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
707                 ((uint32_t)MPU_RegionInit->Enable          << MPU_RLAR_EN_Pos));
708 }
709 /**
710   * @brief  Initialize and configure the memory attributes.
711   * @param  MPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
712   *                the initialization and configuration information.
713   * @retval None
714   */
HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef * MPU_AttributesInit)715 void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit)
716 {
717   MPU_ConfigMemoryAttributes(MPU, MPU_AttributesInit);
718 }
719 
720 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
721 /**
722   * @brief  Initialize and configure the memory attributes for non-secure MPU.
723   * @param  MPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
724   *                the initialization and configuration information.
725   * @retval None
726   */
HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef * MPU_AttributesInit)727 void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit)
728 {
729   MPU_ConfigMemoryAttributes(MPU_NS, MPU_AttributesInit);
730 }
731 #endif /* __ARM_FEATURE_CMSE */
732 
MPU_ConfigMemoryAttributes(MPU_Type * MPUx,MPU_Attributes_InitTypeDef * MPU_AttributesInit)733 static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, MPU_Attributes_InitTypeDef *MPU_AttributesInit)
734 {
735   __IO uint32_t *mair;
736   uint32_t      attr_values;
737   uint32_t      attr_number;
738 
739   /* Check the parameters */
740   assert_param(IS_MPU_ATTRIBUTES_NUMBER(MPU_AttributesInit->Number));
741   /* No need to check Attributes value as all 0x0..0xFF possible */
742 
743   /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */
744   __DMB();
745 
746   if (MPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4)
747   {
748     /* Program MPU_MAIR0 */
749     mair = &(MPUx->MAIR0);
750     attr_number = MPU_AttributesInit->Number;
751   }
752   else
753   {
754     /* Program MPU_MAIR1 */
755     mair = &(MPUx->MAIR1);
756     attr_number = (uint32_t)MPU_AttributesInit->Number - 4U;
757   }
758 
759   attr_values = *(mair);
760   attr_values &=  ~(0xFFU << (attr_number * 8U));
761   *(mair) = attr_values | ((uint32_t)MPU_AttributesInit->Attributes << (attr_number * 8U));
762 }
763 
764 /**
765   * @}
766   */
767 
768 /**
769   * @}
770   */
771 
772 #endif /* HAL_CORTEX_MODULE_ENABLED */
773 /**
774   * @}
775   */
776 
777 /**
778   * @}
779   */
780