1 /**
2   ******************************************************************************
3   * @file    stm32wb0x_hal_cortex.c
4   * @author  MCD Application Team
5   * @brief   CORTEX HAL module driver.
6   *          This file provides firmware functions to manage the following
7   *          functionalities of the CORTEX:
8   *           + Initialization and Configuration functions
9   *           + Peripheral Control functions
10   ******************************************************************************
11   * @attention
12   *
13   * Copyright (c) 2024 STMicroelectronics.
14   * All rights reserved.
15   *
16   * This software is licensed under terms that can be found in the LICENSE file
17   * in the root directory of this software component.
18   * If no LICENSE file comes with this software, it is provided AS-IS.
19   *
20   ******************************************************************************
21   @verbatim
22   ==============================================================================
23                         ##### How to use this driver #####
24   ==============================================================================
25     [..]
26     *** How to configure Interrupts using CORTEX HAL driver ***
27     ===========================================================
28     [..]
29     This section provides functions allowing to configure the NVIC interrupts (IRQ).
30     The Cortex M0+ exceptions are managed by CMSIS functions.
31       (#) Enable and Configure the priority of the selected IRQ Channels.
32              The priority can be 0..3.
33 
34         -@- Lower priority values gives higher priority.
35         -@- Priority Order:
36             (#@) Lowest priority.
37             (#@) Lowest hardware priority (IRQn position).
38 
39       (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
40 
41       (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
42 
43       -@-  Negative value of IRQn_Type are not allowed.
44 
45     *** How to configure Systick using CORTEX HAL driver ***
46     ========================================================
47     [..]
48     Setup SysTick Timer for time base.
49 
50    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
51        is a CMSIS function that:
52         (++) Configures the SysTick Reload register with value passed as function parameter.
53         (++) Configures the SysTick IRQ priority to the lowest value (0x03).
54         (++) Resets the SysTick Counter register.
55         (++) Enables the SysTick Interrupt.
56         (++) Starts the SysTick Counter.
57 
58    (+) You can change the SysTick IRQ priority by calling the
59        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
60        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
61 
62    (+) To adjust the SysTick time base, use the following formula:
63 
64        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
65        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
66        (++) Reload Value should not exceed 0xFFFFFF
67 
68   @endverbatim
69   ******************************************************************************
70   */
71 
72 /* Includes ------------------------------------------------------------------*/
73 #include "stm32wb0x_hal.h"
74 
75 /** @addtogroup STM32WB0x_HAL_Driver
76   * @{
77   */
78 
79 /** @addtogroup CORTEX
80   * @{
81   */
82 
83 #ifdef HAL_CORTEX_MODULE_ENABLED
84 
85 /* Private types -------------------------------------------------------------*/
86 /* Private variables ---------------------------------------------------------*/
87 /* Private constants ---------------------------------------------------------*/
88 /* Private macros ------------------------------------------------------------*/
89 /* Private functions ---------------------------------------------------------*/
90 /* Exported functions --------------------------------------------------------*/
91 
92 /** @addtogroup CORTEX_Exported_Functions
93   * @{
94   */
95 
96 
97 /** @addtogroup CORTEX_Exported_Functions_Group1
98   *  @brief    Initialization and Configuration functions
99   *
100 @verbatim
101   ==============================================================================
102               ##### Initialization and Configuration functions #####
103   ==============================================================================
104     [..]
105       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
106       SysTick functionalities
107 
108 @endverbatim
109   * @{
110   */
111 
112 /**
113   * @brief  Sets the priority of an interrupt.
114   * @param IRQn External interrupt number .
115   *         This parameter can be an enumerator of IRQn_Type enumeration
116   *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32wb0x.h file)
117   * @param PreemptPriority The preemption priority for the IRQn channel.
118   *         This parameter can be a value between 0 and 3.
119   *         A lower priority value indicates a higher priority
120   * @param SubPriority the subpriority level for the IRQ channel.
121   *         with stm32wb0x devices, this parameter is a dummy value and it is ignored, because
122   *         no subpriority supported in Cortex M0+ based products.
123   * @retval None
124   */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)125 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
126 {
127   /* Check the parameters */
128   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
129   NVIC_SetPriority(IRQn, PreemptPriority);
130 }
131 
132 /**
133   * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
134   * @param  IRQn External interrupt number.
135   *         This parameter can be an enumerator of IRQn_Type enumeration
136   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file)
137   * @retval None
138   */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)139 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
140 {
141   /* Check the parameters */
142   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
143 
144   /* Enable interrupt */
145   NVIC_EnableIRQ(IRQn);
146 }
147 
148 /**
149   * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
150   * @param  IRQn External interrupt number.
151   *         This parameter can be an enumerator of IRQn_Type enumeration
152   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file)
153   * @retval None
154   */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)155 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
156 {
157   /* Check the parameters */
158   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
159 
160   /* Disable interrupt */
161   NVIC_DisableIRQ(IRQn);
162 }
163 
164 /**
165   * @brief  Initiate a system reset request to reset the MCU.
166   * @retval None
167   */
HAL_NVIC_SystemReset(void)168 void HAL_NVIC_SystemReset(void)
169 {
170   /* System Reset */
171   NVIC_SystemReset();
172 }
173 
174 /**
175   * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
176   *         Counter is in free running mode to generate periodic interrupts.
177   * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
178   * @retval status:  - 0  Function succeeded.
179   *                  - 1  Function failed.
180   */
HAL_SYSTICK_Config(uint32_t TicksNumb)181 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
182 {
183   return SysTick_Config(TicksNumb);
184 }
185 /**
186   * @}
187   */
188 
189 /** @addtogroup CORTEX_Exported_Functions_Group2
190   *  @brief   Cortex control functions
191   *
192 @verbatim
193   ==============================================================================
194                       ##### Peripheral Control functions #####
195   ==============================================================================
196     [..]
197       This subsection provides a set of functions allowing to control the CORTEX
198       (NVIC, SYSTICK, MPU) functionalities.
199 
200 
201 @endverbatim
202   * @{
203   */
204 
205 /**
206   * @brief  Get the priority of an interrupt.
207   * @param IRQn External interrupt number.
208   *         This parameter can be an enumerator of IRQn_Type enumeration
209   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file)
210   * @retval None
211   */
HAL_NVIC_GetPriority(IRQn_Type IRQn)212 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
213 {
214   /* Get priority for Cortex-M system or device specific interrupts */
215   return NVIC_GetPriority(IRQn);
216 }
217 
218 /**
219   * @brief  Set Pending bit of an external interrupt.
220   * @param  IRQn External interrupt number
221   *         This parameter can be an enumerator of IRQn_Type enumeration
222   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file)
223   * @retval None
224   */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)225 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
226 {
227   /* Check the parameters */
228   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
229 
230   /* Set interrupt pending */
231   NVIC_SetPendingIRQ(IRQn);
232 }
233 
234 /**
235   * @brief  Get Pending Interrupt (read the pending register in the NVIC
236   *         and return the pending bit for the specified interrupt).
237   * @param  IRQn External interrupt number.
238   *         This parameter can be an enumerator of IRQn_Type enumeration
239   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file)
240   * @retval status: - 0  Interrupt status is not pending.
241   *                 - 1  Interrupt status is pending.
242   */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)243 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
244 {
245   /* Check the parameters */
246   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
247 
248   /* Return 1 if pending else 0 */
249   return NVIC_GetPendingIRQ(IRQn);
250 }
251 
252 /**
253   * @brief  Clear the pending bit of an external interrupt.
254   * @param  IRQn External interrupt number.
255   *         This parameter can be an enumerator of IRQn_Type enumeration
256   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file)
257   * @retval None
258   */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)259 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
260 {
261   /* Check the parameters */
262   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
263 
264   /* Clear pending interrupt */
265   NVIC_ClearPendingIRQ(IRQn);
266 }
267 
268 
269 /**
270   * @brief  Handle SYSTICK interrupt request.
271   * @retval None
272   */
HAL_SYSTICK_IRQHandler(void)273 void HAL_SYSTICK_IRQHandler(void)
274 {
275   HAL_SYSTICK_Callback();
276 }
277 
278 /**
279   * @brief  SYSTICK callback.
280   * @retval None
281   */
HAL_SYSTICK_Callback(void)282 __weak void HAL_SYSTICK_Callback(void)
283 {
284   /* NOTE : This function should not be modified, when the callback is needed,
285             the HAL_SYSTICK_Callback could be implemented in the user file
286    */
287 }
288 
289 #if (__MPU_PRESENT == 1U)
290 /**
291   * @brief  Disables the MPU
292   * @retval None
293   */
HAL_MPU_Disable(void)294 void HAL_MPU_Disable(void)
295 {
296   /* Make sure outstanding transfers are done */
297   __DMB();
298 
299   /* Disable the MPU and clear the control register*/
300   MPU->CTRL = 0U;
301 }
302 
303 /**
304   * @brief  Enable the MPU.
305   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
306   *          NMI and privileged access to the default memory
307   *          This parameter can be one of the following values:
308   *            @arg MPU_HFNMI_PRIVDEF_NONE
309   *            @arg MPU_HARDFAULT_NMI
310   *            @arg MPU_PRIVILEGED_DEFAULT
311   *            @arg MPU_HFNMI_PRIVDEF
312   * @retval None
313   */
HAL_MPU_Enable(uint32_t MPU_Control)314 void HAL_MPU_Enable(uint32_t MPU_Control)
315 {
316   /* Enable the MPU */
317   MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
318 
319   /* Ensure MPU setting take effects */
320   __DSB();
321   __ISB();
322 }
323 
324 /**
325   * @brief  Initialize and configure the Region and the memory to be protected.
326   * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
327   *                the initialization and configuration information.
328   * @retval None
329   */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)330 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
331 {
332   /* Check the parameters */
333   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
334   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
335 
336   /* Set the Region number */
337   MPU->RNR = MPU_Init->Number;
338 
339   if ((MPU_Init->Enable) != 0U)
340   {
341     /* Check the parameters */
342     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
343     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
344     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
345     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
346     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
347     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
348     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
349     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
350 
351     MPU->RBAR = MPU_Init->BaseAddress;
352     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
353                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
354                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
355                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
356                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
357                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
358                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
359                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
360                 ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
361   }
362   else
363   {
364     MPU->RBAR = 0x00U;
365     MPU->RASR = 0x00U;
366   }
367 }
368 #endif /* __MPU_PRESENT */
369 
370 /**
371   * @}
372   */
373 
374 /**
375   * @}
376   */
377 
378 #endif /* HAL_CORTEX_MODULE_ENABLED */
379 /**
380   * @}
381   */
382 
383 /**
384   * @}
385   */
386