1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2021 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### How to use this driver #####
25 ==============================================================================
26
27 [..]
28 *** How to configure Interrupts using CORTEX HAL driver ***
29 ===========================================================
30 [..]
31 This section provides functions allowing to configure the NVIC interrupts (IRQ).
32 The Cortex-M33 exceptions are managed by CMSIS functions.
33
34 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
35 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
36 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
37
38 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
39 The pending IRQ priority will be managed only by the sub priority.
40
41 -@- IRQ priority order (sorted by highest to lowest priority):
42 (+@) Lowest pre-emption priority
43 (+@) Lowest sub priority
44 (+@) Lowest hardware priority (IRQ number)
45
46 [..]
47 *** How to configure SysTick using CORTEX HAL driver ***
48 ========================================================
49 [..]
50 Setup SysTick Timer for time base.
51
52 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
53 is a CMSIS function that:
54 (++) Configures the SysTick Reload register with value passed as function parameter.
55 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
56 (++) Resets the SysTick Counter register.
57 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
58 (++) Enables the SysTick Interrupt.
59 (++) Starts the SysTick Counter.
60
61 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
62 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
63 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
64 inside the stm32u5xx_hal_cortex.h file.
65
66 (+) You can change the SysTick IRQ priority by calling the
67 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
68 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
69
70 (+) To adjust the SysTick time base, use the following formula:
71
72 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
73 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
74 (++) Reload Value should not exceed 0xFFFFFF
75
76 [..]
77 *** How to configure MPU using CORTEX HAL driver ***
78 ===========================================================
79 [..]
80 This section provides functions allowing to configure the Memory Protection Unit (MPU).
81
82 (#) Disable the MPU using HAL_MPU_Disable().
83 (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes().
84 (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to
85 the right MPU attributes number.
86 (#) Enable the MPU using HAL_MPU_Enable() function.
87
88 -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory
89 management fault handler MemManage_Handler() when an illegal memory access is performed.
90 -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration
91 from affecting the new MPU configuration.
92 -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context
93 and the same sequence as above applies to configure the non-secure MPU.
94
95 @endverbatim
96 ******************************************************************************
97
98 The table below gives the allowed values of the pre-emption priority and subpriority according
99 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
100
101 ========================================================================================================================
102 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
103 ========================================================================================================================
104 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
105 | | | 4 bits for subpriority
106 ------------------------------------------------------------------------------------------------------------------------
107 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
108 | | | 3 bits for subpriority
109 ------------------------------------------------------------------------------------------------------------------------
110 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
111 | | | 2 bits for subpriority
112 ------------------------------------------------------------------------------------------------------------------------
113 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
114 | | | 1 bit for subpriority
115 ------------------------------------------------------------------------------------------------------------------------
116 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
117 | | | 0 bit for subpriority
118 ========================================================================================================================
119 */
120
121 /* Includes ------------------------------------------------------------------*/
122 #include "stm32u5xx_hal.h"
123
124 /** @addtogroup STM32U5xx_HAL_Driver
125 * @{
126 */
127
128 /** @addtogroup CORTEX
129 * @{
130 */
131
132 #ifdef HAL_CORTEX_MODULE_ENABLED
133
134 /* Private types -------------------------------------------------------------*/
135 /* Private variables ---------------------------------------------------------*/
136 /* Private constants ---------------------------------------------------------*/
137 /* Private macros ------------------------------------------------------------*/
138 /* Private functions ---------------------------------------------------------*/
139 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
140 * @{
141 */
142 static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit);
143 static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
144 /**
145 * @}
146 */
147 /* Exported functions --------------------------------------------------------*/
148
149 /** @addtogroup CORTEX_Exported_Functions
150 * @{
151 */
152
153
154 /** @addtogroup CORTEX_Exported_Functions_Group1
155 * @brief Initialization and Configuration functions
156 *
157 @verbatim
158 ==============================================================================
159 ##### Initialization and Configuration functions #####
160 ==============================================================================
161 [..]
162 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
163 SysTick functionalities
164
165 @endverbatim
166 * @{
167 */
168
169
170 /**
171 * @brief Set the priority grouping field (pre-emption priority and subpriority)
172 * using the required unlock sequence.
173 * @param PriorityGroup: The priority grouping bits length.
174 * This parameter can be one of the following values:
175 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
176 * 4 bits for subpriority
177 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
178 * 3 bits for subpriority
179 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
180 * 2 bits for subpriority
181 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
182 * 1 bit for subpriority
183 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
184 * 0 bit for subpriority
185 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
186 * The pending IRQ priority will be managed only by the subpriority.
187 * @retval None
188 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)189 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
190 {
191 /* Check the parameters */
192 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
193
194 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
195 NVIC_SetPriorityGrouping(PriorityGroup);
196 }
197
198 /**
199 * @brief Set the priority of an interrupt.
200 * @param IRQn: External interrupt number.
201 * This parameter can be an enumerator of IRQn_Type enumeration
202 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
203 * CMSIS device file (stm32u5xxxx.h))
204 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
205 * This parameter can be a value between 0 and 15
206 * A lower priority value indicates a higher priority
207 * @param SubPriority: the subpriority level for the IRQ channel.
208 * This parameter can be a value between 0 and 15
209 * A lower priority value indicates a higher priority.
210 * @retval None
211 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)212 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
213 {
214 uint32_t prioritygroup;
215
216 /* Check the parameters */
217 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
218 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
219
220 prioritygroup = NVIC_GetPriorityGrouping();
221
222 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
223 }
224
225 /**
226 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
227 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
228 * function should be called before.
229 * @param IRQn External interrupt number.
230 * This parameter can be an enumerator of IRQn_Type enumeration
231 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
232 * CMSIS device file (stm32u5xxxx.h))
233 * @retval None
234 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)235 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
236 {
237 /* Check the parameters */
238 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
239
240 /* Enable interrupt */
241 NVIC_EnableIRQ(IRQn);
242 }
243
244 /**
245 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
246 * @param IRQn External interrupt number.
247 * This parameter can be an enumerator of IRQn_Type enumeration
248 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
249 * CMSIS device file (stm32u5xxxx.h))
250 * @retval None
251 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)252 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
253 {
254 /* Check the parameters */
255 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
256
257 /* Disable interrupt */
258 NVIC_DisableIRQ(IRQn);
259 }
260
261 /**
262 * @brief Initiate a system reset request to reset the MCU.
263 * @retval None
264 */
HAL_NVIC_SystemReset(void)265 void HAL_NVIC_SystemReset(void)
266 {
267 /* System Reset */
268 NVIC_SystemReset();
269 }
270
271 /**
272 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
273 * Counter is in free running mode to generate periodic interrupts.
274 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
275 * @retval status: - 0 Function succeeded.
276 * - 1 Function failed.
277 */
HAL_SYSTICK_Config(uint32_t TicksNumb)278 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
279 {
280 if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk)
281 {
282 /* Reload value impossible */
283 return (1UL);
284 }
285
286 /* Set reload register */
287 WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL));
288
289 /* Load the SysTick Counter Value */
290 WRITE_REG(SysTick->VAL, 0UL);
291
292 /* Enable SysTick IRQ and SysTick Timer */
293 SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk));
294
295 /* Function successful */
296 return (0UL);
297 }
298 /**
299 * @}
300 */
301
302 /** @addtogroup CORTEX_Exported_Functions_Group2
303 * @brief Cortex control functions
304 *
305 @verbatim
306 ==============================================================================
307 ##### Peripheral Control functions #####
308 ==============================================================================
309 [..]
310 This subsection provides a set of functions allowing to control the CORTEX
311 (NVIC, SYSTICK, MPU) functionalities.
312
313
314 @endverbatim
315 * @{
316 */
317
318 /**
319 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
320 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
321 */
HAL_NVIC_GetPriorityGrouping(void)322 uint32_t HAL_NVIC_GetPriorityGrouping(void)
323 {
324 /* Get the PRIGROUP[10:8] field value */
325 return NVIC_GetPriorityGrouping();
326 }
327
328 /**
329 * @brief Get the priority of an interrupt.
330 * @param IRQn: External interrupt number.
331 * This parameter can be an enumerator of IRQn_Type enumeration
332 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
333 * CMSIS device file (stm32u5xxxx.h))
334 * @param PriorityGroup: the priority grouping bits length.
335 * This parameter can be one of the following values:
336 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
337 * 4 bits for subpriority
338 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
339 * 3 bits for subpriority
340 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
341 * 2 bits for subpriority
342 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
343 * 1 bit for subpriority
344 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
345 * 0 bit for subpriority
346 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
347 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
348 * @retval None
349 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)350 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority,
351 uint32_t *const pSubPriority)
352 {
353 /* Check the parameters */
354 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
355 /* Get priority for Cortex-M system or device specific interrupts */
356 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
357 }
358
359 /**
360 * @brief Set Pending bit of an external interrupt.
361 * @param IRQn External interrupt number
362 * This parameter can be an enumerator of IRQn_Type enumeration
363 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
364 * CMSIS device file (stm32u5xxxx.h))
365 * @retval None
366 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)367 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
368 {
369 /* Set interrupt pending */
370 NVIC_SetPendingIRQ(IRQn);
371 }
372
373 /**
374 * @brief Get Pending Interrupt (read the pending register in the NVIC
375 * and return the pending bit for the specified interrupt).
376 * @param IRQn External interrupt number.
377 * This parameter can be an enumerator of IRQn_Type enumeration
378 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
379 * CMSIS device file (stm32u5xxxx.h))
380 * @retval status: - 0 Interrupt status is not pending.
381 * - 1 Interrupt status is pending.
382 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)383 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
384 {
385 /* Return 1 if pending else 0 */
386 return NVIC_GetPendingIRQ(IRQn);
387 }
388
389 /**
390 * @brief Clear the pending bit of an external interrupt.
391 * @param IRQn External interrupt number.
392 * This parameter can be an enumerator of IRQn_Type enumeration
393 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
394 * CMSIS device file (stm32u5xxxx.h))
395 * @retval None
396 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)397 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
398 {
399 /* Clear pending interrupt */
400 NVIC_ClearPendingIRQ(IRQn);
401 }
402
403 /**
404 * @brief Get active interrupt (read the active register in NVIC and return the active bit).
405 * @param IRQn External interrupt number
406 * This parameter can be an enumerator of IRQn_Type enumeration
407 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
408 * CMSIS device file (stm32u5xxxx.h))
409 * @retval status: - 0 Interrupt status is not pending.
410 * - 1 Interrupt status is pending.
411 */
HAL_NVIC_GetActive(IRQn_Type IRQn)412 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
413 {
414 /* Return 1 if active else 0 */
415 return NVIC_GetActive(IRQn);
416 }
417
418 /**
419 * @brief Configure the SysTick clock source.
420 * @param CLKSource: specifies the SysTick clock source.
421 * This parameter can be one of the following values:
422 * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source.
423 * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source.
424 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
425 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
426 * @retval None
427 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)428 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
429 {
430 /* Check the parameters */
431 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
432 switch (CLKSource)
433 {
434 /* Select HCLK as Systick clock source */
435 case SYSTICK_CLKSOURCE_HCLK:
436 SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
437 break;
438 /* Select HCLK_DIV8 as Systick clock source */
439 case SYSTICK_CLKSOURCE_HCLK_DIV8:
440 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
441 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (0x00000000U));
442 break;
443 /* Select LSI as Systick clock source */
444 case SYSTICK_CLKSOURCE_LSI:
445 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
446 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_0);
447 break;
448 /* Select LSE as Systick clock source */
449 case SYSTICK_CLKSOURCE_LSE:
450 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
451 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1);
452 break;
453 default:
454 /* Nothing to do */
455 break;
456 }
457 }
458
459 /**
460 * @brief Get the SysTick clock source configuration.
461 * @retval SysTick clock source that can be one of the following values:
462 * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source.
463 * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source.
464 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
465 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
466 */
HAL_SYSTICK_GetCLKSourceConfig(void)467 uint32_t HAL_SYSTICK_GetCLKSourceConfig(void)
468 {
469 uint32_t systick_source;
470 uint32_t systick_rcc_source;
471
472 /* Read SysTick->CTRL register for internal or external clock source */
473 if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U)
474 {
475 /* Internal clock source */
476 systick_source = SYSTICK_CLKSOURCE_HCLK;
477 }
478 else
479 {
480 /* External clock source, check the selected one in RCC */
481 systick_rcc_source = READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL);
482
483 switch (systick_rcc_source)
484 {
485 case (0x00000000U):
486 systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8;
487 break;
488
489 case (RCC_CCIPR1_SYSTICKSEL_0):
490 systick_source = SYSTICK_CLKSOURCE_LSI;
491 break;
492
493 case (RCC_CCIPR1_SYSTICKSEL_1):
494 systick_source = SYSTICK_CLKSOURCE_LSE;
495 break;
496
497 default:
498 systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8;
499 break;
500 }
501 }
502 return systick_source;
503 }
504
505 /**
506 * @brief Handle SYSTICK interrupt request.
507 * @retval None
508 */
HAL_SYSTICK_IRQHandler(void)509 void HAL_SYSTICK_IRQHandler(void)
510 {
511 HAL_SYSTICK_Callback();
512 }
513
514 /**
515 * @brief SYSTICK callback.
516 * @retval None
517 */
HAL_SYSTICK_Callback(void)518 __weak void HAL_SYSTICK_Callback(void)
519 {
520 /* NOTE : This function should not be modified, when the callback is needed,
521 the HAL_SYSTICK_Callback could be implemented in the user file
522 */
523 }
524
525
526 /**
527 * @brief Enable the MPU.
528 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
529 * NMI, FAULTMASK and privileged access to the default memory
530 * This parameter can be one of the following values:
531 * @arg MPU_HFNMI_PRIVDEF_NONE
532 * @arg MPU_HARDFAULT_NMI
533 * @arg MPU_PRIVILEGED_DEFAULT
534 * @arg MPU_HFNMI_PRIVDEF
535 * @retval None
536 */
HAL_MPU_Enable(uint32_t MPU_Control)537 void HAL_MPU_Enable(uint32_t MPU_Control)
538 {
539 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
540
541 /* Enable the MPU */
542 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
543
544 /* Enable fault exceptions */
545 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
546
547 /* Follow ARM recommendation with */
548 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
549 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
550 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
551 }
552
553 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
554 /**
555 * @brief Enable the non-secure MPU.
556 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
557 * NMI, FAULTMASK and privileged access to the default memory
558 * This parameter can be one of the following values:
559 * @arg MPU_HFNMI_PRIVDEF_NONE
560 * @arg MPU_HARDFAULT_NMI
561 * @arg MPU_PRIVILEGED_DEFAULT
562 * @arg MPU_HFNMI_PRIVDEF
563 * @retval None
564 */
HAL_MPU_Enable_NS(uint32_t MPU_Control)565 void HAL_MPU_Enable_NS(uint32_t MPU_Control)
566 {
567 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
568
569 /* Enable the MPU */
570 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
571
572 /* Enable fault exceptions */
573 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
574
575 /* Follow ARM recommendation with */
576 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
577 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
578 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
579 }
580 #endif /* __ARM_FEATURE_CMSE */
581
582 /**
583 * @brief Disable the MPU.
584 * @retval None
585 */
HAL_MPU_Disable(void)586 void HAL_MPU_Disable(void)
587 {
588 __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
589
590 /* Disable fault exceptions */
591 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
592
593 /* Disable the MPU */
594 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
595
596 /* Follow ARM recommendation with */
597 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
598 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
599 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
600 }
601
602 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
603 /**
604 * @brief Disable the non-secure MPU.
605 * @retval None
606 */
HAL_MPU_Disable_NS(void)607 void HAL_MPU_Disable_NS(void)
608 {
609 __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
610
611 /* Disable fault exceptions */
612 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
613
614 /* Disable the MPU */
615 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
616
617 /* Follow ARM recommendation with */
618 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
619 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
620 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
621 }
622 #endif /* __ARM_FEATURE_CMSE */
623
624 /**
625 * @brief Enable the MPU Region.
626 * @retval None
627 * @param RegionNumber Specifies the index of the region to enable.
628 * this parameter can be a value of @ref CORTEX_MPU_Region_Number
629 */
HAL_MPU_EnableRegion(uint32_t RegionNumber)630 void HAL_MPU_EnableRegion(uint32_t RegionNumber)
631 {
632 /* Check the parameters */
633 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
634
635 /* Set the Region number */
636 MPU->RNR = RegionNumber;
637
638 /* Enable the Region */
639 SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
640 }
641
642 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
643 /**
644 * @brief Enable the non-secure MPU Region.
645 * @retval None
646 * @param RegionNumber Specifies the index of the region to enable.
647 * this parameter can be a value of @ref CORTEX_MPU_Region_Number
648 */
HAL_MPU_EnableRegion_NS(uint32_t RegionNumber)649 void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber)
650 {
651 /* Check the parameters */
652 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
653
654 /* Set the Region number */
655 MPU_NS->RNR = RegionNumber;
656
657 /* Enable the Region */
658 SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
659 }
660 #endif /*__ARM_FEATURE_CMSE*/
661
662 /**
663 * @brief Disable the MPU Region.
664 * @retval None
665 * @param RegionNumber Specifies the index of the region to disable.
666 * this parameter can be a value of @ref CORTEX_MPU_Region_Number
667 */
HAL_MPU_DisableRegion(uint32_t RegionNumber)668 void HAL_MPU_DisableRegion(uint32_t RegionNumber)
669 {
670 /* Check the parameters */
671 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
672
673 /* Set the Region number */
674 MPU->RNR = RegionNumber;
675
676 /* Disable the Region */
677 CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
678 }
679
680 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
681 /**
682 * @brief Disable the non-secure MPU Region.
683 * @retval None
684 * @param RegionNumber Specifies the index of the region to disable.
685 * this parameter can be a value of @ref CORTEX_MPU_Region_Number
686 */
HAL_MPU_DisableRegion_NS(uint32_t RegionNumber)687 void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber)
688 {
689 /* Check the parameters */
690 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
691
692 /* Set the Region number */
693 MPU_NS->RNR = RegionNumber;
694
695 /* Disable the Region */
696 CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
697 }
698 #endif /*__ARM_FEATURE_CMSE*/
699
700 /**
701 * @brief Initialize and configure the Region and the memory to be protected.
702 * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
703 * the initialization and configuration information.
704 * @retval None
705 */
HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef * const pMPU_RegionInit)706 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
707 {
708 MPU_ConfigRegion(MPU, pMPU_RegionInit);
709 }
710
711 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
712 /**
713 * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU.
714 * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
715 * the initialization and configuration information.
716 * @retval None
717 */
HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef * const pMPU_RegionInit)718 void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
719 {
720 MPU_ConfigRegion(MPU_NS, pMPU_RegionInit);
721 }
722 #endif /* __ARM_FEATURE_CMSE */
723
724 /**
725 * @brief Initialize and configure the memory attributes.
726 * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
727 * the initialization and configuration information.
728 * @retval None
729 */
HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)730 void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
731 {
732 MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit);
733 }
734
735 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
736 /**
737 * @brief Initialize and configure the memory attributes for non-secure MPU.
738 * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
739 * the initialization and configuration information.
740 * @retval None
741 */
HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)742 void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
743 {
744 MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit);
745 }
746 #endif /* __ARM_FEATURE_CMSE */
747
748 /**
749 * @}
750 */
751
752 /**
753 * @}
754 */
755
756 /** @addtogroup CORTEX_Private_Functions
757 * @{
758 */
MPU_ConfigRegion(MPU_Type * MPUx,const MPU_Region_InitTypeDef * const pMPU_RegionInit)759 static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit)
760 {
761 /* Check the parameters */
762 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
763 assert_param(IS_MPU_INSTANCE(MPUx));
764 #endif /* __ARM_FEATURE_CMSE */
765 assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number));
766 assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable));
767 assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
768 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
769 assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
770
771 /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */
772 __DMB();
773
774 /* Set the Region number */
775 MPUx->RNR = pMPU_RegionInit->Number;
776
777 /* Disable the Region */
778 CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk);
779
780 MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) |
781 ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
782 ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
783 ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
784
785 MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) |
786 ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
787 ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
788 }
789
790
MPU_ConfigMemoryAttributes(MPU_Type * MPUx,const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)791 static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
792 {
793 __IO uint32_t *p_mair;
794 uint32_t attr_values;
795 uint32_t attr_number;
796
797 /* Check the parameters */
798 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
799 assert_param(IS_MPU_INSTANCE(MPUx));
800 #endif /* __ARM_FEATURE_CMSE */
801 assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number));
802 /* No need to check Attributes value as all 0x0..0xFF possible */
803
804 /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */
805 __DMB();
806
807 if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4)
808 {
809 /* Program MPU_MAIR0 */
810 p_mair = &(MPUx->MAIR0);
811 attr_number = pMPU_AttributesInit->Number;
812 }
813 else
814 {
815 /* Program MPU_MAIR1 */
816 p_mair = &(MPUx->MAIR1);
817 attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U;
818 }
819
820 attr_values = *(p_mair);
821 attr_values &= ~(0xFFUL << (attr_number * 8U));
822 *(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U));
823 }
824 /**
825 * @}
826 */
827
828 #endif /* HAL_CORTEX_MODULE_ENABLED */
829 /**
830 * @}
831 */
832
833 /**
834 * @}
835 */
836
837
