1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_LL_SDMMC_H 21 #define STM32U5xx_LL_SDMMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_Driver 31 * @{ 32 */ 33 #if defined (SDMMC1) || defined (SDMMC2) 34 /** @addtogroup SDMMC_LL 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief SDMMC Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t ClockEdge; /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change. 49 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 50 51 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 52 disabled when the bus is idle. 53 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 54 55 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 56 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 57 58 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 59 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 60 61 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 62 This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ 63 64 #if (USE_SD_TRANSCEIVER != 0U) || (USE_SDIO_TRANSCEIVER != 0U) 65 uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. 66 This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ 67 #endif /* USE_SD_TRANSCEIVER || USE_SDIO_TRANSCEIVER */ 68 } SDMMC_InitTypeDef; 69 70 71 /** 72 * @brief SDMMC Command Control structure 73 */ 74 typedef struct 75 { 76 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 77 to a card as part of a command message. If a command 78 contains an argument, it must be loaded into this register 79 before writing the command to the command register. */ 80 81 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 82 Max_Data = 64 */ 83 84 uint32_t Response; /*!< Specifies the SDMMC response type. 85 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 86 87 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 88 enabled or disabled. 89 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 90 91 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 92 is enabled or disabled. 93 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 94 } SDMMC_CmdInitTypeDef; 95 96 97 /** 98 * @brief SDMMC Data Control structure 99 */ 100 typedef struct 101 { 102 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 103 104 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 105 106 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 107 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 108 109 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 110 is a read or write. 111 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 112 113 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 114 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 115 116 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 117 is enabled or disabled. 118 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 119 } SDMMC_DataInitTypeDef; 120 121 /** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure 122 * @{ 123 */ 124 typedef struct 125 { 126 __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list configuration register */ 127 __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register */ 128 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register */ 129 } SDMMC_DMALinkNodeTypeDef; 130 131 typedef struct 132 { 133 uint32_t BufferAddress; /*!< Node Buffer address */ 134 uint32_t BufferSize ; /*!< Node Buffer size */ 135 } SDMMC_DMALinkNodeConfTypeDef; 136 137 typedef struct 138 { 139 SDMMC_DMALinkNodeTypeDef *pHeadNode; /*!< Linked List Node Head */ 140 SDMMC_DMALinkNodeTypeDef *pTailNode; /*!< Linked List Node Head */ 141 uint32_t NodesCounter ; /*!< Node is ready for execution */ 142 } SDMMC_DMALinkedListTypeDef; 143 /** 144 * @} 145 */ 146 147 /* Exported constants --------------------------------------------------------*/ 148 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 149 * @{ 150 */ 151 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 152 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ 153 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ 154 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ 155 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ 156 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ 157 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ 158 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ 159 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ 160 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ 161 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ 162 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ 163 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ 164 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ 165 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ 166 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ 167 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ 168 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ 169 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ 170 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ 171 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ 172 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ 173 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ 174 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ 175 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ 176 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ 177 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ 178 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ 179 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ 180 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ 181 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ 182 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ 183 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ 184 185 /** 186 * @brief Masks for R5 Response 187 */ 188 /** this is the reserved for future use in spec RFU */ 189 #define SDMMC_SDIO_R5_ERROR ((uint32_t)0x00000400U) 190 /** Out of range error */ 191 #define SDMMC_SDIO_R5_OUT_OF_RANGE ((uint32_t)0x00000100U) 192 /** Invalid function number */ 193 #define SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER ((uint32_t)0x00000200U) 194 /** General or an unknown error */ 195 #define SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00000800U) 196 /** SDIO Card current state 197 * 00=DIS (card not selected) 198 * 01=CMD (data line free) 199 * 10=TRN (transfer on data lines) */ 200 #define SDMMC_SDIO_R5_IO_CURRENT_STATE ((uint32_t)0x00003000U) 201 /** Illegal command error */ 202 #define SDMMC_SDIO_R5_ILLEGAL_CMD ((uint32_t)0x00004000U) 203 /** CRC check of previous cmd failed */ 204 #define SDMMC_SDIO_R5_COM_CRC_FAILED ((uint32_t)0x00008000U) 205 206 #define SDMMC_SDIO_R5_ERRORBITS (SDMMC_SDIO_R5_COM_CRC_FAILED | \ 207 SDMMC_SDIO_R5_ILLEGAL_CMD | \ 208 SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR | \ 209 SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER | \ 210 SDMMC_SDIO_R5_OUT_OF_RANGE) 211 /** 212 * @brief SDIO_CMD53_MODE 213 */ 214 #define SDMMC_SDIO_MODE_BYTE 0x00U /*!< Byte Mode */ 215 #define SDMMC_SDIO_MODE_BLOCK 0x01U /*!< Block Mode */ 216 217 /** 218 * @brief SDIO_CMD53_OP_CODE 219 */ 220 #define SDMMC_SDIO_NO_INC 0x00U /*!< No auto indentation */ 221 #define SDMMC_SDIO_AUTO_INC 0x01U /*!< Auto indentation */ 222 223 /** 224 * @brief SDIO_CMD53_RAW 225 */ 226 #define SDMMC_SDIO_WO 0x00U /*!< Write only Flag */ 227 #define SDMMC_SDIO_RAW 0x01U /*!< Read after write Flag */ 228 229 /** 230 * @brief SDMMC Commands Index 231 */ 232 #define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ 233 #define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ 234 #define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 235 #define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ 236 #define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ 237 #define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ 238 #define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 239 #define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ 240 #define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ 241 #define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 242 #define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ 243 #define SDMMC_CMD_VOLTAGE_SWITCH 11U /*!< SD card Voltage switch to 1.8V mode. */ 244 #define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ 245 #define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ 246 #define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ 247 #define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ 248 #define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ 249 /*!< for SDHS and SDXC. */ 250 #define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ 251 #define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ 252 #define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 253 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ 254 #define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ 255 #define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ 256 #define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 257 #define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ 258 #define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ 259 #define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ 260 #define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ 261 #define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ 262 #define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ 263 #define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ 264 #define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ 265 #define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ 266 #define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ 267 #define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ 268 #define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ 269 #define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ 270 #define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ 271 #define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ 272 #define SDMMC_CMD_NO_CMD 64U /*!< No command */ 273 274 /** 275 * @brief Following commands are SD Card Specific commands. 276 * SDMMC_APP_CMD should be sent before sending these commands. 277 */ 278 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ 279 #define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ 280 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ 281 #define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ 282 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 283 #define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ 284 #define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ 285 #define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ 286 287 /** 288 * @brief Following commands are MMC Specific commands. 289 */ 290 #define SDMMC_CMD_MMC_SLEEP_AWAKE 5U /*!< Toggle the device between Sleep state and Standby state. */ 291 292 /** 293 * @brief Following commands are SD Card Specific security commands. 294 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 295 */ 296 #define SDMMC_CMD_SD_APP_GET_MKB 43U 297 #define SDMMC_CMD_SD_APP_GET_MID 44U 298 #define SDMMC_CMD_SD_APP_SET_CER_RN1 45U 299 #define SDMMC_CMD_SD_APP_GET_CER_RN2 46U 300 #define SDMMC_CMD_SD_APP_SET_CER_RES2 47U 301 #define SDMMC_CMD_SD_APP_GET_CER_RES1 48U 302 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U 303 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U 304 #define SDMMC_CMD_SD_APP_SECURE_ERASE 38U 305 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U 306 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U 307 308 /** 309 * @brief Masks for errors Card Status R1 (OCR Register) 310 */ 311 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) 312 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) 313 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) 314 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) 315 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) 316 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) 317 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) 318 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) 319 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) 320 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) 321 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) 322 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) 323 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) 324 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) 325 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) 326 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) 327 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) 328 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) 329 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) 330 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) 331 332 /** 333 * @brief Masks for R6 Response 334 */ 335 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) 336 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) 337 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) 338 339 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) 340 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) 341 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) 342 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) 343 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) 344 #define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U) 345 #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) 346 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) 347 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) 348 #define SDMMC_SDR12_SWITCH_PATTERN ((uint32_t)0x80FFFF00U) 349 350 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) 351 352 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) 353 354 #define SDMMC_ALLZERO ((uint32_t)0x00000000U) 355 356 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) 357 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) 358 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) 359 360 #ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */ 361 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) 362 #endif /* SDMMC_DATATIMEOUT */ 363 364 #ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ 365 #define SDMMC_SWDATATIMEOUT ((uint32_t)0xFFFFFFFFU) 366 #endif /* SDMMC_SWDATATIMEOUT */ 367 368 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) 369 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) 370 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) 371 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) 372 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) 373 374 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) 375 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) 376 377 /* SDMMC FIFO Size */ 378 #define SDMMC_FIFO_SIZE 32U 379 /** 380 * @brief Command Class supported 381 */ 382 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) 383 384 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ 385 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ 386 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ 387 388 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 389 * @{ 390 */ 391 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) 392 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 393 394 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 395 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 396 /** 397 * @} 398 */ 399 400 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 401 * @{ 402 */ 403 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) 404 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 405 406 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 407 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 408 /** 409 * @} 410 */ 411 412 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 413 * @{ 414 */ 415 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) 416 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 417 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 418 419 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 420 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 421 ((WIDE) == SDMMC_BUS_WIDE_8B)) 422 /** 423 * @} 424 */ 425 426 /** @defgroup SDMMC_LL_Speed_Mode 427 * @{ 428 */ 429 #define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U) 430 #define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U) 431 #define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U) 432 #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) 433 #define SDMMC_SPEED_MODE_ULTRA_SDR104 SDMMC_SPEED_MODE_ULTRA 434 #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) 435 #define SDMMC_SPEED_MODE_ULTRA_SDR50 ((uint32_t)0x00000005U) 436 437 #define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ 438 ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ 439 ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ 440 ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ 441 ((MODE) == SDMMC_SPEED_MODE_ULTRA_SDR50) || \ 442 ((MODE) == SDMMC_SPEED_MODE_DDR)) 443 444 /** 445 * @} 446 */ 447 448 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 449 * @{ 450 */ 451 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) 452 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 453 454 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 455 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 456 /** 457 * @} 458 */ 459 460 /** @defgroup SDMMC_LL_Clock_Division Clock Division 461 * @{ 462 */ 463 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ 464 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) 465 /** 466 * @} 467 */ 468 469 /** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present 470 * @{ 471 */ 472 #define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U) 473 #define SDMMC_TRANSCEIVER_NOT_PRESENT ((uint32_t)0x00000001U) 474 #define SDMMC_TRANSCEIVER_PRESENT ((uint32_t)0x00000002U) 475 476 /** 477 * @} 478 */ 479 480 /** @defgroup SDMMC_LL_Command_Index Command Index 481 * @{ 482 */ 483 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 484 /** 485 * @} 486 */ 487 488 /** @defgroup SDMMC_LL_Response_Type Response Type 489 * @{ 490 */ 491 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) 492 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 493 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 494 495 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 496 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 497 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 498 /** 499 * @} 500 */ 501 502 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 503 * @{ 504 */ 505 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U) 506 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 507 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 508 509 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 510 ((WAIT) == SDMMC_WAIT_IT) || \ 511 ((WAIT) == SDMMC_WAIT_PEND)) 512 /** 513 * @} 514 */ 515 516 /** @defgroup SDMMC_LL_CPSM_State CPSM State 517 * @{ 518 */ 519 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) 520 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 521 522 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 523 ((CPSM) == SDMMC_CPSM_ENABLE)) 524 /** 525 * @} 526 */ 527 528 /** @defgroup SDMMC_LL_Response_Registers Response Register 529 * @{ 530 */ 531 #define SDMMC_RESP1 ((uint32_t)0x00000000U) 532 #define SDMMC_RESP2 ((uint32_t)0x00000004U) 533 #define SDMMC_RESP3 ((uint32_t)0x00000008U) 534 #define SDMMC_RESP4 ((uint32_t)0x0000000CU) 535 536 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 537 ((RESP) == SDMMC_RESP2) || \ 538 ((RESP) == SDMMC_RESP3) || \ 539 ((RESP) == SDMMC_RESP4)) 540 541 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode 542 * @{ 543 */ 544 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) 545 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) 546 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) 547 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) 548 549 /** 550 * @} 551 */ 552 553 /** @defgroup SDMMC_LL_Data_Length Data Length 554 * @{ 555 */ 556 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 557 /** 558 * @} 559 */ 560 561 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 562 * @{ 563 */ 564 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) 565 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 566 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 567 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 568 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 569 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 570 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 571 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 572 SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 573 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 574 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 575 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 576 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 577 SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 578 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 579 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 580 SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 581 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \ 582 SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 583 584 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 585 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 586 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 587 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 588 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 589 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 590 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 591 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 592 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 593 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 594 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 595 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 596 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 597 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 598 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 599 /** 600 * @} 601 */ 602 603 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 604 * @{ 605 */ 606 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) 607 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 608 609 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 610 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 611 /** 612 * @} 613 */ 614 615 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 616 * @{ 617 */ 618 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) 619 #define SDMMC_TRANSFER_MODE_SDIO SDMMC_DCTRL_DTMODE_0 620 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 621 622 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 623 ((MODE) == SDMMC_TRANSFER_MODE_SDIO) || \ 624 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 625 /** 626 * @} 627 */ 628 629 /** @defgroup SDMMC_LL_DPSM_State DPSM State 630 * @{ 631 */ 632 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) 633 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 634 635 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 636 ((DPSM) == SDMMC_DPSM_ENABLE)) 637 /** 638 * @} 639 */ 640 641 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 642 * @{ 643 */ 644 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) 645 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 646 647 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 648 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 649 /** 650 * @} 651 */ 652 653 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 654 * @{ 655 */ 656 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 657 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 658 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 659 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 660 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 661 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 662 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 663 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 664 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 665 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE 666 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 667 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE 668 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 669 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 670 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 671 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 672 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE 673 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 674 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE 675 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE 676 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE 677 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE 678 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE 679 /** 680 * @} 681 */ 682 683 /** @defgroup SDMMC_LL_Flags Flags 684 * @{ 685 */ 686 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 687 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 688 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 689 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 690 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 691 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 692 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 693 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 694 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 695 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD 696 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 697 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT 698 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT 699 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT 700 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 701 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 702 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 703 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 704 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 705 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 706 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 707 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END 708 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 709 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL 710 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT 711 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND 712 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP 713 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE 714 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC 715 716 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 717 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 718 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 719 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ 720 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ 721 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ 722 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) 723 724 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 725 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) 726 727 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 728 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ 729 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ 730 SDMMC_FLAG_IDMABTC)) 731 /** 732 * @} 733 */ 734 735 /** @defgroup SDMMC_SDIO_CCCR_Registers 736 * @{ 737 */ 738 /*-------------------------------- CCCR0 ----------------------------------*/ 739 #define SDMMC_SDIO_CCCR0 0x000U /*!< SDIOS Card Common Control Register 0 */ 740 #define SDMMC_SDIO_CCCR0_SD_BYTE0 0x000U /*!< SDIOS Card Common Control Register 0 Byte 0 */ 741 #define SDMMC_SDIO_CCCR0_SD_BYTE1 0x001U /*!< SDIOS Card Common Control Register 0 Byte 1 */ 742 #define SDMMC_SDIO_CCCR0_SD_BYTE2 0x002U /*!< SDIOS Card Common Control Register 0 Byte 2 */ 743 #define SDMMC_SDIO_CCCR0_SD_BYTE3 0x003U /*!< SDIOS Card Common Control Register 0 Byte 3 */ 744 745 /*-------------------------------- CCCR4 ----------------------------------*/ 746 #define SDMMC_SDIO_CCCR4 0x004U /*!< SDIOS Card Common Control Register 4 */ 747 #define SDMMC_SDIO_CCCR4_SD_BYTE0 0x004U /*!< SDIOS Card Common Control Register 4 Byte 0 */ 748 #define SDMMC_SDIO_CCCR4_SD_BYTE1 0x005U /*!< SDIOS Card Common Control Register 4 Byte 1 */ 749 #define SDMMC_SDIO_CCCR4_SD_BYTE2 0x006U /*!< SDIOS Card Common Control Register 4 Byte 2 */ 750 #define SDMMC_SDIO_CCCR4_SD_BYTE3 0x007U /*!< SDIOS Card Common Control Register 4 Byte 3 */ 751 752 /*-------------------------------- CCCR8 ----------------------------------*/ 753 #define SDMMC_SDIO_CCCR8 0x008U /*!< SDIOS Card Common Control Register 8 */ 754 #define SDMMC_SDIO_CCCR8_SD_BYTE0 0x008U /*!< SDIOS Card Common Control Register 8 Byte 0 */ 755 #define SDMMC_SDIO_CCCR8_SD_BYTE1 0x009U /*!< SDIOS Card Common Control Register 8 Byte 1 */ 756 #define SDMMC_SDIO_CCCR8_SD_BYTE2 0x00AU /*!< SDIOS Card Common Control Register 8 Byte 2 */ 757 #define SDMMC_SDIO_CCCR8_SD_BYTE3 0x00BU /*!< SDIOS Card Common Control Register 8 Byte 3 */ 758 759 /*-------------------------------- CCCR12 ---------------------------------*/ 760 #define SDMMC_SDIO_CCCR12 0x00CU /*!< SDIOS Card Common Control Register 12 */ 761 #define SDMMC_SDIO_CCCR12_SD_BYTE0 0x00CU /*!< SDIOS Card Common Control Register 12 Byte 0 */ 762 #define SDMMC_SDIO_CCCR12_SD_BYTE1 0x00DU /*!< SDIOS Card Common Control Register 12 Byte 1 */ 763 #define SDMMC_SDIO_CCCR12_SD_BYTE2 0x00EU /*!< SDIOS Card Common Control Register 12 Byte 2 */ 764 #define SDMMC_SDIO_CCCR12_SD_BYTE3 0x00FU /*!< SDIOS Card Common Control Register 12 Byte 3 */ 765 766 /*-------------------------------- CCCR16 ---------------------------------*/ 767 #define SDMMC_SDIO_CCCR16 0x010U /*!< SDIOS Card Common Control Register 16 */ 768 #define SDMMC_SDIO_CCCR16_SD_BYTE0 0x010U /*!< SDIOS Card Common Control Register 16 Byte 0 */ 769 #define SDMMC_SDIO_CCCR16_SD_BYTE1 0x011U /*!< SDIOS Card Common Control Register 16 Byte 1 */ 770 #define SDMMC_SDIO_CCCR16_SD_BYTE2 0x012U /*!< SDIOS Card Common Control Register 16 Byte 2 */ 771 #define SDMMC_SDIO_CCCR16_SD_BYTE3 0x013U /*!< SDIOS Card Common Control Register 16 Byte 3 */ 772 773 /*-------------------------------- CCCR20 ---------------------------------*/ 774 #define SDMMC_SDIO_CCCR20 0x014U /*!< SDIOS Card Common Control Register 20 */ 775 #define SDMMC_SDIO_CCCR20_SD_BYTE0 0x014U /*!< SDIOS Card Common Control Register 20 Byte 0 */ 776 #define SDMMC_SDIO_CCCR20_SD_BYTE1 0x015U /*!< SDIOS Card Common Control Register 20 Byte 1 */ 777 #define SDMMC_SDIO_CCCR20_SD_BYTE2 0x016U /*!< SDIOS Card Common Control Register 20 Byte 2 */ 778 #define SDMMC_SDIO_CCCR20_SD_BYTE3 0x017U /*!< SDIOS Card Common Control Register 20 Byte 3 */ 779 780 /*-------------------------------- F1BR0 ----------------------------------*/ 781 #define SDMMC_SDIO_F1BR0 0x100U /*!< SDIOS Function 1 Basic Register 0 */ 782 #define SDMMC_SDIO_F1BR0_SD_BYTE0 0x100U /*!< SDIOS Function 1 Basic Register 0 Byte 0 */ 783 #define SDMMC_SDIO_F1BR0_SD_BYTE1 0x101U /*!< SDIOS Function 1 Basic Register 0 Byte 1 */ 784 #define SDMMC_SDIO_F1BR0_SD_BYTE2 0x102U /*!< SDIOS Function 1 Basic Register 0 Byte 2 */ 785 #define SDMMC_SDIO_F1BR0_SD_BYTE3 0x103U /*!< SDIOS Function 1 Basic Register 0 Byte 3 */ 786 787 /*-------------------------------- F1BR8 ----------------------------------*/ 788 #define SDMMC_SDIO_F1BR8 0x108U /*!< SDIOS Function 1 Basic Register 8 */ 789 #define SDMMC_SDIO_F1BR8_SD_BYTE0 0x108U /*!< SDIOS Function 1 Basic Register 8 Byte 0 */ 790 #define SDMMC_SDIO_F1BR8_SD_BYTE1 0x109U /*!< SDIOS Function 1 Basic Register 8 Byte 1 */ 791 #define SDMMC_SDIO_F1BR8_SD_BYTE2 0x10AU /*!< SDIOS Function 1 Basic Register 8 Byte 2 */ 792 #define SDMMC_SDIO_F1BR8_SD_BYTE3 0x10BU /*!< SDIOS Function 1 Basic Register 8 Byte 3 */ 793 794 /*-------------------------------- F1BR12 ---------------------------------*/ 795 #define SDMMC_SDIO_F1BR12 0x10CU /*!< SDIOS Function 1 Basic Register 12 */ 796 #define SDMMC_SDIO_F1BR12_SD_BYTE0 0x10CU /*!< SDIOS Function 1 Basic Register 12 Byte 0 */ 797 #define SDMMC_SDIO_F1BR12_SD_BYTE1 0x10DU /*!< SDIOS Function 1 Basic Register 12 Byte 1 */ 798 #define SDMMC_SDIO_F1BR12_SD_BYTE2 0x10EU /*!< SDIOS Function 1 Basic Register 12 Byte 2 */ 799 #define SDMMC_SDIO_F1BR12_SD_BYTE3 0x10FU /*!< SDIOS Function 1 Basic Register 12 Byte 3 */ 800 801 /*-------------------------------- F1BR16 ---------------------------------*/ 802 #define SDMMC_SDIO_F1BR16 0x110U /*!< SDIOS Function 1 Basic Register 16 */ 803 #define SDMMC_SDIO_F1BR16_SD_BYTE0 0x110U /*!< SDIOS Function 1 Basic Register 16 Byte 0 */ 804 #define SDMMC_SDIO_F1BR16_SD_BYTE1 0x111U /*!< SDIOS Function 1 Basic Register 16 Byte 1 */ 805 #define SDMMC_SDIO_F1BR16_SD_BYTE2 0x112U /*!< SDIOS Function 1 Basic Register 16 Byte 2 */ 806 #define SDMMC_SDIO_F1BR16_SD_BYTE3 0x113U /*!< SDIOS Function 1 Basic Register 16 Byte 3 */ 807 /** 808 * @} 809 */ 810 811 /** 812 * @} 813 */ 814 815 /* Exported macro ------------------------------------------------------------*/ 816 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 817 * @{ 818 */ 819 820 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 821 * @brief SDMMC_LL registers bit address in the alias region 822 * @{ 823 */ 824 /* ---------------------- SDMMC registers bit mask --------------------------- */ 825 /* --- CLKCR Register ---*/ 826 /* CLKCR register clear mask */ 827 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 828 SDMMC_CLKCR_WIDBUS |\ 829 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\ 830 SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\ 831 SDMMC_CLKCR_SELCLKRX)) 832 833 /* --- DCTRL Register ---*/ 834 /* SDMMC DCTRL Clear Mask */ 835 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 836 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 837 838 /* --- CMD Register ---*/ 839 /* CMD Register clear mask */ 840 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 841 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 842 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) 843 844 /* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/ 845 #define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA) 846 847 /* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/ 848 #define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4) 849 850 /* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/ 851 #define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2) 852 /** 853 * @} 854 */ 855 856 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 857 * @brief macros to handle interrupts and specific clock configurations 858 * @{ 859 */ 860 861 /** 862 * @brief Enable the SDMMC device interrupt. 863 * @param __INSTANCE__ Pointer to SDMMC register base 864 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. 865 * This parameter can be one or a combination of the following values: 866 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 867 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 868 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 869 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 870 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 871 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 872 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 873 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 874 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 875 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 876 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 877 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 878 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 879 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 880 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 881 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 882 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 883 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 884 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 885 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 886 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 887 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 888 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 889 * @retval None 890 */ 891 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 892 893 /** 894 * @brief Disable the SDMMC device interrupt. 895 * @param __INSTANCE__ Pointer to SDMMC register base 896 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. 897 * This parameter can be one or a combination of the following values: 898 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 899 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 900 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 901 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 902 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 903 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 904 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 905 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 906 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 907 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 908 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 909 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 910 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 911 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 912 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 913 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 914 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 915 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 916 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 917 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 918 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 919 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 920 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 921 * @retval None 922 */ 923 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 924 925 /** 926 * @brief Checks whether the specified SDMMC flag is set or not. 927 * @param __INSTANCE__ Pointer to SDMMC register base 928 * @param __FLAG__ specifies the flag to check. 929 * This parameter can be one of the following values: 930 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 931 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 932 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 933 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 934 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 935 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 936 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 937 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 938 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 939 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 940 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 941 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 942 * @arg SDMMC_FLAG_DPSMACT: Data path state machine active 943 * @arg SDMMC_FLAG_CPSMACT: Command path state machine active 944 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 945 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 946 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 947 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 948 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 949 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 950 * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 951 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 952 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 953 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 954 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 955 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 956 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 957 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 958 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 959 * @retval The new state of SDMMC_FLAG (SET or RESET). 960 */ 961 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 962 963 964 /** 965 * @brief Clears the SDMMC pending flags. 966 * @param __INSTANCE__ Pointer to SDMMC register base 967 * @param __FLAG__ specifies the flag to clear. 968 * This parameter can be one or a combination of the following values: 969 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 970 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 971 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 972 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 973 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 974 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 975 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 976 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 977 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 978 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 979 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 980 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 981 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 982 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 983 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 984 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 985 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 986 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 987 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 988 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 989 * @retval None 990 */ 991 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 992 993 /** 994 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 995 * @param __INSTANCE__ Pointer to SDMMC register base 996 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. 997 * This parameter can be one of the following values: 998 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 999 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 1000 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 1001 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 1002 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 1003 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 1004 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 1005 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 1006 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 1007 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 1008 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 1009 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 1010 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 1011 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 1012 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 1013 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 1014 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 1015 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 1016 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 1017 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 1018 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 1019 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 1020 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 1021 * @retval The new state of SDMMC_IT (SET or RESET). 1022 */ 1023 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 1024 1025 /** 1026 * @brief Checks the source of specified interrupt. 1027 * @param __INSTANCE__ Pointer to SDMMC register base 1028 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. 1029 * This parameter can be one of the following values: 1030 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 1031 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 1032 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 1033 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 1034 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 1035 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 1036 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 1037 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 1038 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 1039 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 1040 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 1041 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 1042 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 1043 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 1044 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 1045 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 1046 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 1047 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 1048 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 1049 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 1050 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 1051 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 1052 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 1053 * @retval The new state of SDMMC_IT (SET or RESET). 1054 */ 1055 #define __SDMMC_GET_IT_SOURCE(__INSTANCE__, __INTERRUPT__) (((__HANDLE__)->Instance->STA & (__INTERRUPT__))) 1056 1057 /** 1058 * @brief Clears the SDMMC's interrupt pending bits. 1059 * @param __INSTANCE__ Pointer to SDMMC register base 1060 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1061 * This parameter can be one or a combination of the following values: 1062 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 1063 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 1064 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 1065 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 1066 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 1067 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 1068 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 1069 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 1070 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 1071 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 1072 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 1073 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 1074 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 1075 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 1076 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 1077 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 1078 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 1079 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 1080 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 1081 * @retval None 1082 */ 1083 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 1084 1085 /** 1086 * @brief Enable Start the SD I/O Read Wait operation. 1087 * @param __INSTANCE__ Pointer to SDMMC register base 1088 * @retval None 1089 */ 1090 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 1091 1092 /** 1093 * @brief Disable Start the SD I/O Read Wait operations. 1094 * @param __INSTANCE__ Pointer to SDMMC register base 1095 * @retval None 1096 */ 1097 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 1098 1099 /** 1100 * @brief Enable Start the SD I/O Read Wait operation. 1101 * @param __INSTANCE__ Pointer to SDMMC register base 1102 * @retval None 1103 */ 1104 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 1105 1106 /** 1107 * @brief Disable Stop the SD I/O Read Wait operations. 1108 * @param __INSTANCE__ Pointer to SDMMC register base 1109 * @retval None 1110 */ 1111 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 1112 1113 /** 1114 * @brief Enable the SD I/O Mode Operation. 1115 * @param __INSTANCE__ Pointer to SDMMC register base 1116 * @retval None 1117 */ 1118 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 1119 1120 /** 1121 * @brief Disable the SD I/O Mode Operation. 1122 * @param __INSTANCE__ Pointer to SDMMC register base 1123 * @retval None 1124 */ 1125 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 1126 1127 /** 1128 * @brief Enable the SD I/O Suspend command sending. 1129 * @param __INSTANCE__ Pointer to SDMMC register base 1130 * @retval None 1131 */ 1132 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) 1133 1134 /** 1135 * @brief Disable the SD I/O Suspend command sending. 1136 * @param __INSTANCE__ Pointer to SDMMC register base 1137 * @retval None 1138 */ 1139 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) 1140 1141 /** 1142 * @brief Enable the CMDTRANS mode. 1143 * @param __INSTANCE__ Pointer to SDMMC register base 1144 * @retval None 1145 */ 1146 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) 1147 1148 /** 1149 * @brief Disable the CMDTRANS mode. 1150 * @param __INSTANCE__ Pointer to SDMMC register base 1151 * @retval None 1152 */ 1153 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) 1154 1155 /** 1156 * @brief Enable the CMDSTOP mode. 1157 * @param __INSTANCE__ Pointer to SDMMC register base 1158 * @retval None 1159 */ 1160 #define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP) 1161 1162 /** 1163 * @brief Disable the CMDSTOP mode. 1164 * @param __INSTANCE__ Pointer to SDMMC register base 1165 * @retval None 1166 */ 1167 #define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP) 1168 1169 /** 1170 * @} 1171 */ 1172 1173 /** 1174 * @} 1175 */ 1176 1177 /* Exported functions --------------------------------------------------------*/ 1178 /** @addtogroup SDMMC_LL_Exported_Functions 1179 * @{ 1180 */ 1181 1182 /* Initialization/de-initialization functions **********************************/ 1183 /** @addtogroup HAL_SDMMC_LL_Group1 1184 * @{ 1185 */ 1186 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 1187 /** 1188 * @} 1189 */ 1190 1191 /* I/O operation functions *****************************************************/ 1192 /** @addtogroup HAL_SDMMC_LL_Group2 1193 * @{ 1194 */ 1195 uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx); 1196 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 1197 /** 1198 * @} 1199 */ 1200 1201 /* Peripheral Control functions ************************************************/ 1202 /** @addtogroup HAL_SDMMC_LL_Group3 1203 * @{ 1204 */ 1205 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 1206 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); 1207 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 1208 uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); 1209 1210 /* Command path state machine (CPSM) management functions */ 1211 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command); 1212 uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); 1213 uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); 1214 1215 /* Data path state machine (DPSM) management functions */ 1216 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data); 1217 uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); 1218 uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); 1219 1220 /* SDMMC Cards mode management functions */ 1221 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 1222 /** 1223 * @} 1224 */ 1225 1226 /* SDMMC Commands management functions ******************************************/ 1227 /** @addtogroup HAL_SDMMC_LL_Group4 1228 * @{ 1229 */ 1230 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 1231 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1232 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1233 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1234 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1235 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1236 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1237 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1238 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1239 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType); 1240 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 1241 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr); 1242 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 1243 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 1244 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1245 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1246 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 1247 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 1248 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 1249 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1250 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 1251 uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); 1252 uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1253 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1254 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 1255 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); 1256 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1257 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1258 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1259 uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount); 1260 uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse); 1261 uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1262 uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp); 1263 /** 1264 * @} 1265 */ 1266 1267 /* SDMMC Responses management functions *****************************************/ 1268 /** @addtogroup HAL_SDMMC_LL_Group5 1269 * @{ 1270 */ 1271 uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); 1272 uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); 1273 uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); 1274 uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp); 1275 uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData); 1276 uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); 1277 uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); 1278 /** 1279 * @} 1280 */ 1281 1282 /* Linked List functions *******************************************************/ 1283 /** @addtogroup HAL_SDMMC_LL_Group6 1284 * @{ 1285 */ 1286 uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, const SDMMC_DMALinkNodeConfTypeDef *pNodeConf); 1287 uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode, 1288 SDMMC_DMALinkNodeTypeDef *pNode); 1289 uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode); 1290 uint32_t SDMMC_DMALinkedList_LockNode(SDMMC_DMALinkNodeTypeDef *pNode); 1291 uint32_t SDMMC_DMALinkedList_UnlockNode(SDMMC_DMALinkNodeTypeDef *pNode); 1292 uint32_t SDMMC_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList); 1293 uint32_t SDMMC_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList); 1294 /** 1295 * @} 1296 */ 1297 1298 /** 1299 * @} 1300 */ 1301 1302 /** 1303 * @} 1304 */ 1305 1306 /** 1307 * @} 1308 */ 1309 1310 /** 1311 * @} 1312 */ 1313 #endif /* SDMMC1 || SDMMC2 */ 1314 /** 1315 * @} 1316 */ 1317 #ifdef __cplusplus 1318 } 1319 #endif 1320 1321 #endif /* STM32U5xx_LL_SDMMC_H */ 1322
