1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_lpuart.h
4 * @author MCD Application Team
5 * @brief Header file of LPUART LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_LPUART_H
21 #define STM32U5xx_LL_LPUART_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPUART1)
35
36 /** @defgroup LPUART_LL LPUART
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
43 * @{
44 */
45 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
46 static const uint16_t LPUART_PRESCALER_TAB[] =
47 {
48 (uint16_t)1,
49 (uint16_t)2,
50 (uint16_t)4,
51 (uint16_t)6,
52 (uint16_t)8,
53 (uint16_t)10,
54 (uint16_t)12,
55 (uint16_t)16,
56 (uint16_t)32,
57 (uint16_t)64,
58 (uint16_t)128,
59 (uint16_t)256
60 };
61 /**
62 * @}
63 */
64
65 /* Private constants ---------------------------------------------------------*/
66 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
67 * @{
68 */
69 /* Defines used in Baud Rate related macros and corresponding register setting computation */
70 #define LPUART_LPUARTDIV_FREQ_MUL 256U
71 #define LPUART_BRR_MASK 0x000FFFFFU
72 #define LPUART_BRR_MIN_VALUE 0x00000300U
73 /**
74 * @}
75 */
76
77
78 /* Private macros ------------------------------------------------------------*/
79 #if defined(USE_FULL_LL_DRIVER)
80 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
81 * @{
82 */
83 /**
84 * @}
85 */
86 #endif /*USE_FULL_LL_DRIVER*/
87
88 /* Exported types ------------------------------------------------------------*/
89 #if defined(USE_FULL_LL_DRIVER)
90 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
91 * @{
92 */
93
94 /**
95 * @brief LL LPUART Init Structure definition
96 */
97 typedef struct
98 {
99 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
100 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
101
102 This feature can be modified afterwards using unitary
103 function @ref LL_LPUART_SetPrescaler().*/
104
105 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
106
107 This feature can be modified afterwards using unitary
108 function @ref LL_LPUART_SetBaudRate().*/
109
110 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
111 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
112
113 This feature can be modified afterwards using unitary
114 function @ref LL_LPUART_SetDataWidth().*/
115
116 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
117 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
118
119 This feature can be modified afterwards using unitary
120 function @ref LL_LPUART_SetStopBitsLength().*/
121
122 uint32_t Parity; /*!< Specifies the parity mode.
123 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
124
125 This feature can be modified afterwards using unitary
126 function @ref LL_LPUART_SetParity().*/
127
128 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
129 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
130
131 This feature can be modified afterwards using unitary
132 function @ref LL_LPUART_SetTransferDirection().*/
133
134 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
135 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
136
137 This feature can be modified afterwards using unitary
138 function @ref LL_LPUART_SetHWFlowCtrl().*/
139
140 } LL_LPUART_InitTypeDef;
141
142 /**
143 * @}
144 */
145 #endif /* USE_FULL_LL_DRIVER */
146
147 /* Exported constants --------------------------------------------------------*/
148 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
149 * @{
150 */
151
152 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
153 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
154 * @{
155 */
156 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
157 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
158 #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
159 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
160 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
161 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
162 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
163 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
164 /**
165 * @}
166 */
167
168 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
169 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
170 * @{
171 */
172 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
173 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
174 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
175 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
176 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
177 #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
178 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
179 #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
180 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
181 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
182 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
183 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
184 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
185 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
186 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
187 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
188 #define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
189 #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
190 #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
191 #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
192 /**
193 * @}
194 */
195
196 /** @defgroup LPUART_LL_EC_IT IT Defines
197 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
198 * @{
199 */
200 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
201 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
202 interrupt enable */
203 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
204 #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
205 not full interrupt enable */
206 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
207 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
208 #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
209 #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
210 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
211 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
212 #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
213 #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
214 /**
215 * @}
216 */
217
218 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
219 * @{
220 */
221 #define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
222 #define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
223 #define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
224 #define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
225 #define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
226 #define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
227 /**
228 * @}
229 */
230
231 /** @defgroup LPUART_LL_EC_DIRECTION Direction
232 * @{
233 */
234 #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
235 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
236 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
237 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
238 /**
239 * @}
240 */
241
242 /** @defgroup LPUART_LL_EC_PARITY Parity Control
243 * @{
244 */
245 #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
246 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
247 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
248 /**
249 * @}
250 */
251
252 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
253 * @{
254 */
255 #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
256 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
257 /**
258 * @}
259 */
260
261 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
262 * @{
263 */
264 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
265 #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
266 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
267 /**
268 * @}
269 */
270
271 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
272 * @{
273 */
274 #define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
275 #define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
276 #define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
277 #define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
278 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
279 #define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
280 #define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
281 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
282 #define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
283 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
284 #define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
285 USART_PRESC_PRESCALER_1 |\
286 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
287 #define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
288 #define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
289 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
290 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
291 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
292 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
293 USART_PRESC_PRESCALER_1 |\
294 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
295 /**
296 * @}
297 */
298
299 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
300 * @{
301 */
302 #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
303 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
304 /**
305 * @}
306 */
307
308 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
309 * @{
310 */
311 #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
312 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
313 /**
314 * @}
315 */
316
317 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
318 * @{
319 */
320 #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
321 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
322 /**
323 * @}
324 */
325
326 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
327 * @{
328 */
329 #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
330 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
331 /**
332 * @}
333 */
334
335 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
336 * @{
337 */
338 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
339 in positive/direct logic. (1=H, 0=L) */
340 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
341 in negative/inverse logic. (1=L, 0=H).
342 The parity bit is also inverted. */
343 /**
344 * @}
345 */
346
347 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
348 * @{
349 */
350 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
351 following the start bit */
352 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
353 following the start bit */
354 /**
355 * @}
356 */
357
358 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
359 * @{
360 */
361 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
362 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
363 /**
364 * @}
365 */
366
367 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
368 * @{
369 */
370 #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
371 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
372 when there is space in the receive buffer */
373 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
374 when the nCTS input is asserted (tied to 0)*/
375 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
376 /**
377 * @}
378 */
379
380 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
381 * @{
382 */
383 #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
384 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
385 /**
386 * @}
387 */
388
389 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
390 * @{
391 */
392 #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
393 #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
394 /**
395 * @}
396 */
397
398 /** @defgroup LPUART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
399 * @brief LPUART Autonomous Trigger selection
400 * @{
401 */
402 #define LL_LPUART_LPDMA1_CH0_TCF_TRG 0U /*!< LPUART LPDMA1 channel0 Internal Trigger */
403 #define LL_LPUART_LPDMA1_CH1_TCF_TRG 1U /*!< LPUART LPDMA1 channel1 Internal Trigger */
404 #define LL_LPUART_LPDMA1_CH2_TCF_TRG 2U /*!< LPUART LPDMA1 channel2 Internal Trigger */
405 #define LL_LPUART_LPDMA1_CH3_TCF_TRG 3U /*!< LPUART LPDMA1 channel3 Internal Trigger */
406 #define LL_LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */
407 #define LL_LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */
408 #define LL_LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */
409 #define LL_LPUART_LPTIM3_OUT_TRG 7U /*!< LPUART LPTIM3 out Internal Trigger */
410 #define LL_LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */
411 #define LL_LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */
412 #define LL_LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */
413 #define LL_LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */
414 /**
415 * @}
416 */
417
418 /** @defgroup LPUART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
419 * @brief LPUART Autonomous Trigger Polarity
420 * @{
421 */
422 #define LL_LPUART_TRIG_POLARITY_RISING 0x00000000U /*!< LPUART triggered on rising edge */
423 #define LL_LPUART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< LPUART triggered on falling edge */
424 /**
425 * @}
426 */
427 /**
428 * @}
429 */
430
431 /* Exported macro ------------------------------------------------------------*/
432 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
433 * @{
434 */
435
436 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
437 * @{
438 */
439
440 /**
441 * @brief Write a value in LPUART register
442 * @param __INSTANCE__ LPUART Instance
443 * @param __REG__ Register to be written
444 * @param __VALUE__ Value to be written in the register
445 * @retval None
446 */
447 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
448
449 /**
450 * @brief Read a value in LPUART register
451 * @param __INSTANCE__ LPUART Instance
452 * @param __REG__ Register to be read
453 * @retval Register value
454 */
455 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
456 /**
457 * @}
458 */
459
460 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
461 * @{
462 */
463
464 /**
465 * @brief Compute LPUARTDIV value according to Peripheral Clock and
466 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
467 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
468 * @param __PRESCALER__ This parameter can be one of the following values:
469 * @arg @ref LL_LPUART_PRESCALER_DIV1
470 * @arg @ref LL_LPUART_PRESCALER_DIV2
471 * @arg @ref LL_LPUART_PRESCALER_DIV4
472 * @arg @ref LL_LPUART_PRESCALER_DIV6
473 * @arg @ref LL_LPUART_PRESCALER_DIV8
474 * @arg @ref LL_LPUART_PRESCALER_DIV10
475 * @arg @ref LL_LPUART_PRESCALER_DIV12
476 * @arg @ref LL_LPUART_PRESCALER_DIV16
477 * @arg @ref LL_LPUART_PRESCALER_DIV32
478 * @arg @ref LL_LPUART_PRESCALER_DIV64
479 * @arg @ref LL_LPUART_PRESCALER_DIV128
480 * @arg @ref LL_LPUART_PRESCALER_DIV256
481 * @param __BAUDRATE__ Baud Rate value to achieve
482 * @retval LPUARTDIV value to be used for BRR register filling
483 */
484 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
485 ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
486 * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
487
488 /**
489 * @}
490 */
491
492 /**
493 * @}
494 */
495
496 /* Exported functions --------------------------------------------------------*/
497 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
498 * @{
499 */
500
501 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
502 * @{
503 */
504
505 /**
506 * @brief LPUART Enable
507 * @rmtoll CR1 UE LL_LPUART_Enable
508 * @param LPUARTx LPUART Instance
509 * @retval None
510 */
LL_LPUART_Enable(USART_TypeDef * LPUARTx)511 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
512 {
513 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
514 }
515
516 /**
517 * @brief LPUART Disable
518 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
519 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
520 * flags, in the LPUARTx_ISR are set to their default values.
521 * @note In order to go into low-power mode without generating errors on the line,
522 * the TE bit must be reset before and the software must wait
523 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
524 * The DMA requests are also reset when UE = 0 so the DMA channel must
525 * be disabled before resetting the UE bit.
526 * @rmtoll CR1 UE LL_LPUART_Disable
527 * @param LPUARTx LPUART Instance
528 * @retval None
529 */
LL_LPUART_Disable(USART_TypeDef * LPUARTx)530 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
531 {
532 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
533 }
534
535 /**
536 * @brief Indicate if LPUART is enabled
537 * @rmtoll CR1 UE LL_LPUART_IsEnabled
538 * @param LPUARTx LPUART Instance
539 * @retval State of bit (1 or 0).
540 */
LL_LPUART_IsEnabled(const USART_TypeDef * LPUARTx)541 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
542 {
543 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
544 }
545
546 /**
547 * @brief FIFO Mode Enable
548 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
549 * @param LPUARTx LPUART Instance
550 * @retval None
551 */
LL_LPUART_EnableFIFO(USART_TypeDef * LPUARTx)552 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
553 {
554 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
555 }
556
557 /**
558 * @brief FIFO Mode Disable
559 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
560 * @param LPUARTx LPUART Instance
561 * @retval None
562 */
LL_LPUART_DisableFIFO(USART_TypeDef * LPUARTx)563 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
564 {
565 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
566 }
567
568 /**
569 * @brief Indicate if FIFO Mode is enabled
570 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
571 * @param LPUARTx LPUART Instance
572 * @retval State of bit (1 or 0).
573 */
LL_LPUART_IsEnabledFIFO(const USART_TypeDef * LPUARTx)574 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
575 {
576 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
577 }
578
579 /**
580 * @brief Configure TX FIFO Threshold
581 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
582 * @param LPUARTx LPUART Instance
583 * @param Threshold This parameter can be one of the following values:
584 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
585 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
586 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
587 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
588 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
589 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
590 * @retval None
591 */
LL_LPUART_SetTXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)592 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
593 {
594 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
595 }
596
597 /**
598 * @brief Return TX FIFO Threshold Configuration
599 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
600 * @param LPUARTx LPUART Instance
601 * @retval Returned value can be one of the following values:
602 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
603 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
604 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
605 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
606 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
607 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
608 */
LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef * LPUARTx)609 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
610 {
611 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
612 }
613
614 /**
615 * @brief Configure RX FIFO Threshold
616 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
617 * @param LPUARTx LPUART Instance
618 * @param Threshold This parameter can be one of the following values:
619 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
620 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
621 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
622 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
623 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
624 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
625 * @retval None
626 */
LL_LPUART_SetRXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)627 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
628 {
629 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
630 }
631
632 /**
633 * @brief Return RX FIFO Threshold Configuration
634 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
635 * @param LPUARTx LPUART Instance
636 * @retval Returned value can be one of the following values:
637 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
638 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
639 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
640 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
641 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
642 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
643 */
LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef * LPUARTx)644 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
645 {
646 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
647 }
648
649 /**
650 * @brief Configure TX and RX FIFOs Threshold
651 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
652 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
653 * @param LPUARTx LPUART Instance
654 * @param TXThreshold This parameter can be one of the following values:
655 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
656 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
657 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
658 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
659 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
660 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
661 * @param RXThreshold This parameter can be one of the following values:
662 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
663 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
664 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
665 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
666 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
667 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
668 * @retval None
669 */
LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef * LPUARTx,uint32_t TXThreshold,uint32_t RXThreshold)670 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
671 {
672 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
673 (RXThreshold << USART_CR3_RXFTCFG_Pos));
674 }
675
676 /**
677 * @brief LPUART enabled in STOP Mode
678 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
679 * LPUART clock selection is HSI or LSE in RCC.
680 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
681 * @param LPUARTx LPUART Instance
682 * @retval None
683 */
LL_LPUART_EnableInStopMode(USART_TypeDef * LPUARTx)684 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
685 {
686 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
687 }
688
689 /**
690 * @brief LPUART disabled in STOP Mode
691 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
692 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
693 * @param LPUARTx LPUART Instance
694 * @retval None
695 */
LL_LPUART_DisableInStopMode(USART_TypeDef * LPUARTx)696 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
697 {
698 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
699 }
700
701 /**
702 * @brief Indicate if LPUART is enabled in STOP Mode
703 * (able to wake up MCU from Stop mode or not)
704 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
705 * @param LPUARTx LPUART Instance
706 * @retval State of bit (1 or 0).
707 */
LL_LPUART_IsEnabledInStopMode(const USART_TypeDef * LPUARTx)708 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
709 {
710 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
711 }
712
713 /**
714 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
715 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
716 * @param LPUARTx LPUART Instance
717 * @retval None
718 */
LL_LPUART_EnableDirectionRx(USART_TypeDef * LPUARTx)719 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
720 {
721 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
722 }
723
724 /**
725 * @brief Receiver Disable
726 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
727 * @param LPUARTx LPUART Instance
728 * @retval None
729 */
LL_LPUART_DisableDirectionRx(USART_TypeDef * LPUARTx)730 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
731 {
732 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
733 }
734
735 /**
736 * @brief Transmitter Enable
737 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
738 * @param LPUARTx LPUART Instance
739 * @retval None
740 */
LL_LPUART_EnableDirectionTx(USART_TypeDef * LPUARTx)741 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
742 {
743 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
744 }
745
746 /**
747 * @brief Transmitter Disable
748 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
749 * @param LPUARTx LPUART Instance
750 * @retval None
751 */
LL_LPUART_DisableDirectionTx(USART_TypeDef * LPUARTx)752 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
753 {
754 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
755 }
756
757 /**
758 * @brief Configure simultaneously enabled/disabled states
759 * of Transmitter and Receiver
760 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
761 * CR1 TE LL_LPUART_SetTransferDirection
762 * @param LPUARTx LPUART Instance
763 * @param TransferDirection This parameter can be one of the following values:
764 * @arg @ref LL_LPUART_DIRECTION_NONE
765 * @arg @ref LL_LPUART_DIRECTION_RX
766 * @arg @ref LL_LPUART_DIRECTION_TX
767 * @arg @ref LL_LPUART_DIRECTION_TX_RX
768 * @retval None
769 */
LL_LPUART_SetTransferDirection(USART_TypeDef * LPUARTx,uint32_t TransferDirection)770 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
771 {
772 ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
773 }
774
775 /**
776 * @brief Return enabled/disabled states of Transmitter and Receiver
777 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
778 * CR1 TE LL_LPUART_GetTransferDirection
779 * @param LPUARTx LPUART Instance
780 * @retval Returned value can be one of the following values:
781 * @arg @ref LL_LPUART_DIRECTION_NONE
782 * @arg @ref LL_LPUART_DIRECTION_RX
783 * @arg @ref LL_LPUART_DIRECTION_TX
784 * @arg @ref LL_LPUART_DIRECTION_TX_RX
785 */
LL_LPUART_GetTransferDirection(const USART_TypeDef * LPUARTx)786 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
787 {
788 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
789 }
790
791 /**
792 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
793 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
794 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
795 * (depending on data width) and parity is checked on the received data.
796 * @rmtoll CR1 PS LL_LPUART_SetParity\n
797 * CR1 PCE LL_LPUART_SetParity
798 * @param LPUARTx LPUART Instance
799 * @param Parity This parameter can be one of the following values:
800 * @arg @ref LL_LPUART_PARITY_NONE
801 * @arg @ref LL_LPUART_PARITY_EVEN
802 * @arg @ref LL_LPUART_PARITY_ODD
803 * @retval None
804 */
LL_LPUART_SetParity(USART_TypeDef * LPUARTx,uint32_t Parity)805 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
806 {
807 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
808 }
809
810 /**
811 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
812 * @rmtoll CR1 PS LL_LPUART_GetParity\n
813 * CR1 PCE LL_LPUART_GetParity
814 * @param LPUARTx LPUART Instance
815 * @retval Returned value can be one of the following values:
816 * @arg @ref LL_LPUART_PARITY_NONE
817 * @arg @ref LL_LPUART_PARITY_EVEN
818 * @arg @ref LL_LPUART_PARITY_ODD
819 */
LL_LPUART_GetParity(const USART_TypeDef * LPUARTx)820 __STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
821 {
822 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
823 }
824
825 /**
826 * @brief Set Receiver Wake Up method from Mute mode.
827 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
828 * @param LPUARTx LPUART Instance
829 * @param Method This parameter can be one of the following values:
830 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
831 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
832 * @retval None
833 */
LL_LPUART_SetWakeUpMethod(USART_TypeDef * LPUARTx,uint32_t Method)834 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
835 {
836 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
837 }
838
839 /**
840 * @brief Return Receiver Wake Up method from Mute mode
841 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
842 * @param LPUARTx LPUART Instance
843 * @retval Returned value can be one of the following values:
844 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
845 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
846 */
LL_LPUART_GetWakeUpMethod(const USART_TypeDef * LPUARTx)847 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
848 {
849 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
850 }
851
852 /**
853 * @brief Set Word length (nb of data bits, excluding start and stop bits)
854 * @rmtoll CR1 M LL_LPUART_SetDataWidth
855 * @param LPUARTx LPUART Instance
856 * @param DataWidth This parameter can be one of the following values:
857 * @arg @ref LL_LPUART_DATAWIDTH_7B
858 * @arg @ref LL_LPUART_DATAWIDTH_8B
859 * @arg @ref LL_LPUART_DATAWIDTH_9B
860 * @retval None
861 */
LL_LPUART_SetDataWidth(USART_TypeDef * LPUARTx,uint32_t DataWidth)862 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
863 {
864 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
865 }
866
867 /**
868 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
869 * @rmtoll CR1 M LL_LPUART_GetDataWidth
870 * @param LPUARTx LPUART Instance
871 * @retval Returned value can be one of the following values:
872 * @arg @ref LL_LPUART_DATAWIDTH_7B
873 * @arg @ref LL_LPUART_DATAWIDTH_8B
874 * @arg @ref LL_LPUART_DATAWIDTH_9B
875 */
LL_LPUART_GetDataWidth(const USART_TypeDef * LPUARTx)876 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
877 {
878 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
879 }
880
881 /**
882 * @brief Allow switch between Mute Mode and Active mode
883 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
884 * @param LPUARTx LPUART Instance
885 * @retval None
886 */
LL_LPUART_EnableMuteMode(USART_TypeDef * LPUARTx)887 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
888 {
889 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
890 }
891
892 /**
893 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
894 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
895 * @param LPUARTx LPUART Instance
896 * @retval None
897 */
LL_LPUART_DisableMuteMode(USART_TypeDef * LPUARTx)898 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
899 {
900 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
901 }
902
903 /**
904 * @brief Indicate if switch between Mute Mode and Active mode is allowed
905 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
906 * @param LPUARTx LPUART Instance
907 * @retval State of bit (1 or 0).
908 */
LL_LPUART_IsEnabledMuteMode(const USART_TypeDef * LPUARTx)909 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
910 {
911 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
912 }
913
914 /**
915 * @brief Configure Clock source prescaler for baudrate generator and oversampling
916 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
917 * @param LPUARTx LPUART Instance
918 * @param PrescalerValue This parameter can be one of the following values:
919 * @arg @ref LL_LPUART_PRESCALER_DIV1
920 * @arg @ref LL_LPUART_PRESCALER_DIV2
921 * @arg @ref LL_LPUART_PRESCALER_DIV4
922 * @arg @ref LL_LPUART_PRESCALER_DIV6
923 * @arg @ref LL_LPUART_PRESCALER_DIV8
924 * @arg @ref LL_LPUART_PRESCALER_DIV10
925 * @arg @ref LL_LPUART_PRESCALER_DIV12
926 * @arg @ref LL_LPUART_PRESCALER_DIV16
927 * @arg @ref LL_LPUART_PRESCALER_DIV32
928 * @arg @ref LL_LPUART_PRESCALER_DIV64
929 * @arg @ref LL_LPUART_PRESCALER_DIV128
930 * @arg @ref LL_LPUART_PRESCALER_DIV256
931 * @retval None
932 */
LL_LPUART_SetPrescaler(USART_TypeDef * LPUARTx,uint32_t PrescalerValue)933 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
934 {
935 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
936 }
937
938 /**
939 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
940 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
941 * @param LPUARTx LPUART Instance
942 * @retval Returned value can be one of the following values:
943 * @arg @ref LL_LPUART_PRESCALER_DIV1
944 * @arg @ref LL_LPUART_PRESCALER_DIV2
945 * @arg @ref LL_LPUART_PRESCALER_DIV4
946 * @arg @ref LL_LPUART_PRESCALER_DIV6
947 * @arg @ref LL_LPUART_PRESCALER_DIV8
948 * @arg @ref LL_LPUART_PRESCALER_DIV10
949 * @arg @ref LL_LPUART_PRESCALER_DIV12
950 * @arg @ref LL_LPUART_PRESCALER_DIV16
951 * @arg @ref LL_LPUART_PRESCALER_DIV32
952 * @arg @ref LL_LPUART_PRESCALER_DIV64
953 * @arg @ref LL_LPUART_PRESCALER_DIV128
954 * @arg @ref LL_LPUART_PRESCALER_DIV256
955 */
LL_LPUART_GetPrescaler(const USART_TypeDef * LPUARTx)956 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
957 {
958 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
959 }
960
961 /**
962 * @brief Set the length of the stop bits
963 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
964 * @param LPUARTx LPUART Instance
965 * @param StopBits This parameter can be one of the following values:
966 * @arg @ref LL_LPUART_STOPBITS_1
967 * @arg @ref LL_LPUART_STOPBITS_2
968 * @retval None
969 */
LL_LPUART_SetStopBitsLength(USART_TypeDef * LPUARTx,uint32_t StopBits)970 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
971 {
972 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
973 }
974
975 /**
976 * @brief Retrieve the length of the stop bits
977 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
978 * @param LPUARTx LPUART Instance
979 * @retval Returned value can be one of the following values:
980 * @arg @ref LL_LPUART_STOPBITS_1
981 * @arg @ref LL_LPUART_STOPBITS_2
982 */
LL_LPUART_GetStopBitsLength(const USART_TypeDef * LPUARTx)983 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
984 {
985 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
986 }
987
988 /**
989 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
990 * @note Call of this function is equivalent to following function call sequence :
991 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
992 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
993 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
994 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
995 * CR1 PCE LL_LPUART_ConfigCharacter\n
996 * CR1 M LL_LPUART_ConfigCharacter\n
997 * CR2 STOP LL_LPUART_ConfigCharacter
998 * @param LPUARTx LPUART Instance
999 * @param DataWidth This parameter can be one of the following values:
1000 * @arg @ref LL_LPUART_DATAWIDTH_7B
1001 * @arg @ref LL_LPUART_DATAWIDTH_8B
1002 * @arg @ref LL_LPUART_DATAWIDTH_9B
1003 * @param Parity This parameter can be one of the following values:
1004 * @arg @ref LL_LPUART_PARITY_NONE
1005 * @arg @ref LL_LPUART_PARITY_EVEN
1006 * @arg @ref LL_LPUART_PARITY_ODD
1007 * @param StopBits This parameter can be one of the following values:
1008 * @arg @ref LL_LPUART_STOPBITS_1
1009 * @arg @ref LL_LPUART_STOPBITS_2
1010 * @retval None
1011 */
LL_LPUART_ConfigCharacter(USART_TypeDef * LPUARTx,uint32_t DataWidth,uint32_t Parity,uint32_t StopBits)1012 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
1013 uint32_t StopBits)
1014 {
1015 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
1016 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
1017 }
1018
1019 /**
1020 * @brief Configure TX/RX pins swapping setting.
1021 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
1022 * @param LPUARTx LPUART Instance
1023 * @param SwapConfig This parameter can be one of the following values:
1024 * @arg @ref LL_LPUART_TXRX_STANDARD
1025 * @arg @ref LL_LPUART_TXRX_SWAPPED
1026 * @retval None
1027 */
LL_LPUART_SetTXRXSwap(USART_TypeDef * LPUARTx,uint32_t SwapConfig)1028 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
1029 {
1030 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
1031 }
1032
1033 /**
1034 * @brief Retrieve TX/RX pins swapping configuration.
1035 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
1036 * @param LPUARTx LPUART Instance
1037 * @retval Returned value can be one of the following values:
1038 * @arg @ref LL_LPUART_TXRX_STANDARD
1039 * @arg @ref LL_LPUART_TXRX_SWAPPED
1040 */
LL_LPUART_GetTXRXSwap(const USART_TypeDef * LPUARTx)1041 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
1042 {
1043 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
1044 }
1045
1046 /**
1047 * @brief Configure RX pin active level logic
1048 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
1049 * @param LPUARTx LPUART Instance
1050 * @param PinInvMethod This parameter can be one of the following values:
1051 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1052 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1053 * @retval None
1054 */
LL_LPUART_SetRXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1055 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1056 {
1057 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
1058 }
1059
1060 /**
1061 * @brief Retrieve RX pin active level logic configuration
1062 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
1063 * @param LPUARTx LPUART Instance
1064 * @retval Returned value can be one of the following values:
1065 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1066 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1067 */
LL_LPUART_GetRXPinLevel(const USART_TypeDef * LPUARTx)1068 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
1069 {
1070 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
1071 }
1072
1073 /**
1074 * @brief Configure TX pin active level logic
1075 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
1076 * @param LPUARTx LPUART Instance
1077 * @param PinInvMethod This parameter can be one of the following values:
1078 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1079 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1080 * @retval None
1081 */
LL_LPUART_SetTXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1082 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1083 {
1084 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
1085 }
1086
1087 /**
1088 * @brief Retrieve TX pin active level logic configuration
1089 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
1090 * @param LPUARTx LPUART Instance
1091 * @retval Returned value can be one of the following values:
1092 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1093 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1094 */
LL_LPUART_GetTXPinLevel(const USART_TypeDef * LPUARTx)1095 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
1096 {
1097 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
1098 }
1099
1100 /**
1101 * @brief Configure Binary data logic.
1102 *
1103 * @note Allow to define how Logical data from the data register are send/received :
1104 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
1105 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
1106 * @param LPUARTx LPUART Instance
1107 * @param DataLogic This parameter can be one of the following values:
1108 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1109 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1110 * @retval None
1111 */
LL_LPUART_SetBinaryDataLogic(USART_TypeDef * LPUARTx,uint32_t DataLogic)1112 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
1113 {
1114 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
1115 }
1116
1117 /**
1118 * @brief Retrieve Binary data configuration
1119 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
1120 * @param LPUARTx LPUART Instance
1121 * @retval Returned value can be one of the following values:
1122 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1123 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1124 */
LL_LPUART_GetBinaryDataLogic(const USART_TypeDef * LPUARTx)1125 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
1126 {
1127 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
1128 }
1129
1130 /**
1131 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
1132 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1133 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1134 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
1135 * @param LPUARTx LPUART Instance
1136 * @param BitOrder This parameter can be one of the following values:
1137 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1138 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1139 * @retval None
1140 */
LL_LPUART_SetTransferBitOrder(USART_TypeDef * LPUARTx,uint32_t BitOrder)1141 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
1142 {
1143 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
1144 }
1145
1146 /**
1147 * @brief Return transfer bit order (either Less or Most Significant Bit First)
1148 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1149 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1150 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
1151 * @param LPUARTx LPUART Instance
1152 * @retval Returned value can be one of the following values:
1153 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1154 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1155 */
LL_LPUART_GetTransferBitOrder(const USART_TypeDef * LPUARTx)1156 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
1157 {
1158 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
1159 }
1160
1161 /**
1162 * @brief Set Address of the LPUART node.
1163 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
1164 * for wake up with address mark detection.
1165 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
1166 * (b7-b4 should be set to 0)
1167 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
1168 * (This is used in multiprocessor communication during Mute mode or Stop mode,
1169 * for wake up with 7-bit address mark detection.
1170 * The MSB of the character sent by the transmitter should be equal to 1.
1171 * It may also be used for character detection during normal reception,
1172 * Mute mode inactive (for example, end of block detection in ModBus protocol).
1173 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
1174 * value and CMF flag is set on match)
1175 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
1176 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
1177 * @param LPUARTx LPUART Instance
1178 * @param AddressLen This parameter can be one of the following values:
1179 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1180 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1181 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
1182 * @retval None
1183 */
LL_LPUART_ConfigNodeAddress(USART_TypeDef * LPUARTx,uint32_t AddressLen,uint32_t NodeAddress)1184 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
1185 {
1186 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
1187 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
1188 }
1189
1190 /**
1191 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
1192 * @note If 4-bit Address Detection is selected in ADDM7,
1193 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
1194 * If 7-bit Address Detection is selected in ADDM7,
1195 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
1196 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
1197 * @param LPUARTx LPUART Instance
1198 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
1199 */
LL_LPUART_GetNodeAddress(const USART_TypeDef * LPUARTx)1200 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
1201 {
1202 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
1203 }
1204
1205 /**
1206 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
1207 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
1208 * @param LPUARTx LPUART Instance
1209 * @retval Returned value can be one of the following values:
1210 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1211 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1212 */
LL_LPUART_GetNodeAddressLen(const USART_TypeDef * LPUARTx)1213 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
1214 {
1215 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
1216 }
1217
1218 /**
1219 * @brief Enable RTS HW Flow Control
1220 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
1221 * @param LPUARTx LPUART Instance
1222 * @retval None
1223 */
LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1224 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1225 {
1226 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1227 }
1228
1229 /**
1230 * @brief Disable RTS HW Flow Control
1231 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
1232 * @param LPUARTx LPUART Instance
1233 * @retval None
1234 */
LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1235 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1236 {
1237 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1238 }
1239
1240 /**
1241 * @brief Enable CTS HW Flow Control
1242 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
1243 * @param LPUARTx LPUART Instance
1244 * @retval None
1245 */
LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1246 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1247 {
1248 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1249 }
1250
1251 /**
1252 * @brief Disable CTS HW Flow Control
1253 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
1254 * @param LPUARTx LPUART Instance
1255 * @retval None
1256 */
LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1257 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1258 {
1259 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1260 }
1261
1262 /**
1263 * @brief Configure HW Flow Control mode (both CTS and RTS)
1264 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
1265 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
1266 * @param LPUARTx LPUART Instance
1267 * @param HardwareFlowControl This parameter can be one of the following values:
1268 * @arg @ref LL_LPUART_HWCONTROL_NONE
1269 * @arg @ref LL_LPUART_HWCONTROL_RTS
1270 * @arg @ref LL_LPUART_HWCONTROL_CTS
1271 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1272 * @retval None
1273 */
LL_LPUART_SetHWFlowCtrl(USART_TypeDef * LPUARTx,uint32_t HardwareFlowControl)1274 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1275 {
1276 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1277 }
1278
1279 /**
1280 * @brief Return HW Flow Control configuration (both CTS and RTS)
1281 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
1282 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
1283 * @param LPUARTx LPUART Instance
1284 * @retval Returned value can be one of the following values:
1285 * @arg @ref LL_LPUART_HWCONTROL_NONE
1286 * @arg @ref LL_LPUART_HWCONTROL_RTS
1287 * @arg @ref LL_LPUART_HWCONTROL_CTS
1288 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1289 */
LL_LPUART_GetHWFlowCtrl(const USART_TypeDef * LPUARTx)1290 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
1291 {
1292 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1293 }
1294
1295 /**
1296 * @brief Enable Overrun detection
1297 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
1298 * @param LPUARTx LPUART Instance
1299 * @retval None
1300 */
LL_LPUART_EnableOverrunDetect(USART_TypeDef * LPUARTx)1301 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1302 {
1303 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1304 }
1305
1306 /**
1307 * @brief Disable Overrun detection
1308 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
1309 * @param LPUARTx LPUART Instance
1310 * @retval None
1311 */
LL_LPUART_DisableOverrunDetect(USART_TypeDef * LPUARTx)1312 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1313 {
1314 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1315 }
1316
1317 /**
1318 * @brief Indicate if Overrun detection is enabled
1319 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
1320 * @param LPUARTx LPUART Instance
1321 * @retval State of bit (1 or 0).
1322 */
LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef * LPUARTx)1323 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
1324 {
1325 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1326 }
1327
1328 /**
1329 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
1330 *
1331 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
1332 * according to used Peripheral Clock and expected Baud Rate values
1333 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
1334 * (Baud rate value != 0).
1335 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
1336 * a care should be taken when generating high baud rates using high PeriphClk
1337 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
1338 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
1339 * @param LPUARTx LPUART Instance
1340 * @param PeriphClk Peripheral Clock
1341 * @param PrescalerValue This parameter can be one of the following values:
1342 * @arg @ref LL_LPUART_PRESCALER_DIV1
1343 * @arg @ref LL_LPUART_PRESCALER_DIV2
1344 * @arg @ref LL_LPUART_PRESCALER_DIV4
1345 * @arg @ref LL_LPUART_PRESCALER_DIV6
1346 * @arg @ref LL_LPUART_PRESCALER_DIV8
1347 * @arg @ref LL_LPUART_PRESCALER_DIV10
1348 * @arg @ref LL_LPUART_PRESCALER_DIV12
1349 * @arg @ref LL_LPUART_PRESCALER_DIV16
1350 * @arg @ref LL_LPUART_PRESCALER_DIV32
1351 * @arg @ref LL_LPUART_PRESCALER_DIV64
1352 * @arg @ref LL_LPUART_PRESCALER_DIV128
1353 * @arg @ref LL_LPUART_PRESCALER_DIV256
1354 * @param BaudRate Baud Rate
1355 * @retval None
1356 */
LL_LPUART_SetBaudRate(USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue,uint32_t BaudRate)1357 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
1358 uint32_t BaudRate)
1359 {
1360 if (BaudRate != 0U)
1361 {
1362 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
1363 }
1364 }
1365
1366 /**
1367 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
1368 * (full BRR content), and to used Peripheral Clock values
1369 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
1370 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
1371 * @param LPUARTx LPUART Instance
1372 * @param PeriphClk Peripheral Clock
1373 * @param PrescalerValue This parameter can be one of the following values:
1374 * @arg @ref LL_LPUART_PRESCALER_DIV1
1375 * @arg @ref LL_LPUART_PRESCALER_DIV2
1376 * @arg @ref LL_LPUART_PRESCALER_DIV4
1377 * @arg @ref LL_LPUART_PRESCALER_DIV6
1378 * @arg @ref LL_LPUART_PRESCALER_DIV8
1379 * @arg @ref LL_LPUART_PRESCALER_DIV10
1380 * @arg @ref LL_LPUART_PRESCALER_DIV12
1381 * @arg @ref LL_LPUART_PRESCALER_DIV16
1382 * @arg @ref LL_LPUART_PRESCALER_DIV32
1383 * @arg @ref LL_LPUART_PRESCALER_DIV64
1384 * @arg @ref LL_LPUART_PRESCALER_DIV128
1385 * @arg @ref LL_LPUART_PRESCALER_DIV256
1386 * @retval Baud Rate
1387 */
LL_LPUART_GetBaudRate(const USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue)1388 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
1389 uint32_t PrescalerValue)
1390 {
1391 uint32_t lpuartdiv;
1392 uint32_t brrresult;
1393 uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
1394
1395 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1396
1397 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1398 {
1399 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1400 }
1401 else
1402 {
1403 brrresult = 0x0UL;
1404 }
1405
1406 return (brrresult);
1407 }
1408
1409 /**
1410 * @}
1411 */
1412
1413 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
1414 * @{
1415 */
1416
1417 /**
1418 * @brief Enable Single Wire Half-Duplex mode
1419 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
1420 * @param LPUARTx LPUART Instance
1421 * @retval None
1422 */
LL_LPUART_EnableHalfDuplex(USART_TypeDef * LPUARTx)1423 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1424 {
1425 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1426 }
1427
1428 /**
1429 * @brief Disable Single Wire Half-Duplex mode
1430 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
1431 * @param LPUARTx LPUART Instance
1432 * @retval None
1433 */
LL_LPUART_DisableHalfDuplex(USART_TypeDef * LPUARTx)1434 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1435 {
1436 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1437 }
1438
1439 /**
1440 * @brief Indicate if Single Wire Half-Duplex mode is enabled
1441 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
1442 * @param LPUARTx LPUART Instance
1443 * @retval State of bit (1 or 0).
1444 */
LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef * LPUARTx)1445 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
1446 {
1447 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1448 }
1449
1450 /**
1451 * @}
1452 */
1453
1454 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
1455 * @{
1456 */
1457
1458 /**
1459 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1460 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
1461 * @param LPUARTx LPUART Instance
1462 * @param Time Value between Min_Data=0 and Max_Data=31
1463 * @retval None
1464 */
LL_LPUART_SetDEDeassertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1465 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1466 {
1467 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1468 }
1469
1470 /**
1471 * @brief Return DEDT (Driver Enable De-Assertion Time)
1472 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
1473 * @param LPUARTx LPUART Instance
1474 * @retval Time value expressed on 5 bits ([4:0] bits) : c
1475 */
LL_LPUART_GetDEDeassertionTime(const USART_TypeDef * LPUARTx)1476 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
1477 {
1478 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1479 }
1480
1481 /**
1482 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1483 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
1484 * @param LPUARTx LPUART Instance
1485 * @param Time Value between Min_Data=0 and Max_Data=31
1486 * @retval None
1487 */
LL_LPUART_SetDEAssertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1488 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1489 {
1490 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1491 }
1492
1493 /**
1494 * @brief Return DEAT (Driver Enable Assertion Time)
1495 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
1496 * @param LPUARTx LPUART Instance
1497 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
1498 */
LL_LPUART_GetDEAssertionTime(const USART_TypeDef * LPUARTx)1499 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
1500 {
1501 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1502 }
1503
1504 /**
1505 * @brief Enable Driver Enable (DE) Mode
1506 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
1507 * @param LPUARTx LPUART Instance
1508 * @retval None
1509 */
LL_LPUART_EnableDEMode(USART_TypeDef * LPUARTx)1510 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1511 {
1512 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1513 }
1514
1515 /**
1516 * @brief Disable Driver Enable (DE) Mode
1517 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
1518 * @param LPUARTx LPUART Instance
1519 * @retval None
1520 */
LL_LPUART_DisableDEMode(USART_TypeDef * LPUARTx)1521 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1522 {
1523 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1524 }
1525
1526 /**
1527 * @brief Indicate if Driver Enable (DE) Mode is enabled
1528 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
1529 * @param LPUARTx LPUART Instance
1530 * @retval State of bit (1 or 0).
1531 */
LL_LPUART_IsEnabledDEMode(const USART_TypeDef * LPUARTx)1532 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
1533 {
1534 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1535 }
1536
1537 /**
1538 * @brief Select Driver Enable Polarity
1539 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
1540 * @param LPUARTx LPUART Instance
1541 * @param Polarity This parameter can be one of the following values:
1542 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1543 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1544 * @retval None
1545 */
LL_LPUART_SetDESignalPolarity(USART_TypeDef * LPUARTx,uint32_t Polarity)1546 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1547 {
1548 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1549 }
1550
1551 /**
1552 * @brief Return Driver Enable Polarity
1553 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
1554 * @param LPUARTx LPUART Instance
1555 * @retval Returned value can be one of the following values:
1556 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1557 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1558 */
LL_LPUART_GetDESignalPolarity(const USART_TypeDef * LPUARTx)1559 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
1560 {
1561 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1562 }
1563
1564 /**
1565 * @}
1566 */
1567
1568 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
1569 * @{
1570 */
1571
1572 /**
1573 * @brief Check if the LPUART Parity Error Flag is set or not
1574 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
1575 * @param LPUARTx LPUART Instance
1576 * @retval State of bit (1 or 0).
1577 */
LL_LPUART_IsActiveFlag_PE(const USART_TypeDef * LPUARTx)1578 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
1579 {
1580 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1581 }
1582
1583 /**
1584 * @brief Check if the LPUART Framing Error Flag is set or not
1585 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
1586 * @param LPUARTx LPUART Instance
1587 * @retval State of bit (1 or 0).
1588 */
LL_LPUART_IsActiveFlag_FE(const USART_TypeDef * LPUARTx)1589 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
1590 {
1591 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1592 }
1593
1594 /**
1595 * @brief Check if the LPUART Noise error detected Flag is set or not
1596 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
1597 * @param LPUARTx LPUART Instance
1598 * @retval State of bit (1 or 0).
1599 */
LL_LPUART_IsActiveFlag_NE(const USART_TypeDef * LPUARTx)1600 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
1601 {
1602 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1603 }
1604
1605 /**
1606 * @brief Check if the LPUART OverRun Error Flag is set or not
1607 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
1608 * @param LPUARTx LPUART Instance
1609 * @retval State of bit (1 or 0).
1610 */
LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef * LPUARTx)1611 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
1612 {
1613 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1614 }
1615
1616 /**
1617 * @brief Check if the LPUART IDLE line detected Flag is set or not
1618 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
1619 * @param LPUARTx LPUART Instance
1620 * @retval State of bit (1 or 0).
1621 */
LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef * LPUARTx)1622 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
1623 {
1624 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1625 }
1626
1627 #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
1628
1629 /**
1630 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
1631 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1632 * @param LPUARTx LPUART Instance
1633 * @retval State of bit (1 or 0).
1634 */
LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef * LPUARTx)1635 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
1636 {
1637 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
1638 }
1639
1640 /**
1641 * @brief Check if the LPUART Transmission Complete Flag is set or not
1642 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
1643 * @param LPUARTx LPUART Instance
1644 * @retval State of bit (1 or 0).
1645 */
LL_LPUART_IsActiveFlag_TC(const USART_TypeDef * LPUARTx)1646 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
1647 {
1648 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1649 }
1650
1651 #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
1652
1653 /**
1654 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
1655 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
1656 * @param LPUARTx LPUART Instance
1657 * @retval State of bit (1 or 0).
1658 */
LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef * LPUARTx)1659 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
1660 {
1661 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
1662 }
1663
1664 /**
1665 * @brief Check if the LPUART CTS interrupt Flag is set or not
1666 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
1667 * @param LPUARTx LPUART Instance
1668 * @retval State of bit (1 or 0).
1669 */
LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef * LPUARTx)1670 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
1671 {
1672 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1673 }
1674
1675 /**
1676 * @brief Check if the LPUART CTS Flag is set or not
1677 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
1678 * @param LPUARTx LPUART Instance
1679 * @retval State of bit (1 or 0).
1680 */
LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef * LPUARTx)1681 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
1682 {
1683 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1684 }
1685
1686 /**
1687 * @brief Check if the LPUART Busy Flag is set or not
1688 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
1689 * @param LPUARTx LPUART Instance
1690 * @retval State of bit (1 or 0).
1691 */
LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef * LPUARTx)1692 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
1693 {
1694 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1695 }
1696
1697 /**
1698 * @brief Check if the LPUART Character Match Flag is set or not
1699 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
1700 * @param LPUARTx LPUART Instance
1701 * @retval State of bit (1 or 0).
1702 */
LL_LPUART_IsActiveFlag_CM(const USART_TypeDef * LPUARTx)1703 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
1704 {
1705 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1706 }
1707
1708 /**
1709 * @brief Check if the LPUART Send Break Flag is set or not
1710 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
1711 * @param LPUARTx LPUART Instance
1712 * @retval State of bit (1 or 0).
1713 */
LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef * LPUARTx)1714 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
1715 {
1716 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1717 }
1718
1719 /**
1720 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
1721 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
1722 * @param LPUARTx LPUART Instance
1723 * @retval State of bit (1 or 0).
1724 */
LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef * LPUARTx)1725 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
1726 {
1727 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1728 }
1729
1730 /**
1731 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
1732 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
1733 * @param LPUARTx LPUART Instance
1734 * @retval State of bit (1 or 0).
1735 */
LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef * LPUARTx)1736 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
1737 {
1738 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1739 }
1740
1741 /**
1742 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
1743 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
1744 * @param LPUARTx LPUART Instance
1745 * @retval State of bit (1 or 0).
1746 */
LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef * LPUARTx)1747 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
1748 {
1749 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1750 }
1751
1752 /**
1753 * @brief Check if the LPUART TX FIFO Empty Flag is set or not
1754 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
1755 * @param LPUARTx LPUART Instance
1756 * @retval State of bit (1 or 0).
1757 */
LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef * LPUARTx)1758 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
1759 {
1760 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
1761 }
1762
1763 /**
1764 * @brief Check if the LPUART RX FIFO Full Flag is set or not
1765 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
1766 * @param LPUARTx LPUART Instance
1767 * @retval State of bit (1 or 0).
1768 */
LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef * LPUARTx)1769 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
1770 {
1771 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
1772 }
1773
1774 /**
1775 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
1776 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
1777 * @param LPUARTx LPUART Instance
1778 * @retval State of bit (1 or 0).
1779 */
LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef * LPUARTx)1780 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
1781 {
1782 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
1783 }
1784
1785 /**
1786 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
1787 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
1788 * @param LPUARTx LPUART Instance
1789 * @retval State of bit (1 or 0).
1790 */
LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef * LPUARTx)1791 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
1792 {
1793 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
1794 }
1795
1796 /**
1797 * @brief Clear Parity Error Flag
1798 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
1799 * @param LPUARTx LPUART Instance
1800 * @retval None
1801 */
LL_LPUART_ClearFlag_PE(USART_TypeDef * LPUARTx)1802 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1803 {
1804 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1805 }
1806
1807 /**
1808 * @brief Clear Framing Error Flag
1809 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
1810 * @param LPUARTx LPUART Instance
1811 * @retval None
1812 */
LL_LPUART_ClearFlag_FE(USART_TypeDef * LPUARTx)1813 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1814 {
1815 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1816 }
1817
1818 /**
1819 * @brief Clear Noise detected Flag
1820 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
1821 * @param LPUARTx LPUART Instance
1822 * @retval None
1823 */
LL_LPUART_ClearFlag_NE(USART_TypeDef * LPUARTx)1824 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1825 {
1826 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
1827 }
1828
1829 /**
1830 * @brief Clear OverRun Error Flag
1831 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
1832 * @param LPUARTx LPUART Instance
1833 * @retval None
1834 */
LL_LPUART_ClearFlag_ORE(USART_TypeDef * LPUARTx)1835 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1836 {
1837 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1838 }
1839
1840 /**
1841 * @brief Clear IDLE line detected Flag
1842 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
1843 * @param LPUARTx LPUART Instance
1844 * @retval None
1845 */
LL_LPUART_ClearFlag_IDLE(USART_TypeDef * LPUARTx)1846 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
1847 {
1848 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
1849 }
1850
1851 /**
1852 * @brief Clear Transmission Complete Flag
1853 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
1854 * @param LPUARTx LPUART Instance
1855 * @retval None
1856 */
LL_LPUART_ClearFlag_TC(USART_TypeDef * LPUARTx)1857 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
1858 {
1859 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
1860 }
1861
1862 /**
1863 * @brief Clear CTS Interrupt Flag
1864 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
1865 * @param LPUARTx LPUART Instance
1866 * @retval None
1867 */
LL_LPUART_ClearFlag_nCTS(USART_TypeDef * LPUARTx)1868 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
1869 {
1870 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
1871 }
1872
1873 /**
1874 * @brief Clear Character Match Flag
1875 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
1876 * @param LPUARTx LPUART Instance
1877 * @retval None
1878 */
LL_LPUART_ClearFlag_CM(USART_TypeDef * LPUARTx)1879 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
1880 {
1881 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
1882 }
1883
1884 /**
1885 * @}
1886 */
1887
1888 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
1889 * @{
1890 */
1891
1892 /**
1893 * @brief Enable IDLE Interrupt
1894 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
1895 * @param LPUARTx LPUART Instance
1896 * @retval None
1897 */
LL_LPUART_EnableIT_IDLE(USART_TypeDef * LPUARTx)1898 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
1899 {
1900 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
1901 }
1902
1903 #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
1904
1905 /**
1906 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
1907 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
1908 * @param LPUARTx LPUART Instance
1909 * @retval None
1910 */
LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)1911 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1912 {
1913 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
1914 }
1915
1916 /**
1917 * @brief Enable Transmission Complete Interrupt
1918 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
1919 * @param LPUARTx LPUART Instance
1920 * @retval None
1921 */
LL_LPUART_EnableIT_TC(USART_TypeDef * LPUARTx)1922 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
1923 {
1924 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
1925 }
1926
1927 #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
1928
1929 /**
1930 * @brief Enable TX Empty and TX FIFO Not Full Interrupt
1931 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
1932 * @param LPUARTx LPUART Instance
1933 * @retval None
1934 */
LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)1935 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
1936 {
1937 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
1938 }
1939
1940 /**
1941 * @brief Enable Parity Error Interrupt
1942 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
1943 * @param LPUARTx LPUART Instance
1944 * @retval None
1945 */
LL_LPUART_EnableIT_PE(USART_TypeDef * LPUARTx)1946 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
1947 {
1948 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
1949 }
1950
1951 /**
1952 * @brief Enable Character Match Interrupt
1953 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
1954 * @param LPUARTx LPUART Instance
1955 * @retval None
1956 */
LL_LPUART_EnableIT_CM(USART_TypeDef * LPUARTx)1957 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
1958 {
1959 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
1960 }
1961
1962 /**
1963 * @brief Enable TX FIFO Empty Interrupt
1964 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
1965 * @param LPUARTx LPUART Instance
1966 * @retval None
1967 */
LL_LPUART_EnableIT_TXFE(USART_TypeDef * LPUARTx)1968 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
1969 {
1970 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
1971 }
1972
1973 /**
1974 * @brief Enable RX FIFO Full Interrupt
1975 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
1976 * @param LPUARTx LPUART Instance
1977 * @retval None
1978 */
LL_LPUART_EnableIT_RXFF(USART_TypeDef * LPUARTx)1979 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
1980 {
1981 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
1982 }
1983
1984 /**
1985 * @brief Enable Error Interrupt
1986 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
1987 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
1988 * - 0: Interrupt is inhibited
1989 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
1990 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
1991 * @param LPUARTx LPUART Instance
1992 * @retval None
1993 */
LL_LPUART_EnableIT_ERROR(USART_TypeDef * LPUARTx)1994 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
1995 {
1996 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
1997 }
1998
1999 /**
2000 * @brief Enable CTS Interrupt
2001 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
2002 * @param LPUARTx LPUART Instance
2003 * @retval None
2004 */
LL_LPUART_EnableIT_CTS(USART_TypeDef * LPUARTx)2005 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
2006 {
2007 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2008 }
2009
2010 /**
2011 * @brief Enable TX FIFO Threshold Interrupt
2012 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
2013 * @param LPUARTx LPUART Instance
2014 * @retval None
2015 */
LL_LPUART_EnableIT_TXFT(USART_TypeDef * LPUARTx)2016 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
2017 {
2018 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2019 }
2020
2021 /**
2022 * @brief Enable RX FIFO Threshold Interrupt
2023 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
2024 * @param LPUARTx LPUART Instance
2025 * @retval None
2026 */
LL_LPUART_EnableIT_RXFT(USART_TypeDef * LPUARTx)2027 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
2028 {
2029 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2030 }
2031
2032 /**
2033 * @brief Disable IDLE Interrupt
2034 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
2035 * @param LPUARTx LPUART Instance
2036 * @retval None
2037 */
LL_LPUART_DisableIT_IDLE(USART_TypeDef * LPUARTx)2038 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
2039 {
2040 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2041 }
2042
2043 #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2044
2045 /**
2046 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
2047 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
2048 * @param LPUARTx LPUART Instance
2049 * @retval None
2050 */
LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)2051 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2052 {
2053 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2054 }
2055
2056 /**
2057 * @brief Disable Transmission Complete Interrupt
2058 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
2059 * @param LPUARTx LPUART Instance
2060 * @retval None
2061 */
LL_LPUART_DisableIT_TC(USART_TypeDef * LPUARTx)2062 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
2063 {
2064 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2065 }
2066
2067 #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
2068
2069 /**
2070 * @brief Disable TX Empty and TX FIFO Not Full Interrupt
2071 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
2072 * @param LPUARTx LPUART Instance
2073 * @retval None
2074 */
LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)2075 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2076 {
2077 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2078 }
2079
2080 /**
2081 * @brief Disable Parity Error Interrupt
2082 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
2083 * @param LPUARTx LPUART Instance
2084 * @retval None
2085 */
LL_LPUART_DisableIT_PE(USART_TypeDef * LPUARTx)2086 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
2087 {
2088 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2089 }
2090
2091 /**
2092 * @brief Disable Character Match Interrupt
2093 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
2094 * @param LPUARTx LPUART Instance
2095 * @retval None
2096 */
LL_LPUART_DisableIT_CM(USART_TypeDef * LPUARTx)2097 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
2098 {
2099 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2100 }
2101
2102 /**
2103 * @brief Disable TX FIFO Empty Interrupt
2104 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
2105 * @param LPUARTx LPUART Instance
2106 * @retval None
2107 */
LL_LPUART_DisableIT_TXFE(USART_TypeDef * LPUARTx)2108 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
2109 {
2110 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2111 }
2112
2113 /**
2114 * @brief Disable RX FIFO Full Interrupt
2115 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
2116 * @param LPUARTx LPUART Instance
2117 * @retval None
2118 */
LL_LPUART_DisableIT_RXFF(USART_TypeDef * LPUARTx)2119 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
2120 {
2121 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2122 }
2123
2124 /**
2125 * @brief Disable Error Interrupt
2126 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2127 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2128 * - 0: Interrupt is inhibited
2129 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2130 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
2131 * @param LPUARTx LPUART Instance
2132 * @retval None
2133 */
LL_LPUART_DisableIT_ERROR(USART_TypeDef * LPUARTx)2134 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
2135 {
2136 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
2137 }
2138
2139 /**
2140 * @brief Disable CTS Interrupt
2141 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
2142 * @param LPUARTx LPUART Instance
2143 * @retval None
2144 */
LL_LPUART_DisableIT_CTS(USART_TypeDef * LPUARTx)2145 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
2146 {
2147 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2148 }
2149
2150 /**
2151 * @brief Disable TX FIFO Threshold Interrupt
2152 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
2153 * @param LPUARTx LPUART Instance
2154 * @retval None
2155 */
LL_LPUART_DisableIT_TXFT(USART_TypeDef * LPUARTx)2156 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
2157 {
2158 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2159 }
2160
2161 /**
2162 * @brief Disable RX FIFO Threshold Interrupt
2163 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
2164 * @param LPUARTx LPUART Instance
2165 * @retval None
2166 */
LL_LPUART_DisableIT_RXFT(USART_TypeDef * LPUARTx)2167 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
2168 {
2169 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2170 }
2171
2172 /**
2173 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
2174 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
2175 * @param LPUARTx LPUART Instance
2176 * @retval State of bit (1 or 0).
2177 */
LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef * LPUARTx)2178 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
2179 {
2180 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
2181 }
2182
2183 #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2184
2185 /**
2186 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
2187 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2188 * @param LPUARTx LPUART Instance
2189 * @retval State of bit (1 or 0).
2190 */
LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef * LPUARTx)2191 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
2192 {
2193 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
2194 }
2195
2196 /**
2197 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
2198 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
2199 * @param LPUARTx LPUART Instance
2200 * @retval State of bit (1 or 0).
2201 */
LL_LPUART_IsEnabledIT_TC(const USART_TypeDef * LPUARTx)2202 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
2203 {
2204 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
2205 }
2206
2207 #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
2208
2209 /**
2210 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
2211 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
2212 * @param LPUARTx LPUART Instance
2213 * @retval State of bit (1 or 0).
2214 */
LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef * LPUARTx)2215 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
2216 {
2217 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
2218 }
2219
2220 /**
2221 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
2222 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
2223 * @param LPUARTx LPUART Instance
2224 * @retval State of bit (1 or 0).
2225 */
LL_LPUART_IsEnabledIT_PE(const USART_TypeDef * LPUARTx)2226 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
2227 {
2228 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
2229 }
2230
2231 /**
2232 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
2233 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
2234 * @param LPUARTx LPUART Instance
2235 * @retval State of bit (1 or 0).
2236 */
LL_LPUART_IsEnabledIT_CM(const USART_TypeDef * LPUARTx)2237 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
2238 {
2239 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
2240 }
2241
2242 /**
2243 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
2244 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
2245 * @param LPUARTx LPUART Instance
2246 * @retval State of bit (1 or 0).
2247 */
LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef * LPUARTx)2248 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
2249 {
2250 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
2251 }
2252
2253 /**
2254 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
2255 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
2256 * @param LPUARTx LPUART Instance
2257 * @retval State of bit (1 or 0).
2258 */
LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef * LPUARTx)2259 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
2260 {
2261 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
2262 }
2263
2264 /**
2265 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
2266 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
2267 * @param LPUARTx LPUART Instance
2268 * @retval State of bit (1 or 0).
2269 */
LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef * LPUARTx)2270 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
2271 {
2272 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
2273 }
2274
2275 /**
2276 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
2277 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
2278 * @param LPUARTx LPUART Instance
2279 * @retval State of bit (1 or 0).
2280 */
LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef * LPUARTx)2281 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
2282 {
2283 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
2284 }
2285
2286 /**
2287 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
2288 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
2289 * @param LPUARTx LPUART Instance
2290 * @retval State of bit (1 or 0).
2291 */
LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef * LPUARTx)2292 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
2293 {
2294 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
2295 }
2296
2297 /**
2298 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
2299 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
2300 * @param LPUARTx LPUART Instance
2301 * @retval State of bit (1 or 0).
2302 */
LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef * LPUARTx)2303 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
2304 {
2305 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
2306 }
2307
2308 /**
2309 * @}
2310 */
2311
2312 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
2313 * @{
2314 */
2315
2316 /**
2317 * @brief Enable DMA Mode for reception
2318 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
2319 * @param LPUARTx LPUART Instance
2320 * @retval None
2321 */
LL_LPUART_EnableDMAReq_RX(USART_TypeDef * LPUARTx)2322 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
2323 {
2324 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2325 }
2326
2327 /**
2328 * @brief Disable DMA Mode for reception
2329 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
2330 * @param LPUARTx LPUART Instance
2331 * @retval None
2332 */
LL_LPUART_DisableDMAReq_RX(USART_TypeDef * LPUARTx)2333 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
2334 {
2335 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2336 }
2337
2338 /**
2339 * @brief Check if DMA Mode is enabled for reception
2340 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
2341 * @param LPUARTx LPUART Instance
2342 * @retval State of bit (1 or 0).
2343 */
LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef * LPUARTx)2344 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
2345 {
2346 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
2347 }
2348
2349 /**
2350 * @brief Enable DMA Mode for transmission
2351 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
2352 * @param LPUARTx LPUART Instance
2353 * @retval None
2354 */
LL_LPUART_EnableDMAReq_TX(USART_TypeDef * LPUARTx)2355 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
2356 {
2357 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2358 }
2359
2360 /**
2361 * @brief Disable DMA Mode for transmission
2362 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
2363 * @param LPUARTx LPUART Instance
2364 * @retval None
2365 */
LL_LPUART_DisableDMAReq_TX(USART_TypeDef * LPUARTx)2366 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
2367 {
2368 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2369 }
2370
2371 /**
2372 * @brief Check if DMA Mode is enabled for transmission
2373 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
2374 * @param LPUARTx LPUART Instance
2375 * @retval State of bit (1 or 0).
2376 */
LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef * LPUARTx)2377 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
2378 {
2379 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2380 }
2381
2382 /**
2383 * @brief Enable DMA Disabling on Reception Error
2384 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
2385 * @param LPUARTx LPUART Instance
2386 * @retval None
2387 */
LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2388 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2389 {
2390 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2391 }
2392
2393 /**
2394 * @brief Disable DMA Disabling on Reception Error
2395 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
2396 * @param LPUARTx LPUART Instance
2397 * @retval None
2398 */
LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2399 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2400 {
2401 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2402 }
2403
2404 /**
2405 * @brief Indicate if DMA Disabling on Reception Error is disabled
2406 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
2407 * @param LPUARTx LPUART Instance
2408 * @retval State of bit (1 or 0).
2409 */
LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef * LPUARTx)2410 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
2411 {
2412 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2413 }
2414
2415 /**
2416 * @brief Get the LPUART data register address used for DMA transfer
2417 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
2418 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
2419 * @param LPUARTx LPUART Instance
2420 * @param Direction This parameter can be one of the following values:
2421 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
2422 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
2423 * @retval Address of data register
2424 */
LL_LPUART_DMA_GetRegAddr(const USART_TypeDef * LPUARTx,uint32_t Direction)2425 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
2426 {
2427 uint32_t data_reg_addr;
2428
2429 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2430 {
2431 /* return address of TDR register */
2432 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
2433 }
2434 else
2435 {
2436 /* return address of RDR register */
2437 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
2438 }
2439
2440 return data_reg_addr;
2441 }
2442
2443 /**
2444 * @}
2445 */
2446
2447 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
2448 * @{
2449 */
2450
2451 /**
2452 * @brief Read Receiver Data register (Receive Data value, 8 bits)
2453 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
2454 * @param LPUARTx LPUART Instance
2455 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
2456 */
LL_LPUART_ReceiveData8(const USART_TypeDef * LPUARTx)2457 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
2458 {
2459 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2460 }
2461
2462 /**
2463 * @brief Read Receiver Data register (Receive Data value, 9 bits)
2464 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
2465 * @param LPUARTx LPUART Instance
2466 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
2467 */
LL_LPUART_ReceiveData9(const USART_TypeDef * LPUARTx)2468 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
2469 {
2470 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2471 }
2472
2473 /**
2474 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
2475 * @rmtoll TDR TDR LL_LPUART_TransmitData8
2476 * @param LPUARTx LPUART Instance
2477 * @param Value between Min_Data=0x00 and Max_Data=0xFF
2478 * @retval None
2479 */
LL_LPUART_TransmitData8(USART_TypeDef * LPUARTx,uint8_t Value)2480 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2481 {
2482 LPUARTx->TDR = Value;
2483 }
2484
2485 /**
2486 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
2487 * @rmtoll TDR TDR LL_LPUART_TransmitData9
2488 * @param LPUARTx LPUART Instance
2489 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
2490 * @retval None
2491 */
LL_LPUART_TransmitData9(USART_TypeDef * LPUARTx,uint16_t Value)2492 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2493 {
2494 LPUARTx->TDR = Value & 0x1FFUL;
2495 }
2496
2497 /**
2498 * @}
2499 */
2500
2501 /** @defgroup LPUART_LL_EF_Execution Execution
2502 * @{
2503 */
2504
2505 /**
2506 * @brief Request Break sending
2507 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
2508 * @param LPUARTx LPUART Instance
2509 * @retval None
2510 */
LL_LPUART_RequestBreakSending(USART_TypeDef * LPUARTx)2511 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2512 {
2513 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2514 }
2515
2516 /**
2517 * @brief Put LPUART in mute mode and set the RWU flag
2518 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
2519 * @param LPUARTx LPUART Instance
2520 * @retval None
2521 */
LL_LPUART_RequestEnterMuteMode(USART_TypeDef * LPUARTx)2522 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2523 {
2524 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2525 }
2526
2527 /**
2528 * @brief Request a Receive Data and FIFO flush
2529 * @note Allows to discard the received data without reading them, and avoid an overrun
2530 * condition.
2531 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
2532 * @param LPUARTx LPUART Instance
2533 * @retval None
2534 */
LL_LPUART_RequestRxDataFlush(USART_TypeDef * LPUARTx)2535 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2536 {
2537 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2538 }
2539
2540 /**
2541 * @brief Request a Transmit data FIFO flush
2542 * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This
2543 * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register).
2544 * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
2545 * FIFO mode feature is supported by the USARTx instance.
2546 * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush
2547 * @param LPUARTx LPUART Instance
2548 * @retval None
2549 */
LL_LPUART_RequestTxDataFlush(USART_TypeDef * LPUARTx)2550 __STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx)
2551 {
2552 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
2553 }
2554
2555 /**
2556 * @}
2557 */
2558
2559 /** @defgroup LPUART_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature
2560 * @{
2561 */
2562
2563 /**
2564 * @brief Enable Selected Trigger
2565 * @rmtoll AUTOCR TRIGEN LL_LPUART_Enable_SelectedTrigger
2566 * @param LPUARTx LPUART Instance
2567 * @retval None
2568 */
LL_LPUART_Enable_SelectedTrigger(USART_TypeDef * LPUARTx)2569 __STATIC_INLINE void LL_LPUART_Enable_SelectedTrigger(USART_TypeDef *LPUARTx)
2570 {
2571 SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN);
2572 }
2573
2574 /**
2575 * @brief Disable Selected Trigger
2576 * @rmtoll AUTOCR TRIGEN LL_LPUART_Disable_SelectedTrigger
2577 * @param LPUARTx LPUART Instance
2578 * @retval None
2579 */
LL_LPUART_Disable_SelectedTrigger(USART_TypeDef * LPUARTx)2580 __STATIC_INLINE void LL_LPUART_Disable_SelectedTrigger(USART_TypeDef *LPUARTx)
2581 {
2582 CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN);
2583 }
2584
2585 /**
2586 * @brief Indicate if selected Trigger is disabled or enabled
2587 * @rmtoll AUTOCR TRIGEN LL_LPUART_IsEnabled_SelectedTrigger
2588 * @param LPUARTx LPUART Instance
2589 * @retval State of bit (1 or 0).
2590 */
LL_LPUART_IsEnabled_SelectedTrigger(const USART_TypeDef * LPUARTx)2591 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled_SelectedTrigger(const USART_TypeDef *LPUARTx)
2592 {
2593 return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL);
2594 }
2595
2596 /**
2597 * @brief Enable Autonomous Send Idle Frame feature
2598 * @rmtoll AUTOCR IDLEDIS LL_LPUART_Enable_AutonomousSendIdleFrame
2599 * @param LPUARTx LPUART Instance
2600 * @retval None
2601 */
LL_LPUART_Enable_AutonomousSendIdleFrame(USART_TypeDef * LPUARTx)2602 __STATIC_INLINE void LL_LPUART_Enable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx)
2603 {
2604 CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
2605 }
2606
2607 /**
2608 * @brief Disable Autonomous Send Idle Frame feature
2609 * @rmtoll AUTOCR IDLEDIS LL_LPUART_Disable_AutonomousSendIdleFrame
2610 * @param LPUARTx LPUART Instance
2611 * @retval None
2612 */
LL_LPUART_Disable_AutonomousSendIdleFrame(USART_TypeDef * LPUARTx)2613 __STATIC_INLINE void LL_LPUART_Disable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx)
2614 {
2615 SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
2616 }
2617
2618 /**
2619 * @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled
2620 * @rmtoll AUTOCR IDLEDIS LL_LPUART_IsEnabled_AutonomousSendIdleFrame
2621 * @param LPUARTx LPUART Instance
2622 * @retval State of bit (1 or 0).
2623 */
LL_LPUART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef * LPUARTx)2624 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef *LPUARTx)
2625 {
2626 return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL);
2627 }
2628
2629 /**
2630 * @brief Configure the Number of transferred data in bytes
2631 * @rmtoll AUTOCR TDN LL_LPUART_SetNbTxData
2632 * @param LPUARTx LPUART Instance
2633 * @param Nbdata This parameter can be a value between 0 and 0xFFFF
2634 * @retval None
2635 */
LL_LPUART_SetNbTxData(USART_TypeDef * LPUARTx,uint32_t Nbdata)2636 __STATIC_INLINE void LL_LPUART_SetNbTxData(USART_TypeDef *LPUARTx, uint32_t Nbdata)
2637 {
2638 MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata);
2639 }
2640
2641 /**
2642 * @brief Retrieve the Number of transferred data in bytes
2643 * @rmtoll AUTOCR TDN LL_LPUART_GetNbTxData
2644 * @param LPUARTx LPUART Instance
2645 * @retval Returned value can be a value between 0 and 0xFFFF
2646 */
LL_LPUART_GetNbTxData(const USART_TypeDef * LPUARTx)2647 __STATIC_INLINE uint32_t LL_LPUART_GetNbTxData(const USART_TypeDef *LPUARTx)
2648 {
2649 return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TDN));
2650 }
2651
2652 /**
2653 * @brief Set the trigger polarity
2654 * @rmtoll AUTOCR TRIGPOL LL_LPUART_SetTriggerPolarity
2655 * @param LPUARTx LPUART Instance
2656 * @param Polarity This parameter can be one of the following values:
2657 * @arg @ref LL_LPUART_TRIG_POLARITY_RISING
2658 * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING
2659 * @retval None
2660 */
LL_LPUART_SetTriggerPolarity(USART_TypeDef * LPUARTx,uint32_t Polarity)2661 __STATIC_INLINE void LL_LPUART_SetTriggerPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
2662 {
2663 MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity);
2664 }
2665
2666 /**
2667 * @brief Get the trigger polarity
2668 * @rmtoll AUTOCR TRIGPOL LL_LPUART_GetTriggerPolarity
2669 * @param LPUARTx LPUART Instance
2670 * @retval Returned value can be one of the following values:
2671 * @arg @ref LL_LPUART_TRIG_POLARITY_RISING
2672 * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING
2673 */
LL_LPUART_GetTriggerPolarity(const USART_TypeDef * LPUARTx)2674 __STATIC_INLINE uint32_t LL_LPUART_GetTriggerPolarity(const USART_TypeDef *LPUARTx)
2675 {
2676 return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL));
2677 }
2678
2679 /**
2680 * @brief Set the selected trigger
2681 * @rmtoll AUTOCR TRIGSEL LL_LPUART_SetSelectedTrigger
2682 * @param LPUARTx LPUART Instance
2683 * @param Trigger This parameter can be one of the following values:
2684 * @arg @ref LL_LPUART_LPDMA1_CH0_TCF_TRG
2685 * @arg @ref LL_LPUART_LPDMA1_CH1_TCF_TRG
2686 * @arg @ref LL_LPUART_LPDMA1_CH2_TCF_TRG
2687 * @arg @ref LL_LPUART_LPDMA1_CH3_TCF_TRG
2688 * @arg @ref LL_LPUART_EXTI_LINE6_TRG
2689 * @arg @ref LL_LPUART_EXTI_LINE8_TRG
2690 * @arg @ref LL_LPUART_LPTIM1_OUT_TRG
2691 * @arg @ref LL_LPUART_LPTIM3_OUT_TRG
2692 * @arg @ref LL_LPUART_COMP1_OUT_TRG
2693 * @arg @ref LL_LPUART_COMP2_OUT_TRG
2694 * @arg @ref LL_LPUART_RTC_ALRA_TRG
2695 * @arg @ref LL_LPUART_RTC_WUT_TRG
2696 * @retval None
2697 */
LL_LPUART_SetSelectedTrigger(USART_TypeDef * LPUARTx,uint32_t Trigger)2698 __STATIC_INLINE void LL_LPUART_SetSelectedTrigger(USART_TypeDef *LPUARTx, uint32_t Trigger)
2699 {
2700 MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos));
2701 }
2702
2703 /**
2704 * @brief Get the selected trigger
2705 * @rmtoll AUTOCR TRIGSEL LL_LPUART_GetSelectedTrigger
2706 * @param LPUARTx LPUART Instance
2707 * @retval Returned value can be one of the following values:
2708 * @arg @ref LL_LPUART_LPDMA1_CH0_TCF_TRG
2709 * @arg @ref LL_LPUART_LPDMA1_CH1_TCF_TRG
2710 * @arg @ref LL_LPUART_LPDMA1_CH2_TCF_TRG
2711 * @arg @ref LL_LPUART_LPDMA1_CH3_TCF_TRG
2712 * @arg @ref LL_LPUART_EXTI_LINE6_TRG
2713 * @arg @ref LL_LPUART_EXTI_LINE8_TRG
2714 * @arg @ref LL_LPUART_LPTIM1_OUT_TRG
2715 * @arg @ref LL_LPUART_LPTIM3_OUT_TRG
2716 * @arg @ref LL_LPUART_COMP1_OUT_TRG
2717 * @arg @ref LL_LPUART_COMP2_OUT_TRG
2718 * @arg @ref LL_LPUART_RTC_ALRA_TRG
2719 * @arg @ref LL_LPUART_RTC_WUT_TRG
2720 */
LL_LPUART_GetSelectedTrigger(const USART_TypeDef * LPUARTx)2721 __STATIC_INLINE uint32_t LL_LPUART_GetSelectedTrigger(const USART_TypeDef *LPUARTx)
2722 {
2723 return (uint32_t)((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos));
2724 }
2725
2726 /**
2727 * @}
2728 */
2729
2730 #if defined(USE_FULL_LL_DRIVER)
2731 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
2732 * @{
2733 */
2734 ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
2735 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
2736 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2737 /**
2738 * @}
2739 */
2740 #endif /* USE_FULL_LL_DRIVER */
2741
2742 /**
2743 * @}
2744 */
2745
2746 /**
2747 * @}
2748 */
2749
2750 #endif /* LPUART1 */
2751
2752 /**
2753 * @}
2754 */
2755
2756 #ifdef __cplusplus
2757 }
2758 #endif
2759
2760 #endif /* STM32U5xx_LL_LPUART_H */
2761
