1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_uart_ex.h 4 * @author MCD Application Team 5 * @brief Header file of UART HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_UART_EX_H 21 #define STM32U5xx_HAL_UART_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup UARTEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup UARTEx_Exported_Types UARTEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief UART wake up from stop mode parameters 45 */ 46 typedef struct 47 { 48 uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). 49 This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. 50 If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must 51 be filled up. */ 52 53 uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. 54 This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ 55 56 uint8_t Address; /*!< UART/USART node address (7-bit long max). */ 57 } UART_WakeUpTypeDef; 58 59 /** 60 * @brief UART Autonomous mode parameters 61 */ 62 typedef struct 63 { 64 uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.This parameter can be a value of 65 @ref UARTEx_Autonomous_mode.*/ 66 67 uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically. 68 This parameter can be a value of @ref UARTEx_Autonomous_Trigger_selection 69 or @ref UARTEx_Low_Power_Autonomous_Trigger_selection.*/ 70 71 uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity. 72 This parameter can be a value of @ref UARTEx_Autonomous_Trigger_Polarity */ 73 74 uint32_t DataSize; /*!< Specifies the transmitted data size in byte */ 75 76 uint32_t IdleFrame; /*!< Specifies whether the IDLE frame transmission is enabled or disabled. 77 This parameter can be a value of @ref UARTEx_Autonomous_IDLE_FRAME. */ 78 } UART_AutonomousModeConfTypeDef; 79 80 /** 81 * @} 82 */ 83 84 /* Exported constants --------------------------------------------------------*/ 85 /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants 86 * @{ 87 */ 88 89 /** @defgroup UARTEx_Word_Length UARTEx Word Length 90 * @{ 91 */ 92 #define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ 93 #define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ 94 #define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ 95 /** 96 * @} 97 */ 98 99 /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length 100 * @{ 101 */ 102 #define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ 103 #define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ 104 /** 105 * @} 106 */ 107 108 /** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode 109 * @brief UART FIFO mode 110 * @{ 111 */ 112 #define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ 113 #define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ 114 /** 115 * @} 116 */ 117 118 /** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level 119 * @brief UART TXFIFO threshold level 120 * @{ 121 */ 122 #define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ 123 #define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ 124 #define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ 125 #define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ 126 #define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ 127 #define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ 128 /** 129 * @} 130 */ 131 132 /** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level 133 * @brief UART RXFIFO threshold level 134 * @{ 135 */ 136 #define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ 137 #define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ 138 #define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ 139 #define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ 140 #define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ 141 #define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ 142 /** 143 * @} 144 */ 145 146 /** @defgroup UARTEx_Autonomous_mode UARTEx Autonomous Mode 147 * @brief UART Autonomous mode 148 * @{ 149 */ 150 #define UART_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */ 151 #define UART_AUTONOMOUS_MODE_ENABLE USART_AUTOCR_TRIGEN /*!< Autonomous mode enable */ 152 /** 153 * @} 154 */ 155 156 /** @defgroup UARTEx_Autonomous_Trigger_Polarity UARTEx Autonomous Trigger Polarity 157 * @brief UART Trigger polarity edge selection 158 * @{ 159 */ 160 #define UART_TRIG_POLARITY_RISING 0x00000000U /*!< UART triggered on rising edge */ 161 #define UART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< UART triggered on falling edge */ 162 /** 163 * @} 164 */ 165 166 /** @defgroup UARTEx_Autonomous_IDLE_FRAME UARTEx Autonomous IDLE Frame 167 * @brief UART IDLE frame transmission 168 * @{ 169 */ 170 #define UART_IDLE_FRAME_ENABLE 0x00000000U /*!< IDLE Frame sent after enabling the transmitter */ 171 #define UART_IDLE_FRAME_DISABLE USART_AUTOCR_IDLEDIS /*!< IDLE Frame not sent after enabling the transmitter */ 172 /** 173 * @} 174 */ 175 176 /** @defgroup UARTEx_Autonomous_Trigger_selection UARTEx Autonomous trigger selection 177 * @brief UART Autonomous Trigger selection 178 * @{ 179 */ 180 #define UART_GPDMA1_CH0_TCF_TRG 0U /*!< UART GPDMA1 channel0 Internal Trigger */ 181 #define UART_GPDMA1_CH1_TCF_TRG 1U /*!< UART GPDMA1 channel1 Internal Trigger */ 182 #define UART_GPDMA1_CH2_TCF_TRG 2U /*!< UART GPDMA1 channel2 Internal Trigger */ 183 #define UART_GPDMA1_CH3_TCF_TRG 3U /*!< UART GPDMA1 channel3 Internal Trigger */ 184 #define UART_EXTI_LINE6_TRG 4U /*!< UART EXTI line 6 Internal Trigger */ 185 #define UART_EXTI_LINE9_TRG 5U /*!< UART EXTI line 9 Internal Trigger */ 186 #define UART_LPTIM1_OUT_TRG 6U /*!< UART LPTIM1 out Internal Trigger */ 187 #define UART_LPTIM2_OUT_TRG 7U /*!< UART LPTIM2 out Internal Trigger */ 188 #define UART_COMP1_OUT_TRG 8U /*!< UART COMP1 out Internal Trigger */ 189 #define UART_COMP2_OUT_TRG 9U /*!< UART COMP2 out Internal Trigger */ 190 #define UART_RTC_ALRA_TRG 10U /*!< UART RTC alarm Internal Trigger */ 191 #define UART_RTC_WUT_TRG 11U /*!< UART RTC wakeup Internal Trigger */ 192 /** 193 * @} 194 */ 195 196 /** @defgroup UARTEx_Low_Power_Autonomous_Trigger_selection UARTEx Low Power Autonomous trigger selection 197 * @brief LPUART Autonomous Trigger selection 198 * @{ 199 */ 200 #define LPUART_LPDMA1_CH0_TCF_TRG 0U /*!< LPUART LPDMA1 channel0 Internal Trigger */ 201 #define LPUART_LPDMA1_CH1_TCF_TRG 1U /*!< LPUART LPDMA1 channel1 Internal Trigger */ 202 #define LPUART_LPDMA1_CH2_TCF_TRG 2U /*!< LPUART LPDMA1 channel2 Internal Trigger */ 203 #define LPUART_LPDMA1_CH3_TCF_TRG 3U /*!< LPUART LPDMA1 channel3 Internal Trigger */ 204 #define LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */ 205 #define LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */ 206 #define LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */ 207 #define LPUART_LPTIM3_OUT_TRG 7U /*!< LPUART LPTIM3 out Internal Trigger */ 208 #define LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */ 209 #define LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */ 210 #define LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */ 211 #define LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */ 212 /** 213 * @} 214 */ 215 216 /** 217 * @} 218 */ 219 220 /* Exported macros -----------------------------------------------------------*/ 221 /* Exported functions --------------------------------------------------------*/ 222 /** @addtogroup UARTEx_Exported_Functions 223 * @{ 224 */ 225 226 /** @addtogroup UARTEx_Exported_Functions_Group1 227 * @{ 228 */ 229 230 /* Initialization and de-initialization functions ****************************/ 231 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, 232 uint32_t DeassertionTime); 233 234 /** 235 * @} 236 */ 237 238 /** @addtogroup UARTEx_Exported_Functions_Group2 239 * @{ 240 */ 241 242 void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); 243 void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); 244 245 /** 246 * @} 247 */ 248 249 /** @addtogroup UARTEx_Exported_Functions_Group3 250 * @{ 251 */ 252 253 /* Peripheral Control functions **********************************************/ 254 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); 255 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); 256 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); 257 258 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); 259 260 HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); 261 HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); 262 HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); 263 HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); 264 265 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, 266 uint32_t Timeout); 267 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); 268 #if defined(HAL_DMA_MODULE_ENABLED) 269 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); 270 #endif /* HAL_DMA_MODULE_ENABLED */ 271 272 HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); 273 274 /* Autonomous Mode Control functions **********************************************/ 275 HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, 276 const UART_AutonomousModeConfTypeDef *sConfig); 277 HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart, 278 UART_AutonomousModeConfTypeDef *sConfig); 279 HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart); 280 281 282 /** 283 * @} 284 */ 285 286 /** 287 * @} 288 */ 289 290 /* Private macros ------------------------------------------------------------*/ 291 /** @defgroup UARTEx_Private_Macros UARTEx Private Macros 292 * @{ 293 */ 294 295 /** @brief Report the UART clock source. 296 * @param __HANDLE__ specifies the UART Handle. 297 * @param __CLOCKSOURCE__ output variable. 298 * @retval UART clocking source, written in __CLOCKSOURCE__. 299 */ 300 #if defined(USART6) 301 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ 302 do { \ 303 if((__HANDLE__)->Instance == USART1) \ 304 { \ 305 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ 306 } \ 307 else if((__HANDLE__)->Instance == USART2) \ 308 { \ 309 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ 310 } \ 311 else if((__HANDLE__)->Instance == USART3) \ 312 { \ 313 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ 314 } \ 315 else if((__HANDLE__)->Instance == UART4) \ 316 { \ 317 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ 318 } \ 319 else if((__HANDLE__)->Instance == UART5) \ 320 { \ 321 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ 322 } \ 323 else if((__HANDLE__)->Instance == USART6) \ 324 { \ 325 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \ 326 } \ 327 else if((__HANDLE__)->Instance == LPUART1) \ 328 { \ 329 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ 330 } \ 331 else \ 332 { \ 333 (__CLOCKSOURCE__) = 0U; \ 334 } \ 335 } while(0U) 336 #elif defined(USART2) 337 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ 338 do { \ 339 if((__HANDLE__)->Instance == USART1) \ 340 { \ 341 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ 342 } \ 343 else if((__HANDLE__)->Instance == USART2) \ 344 { \ 345 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ 346 } \ 347 else if((__HANDLE__)->Instance == USART3) \ 348 { \ 349 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ 350 } \ 351 else if((__HANDLE__)->Instance == UART4) \ 352 { \ 353 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ 354 } \ 355 else if((__HANDLE__)->Instance == UART5) \ 356 { \ 357 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ 358 } \ 359 else if((__HANDLE__)->Instance == LPUART1) \ 360 { \ 361 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ 362 } \ 363 else \ 364 { \ 365 (__CLOCKSOURCE__) = 0U; \ 366 } \ 367 } while(0U) 368 #else 369 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ 370 do { \ 371 if((__HANDLE__)->Instance == USART1) \ 372 { \ 373 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ 374 } \ 375 else if((__HANDLE__)->Instance == USART3) \ 376 { \ 377 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ 378 } \ 379 else if((__HANDLE__)->Instance == UART4) \ 380 { \ 381 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ 382 } \ 383 else if((__HANDLE__)->Instance == UART5) \ 384 { \ 385 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ 386 } \ 387 else if((__HANDLE__)->Instance == LPUART1) \ 388 { \ 389 (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ 390 } \ 391 else \ 392 { \ 393 (__CLOCKSOURCE__) = 0U; \ 394 } \ 395 } while(0U) 396 #endif /* USART6 */ 397 398 /** @brief Report the UART mask to apply to retrieve the received data 399 * according to the word length and to the parity bits activation. 400 * @note If PCE = 1, the parity bit is not included in the data extracted 401 * by the reception API(). 402 * This masking operation is not carried out in the case of 403 * DMA transfers. 404 * @param __HANDLE__ specifies the UART Handle. 405 * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. 406 */ 407 #define UART_MASK_COMPUTATION(__HANDLE__) \ 408 do { \ 409 if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ 410 { \ 411 if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ 412 { \ 413 (__HANDLE__)->Mask = 0x01FFU ; \ 414 } \ 415 else \ 416 { \ 417 (__HANDLE__)->Mask = 0x00FFU ; \ 418 } \ 419 } \ 420 else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ 421 { \ 422 if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ 423 { \ 424 (__HANDLE__)->Mask = 0x00FFU ; \ 425 } \ 426 else \ 427 { \ 428 (__HANDLE__)->Mask = 0x007FU ; \ 429 } \ 430 } \ 431 else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ 432 { \ 433 if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ 434 { \ 435 (__HANDLE__)->Mask = 0x007FU ; \ 436 } \ 437 else \ 438 { \ 439 (__HANDLE__)->Mask = 0x003FU ; \ 440 } \ 441 } \ 442 else \ 443 { \ 444 (__HANDLE__)->Mask = 0x0000U; \ 445 } \ 446 } while(0U) 447 448 /** 449 * @brief Ensure that UART frame length is valid. 450 * @param __LENGTH__ UART frame length. 451 * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) 452 */ 453 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ 454 ((__LENGTH__) == UART_WORDLENGTH_8B) || \ 455 ((__LENGTH__) == UART_WORDLENGTH_9B)) 456 457 /** 458 * @brief Ensure that UART wake-up address length is valid. 459 * @param __ADDRESS__ UART wake-up address length. 460 * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) 461 */ 462 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ 463 ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) 464 465 /** 466 * @brief Ensure that UART TXFIFO threshold level is valid. 467 * @param __THRESHOLD__ UART TXFIFO threshold level. 468 * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) 469 */ 470 #define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ 471 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ 472 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ 473 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ 474 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ 475 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) 476 477 /** 478 * @brief Ensure that UART RXFIFO threshold level is valid. 479 * @param __THRESHOLD__ UART RXFIFO threshold level. 480 * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) 481 */ 482 #define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ 483 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ 484 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ 485 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ 486 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ 487 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) 488 489 /** 490 * @brief Ensure that UART Trigger polarity state is valid. 491 * @param __POLARITY__ UART Trigger polarity. 492 * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) 493 */ 494 #define IS_UART_TRIGGER_POLARITY(__POLARITY__) (((__POLARITY__) == UART_TRIG_POLARITY_RISING) ||\ 495 ((__POLARITY__) == UART_TRIG_POLARITY_FALLING)) 496 497 /** 498 * @brief Ensure that UART IDLE Frame Transmit state is valid. 499 * @param __IDLE__ UART IDLE Frame Transmit state. 500 * @retval SET (__IDLE__ is valid) or RESET (__IDLE__ is invalid) 501 */ 502 #define IS_UART_IDLE_FRAME_TRANSMIT(__IDLE__) (((__IDLE__) == UART_IDLE_FRAME_ENABLE) ||\ 503 ((__IDLE__) == UART_IDLE_FRAME_DISABLE)) 504 505 /** 506 * @brief Ensure that UART Trigger source selection is valid. 507 * @param __SOURCE__ UART Trigger source selection. 508 * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) 509 */ 510 #define IS_UART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U) 511 512 /** 513 * @brief Ensure that LPUART Trigger source selection is valid. 514 * @param __SOURCE__ LPUART Trigger source selection. 515 * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) 516 */ 517 #define IS_LPUART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U) 518 519 /** 520 * @brief Ensure that the number of transferred data is valid. 521 * @param __SOURCE__ UART TX data size. 522 * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) 523 */ 524 #define IS_UART_TX_DATA_SIZE(__SOURCE__) ((__SOURCE__) <= 0xFFFFU) 525 526 /** 527 * @} 528 */ 529 530 /* Private functions ---------------------------------------------------------*/ 531 532 /** 533 * @} 534 */ 535 536 /** 537 * @} 538 */ 539 540 #ifdef __cplusplus 541 } 542 #endif 543 544 #endif /* STM32U5xx_HAL_UART_EX_H */ 545
