1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_tsc.h 4 * @author MCD Application Team 5 * @brief Header file of TSC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_TSC_H 21 #define STM32U5xx_HAL_TSC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 31 /** @addtogroup STM32U5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup TSC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup TSC_Exported_Types TSC Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief TSC state structure definition 46 */ 47 typedef enum 48 { 49 HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ 50 HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ 51 HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ 52 HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ 53 } HAL_TSC_StateTypeDef; 54 55 /** 56 * @brief TSC group status structure definition 57 */ 58 typedef enum 59 { 60 TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ 61 TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ 62 } TSC_GroupStatusTypeDef; 63 64 /** 65 * @brief TSC init structure definition 66 */ 67 typedef struct 68 { 69 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 70 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 71 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 72 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 73 FunctionalState SpreadSpectrum; /*!< Spread spectrum activation 74 This parameter can be set to ENABLE or DISABLE. */ 75 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 76 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 77 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 78 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 79 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 80 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 81 uint32_t MaxCountValue; /*!< Max count value 82 This parameter can be a value of @ref TSC_MaxCount_Value */ 83 uint32_t IODefaultMode; /*!< IO default mode 84 This parameter can be a value of @ref TSC_IO_Default_Mode */ 85 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 86 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 87 uint32_t AcquisitionMode; /*!< Acquisition mode 88 This parameter can be a value of @ref TSC_Acquisition_Mode */ 89 FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation 90 This parameter can be set to ENABLE or DISABLE. */ 91 uint32_t ChannelIOs; /*!< Channel IOs mask */ 92 uint32_t ShieldIOs; /*!< Shield IOs mask */ 93 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 94 } TSC_InitTypeDef; 95 96 /** 97 * @brief TSC IOs configuration structure definition 98 */ 99 typedef struct 100 { 101 uint32_t ChannelIOs; /*!< Channel IOs mask */ 102 uint32_t ShieldIOs; /*!< Shield IOs mask */ 103 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 104 } TSC_IOConfigTypeDef; 105 106 /** 107 * @brief TSC handle Structure definition 108 */ 109 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 110 typedef struct __TSC_HandleTypeDef 111 #else 112 typedef struct 113 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 114 { 115 TSC_TypeDef *Instance; /*!< Register base address */ 116 TSC_InitTypeDef Init; /*!< Initialization parameters */ 117 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 118 HAL_LockTypeDef Lock; /*!< Lock feature */ 119 __IO uint32_t ErrorCode; /*!< TSC Error code */ 120 121 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 122 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ 123 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ 124 125 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ 126 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ 127 128 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 129 } TSC_HandleTypeDef; 130 131 enum 132 { 133 TSC_GROUP1_IDX = 0x00UL, 134 TSC_GROUP2_IDX, 135 TSC_GROUP3_IDX, 136 TSC_GROUP4_IDX, 137 TSC_GROUP5_IDX, 138 TSC_GROUP6_IDX, 139 TSC_GROUP7_IDX, 140 #if defined(TSC_IOCCR_G8_IO1) 141 TSC_GROUP8_IDX, 142 #endif /* TSC_IOCCR_G8_IO1 */ 143 TSC_NB_OF_GROUPS 144 }; 145 146 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 147 /** 148 * @brief HAL TSC Callback ID enumeration definition 149 */ 150 typedef enum 151 { 152 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ 153 HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ 154 155 HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ 156 HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ 157 158 } HAL_TSC_CallbackIDTypeDef; 159 160 /** 161 * @brief HAL TSC Callback pointer definition 162 */ 163 typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ 164 165 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 166 167 /** 168 * @} 169 */ 170 171 /* Exported constants --------------------------------------------------------*/ 172 /** @defgroup TSC_Exported_Constants TSC Exported Constants 173 * @{ 174 */ 175 176 /** @defgroup TSC_Error_Code_definition TSC Error Code definition 177 * @brief TSC Error Code definition 178 * @{ 179 */ 180 #define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ 181 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 182 #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ 183 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 189 * @{ 190 */ 191 #define TSC_CTPH_1CYCLE 0x00000000UL 192 /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ 193 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 194 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ 195 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 196 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ 197 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 198 /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ 199 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 200 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ 201 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 202 /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ 203 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 204 /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ 205 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 206 /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ 207 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 208 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ 209 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) 210 /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ 211 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) 212 /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ 213 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 214 /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ 215 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) 216 /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ 217 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 218 /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ 219 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 220 /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ 221 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 222 /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ 223 /** 224 * @} 225 */ 226 227 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 228 * @{ 229 */ 230 #define TSC_CTPL_1CYCLE 0x00000000UL 231 /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ 232 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 233 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ 234 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 235 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ 236 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 237 /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ 238 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 239 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ 240 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 241 /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ 242 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 243 /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ 244 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 245 /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ 246 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 247 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ 248 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) 249 /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ 250 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) 251 /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ 252 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 253 /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ 254 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) 255 /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ 256 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 257 /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ 258 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 259 /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ 260 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 261 /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ 262 /** 263 * @} 264 */ 265 266 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 267 * @{ 268 */ 269 #define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ 270 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ 271 /** 272 * @} 273 */ 274 275 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 276 * @{ 277 */ 278 #define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ 279 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ 280 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ 281 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ 282 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ 283 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ 284 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ 285 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup TSC_MaxCount_Value Max Count Value 291 * @{ 292 */ 293 #define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ 294 #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ 295 #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ 296 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ 297 #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ 298 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ 299 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ 300 /** 301 * @} 302 */ 303 304 /** @defgroup TSC_IO_Default_Mode IO Default Mode 305 * @{ 306 */ 307 #define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ 308 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ 309 /** 310 * @} 311 */ 312 313 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 314 * @{ 315 */ 316 #define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ 317 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ 318 /** 319 * @} 320 */ 321 322 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 323 * @{ 324 */ 325 #define TSC_ACQ_MODE_NORMAL 0x00000000UL 326 /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ 327 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM 328 /*!< Synchronized acquisition mode (acquisition starts if START bit is set and 329 when the selected signal is detected on the SYNC input pin) */ 330 /** 331 * @} 332 */ 333 334 /** @defgroup TSC_interrupts_definition Interrupts definition 335 * @{ 336 */ 337 #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ 338 #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ 339 /** 340 * @} 341 */ 342 343 /** @defgroup TSC_flags_definition Flags definition 344 * @{ 345 */ 346 #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ 347 #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ 348 /** 349 * @} 350 */ 351 352 /** @defgroup TSC_Group_definition Group definition 353 * @{ 354 */ 355 #define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) 356 #define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) 357 #define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) 358 #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) 359 #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) 360 #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) 361 #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) 362 #if defined(TSC_IOCCR_G8_IO1) 363 #define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) 364 #endif /* TSC_IOCCR_G8_IO1 */ 365 366 #define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ 367 368 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ 369 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ 370 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ 371 #if defined(TSC_IOCCR_G1_IO4) 372 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ 373 #else 374 #define TSC_GROUP1_IO4 TSC_GROUPX_NOT_SUPPORTED /*!< TSC Group1 IO4 not supported */ 375 #endif /* TSC_IOCCR_G1_IO4 */ 376 377 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ 378 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ 379 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ 380 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ 381 382 #if defined(TSC_IOCCR_G3_IO1) 383 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ 384 #else 385 #define TSC_GROUP3_IO1 TSC_GROUPX_NOT_SUPPORTED /*!< TSC Group3 IO1 not supported */ 386 #endif /* TSC_IOCCR_G3_IO1 */ 387 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ 388 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ 389 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ 390 391 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ 392 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ 393 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ 394 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ 395 396 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ 397 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ 398 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ 399 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ 400 401 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ 402 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ 403 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ 404 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ 405 406 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ 407 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ 408 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ 409 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ 410 #if defined(TSC_IOCCR_G8_IO1) 411 412 #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ 413 #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ 414 #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ 415 #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ 416 #else 417 418 #define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ 419 #define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ 420 #define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ 421 #define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ 422 #endif /* TSC_IOCCR_G8_IO1 */ 423 /** 424 * @} 425 */ 426 427 /** 428 * @} 429 */ 430 431 /* Exported macros -----------------------------------------------------------*/ 432 433 /** @defgroup TSC_Exported_Macros TSC Exported Macros 434 * @{ 435 */ 436 437 /** @brief Reset TSC handle state. 438 * @param __HANDLE__ TSC handle 439 * @retval None 440 */ 441 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 442 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 443 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 444 (__HANDLE__)->MspInitCallback = NULL; \ 445 (__HANDLE__)->MspDeInitCallback = NULL; \ 446 } while(0) 447 #else 448 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 449 #endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */ 450 451 /** 452 * @brief Enable the TSC peripheral. 453 * @param __HANDLE__ TSC handle 454 * @retval None 455 */ 456 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 457 458 /** 459 * @brief Disable the TSC peripheral. 460 * @param __HANDLE__ TSC handle 461 * @retval None 462 */ 463 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) 464 465 /** 466 * @brief Start acquisition. 467 * @param __HANDLE__ TSC handle 468 * @retval None 469 */ 470 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 471 472 /** 473 * @brief Stop acquisition. 474 * @param __HANDLE__ TSC handle 475 * @retval None 476 */ 477 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) 478 479 /** 480 * @brief Set IO default mode to output push-pull low. 481 * @param __HANDLE__ TSC handle 482 * @retval None 483 */ 484 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) 485 486 /** 487 * @brief Set IO default mode to input floating. 488 * @param __HANDLE__ TSC handle 489 * @retval None 490 */ 491 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 492 493 /** 494 * @brief Set synchronization polarity to falling edge. 495 * @param __HANDLE__ TSC handle 496 * @retval None 497 */ 498 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) 499 500 /** 501 * @brief Set synchronization polarity to rising edge and high level. 502 * @param __HANDLE__ TSC handle 503 * @retval None 504 */ 505 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 506 507 /** 508 * @brief Enable TSC interrupt. 509 * @param __HANDLE__ TSC handle 510 * @param __INTERRUPT__ TSC interrupt 511 * @retval None 512 */ 513 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 514 515 /** 516 * @brief Disable TSC interrupt. 517 * @param __HANDLE__ TSC handle 518 * @param __INTERRUPT__ TSC interrupt 519 * @retval None 520 */ 521 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 522 523 /** @brief Check whether the specified TSC interrupt source is enabled or not. 524 * @param __HANDLE__ TSC Handle 525 * @param __INTERRUPT__ TSC interrupt 526 * @retval SET or RESET 527 */ 528 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ 529 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\ 530 RESET) 531 532 /** 533 * @brief Check whether the specified TSC flag is set or not. 534 * @param __HANDLE__ TSC handle 535 * @param __FLAG__ TSC flag 536 * @retval SET or RESET 537 */ 538 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\ 539 & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 540 541 /** 542 * @brief Clear the TSC's pending flag. 543 * @param __HANDLE__ TSC handle 544 * @param __FLAG__ TSC flag 545 * @retval None 546 */ 547 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 548 549 /** 550 * @brief Enable schmitt trigger hysteresis on a group of IOs. 551 * @param __HANDLE__ TSC handle 552 * @param __GX_IOY_MASK__ IOs mask 553 * @retval None 554 */ 555 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 556 557 /** 558 * @brief Disable schmitt trigger hysteresis on a group of IOs. 559 * @param __HANDLE__ TSC handle 560 * @param __GX_IOY_MASK__ IOs mask 561 * @retval None 562 */ 563 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\ 564 &= (~(__GX_IOY_MASK__))) 565 566 /** 567 * @brief Open analog switch on a group of IOs. 568 * @param __HANDLE__ TSC handle 569 * @param __GX_IOY_MASK__ IOs mask 570 * @retval None 571 */ 572 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\ 573 &= (~(__GX_IOY_MASK__))) 574 575 /** 576 * @brief Close analog switch on a group of IOs. 577 * @param __HANDLE__ TSC handle 578 * @param __GX_IOY_MASK__ IOs mask 579 * @retval None 580 */ 581 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 582 583 /** 584 * @brief Enable a group of IOs in channel mode. 585 * @param __HANDLE__ TSC handle 586 * @param __GX_IOY_MASK__ IOs mask 587 * @retval None 588 */ 589 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 590 591 /** 592 * @brief Disable a group of channel IOs. 593 * @param __HANDLE__ TSC handle 594 * @param __GX_IOY_MASK__ IOs mask 595 * @retval None 596 */ 597 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\ 598 &= (~(__GX_IOY_MASK__))) 599 600 /** 601 * @brief Enable a group of IOs in sampling mode. 602 * @param __HANDLE__ TSC handle 603 * @param __GX_IOY_MASK__ IOs mask 604 * @retval None 605 */ 606 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 607 608 /** 609 * @brief Disable a group of sampling IOs. 610 * @param __HANDLE__ TSC handle 611 * @param __GX_IOY_MASK__ IOs mask 612 * @retval None 613 */ 614 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) 615 616 /** 617 * @brief Enable acquisition groups. 618 * @param __HANDLE__ TSC handle 619 * @param __GX_MASK__ Groups mask 620 * @retval None 621 */ 622 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 623 624 /** 625 * @brief Disable acquisition groups. 626 * @param __HANDLE__ TSC handle 627 * @param __GX_MASK__ Groups mask 628 * @retval None 629 */ 630 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) 631 632 /** @brief Gets acquisition group status. 633 * @param __HANDLE__ TSC Handle 634 * @param __GX_INDEX__ Group index 635 * @retval SET or RESET 636 */ 637 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 638 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \ 639 (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 640 641 /** 642 * @} 643 */ 644 645 /* Private macros ------------------------------------------------------------*/ 646 647 /** @defgroup TSC_Private_Macros TSC Private Macros 648 * @{ 649 */ 650 651 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 652 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 653 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 654 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 655 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 656 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 657 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 658 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 659 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 660 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 661 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 662 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 663 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 664 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 665 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 666 ((__VALUE__) == TSC_CTPH_16CYCLES)) 667 668 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 669 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 670 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 671 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 672 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 673 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 674 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 675 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 676 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 677 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 678 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 679 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 680 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 681 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 682 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 683 ((__VALUE__) == TSC_CTPL_16CYCLES)) 684 685 #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 686 || ((FunctionalState)(__VALUE__) == ENABLE)) 687 688 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) 689 690 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 691 692 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 693 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 694 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 695 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 696 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 697 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 698 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 699 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 700 701 #define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ 702 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 703 ((__CTPL__) > TSC_CTPL_2CYCLES))) || \ 704 (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ 705 ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ 706 (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \ 707 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 708 ((__CTPL__) > TSC_CTPL_1CYCLE)))) 709 710 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 711 ((__VALUE__) == TSC_MCV_511) || \ 712 ((__VALUE__) == TSC_MCV_1023) || \ 713 ((__VALUE__) == TSC_MCV_2047) || \ 714 ((__VALUE__) == TSC_MCV_4095) || \ 715 ((__VALUE__) == TSC_MCV_8191) || \ 716 ((__VALUE__) == TSC_MCV_16383)) 717 718 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 719 720 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\ 721 || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 722 723 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 724 725 #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 726 || ((FunctionalState)(__VALUE__) == ENABLE)) 727 728 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ 729 || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) 730 731 732 #define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ 733 (((__VALUE__) == 0UL) ||\ 734 (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 735 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 736 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 737 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 738 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 739 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 740 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 741 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 742 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 743 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 744 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 745 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 746 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 747 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 748 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 749 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 750 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 751 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 752 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 753 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 754 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 755 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 756 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 757 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 758 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 759 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 760 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 761 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ 762 (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ 763 (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ 764 (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ 765 (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) 766 767 /** 768 * @} 769 */ 770 771 /* Exported functions --------------------------------------------------------*/ 772 /** @addtogroup TSC_Exported_Functions 773 * @{ 774 */ 775 776 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 777 * @{ 778 */ 779 /* Initialization and de-initialization functions *****************************/ 780 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); 781 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 782 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); 783 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); 784 785 /* Callbacks Register/UnRegister functions ***********************************/ 786 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 787 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, 788 pTSC_CallbackTypeDef pCallback); 789 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); 790 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 791 /** 792 * @} 793 */ 794 795 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 796 * @{ 797 */ 798 /* IO operation functions *****************************************************/ 799 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); 800 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); 801 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); 802 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); 803 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); 804 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index); 805 uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index); 806 /** 807 * @} 808 */ 809 810 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 811 * @{ 812 */ 813 /* Peripheral Control functions ***********************************************/ 814 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config); 815 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); 816 /** 817 * @} 818 */ 819 820 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 821 * @{ 822 */ 823 /* Peripheral State and Error functions ***************************************/ 824 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); 825 /** 826 * @} 827 */ 828 829 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 830 * @{ 831 */ 832 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 833 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); 834 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); 835 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); 836 /** 837 * @} 838 */ 839 840 /** 841 * @} 842 */ 843 844 /** 845 * @} 846 */ 847 848 /** 849 * @} 850 */ 851 852 #ifdef __cplusplus 853 } 854 #endif 855 856 #endif /* STM32U5xx_HAL_TSC_H */ 857
