1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_ospi.h 4 * @author MCD Application Team 5 * @brief Header file of OSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_OSPI_H 21 #define STM32U5xx_HAL_OSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 #include "stm32u5xx_ll_dlyb.h" 30 31 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) 32 33 /** @addtogroup STM32U5xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup OSPI 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup OSPI_Exported_Types OSPI Exported Types 43 * @{ 44 */ 45 #define HAL_OSPI_DLYB_CfgTypeDef LL_DLYB_CfgTypeDef 46 47 /** 48 * @brief OSPI Init structure definition 49 */ 50 typedef struct 51 { 52 uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt 53 indicating that data are available in reception or free place 54 is available in transmission. 55 This parameter can be a value between 1 and 32 */ 56 uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to 57 quad mode on two different devices to increase the throughput. 58 This parameter can be a value of @ref OSPI_DualQuad */ 59 uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI. 60 This parameter can be a value of @ref OSPI_MemoryType */ 61 uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI, 62 it corresponds to the number of address bits required to access 63 the external device. 64 This parameter can be a value between 1 and 32 */ 65 uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select 66 must remain high between commands. 67 This parameter can be a value between 1 and 8 */ 68 uint32_t FreeRunningClock; /*!< It enables or not the free running clock. 69 This parameter can be a value of @ref OSPI_FreeRunningClock */ 70 uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. 71 This parameter can be a value of @ref OSPI_ClockMode */ 72 uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. 73 This parameter can be a value of @ref OSPI_WrapSize */ 74 uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating 75 the external clock based on the AHB clock. 76 This parameter can be a value between 1 and 256 */ 77 uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order 78 to take in account external signal delays. 79 This parameter can be a value of @ref OSPI_SampleShifting */ 80 uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. 81 This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ 82 uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and 83 defines the boundary of bytes to release the chip select. 84 This parameter can be a value between 0 and 31 */ 85 uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected 86 by the delay block. 87 This parameter can be a value of @ref OSPI_DelayBlockBypass */ 88 uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is 89 released every MaxTran+1 bytes when the other OctoSPI request the access 90 to the bus. 91 This parameter can be a value between 0 and 255 */ 92 uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every 93 Refresh+1 clock cycles. 94 This parameter can be a value between 0 and 0xFFFFFFFF */ 95 } OSPI_InitTypeDef; 96 97 /** 98 * @brief HAL OSPI Handle Structure definition 99 */ 100 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 101 typedef struct __OSPI_HandleTypeDef 102 #else 103 typedef struct 104 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 105 { 106 OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */ 107 OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */ 108 uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */ 109 __IO uint32_t XferSize; /*!< Number of data to transfer */ 110 __IO uint32_t XferCount; /*!< Counter of data transferred */ 111 DMA_HandleTypeDef *hdma; /*!< Handle of the DMA channel used for the transfer */ 112 __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */ 113 __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ 114 uint32_t Timeout; /*!< Timeout used for the OSPI external device access */ 115 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 116 void (* ErrorCallback)(struct __OSPI_HandleTypeDef *hospi); 117 void (* AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 118 void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); 119 void (* CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 120 void (* RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 121 void (* TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 122 void (* RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 123 void (* TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 124 void (* StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi); 125 void (* TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi); 126 127 void (* MspInitCallback)(struct __OSPI_HandleTypeDef *hospi); 128 void (* MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi); 129 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 130 } OSPI_HandleTypeDef; 131 132 /** 133 * @brief HAL OSPI Regular Command Structure definition 134 */ 135 typedef struct 136 { 137 uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or 138 to the registers for the write operation (these registers are only 139 used for memory-mapped mode). 140 This parameter can be a value of @ref OSPI_OperationType */ 141 uint32_t FlashId; /*!< It indicates which external device is selected for this command (it 142 applies only if Dualquad is disabled in the initialization structure). 143 This parameter can be a value of @ref OSPI_FlashID */ 144 uint32_t Instruction; /*!< It contains the instruction to be sent to the device. 145 This parameter can be a value between 0 and 0xFFFFFFFF */ 146 uint32_t InstructionMode; /*!< It indicates the mode of the instruction. 147 This parameter can be a value of @ref OSPI_InstructionMode */ 148 uint32_t InstructionSize; /*!< It indicates the size of the instruction. 149 This parameter can be a value of @ref OSPI_InstructionSize */ 150 uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase. 151 This parameter can be a value of @ref OSPI_InstructionDtrMode */ 152 uint32_t Address; /*!< It contains the address to be sent to the device. 153 This parameter can be a value between 0 and 0xFFFFFFFF */ 154 uint32_t AddressMode; /*!< It indicates the mode of the address. 155 This parameter can be a value of @ref OSPI_AddressMode */ 156 uint32_t AddressSize; /*!< It indicates the size of the address. 157 This parameter can be a value of @ref OSPI_AddressSize */ 158 uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase. 159 This parameter can be a value of @ref OSPI_AddressDtrMode */ 160 uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. 161 This parameter can be a value between 0 and 0xFFFFFFFF */ 162 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. 163 This parameter can be a value of @ref OSPI_AlternateBytesMode */ 164 uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes. 165 This parameter can be a value of @ref OSPI_AlternateBytesSize */ 166 uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase. 167 This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ 168 uint32_t DataMode; /*!< It indicates the mode of the data. 169 This parameter can be a value of @ref OSPI_DataMode */ 170 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 171 This field is only used for indirect mode. 172 This parameter can be a value between 1 and 0xFFFFFFFF */ 173 uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase. 174 This parameter can be a value of @ref OSPI_DataDtrMode */ 175 uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. 176 This parameter can be a value between 0 and 31 */ 177 uint32_t DQSMode; /*!< It enables or not the data strobe management. 178 This parameter can be a value of @ref OSPI_DQSMode */ 179 uint32_t SIOOMode; /*!< It enables or not the SIOO mode. 180 This parameter can be a value of @ref OSPI_SIOOMode */ 181 } OSPI_RegularCmdTypeDef; 182 183 /** 184 * @brief HAL OSPI Hyperbus Configuration Structure definition 185 */ 186 typedef struct 187 { 188 uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time. 189 This parameter can be a value between 0 and 255 */ 190 uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time. 191 This parameter can be a value between 0 and 255 */ 192 uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. 193 This parameter can be a value of @ref OSPI_WriteZeroLatency */ 194 uint32_t LatencyMode; /*!< It configures the latency mode. 195 This parameter can be a value of @ref OSPI_LatencyMode */ 196 } OSPI_HyperbusCfgTypeDef; 197 198 /** 199 * @brief HAL OSPI Hyperbus Command Structure definition 200 */ 201 typedef struct 202 { 203 uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. 204 This parameter can be a value of @ref OSPI_AddressSpace */ 205 uint32_t Address; /*!< It contains the address to be sent tot he device. 206 This parameter can be a value between 0 and 0xFFFFFFFF */ 207 uint32_t AddressSize; /*!< It indicates the size of the address. 208 This parameter can be a value of @ref OSPI_AddressSize */ 209 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 210 This field is only used for indirect mode. 211 This parameter can be a value between 1 and 0xFFFFFFFF 212 In case of autopolling mode, this parameter can be any value between 1 and 4 */ 213 uint32_t DQSMode; /*!< It enables or not the data strobe management. 214 This parameter can be a value of @ref OSPI_DQSMode */ 215 } OSPI_HyperbusCmdTypeDef; 216 217 /** 218 * @brief HAL OSPI Auto Polling mode configuration structure definition 219 */ 220 typedef struct 221 { 222 uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match. 223 This parameter can be any value between 0 and 0xFFFFFFFF */ 224 uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received. 225 This parameter can be any value between 0 and 0xFFFFFFFF */ 226 uint32_t MatchMode; /*!< Specifies the method used for determining a match. 227 This parameter can be a value of @ref OSPI_MatchMode */ 228 uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. 229 This parameter can be a value of @ref OSPI_AutomaticStop */ 230 uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases. 231 This parameter can be any value between 0 and 0xFFFF */ 232 } OSPI_AutoPollingTypeDef; 233 234 /** 235 * @brief HAL OSPI Memory Mapped mode configuration structure definition 236 */ 237 typedef struct 238 { 239 uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. 240 This parameter can be a value of @ref OSPI_TimeOutActivation */ 241 uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select. 242 This parameter can be any value between 0 and 0xFFFF */ 243 } OSPI_MemoryMappedTypeDef; 244 245 #if defined (OCTOSPIM) 246 /** 247 * @brief HAL OSPI IO Manager Configuration structure definition 248 */ 249 typedef struct 250 { 251 uint32_t ClkPort; /*!< It indicates which port of the OSPI IO Manager is used for the CLK pins. 252 This parameter can be a value between 1 and 8 */ 253 uint32_t DQSPort; /*!< It indicates which port of the OSPI IO Manager is used for the DQS pin. 254 This parameter can be a value between 0 and 8, 0 means that signal not used */ 255 uint32_t NCSPort; /*!< It indicates which port of the OSPI IO Manager is used for the NCS pin. 256 This parameter can be a value between 1 and 8 */ 257 uint32_t IOLowPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. 258 This parameter can be a value of @ref OSPIM_IOPort */ 259 uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. 260 This parameter can be a value of @ref OSPIM_IOPort */ 261 uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected 262 if some signals are multiplexed in the OSPI IO Manager with the other OSPI. 263 This parameter can be a value between 1 and 256 */ 264 } OSPIM_CfgTypeDef; 265 #endif /*(OCTOSPIM)*/ 266 267 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 268 /** 269 * @brief HAL OSPI Callback ID enumeration definition 270 */ 271 typedef enum 272 { 273 HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ 274 HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ 275 HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ 276 HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ 277 HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ 278 HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ 279 HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ 280 HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ 281 HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ 282 HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ 283 284 HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ 285 HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ 286 } HAL_OSPI_CallbackIDTypeDef; 287 288 /** 289 * @brief HAL OSPI Callback pointer definition 290 */ 291 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); 292 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 293 /** 294 * @} 295 */ 296 297 /* Exported constants --------------------------------------------------------*/ 298 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants 299 * @{ 300 */ 301 302 /** @defgroup OSPI_State OSPI State 303 * @{ 304 */ 305 #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ 306 #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 307 #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ 308 #define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 309 #define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ 310 #define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ 311 #define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ 312 #define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ 313 #define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ 314 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ 315 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ 316 #define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ 317 #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ 318 /** 319 * @} 320 */ 321 322 /** @defgroup OSPI_ErrorCode OSPI Error Code 323 * @{ 324 */ 325 #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 326 #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 327 #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ 328 #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ 329 #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ 330 #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ 331 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 332 #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ 333 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ 334 /** 335 * @} 336 */ 337 338 /** @defgroup OSPI_DualQuad OSPI Dual-Quad 339 * @{ 340 */ 341 #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ 342 #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DMM) /*!< Dual-Quad mode enabled */ 343 /** 344 * @} 345 */ 346 347 /** @defgroup OSPI_MemoryType OSPI Memory Type 348 * @{ 349 */ 350 #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ 351 #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ 352 #define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */ 353 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ 354 #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 355 /** 356 * @} 357 */ 358 359 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock 360 * @{ 361 */ 362 #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ 363 #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ 364 /** 365 * @} 366 */ 367 368 /** @defgroup OSPI_ClockMode OSPI Clock Mode 369 * @{ 370 */ 371 #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ 372 #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 373 /** 374 * @} 375 */ 376 377 /** @defgroup OSPI_WrapSize OSPI Wrap-Size 378 * @{ 379 */ 380 #define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ 381 #define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ 382 #define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ 383 #define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ 384 #define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ 385 /** 386 * @} 387 */ 388 389 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting 390 * @{ 391 */ 392 #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ 393 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 394 /** 395 * @} 396 */ 397 398 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle 399 * @{ 400 */ 401 #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ 402 #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 403 /** 404 * @} 405 */ 406 407 /** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas 408 * @{ 409 */ 410 #define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U) /*!< Sampling clock is delayed by the delay block */ 411 #define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */ 412 /** 413 * @} 414 */ 415 416 /** @defgroup OSPI_OperationType OSPI Operation Type 417 * @{ 418 */ 419 #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 420 #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ 421 #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ 422 #define HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ 423 /** 424 * @} 425 */ 426 427 /** @defgroup OSPI_FlashID OSPI Flash Id 428 * @{ 429 */ 430 #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ 431 #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_MSEL) /*!< FLASH 2 selected */ 432 /** 433 * @} 434 */ 435 436 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode 437 * @{ 438 */ 439 #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ 440 #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 441 #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 442 #define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 443 #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 444 /** 445 * @} 446 */ 447 448 /** @defgroup OSPI_InstructionSize OSPI Instruction Size 449 * @{ 450 */ 451 #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ 452 #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 453 #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 454 #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ 455 /** 456 * @} 457 */ 458 459 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode 460 * @{ 461 */ 462 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ 463 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 464 /** 465 * @} 466 */ 467 468 /** @defgroup OSPI_AddressMode OSPI Address Mode 469 * @{ 470 */ 471 #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ 472 #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ 473 #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ 474 #define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 475 #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 476 /** 477 * @} 478 */ 479 480 /** @defgroup OSPI_AddressSize OSPI Address Size 481 * @{ 482 */ 483 #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ 484 #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 485 #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 486 #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ 487 /** 488 * @} 489 */ 490 491 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode 492 * @{ 493 */ 494 #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ 495 #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 496 /** 497 * @} 498 */ 499 500 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode 501 * @{ 502 */ 503 #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ 504 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 505 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 506 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 507 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 508 /** 509 * @} 510 */ 511 512 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size 513 * @{ 514 */ 515 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ 516 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 517 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 518 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 519 /** 520 * @} 521 */ 522 523 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode 524 * @{ 525 */ 526 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 527 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 528 /** 529 * @} 530 */ 531 532 /** @defgroup OSPI_DataMode OSPI Data Mode 533 * @{ 534 */ 535 #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ 536 #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ 537 #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ 538 #define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ 539 #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ 540 /** 541 * @} 542 */ 543 544 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode 545 * @{ 546 */ 547 #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ 548 #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 549 /** 550 * @} 551 */ 552 553 /** @defgroup OSPI_DQSMode OSPI DQS Mode 554 * @{ 555 */ 556 #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ 557 #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ 558 /** 559 * @} 560 */ 561 562 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode 563 * @{ 564 */ 565 #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ 566 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ 567 /** 568 * @} 569 */ 570 571 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation 572 * @{ 573 */ 574 #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ 575 #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ 576 /** 577 * @} 578 */ 579 580 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode 581 * @{ 582 */ 583 #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ 584 #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ 585 /** 586 * @} 587 */ 588 589 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space 590 * @{ 591 */ 592 #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ 593 #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 594 /** 595 * @} 596 */ 597 598 /** @defgroup OSPI_MatchMode OSPI Match Mode 599 * @{ 600 */ 601 #define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ 602 #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 603 /** 604 * @} 605 */ 606 607 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop 608 * @{ 609 */ 610 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ 611 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 612 /** 613 * @} 614 */ 615 616 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation 617 * @{ 618 */ 619 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 620 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 621 /** 622 * @} 623 */ 624 625 /** @defgroup OSPI_Flags OSPI Flags 626 * @{ 627 */ 628 #define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 629 #define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 630 #define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 631 #define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 632 #define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 633 #define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 634 /** 635 * @} 636 */ 637 638 /** @defgroup OSPI_Interrupts OSPI Interrupts 639 * @{ 640 */ 641 #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 642 #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ 643 #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 644 #define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 645 #define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 646 /** 647 * @} 648 */ 649 650 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition 651 * @{ 652 */ 653 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ 654 /** 655 * @} 656 */ 657 658 #if defined (OCTOSPIM) 659 /** @defgroup OSPI_IO_Manger_IOPort OSPI IO Manager IO Port 660 * @{ 661 */ 662 #define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */ 663 #define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ 664 #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ 665 #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ 666 #define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */ 667 #define HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U)) /*!< Port 3 - IO[3:0] */ 668 #define HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U)) /*!< Port 3 - IO[7:4] */ 669 #define HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U)) /*!< Port 4 - IO[3:0] */ 670 #define HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U)) /*!< Port 4 - IO[7:4] */ 671 #define HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U)) /*!< Port 5 - IO[3:0] */ 672 #define HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U)) /*!< Port 5 - IO[7:4] */ 673 #define HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U)) /*!< Port 6 - IO[3:0] */ 674 #define HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U)) /*!< Port 6 - IO[7:4] */ 675 #define HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U)) /*!< Port 7 - IO[3:0] */ 676 #define HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U)) /*!< Port 7 - IO[7:4] */ 677 #define HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U)) /*!< Port 8 - IO[3:0] */ 678 #define HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U)) /*!< Port 8 - IO[7:4] */ 679 /** 680 * @} 681 */ 682 #endif /*(OCTOSPIM)*/ 683 /** 684 * @} 685 */ 686 687 /* Exported macros -----------------------------------------------------------*/ 688 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros 689 * @{ 690 */ 691 /** @brief Reset OSPI handle state. 692 * @param __HANDLE__ specifies the OSPI Handle. 693 * @retval None 694 */ 695 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 696 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 697 (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ 698 (__HANDLE__)->MspInitCallback = NULL; \ 699 (__HANDLE__)->MspDeInitCallback = NULL; \ 700 } while(0) 701 #else 702 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) 703 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 704 705 /** @brief Enable the OSPI peripheral. 706 * @param __HANDLE__ specifies the OSPI Handle. 707 * @retval None 708 */ 709 #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 710 711 /** @brief Disable the OSPI peripheral. 712 * @param __HANDLE__ specifies the OSPI Handle. 713 * @retval None 714 */ 715 #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 716 717 /** @brief Enable the specified OSPI interrupt. 718 * @param __HANDLE__ specifies the OSPI Handle. 719 * @param __INTERRUPT__ specifies the OSPI interrupt source to enable. 720 * This parameter can be one of the following values: 721 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 722 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 723 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 724 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 725 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 726 * @retval None 727 */ 728 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 729 730 731 /** @brief Disable the specified OSPI interrupt. 732 * @param __HANDLE__ specifies the OSPI Handle. 733 * @param __INTERRUPT__ specifies the OSPI interrupt source to disable. 734 * This parameter can be one of the following values: 735 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 736 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 737 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 738 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 739 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 740 * @retval None 741 */ 742 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 743 744 /** @brief Check whether the specified OSPI interrupt source is enabled or not. 745 * @param __HANDLE__ specifies the OSPI Handle. 746 * @param __INTERRUPT__ specifies the OSPI interrupt source to check. 747 * This parameter can be one of the following values: 748 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 749 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 750 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 751 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 752 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 753 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 754 */ 755 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ 756 == (__INTERRUPT__)) 757 758 /** 759 * @brief Check whether the selected OSPI flag is set or not. 760 * @param __HANDLE__ specifies the OSPI Handle. 761 * @param __FLAG__ specifies the OSPI flag to check. 762 * This parameter can be one of the following values: 763 * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag 764 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 765 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 766 * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag 767 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 768 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 769 * @retval None 770 */ 771 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ 772 != 0U) ? SET : RESET) 773 774 /** @brief Clears the specified OSPI's flag status. 775 * @param __HANDLE__ specifies the OSPI Handle. 776 * @param __FLAG__ specifies the OSPI clear register flag that needs to be set 777 * This parameter can be one of the following values: 778 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 779 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 780 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 781 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 782 * @retval None 783 */ 784 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 785 786 /** 787 * @} 788 */ 789 790 /* Exported functions --------------------------------------------------------*/ 791 /** @addtogroup OSPI_Exported_Functions OSPI Exported Functions 792 * @{ 793 */ 794 795 /* Initialization/de-initialization functions ********************************/ 796 /** @addtogroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions 797 * @{ 798 */ 799 HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi); 800 void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi); 801 HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi); 802 void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi); 803 804 /** 805 * @} 806 */ 807 808 /* IO operation functions *****************************************************/ 809 /** @addtogroup OSPI_Exported_Functions_Group2 Input and Output operation functions 810 * @{ 811 */ 812 /* OSPI IRQ handler function */ 813 void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi); 814 815 /* OSPI command configuration functions */ 816 HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); 817 HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); 818 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); 819 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); 820 821 /* OSPI indirect mode functions */ 822 HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 823 HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 824 HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 825 HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 826 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 827 HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 828 829 /* OSPI status flag polling mode functions */ 830 HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 831 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); 832 833 /* OSPI memory-mapped mode functions */ 834 HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); 835 836 /* Callback functions in non-blocking modes ***********************************/ 837 void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi); 838 void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi); 839 void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); 840 841 /* OSPI indirect mode functions */ 842 void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi); 843 void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi); 844 void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi); 845 void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi); 846 void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi); 847 848 /* OSPI status flag polling mode functions */ 849 void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi); 850 851 /* OSPI memory-mapped mode functions */ 852 void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi); 853 854 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 855 /* OSPI callback registering/unregistering */ 856 HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, 857 pOSPI_CallbackTypeDef pCallback); 858 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); 859 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 860 /** 861 * @} 862 */ 863 864 /* Peripheral Control and State functions ************************************/ 865 /** @addtogroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions 866 * @{ 867 */ 868 HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi); 869 HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi); 870 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold); 871 uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi); 872 HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout); 873 uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi); 874 uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi); 875 876 /** 877 * @} 878 */ 879 880 #if defined (OCTOSPIM) 881 /* OSPI IO Manager configuration function ************************************/ 882 /** @addtogroup OSPI_Exported_Functions_Group4 IO Manager configuration function 883 * @{ 884 */ 885 HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); 886 887 /** 888 * @} 889 */ 890 891 #endif /*(OCTOSPIM)*/ 892 893 /* OSPI Delay Block function ************************************/ 894 /** @addtogroup OSPI_Exported_Functions_Group5 Delay Block function 895 * @{ 896 */ 897 HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); 898 HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(const OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); 899 HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); 900 901 /** 902 * @} 903 */ 904 /** 905 * @} 906 */ 907 /* End of exported functions -------------------------------------------------*/ 908 909 /* Private macros ------------------------------------------------------------*/ 910 /** 911 @cond 0 912 */ 913 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) 914 915 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ 916 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) 917 918 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 919 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 920 ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \ 921 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ 922 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 923 924 #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) 925 926 #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) 927 928 #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ 929 ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) 930 931 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ 932 ((MODE) == HAL_OSPI_CLOCK_MODE_3)) 933 934 #define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \ 935 ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \ 936 ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \ 937 ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ 938 ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) 939 940 #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) 941 942 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ 943 ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) 944 945 #define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ 946 ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) 947 948 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ 949 ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ 950 ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG) || \ 951 ((TYPE) == HAL_OSPI_OPTYPE_WRAP_CFG)) 952 953 #define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \ 954 ((FLASHID) == HAL_OSPI_FLASH_ID_2)) 955 956 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ 957 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ 958 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ 959 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ 960 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) 961 962 #define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ 963 ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ 964 ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ 965 ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) 966 967 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ 968 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) 969 970 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ 971 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ 972 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ 973 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ 974 ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) 975 976 #define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ 977 ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ 978 ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ 979 ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) 980 981 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ 982 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) 983 984 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ 985 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ 986 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ 987 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ 988 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) 989 990 #define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ 991 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ 992 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ 993 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) 994 995 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ 996 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) 997 998 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ 999 ((MODE) == HAL_OSPI_DATA_1_LINE) || \ 1000 ((MODE) == HAL_OSPI_DATA_2_LINES) || \ 1001 ((MODE) == HAL_OSPI_DATA_4_LINES) || \ 1002 ((MODE) == HAL_OSPI_DATA_8_LINES)) 1003 1004 #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) 1005 1006 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ 1007 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) 1008 1009 #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 1010 1011 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ 1012 ((MODE) == HAL_OSPI_DQS_ENABLE)) 1013 1014 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ 1015 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) 1016 1017 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) 1018 1019 #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) 1020 1021 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ 1022 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) 1023 1024 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ 1025 ((MODE) == HAL_OSPI_FIXED_LATENCY)) 1026 1027 #define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ 1028 ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) 1029 1030 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ 1031 ((MODE) == HAL_OSPI_MATCH_MODE_OR)) 1032 1033 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ 1034 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) 1035 1036 #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 1037 1038 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 1039 1040 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ 1041 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) 1042 1043 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 1044 1045 #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) 1046 1047 #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ 1048 ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED)) 1049 1050 #define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) 1051 #if defined(OCTOSPIM) 1052 1053 #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) 1054 1055 #define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U) 1056 1057 #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \ 1058 ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ 1059 ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ 1060 ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ 1061 ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \ 1062 ((PORT) == HAL_OSPIM_IOPORT_3_LOW) || \ 1063 ((PORT) == HAL_OSPIM_IOPORT_3_HIGH) || \ 1064 ((PORT) == HAL_OSPIM_IOPORT_4_LOW) || \ 1065 ((PORT) == HAL_OSPIM_IOPORT_4_HIGH) || \ 1066 ((PORT) == HAL_OSPIM_IOPORT_5_LOW) || \ 1067 ((PORT) == HAL_OSPIM_IOPORT_5_HIGH) || \ 1068 ((PORT) == HAL_OSPIM_IOPORT_6_LOW) || \ 1069 ((PORT) == HAL_OSPIM_IOPORT_6_HIGH) || \ 1070 ((PORT) == HAL_OSPIM_IOPORT_7_LOW) || \ 1071 ((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \ 1072 ((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \ 1073 ((PORT) == HAL_OSPIM_IOPORT_8_HIGH)) 1074 1075 #if defined (OCTOSPIM_CR_MUXEN) 1076 #define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) 1077 #endif /*(OCTOSPIM_CR_MUXEN)*/ 1078 #endif /*(OCTOSPIM)*/ 1079 /** 1080 @endcond 1081 */ 1082 1083 /* End of private macros -----------------------------------------------------*/ 1084 1085 /** 1086 * @} 1087 */ 1088 1089 /** 1090 * @} 1091 */ 1092 1093 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ 1094 1095 #ifdef __cplusplus 1096 } 1097 #endif 1098 1099 #endif /* STM32U5xx_HAL_OSPI_H */ 1100
