1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_dma2d.h 4 * @author MCD Application Team 5 * @brief Header file of DMA2D HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_DMA2D_H 21 #define STM32U5xx_HAL_DMA2D_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 #if defined (DMA2D) 35 36 /** @addtogroup DMA2D DMA2D 37 * @brief DMA2D HAL module driver 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 43 * @{ 44 */ 45 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 46 47 /** 48 * @brief DMA2D CLUT Structure definition 49 */ 50 typedef struct 51 { 52 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 53 54 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 55 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 56 57 uint32_t Size; /*!< Configures the DMA2D CLUT size. 58 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 59 } DMA2D_CLUTCfgTypeDef; 60 61 /** 62 * @brief DMA2D Init structure definition 63 */ 64 typedef struct 65 { 66 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 67 This parameter can be one value of @ref DMA2D_Mode. */ 68 69 uint32_t ColorMode; /*!< Configures the color format of the output image. 70 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 71 72 uint32_t OutputOffset; /*!< Specifies the Offset value. 73 This parameter must be a number between 74 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 75 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. 76 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 77 78 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) 79 for the output pixel format converter. 80 This parameter can be one value of @ref DMA2D_RB_Swap. */ 81 82 83 uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). 84 This parameter can be one value of @ref DMA2D_Bytes_Swap. */ 85 86 uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. 87 This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ 88 89 } DMA2D_InitTypeDef; 90 91 92 /** 93 * @brief DMA2D Layer structure definition 94 */ 95 typedef struct 96 { 97 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 98 This parameter must be a number between 99 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 100 101 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 102 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 103 104 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 105 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 106 107 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value 108 in case of A8 or A4 color mode. 109 This parameter must be a number between Min_Data = 0x00 110 and Max_Data = 0xFF except for the color modes detailed below. 111 @note In case of A8 or A4 color mode (ARGB), 112 this parameter must be a number between 113 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 114 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 115 - InputAlpha[16:23] is the red value RED[0:7] 116 - InputAlpha[8:15] is the green value GREEN[0:7] 117 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 118 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. 119 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 120 121 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). 122 This parameter can be one value of @ref DMA2D_RB_Swap. */ 123 124 #if defined(DMA2D_FGPFCCR_CSS) 125 uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode 126 This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */ 127 #endif /* DMA2D_FGPFCCR_CSS */ 128 129 } DMA2D_LayerCfgTypeDef; 130 131 /** 132 * @brief HAL DMA2D State structures definition 133 */ 134 typedef enum 135 { 136 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 137 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 138 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 139 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 140 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 141 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 142 } HAL_DMA2D_StateTypeDef; 143 144 /** 145 * @brief DMA2D handle Structure definition 146 */ 147 typedef struct __DMA2D_HandleTypeDef 148 { 149 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 150 151 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 152 153 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ 154 155 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ 156 157 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 158 void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ 159 160 void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ 161 162 void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ 163 164 void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ 165 166 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 167 168 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 169 170 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 171 172 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 173 174 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 175 } DMA2D_HandleTypeDef; 176 177 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 178 /** 179 * @brief HAL DMA2D Callback pointer definition 180 */ 181 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ 182 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 183 /** 184 * @} 185 */ 186 187 /* Exported constants --------------------------------------------------------*/ 188 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 189 * @{ 190 */ 191 192 /** @defgroup DMA2D_Error_Code DMA2D Error Code 193 * @{ 194 */ 195 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 196 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 197 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 198 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 199 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 200 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 201 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 202 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 203 204 /** 205 * @} 206 */ 207 208 /** @defgroup DMA2D_Mode DMA2D Mode 209 * @{ 210 */ 211 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 212 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 213 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 214 #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ 215 #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ 216 #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ 217 /** 218 * @} 219 */ 220 221 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 222 * @{ 223 */ 224 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 225 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 226 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 227 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 228 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 229 /** 230 * @} 231 */ 232 233 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 234 * @{ 235 */ 236 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 237 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 238 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 239 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 240 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 241 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 242 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 243 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 244 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 245 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 246 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 247 #if defined(DMA2D_FGPFCCR_CSS) 248 #define DMA2D_INPUT_YCBCR 0x0000000BU /*!< YCbCr color mode */ 249 #endif /* DMA2D_FGPFCCR_CSS */ 250 /** 251 * @} 252 */ 253 254 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 255 * @{ 256 */ 257 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 258 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 259 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 260 with original alpha channel value */ 261 /** 262 * @} 263 */ 264 265 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion 266 * @{ 267 */ 268 #define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 269 #define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ 270 /** 271 * @} 272 */ 273 274 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap 275 * @{ 276 */ 277 #define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ 278 #define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ 279 /** 280 * @} 281 */ 282 283 284 285 /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode 286 * @{ 287 */ 288 #define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ 289 #define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ 290 /** 291 * @} 292 */ 293 294 /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap 295 * @{ 296 */ 297 #define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ 298 #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ 299 /** 300 * @} 301 */ 302 303 #if defined(DMA2D_FGPFCCR_CSS) 304 /** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling 305 * @{ 306 */ 307 #define DMA2D_NO_CSS 0x00000000U /*!< No chroma sub-sampling 4:4:4 */ 308 #define DMA2D_CSS_422 0x00000001U /*!< chroma sub-sampling 4:2:2 */ 309 #define DMA2D_CSS_420 0x00000002U /*!< chroma sub-sampling 4:2:0 */ 310 /** 311 * @} 312 */ 313 #endif /* DMA2D_FGPFCCR_CSS */ 314 315 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 316 * @{ 317 */ 318 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 319 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 320 /** 321 * @} 322 */ 323 324 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 325 * @{ 326 */ 327 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 328 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 329 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 330 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 331 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 332 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 333 /** 334 * @} 335 */ 336 337 /** @defgroup DMA2D_Flags DMA2D Flags 338 * @{ 339 */ 340 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 341 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 342 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 343 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 344 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 345 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 346 /** 347 * @} 348 */ 349 350 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 351 /** 352 * @brief HAL DMA2D common Callback ID enumeration definition 353 */ 354 typedef enum 355 { 356 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 357 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 358 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 359 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 360 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 361 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 362 } HAL_DMA2D_CallbackIDTypeDef; 363 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 364 365 366 /** 367 * @} 368 */ 369 /* Exported macros ------------------------------------------------------------*/ 370 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 371 * @{ 372 */ 373 374 /** @brief Reset DMA2D handle state 375 * @param __HANDLE__ specifies the DMA2D handle. 376 * @retval None 377 */ 378 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 379 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 380 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 381 (__HANDLE__)->MspInitCallback = NULL; \ 382 (__HANDLE__)->MspDeInitCallback = NULL; \ 383 }while(0) 384 #else 385 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 386 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 387 388 389 /** 390 * @brief Enable the DMA2D. 391 * @param __HANDLE__ DMA2D handle 392 * @retval None. 393 */ 394 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 395 396 397 /* Interrupt & Flag management */ 398 /** 399 * @brief Get the DMA2D pending flags. 400 * @param __HANDLE__ DMA2D handle 401 * @param __FLAG__ flag to check. 402 * This parameter can be any combination of the following values: 403 * @arg DMA2D_FLAG_CE: Configuration error flag 404 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 405 * @arg DMA2D_FLAG_CAE: CLUT access error flag 406 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 407 * @arg DMA2D_FLAG_TC: Transfer complete flag 408 * @arg DMA2D_FLAG_TE: Transfer error flag 409 * @retval The state of FLAG. 410 */ 411 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 412 413 /** 414 * @brief Clear the DMA2D pending flags. 415 * @param __HANDLE__ DMA2D handle 416 * @param __FLAG__ specifies the flag to clear. 417 * This parameter can be any combination of the following values: 418 * @arg DMA2D_FLAG_CE: Configuration error flag 419 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 420 * @arg DMA2D_FLAG_CAE: CLUT access error flag 421 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 422 * @arg DMA2D_FLAG_TC: Transfer complete flag 423 * @arg DMA2D_FLAG_TE: Transfer error flag 424 * @retval None 425 */ 426 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 427 428 /** 429 * @brief Enable the specified DMA2D interrupts. 430 * @param __HANDLE__ DMA2D handle 431 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 432 * This parameter can be any combination of the following values: 433 * @arg DMA2D_IT_CE: Configuration error interrupt mask 434 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 435 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 436 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 437 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 438 * @arg DMA2D_IT_TE: Transfer error interrupt mask 439 * @retval None 440 */ 441 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 442 443 /** 444 * @brief Disable the specified DMA2D interrupts. 445 * @param __HANDLE__ DMA2D handle 446 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 447 * This parameter can be any combination of the following values: 448 * @arg DMA2D_IT_CE: Configuration error interrupt mask 449 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 450 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 451 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 452 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 453 * @arg DMA2D_IT_TE: Transfer error interrupt mask 454 * @retval None 455 */ 456 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 457 458 /** 459 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 460 * @param __HANDLE__ DMA2D handle 461 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 462 * This parameter can be one of the following values: 463 * @arg DMA2D_IT_CE: Configuration error interrupt mask 464 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 465 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 466 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 467 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 468 * @arg DMA2D_IT_TE: Transfer error interrupt mask 469 * @retval The state of INTERRUPT source. 470 */ 471 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 472 473 /** 474 * @} 475 */ 476 477 /* Exported functions --------------------------------------------------------*/ 478 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 479 * @{ 480 */ 481 482 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 483 * @{ 484 */ 485 486 /* Initialization and de-initialization functions *******************************/ 487 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 488 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); 489 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); 490 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); 491 /* Callbacks Register/UnRegister functions ***********************************/ 492 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 493 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, 494 pDMA2D_CallbackTypeDef pCallback); 495 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 496 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 497 498 /** 499 * @} 500 */ 501 502 503 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 504 * @{ 505 */ 506 507 /* IO operation functions *******************************************************/ 508 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 509 uint32_t Height); 510 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 511 uint32_t DstAddress, uint32_t Width, uint32_t Height); 512 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 513 uint32_t Height); 514 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 515 uint32_t DstAddress, uint32_t Width, uint32_t Height); 516 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 517 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 518 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 519 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 520 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, 521 uint32_t LayerIdx); 522 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, 523 uint32_t LayerIdx); 524 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 525 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 526 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 527 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 528 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 529 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 530 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 531 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 532 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 533 534 /** 535 * @} 536 */ 537 538 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 539 * @{ 540 */ 541 542 /* Peripheral Control functions *************************************************/ 543 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 544 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 545 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 546 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 547 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 548 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 549 550 /** 551 * @} 552 */ 553 554 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 555 * @{ 556 */ 557 558 /* Peripheral State functions ***************************************************/ 559 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d); 560 uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d); 561 562 /** 563 * @} 564 */ 565 566 /** 567 * @} 568 */ 569 570 /* Private constants ---------------------------------------------------------*/ 571 572 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 573 * @{ 574 */ 575 576 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 577 * @{ 578 */ 579 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 580 /** 581 * @} 582 */ 583 584 /** @defgroup DMA2D_Color_Value DMA2D Color Value 585 * @{ 586 */ 587 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 588 /** 589 * @} 590 */ 591 592 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 593 * @{ 594 */ 595 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 596 /** 597 * @} 598 */ 599 600 /** @defgroup DMA2D_Layers DMA2D Layers 601 * @{ 602 */ 603 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 604 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 605 /** 606 * @} 607 */ 608 609 /** @defgroup DMA2D_Offset DMA2D Offset 610 * @{ 611 */ 612 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 613 /** 614 * @} 615 */ 616 617 /** @defgroup DMA2D_Size DMA2D Size 618 * @{ 619 */ 620 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 621 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 622 /** 623 * @} 624 */ 625 626 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 627 * @{ 628 */ 629 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 630 /** 631 * @} 632 */ 633 634 /** 635 * @} 636 */ 637 638 639 /* Private macros ------------------------------------------------------------*/ 640 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 641 * @{ 642 */ 643 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ 644 || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 645 646 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 647 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ 648 ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) 649 650 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ 651 ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 652 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ 653 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 654 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 655 656 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 657 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 658 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 659 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 660 661 #if defined(DMA2D_FGPFCCR_CSS) 662 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ 663 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 664 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ 665 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 666 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ 667 ((INPUT_CM) == DMA2D_INPUT_L8) || \ 668 ((INPUT_CM) == DMA2D_INPUT_AL44) || \ 669 ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 670 ((INPUT_CM) == DMA2D_INPUT_L4) || \ 671 ((INPUT_CM) == DMA2D_INPUT_A8) || \ 672 ((INPUT_CM) == DMA2D_INPUT_A4) || \ 673 ((INPUT_CM) == DMA2D_INPUT_YCBCR)) 674 #else 675 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ 676 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 677 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ 678 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 679 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ 680 ((INPUT_CM) == DMA2D_INPUT_L8) || \ 681 ((INPUT_CM) == DMA2D_INPUT_AL44) || \ 682 ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 683 ((INPUT_CM) == DMA2D_INPUT_L4) || \ 684 ((INPUT_CM) == DMA2D_INPUT_A8) || \ 685 ((INPUT_CM) == DMA2D_INPUT_A4)) 686 #endif /* DMA2D_FGPFCCR_CSS */ 687 688 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 689 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 690 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 691 692 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ 693 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) 694 695 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ 696 ((RB_Swap) == DMA2D_RB_SWAP)) 697 698 #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ 699 ((LOM) == DMA2D_LOM_BYTES)) 700 701 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ 702 ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) 703 704 #if defined(DMA2D_FGPFCCR_CSS) 705 #define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \ 706 ((CSS) == DMA2D_CSS_422) || \ 707 ((CSS) == DMA2D_CSS_420)) 708 #endif /* DMA2D_FGPFCCR_CSS */ 709 710 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 711 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 712 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 713 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 714 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 715 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 716 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 717 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 718 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 719 /** 720 * @} 721 */ 722 723 /** 724 * @} 725 */ 726 727 #endif /* defined (DMA2D) */ 728 729 /** 730 * @} 731 */ 732 733 #ifdef __cplusplus 734 } 735 #endif 736 737 #endif /* STM32U5xx_HAL_DMA2D_H */ 738
