1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32n6xx_ll_adc.h"
22 #include "stm32n6xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32N6xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency */
64 /* Unit: CPU cycles. */
65 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
66 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
67 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68
69 /**
70 * @}
71 */
72
73 /* Private macros ------------------------------------------------------------*/
74
75 /** @addtogroup ADC_LL_Private_Macros
76 * @{
77 */
78
79 /* Check of parameters for configuration of ADC hierarchical scope: */
80 /* common to several ADC instances. */
81 /* (None) */
82
83 /* Check of parameters for configuration of ADC hierarchical scope: */
84 /* ADC instance. */
85 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
86 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
87 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
88 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
89 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
90 )
91
92 #define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__) \
93 ( ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \
94 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1) \
95 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2) \
96 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3) \
97 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4) \
98 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5) \
99 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6) \
100 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7) \
101 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8) \
102 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9) \
103 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10) \
104 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11) \
105 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12) \
106 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13) \
107 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14) \
108 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15) \
109 )
110
111 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
112 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
113 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
114 )
115
116 /* Check of parameters for configuration of ADC hierarchical scope: */
117 /* ADC group regular */
118 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
119 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
120 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
121 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
122 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
123 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
124 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
125 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
126 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_TRGO) \
133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_CH1) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_TRGO) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM12_TRGO) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM18_TRGO) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) \
145 )
146
147 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
148 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
149 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
150 )
151
152 #define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__) \
153 (((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \
154 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
155 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
156 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_MDF_TRANSFER) \
157 )
158
159 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
160 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
161 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
162 )
163
164 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
165 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
166 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
167 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
168 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
169 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
170 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
171 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
172 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
173 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
174 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
175 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
176 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
177 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
178 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
179 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
180 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
181 )
182
183 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
184 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
185 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
186 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
187 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
188 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
189 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
190 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
191 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
192 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
193 )
194
195 /* Check of parameters for configuration of ADC hierarchical scope: */
196 /* ADC group injected */
197 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
198 (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
199 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
200 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
201 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
202 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
203 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
204 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
205 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
206 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
207 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
208 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
209 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
210 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
211 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
212 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
213 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
214 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
215 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_CH2) \
216 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_TRGO) \
217 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM12_TRGO) \
218 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
219 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM18_TRGO) \
220 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2) \
221 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2) \
222 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_CH2) \
223 )
224
225 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
226 (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
227 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
228 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
229 )
230
231 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
232 (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
233 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
234 )
235
236 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
237 (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
238 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
239 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
240 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
241 )
242
243 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
244 (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
245 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
246 )
247
248 #if defined(ADC_MULTIMODE_SUPPORT)
249 /* Check of parameters for configuration of ADC hierarchical scope: */
250 /* multimode. */
251 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
252 (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
253 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
254 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
255 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
256 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
257 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
258 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
259 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
260 )
261
262 #define IS_LL_ADC_MULTI_DATA_FORMAT(__MULTI_DATA_FORMAT__) \
263 (((__MULTI_DATA_FORMAT__) == LL_ADC_MULTI_REG_DATA_EACH_ADC) \
264 || ((__MULTI_DATA_FORMAT__) == LL_ADC_MULTI_REG_DATA_COMMON_32B) \
265 || ((__MULTI_DATA_FORMAT__) == LL_ADC_MULTI_REG_DATA_COMMON_16B) \
266 )
267
268 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
269 (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
270 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
271 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
272 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
273 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
274 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
275 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
276 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
277 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
278 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
279 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
280 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
281 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
282 )
283
284 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
285 (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
286 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
287 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
288 )
289
290 #endif /* ADC_MULTIMODE_SUPPORT */
291
292 /**
293 * @}
294 */
295
296
297 /* Private function prototypes -----------------------------------------------*/
298
299 /* Exported functions --------------------------------------------------------*/
300 /** @addtogroup ADC_LL_Exported_Functions
301 * @{
302 */
303
304 /** @addtogroup ADC_LL_EF_Init
305 * @{
306 */
307
308 /**
309 * @brief De-initialize registers of all ADC instances belonging to
310 * the same ADC common instance to their default reset values.
311 * @note This function is performing a hard reset, using high level
312 * clock source RCC ADC reset.
313 * Caution: On this STM32 series, if several ADC instances are available
314 * on the selected device, RCC ADC reset will reset
315 * all ADC instances belonging to the common ADC instance.
316 * To de-initialize only 1 ADC instance, use
317 * function @ref LL_ADC_DeInit().
318 * @param ADCxy_COMMON ADC common instance
319 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
320 * @retval An ErrorStatus enumeration value:
321 * - SUCCESS: ADC common registers are de-initialized
322 * - ERROR: not applicable
323 */
LL_ADC_CommonDeInit(const ADC_Common_TypeDef * ADCxy_COMMON)324 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON)
325 {
326 /* Check the parameters */
327 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
328
329 /* Force reset of ADC clock (bus clock) */
330 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12);
331
332 /* Release reset of ADC clock (bus clock) */
333 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
334
335 return SUCCESS;
336 }
337
338 /**
339 * @brief Initialize some features of ADC common parameters
340 * (all ADC instances belonging to the same ADC common instance)
341 * and multimode (for devices with several ADC instances available).
342 * @note The setting of ADC common parameters is conditioned to
343 * ADC instances state:
344 * All ADC instances belonging to the same ADC common instance
345 * must be disabled.
346 * @param ADCxy_COMMON ADC common instance
347 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
348 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
349 * @retval An ErrorStatus enumeration value:
350 * - SUCCESS: ADC common registers are initialized
351 * - ERROR: ADC common registers are not initialized
352 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,const LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)353 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
354 {
355 ErrorStatus status = SUCCESS;
356
357 /* Check the parameters */
358 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
359 #if defined(ADC_MULTIMODE_SUPPORT)
360 assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode));
361 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
362 {
363 assert_param(IS_LL_ADC_MULTI_DATA_FORMAT(pADC_CommonInitStruct->MultiDataFormat));
364 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay));
365 }
366 #endif /* ADC_MULTIMODE_SUPPORT */
367
368 /* Note: Hardware constraint (refer to description of functions */
369 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
370 /* On this STM32 series, setting of these features is conditioned to */
371 /* ADC state: */
372 /* All ADC instances of the ADC common group must be disabled. */
373 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
374 {
375 /* Configuration of ADC hierarchical scope: */
376 /* - common to several ADC */
377 /* (all ADC instances belonging to the same ADC common instance) */
378 /* - multimode (if several ADC instances available on the */
379 /* selected device) */
380 #if defined(ADC_MULTIMODE_SUPPORT)
381 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
382 {
383 MODIFY_REG(ADCxy_COMMON->CCR,
384 ADC_CCR_DUAL
385 | ADC_CCR_DAMDF
386 | ADC_CCR_DELAY
387 ,
388 pADC_CommonInitStruct->Multimode
389 | pADC_CommonInitStruct->MultiDataFormat
390 | pADC_CommonInitStruct->MultiTwoSamplingDelay
391 );
392 }
393 else
394 {
395 MODIFY_REG(ADCxy_COMMON->CCR,
396 ADC_CCR_DUAL
397 | ADC_CCR_DAMDF
398 | ADC_CCR_DELAY
399 ,
400 LL_ADC_MULTI_INDEPENDENT
401 );
402 }
403 #else
404 /* No configuration to perform */
405 #endif /* ADC_MULTIMODE_SUPPORT */
406 }
407 else
408 {
409 /* Initialization error: One or several ADC instances belonging to */
410 /* the same ADC common instance are not disabled. */
411 status = ERROR;
412 }
413
414 return status;
415 }
416
417 /**
418 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
419 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
420 * whose fields will be set to default values.
421 * @retval None
422 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)423 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
424 {
425 /* Set ADC_CommonInitStruct fields to default values */
426 /* Set fields of ADC common */
427 /* (all ADC instances belonging to the same ADC common instance) */
428 #if defined(ADC_MULTIMODE_SUPPORT)
429 /* Set fields of ADC multimode */
430 pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
431 pADC_CommonInitStruct->MultiDataFormat = LL_ADC_MULTI_REG_DATA_EACH_ADC;
432 pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
433 #endif /* ADC_MULTIMODE_SUPPORT */
434 }
435
436 /**
437 * @brief De-initialize registers of the selected ADC instance
438 * to their default reset values.
439 * @note To reset all ADC instances quickly (perform a hard reset),
440 * use function @ref LL_ADC_CommonDeInit().
441 * @note If this functions returns error status, it means that ADC instance
442 * is in an unknown state.
443 * In this case, perform a hard reset using high level
444 * clock source RCC ADC reset.
445 * Caution: On this STM32 series, if several ADC instances are available
446 * on the selected device, RCC ADC reset will reset
447 * all ADC instances belonging to the common ADC instance.
448 * Refer to function @ref LL_ADC_CommonDeInit().
449 * @param ADCx ADC instance
450 * @retval An ErrorStatus enumeration value:
451 * - SUCCESS: ADC registers are de-initialized
452 * - ERROR: ADC registers are not de-initialized
453 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)454 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
455 {
456 ErrorStatus status = SUCCESS;
457
458 __IO uint32_t timeout_cpu_cycles = 0UL;
459
460 /* Check the parameters */
461 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
462
463 /* Disable ADC instance if not already disabled. */
464 if (LL_ADC_IsEnabled(ADCx) == 1UL)
465 {
466 /* Stop potential ADC conversion on going on ADC group regular. */
467 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
468 {
469 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
470 {
471 LL_ADC_REG_StopConversion(ADCx);
472 }
473 }
474
475 /* Stop potential ADC conversion on going on ADC group injected. */
476 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
477 {
478 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
479 {
480 LL_ADC_INJ_StopConversion(ADCx);
481 }
482 }
483
484 /* Wait for ADC conversions are effectively stopped */
485 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
486 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
487 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
488 {
489 timeout_cpu_cycles--;
490 if (timeout_cpu_cycles == 0UL)
491 {
492 /* Time-out error */
493 status = ERROR;
494 break;
495 }
496 }
497
498 /* Disable the ADC instance */
499 LL_ADC_Disable(ADCx);
500
501 /* Wait for ADC instance is effectively disabled */
502 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
503 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
504 {
505 timeout_cpu_cycles--;
506 if (timeout_cpu_cycles == 0UL)
507 {
508 /* Time-out error */
509 status = ERROR;
510 break;
511 }
512 }
513 }
514
515 /* Check whether ADC state is compliant with expected state */
516 if (READ_BIT(ADCx->CR,
517 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
518 | ADC_CR_ADDIS | ADC_CR_ADEN)
519 )
520 == 0UL)
521 {
522 /* ========== Reset ADC registers ========== */
523 /* Reset register IER */
524 CLEAR_BIT(ADCx->IER,
525 (LL_ADC_IT_ADRDY
526 | LL_ADC_IT_EOC
527 | LL_ADC_IT_EOS
528 | LL_ADC_IT_OVR
529 | LL_ADC_IT_EOSMP
530 | LL_ADC_IT_JEOC
531 | LL_ADC_IT_JEOS
532 | LL_ADC_IT_AWD1
533 | LL_ADC_IT_AWD2
534 | LL_ADC_IT_AWD3
535 )
536 );
537
538 /* Reset register ISR */
539 SET_BIT(ADCx->ISR,
540 (LL_ADC_FLAG_ADRDY
541 | LL_ADC_FLAG_EOC
542 | LL_ADC_FLAG_EOS
543 | LL_ADC_FLAG_OVR
544 | LL_ADC_FLAG_EOSMP
545 | LL_ADC_FLAG_JEOC
546 | LL_ADC_FLAG_JEOS
547 | LL_ADC_FLAG_AWD1
548 | LL_ADC_FLAG_AWD2
549 | LL_ADC_FLAG_AWD3
550 )
551 );
552
553 /* Reset register CR */
554 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
555 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
556 /* access mode "read-set": no direct reset applicable. */
557 /* - Reset Calibration mode to default setting (single ended). */
558 /* - Enable ADC deep power down. */
559 /* Note: ADC internal voltage regulator disable and ADC deep power */
560 /* down enable are conditioned to ADC state disabled: */
561 /* already done above. */
562 CLEAR_BIT(ADCx->CR, ADC_CR_ADCALDIF);
563 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
564
565 /* Reset register CFGR */
566 CLEAR_BIT(ADCx->CFGR1,
567 ADC_CFGR1_AWD1CH | ADC_CFGR1_JAUTO | ADC_CFGR1_JAWD1EN |
568 ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_JDISCEN |
569 ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN | ADC_CFGR1_AUTDLY |
570 ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
571 ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL |
572 ADC_CFGR1_RES | ADC_CFGR1_DMNGT);
573
574
575 /* Reset register CFGR2 */
576 CLEAR_BIT(ADCx->CFGR2,
577 (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
578 | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG
579 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
580 );
581
582 /* Reset register SMPR1 */
583 CLEAR_BIT(ADCx->SMPR1,
584 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
585 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
586 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
587 );
588
589 /* Reset register SMPR2 */
590 CLEAR_BIT(ADCx->SMPR2,
591 (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
592 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
593 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
594 );
595
596 /* Reset registers of AWD1 thresholds */
597 CLEAR_BIT(ADCx->AWD1LTR, ADC_AWD1LTR_LTR);
598 SET_BIT(ADCx->AWD1HTR, ADC_AWD1HTR_HTR & (~ADC_AWD1HTR_HTR_22));
599
600 /* Reset registers of AWD2 thresholds */
601 CLEAR_BIT(ADCx->AWD2LTR, ADC_AWD2LTR_LTR);
602 SET_BIT(ADCx->AWD2HTR, ADC_AWD2HTR_HTR & (~ADC_AWD2HTR_HTR_22));
603
604 /* Reset registers of AWD3 thresholds */
605 CLEAR_BIT(ADCx->AWD3LTR, ADC_AWD3LTR_LTR);
606 SET_BIT(ADCx->AWD3HTR, ADC_AWD3HTR_HTR & (~ADC_AWD3HTR_HTR_22));
607
608 /* Reset register SQR1 */
609 CLEAR_BIT(ADCx->SQR1,
610 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
611 | ADC_SQR1_SQ1 | ADC_SQR1_L)
612 );
613
614 /* Reset register SQR2 */
615 CLEAR_BIT(ADCx->SQR2,
616 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
617 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
618 );
619
620 /* Reset register SQR3 */
621 CLEAR_BIT(ADCx->SQR3,
622 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
623 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
624 );
625
626 /* Reset register SQR4 */
627 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
628
629 /* Reset register JSQR */
630 CLEAR_BIT(ADCx->JSQR,
631 (ADC_JSQR_JL
632 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
633 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
634 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
635 );
636
637 /* Reset register DR */
638 /* Note: bits in access mode read only, no direct reset applicable */
639
640 /* Reset register OFR1 */
641 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET);
642 /* Reset register OFCFGR1 */
643 CLEAR_BIT(ADCx->OFCFGR1, ADC_OFCFGR1_SSAT | ADC_OFCFGR1_USAT | ADC_OFCFGR1_POSOFF | ADC_OFCFGR1_OFFSET_CH);
644 /* Reset register OFR2 */
645 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET);
646 /* Reset register OFCFGR2 */
647 CLEAR_BIT(ADCx->OFCFGR2, ADC_OFCFGR2_SSAT | ADC_OFCFGR2_USAT | ADC_OFCFGR2_POSOFF | ADC_OFCFGR2_OFFSET_CH);
648 /* Reset register OFR3 */
649 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET);
650 /* Reset register OFCFGR3 */
651 CLEAR_BIT(ADCx->OFCFGR3, ADC_OFCFGR3_SSAT | ADC_OFCFGR3_USAT | ADC_OFCFGR3_POSOFF | ADC_OFCFGR3_OFFSET_CH);
652 /* Reset register OFR4 */
653 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET);
654 /* Reset register OFCFGR4 */
655 CLEAR_BIT(ADCx->OFCFGR4, ADC_OFCFGR4_SSAT | ADC_OFCFGR4_USAT | ADC_OFCFGR4_POSOFF | ADC_OFCFGR4_OFFSET_CH);
656
657 /* Reset register GCOMP */
658 /* Note: Bitfield ADC_GCOMP_GCOMPCOEFF reset value is 0x1000 */
659 MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMP | ADC_GCOMP_GCOMPCOEFF, 0x1000UL);
660
661 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
662 /* Note: bits in access mode read only, no direct reset applicable */
663
664 /* Reset register AWD2CR */
665 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
666
667 /* Reset register AWD3CR */
668 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
669
670 /* Reset register DIFSEL */
671 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
672
673 /* Reset register PCSEL */
674 CLEAR_BIT(ADCx->PCSEL, ADC_PCSEL_PCSEL);
675
676 /* Reset register CALFACT */
677 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
678 }
679 else
680 {
681 /* ADC instance is in an unknown state */
682 /* Need to performing a hard reset of ADC instance, using high level */
683 /* clock source RCC ADC reset. */
684 /* Caution: On this STM32 series, if several ADC instances are available */
685 /* on the selected device, RCC ADC reset will reset */
686 /* all ADC instances belonging to the common ADC instance. */
687 /* Caution: On this STM32 series, if several ADC instances are available */
688 /* on the selected device, RCC ADC reset will reset */
689 /* all ADC instances belonging to the common ADC instance. */
690 status = ERROR;
691 }
692
693 return status;
694 }
695
696 /**
697 * @brief Initialize some features of ADC instance.
698 * @note These parameters have an impact on ADC scope: ADC instance.
699 * Affects both group regular and group injected (availability
700 * of ADC group injected depends on STM32 families).
701 * Refer to corresponding unitary functions into
702 * @ref ADC_LL_EF_Configuration_ADC_Instance .
703 * @note The setting of these parameters by function @ref LL_ADC_Init()
704 * is conditioned to ADC state:
705 * ADC instance must be disabled.
706 * This condition is applied to all ADC features, for efficiency
707 * and compatibility over all STM32 families. However, the different
708 * features can be set under different ADC state conditions
709 * (setting possible with ADC enabled without conversion on going,
710 * ADC enabled with conversion on going, ...)
711 * Each feature can be updated afterwards with a unitary function
712 * and potentially with ADC in a different state than disabled,
713 * refer to description of each function for setting
714 * conditioned to ADC state.
715 * @note After using this function, some other features must be configured
716 * using LL unitary functions.
717 * The minimum configuration remaining to be done is:
718 * - Set ADC group regular or group injected sequencer:
719 * map channel on the selected sequencer rank.
720 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
721 * - Set ADC channel sampling time
722 * Refer to function LL_ADC_SetChannelSamplingTime();
723 * @param ADCx ADC instance
724 * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
725 * @retval An ErrorStatus enumeration value:
726 * - SUCCESS: ADC registers are initialized
727 * - ERROR: ADC registers are not initialized
728 */
LL_ADC_Init(ADC_TypeDef * ADCx,const LL_ADC_InitTypeDef * pADC_InitStruct)729 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
730 {
731 ErrorStatus status = SUCCESS;
732
733 /* Check the parameters */
734 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
735
736 assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
737 assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
738 assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(pADC_InitStruct->LeftBitShift));
739
740 /* Note: Hardware constraint (refer to description of this function): */
741 /* ADC instance must be disabled. */
742 if (LL_ADC_IsEnabled(ADCx) == 0UL)
743 {
744 /* Configuration of ADC hierarchical scope: */
745 /* - ADC instance */
746 /* - Set ADC data resolution */
747 /* - Set ADC conversion data alignment */
748 /* - Set ADC low power mode */
749 MODIFY_REG(ADCx->CFGR1,
750 ADC_CFGR1_RES
751 | ADC_CFGR1_AUTDLY
752 ,
753 pADC_InitStruct->Resolution
754 | pADC_InitStruct->LowPowerMode
755 );
756
757 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, pADC_InitStruct->LeftBitShift);
758 }
759 else
760 {
761 /* Initialization error: ADC instance is not disabled. */
762 status = ERROR;
763 }
764
765 return status;
766 }
767
768 /**
769 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
770 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
771 * whose fields will be set to default values.
772 * @retval None
773 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * pADC_InitStruct)774 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
775 {
776 /* Set ADC_InitStruct fields to default values */
777 /* Set fields of ADC instance */
778 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
779 pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
780 pADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE;
781 }
782
783 /**
784 * @brief Initialize some features of ADC group regular.
785 * @note These parameters have an impact on ADC scope: ADC group regular.
786 * Refer to corresponding unitary functions into
787 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
788 * (functions with prefix "REG").
789 * @note The setting of these parameters by function @ref LL_ADC_Init()
790 * is conditioned to ADC state:
791 * ADC instance must be disabled.
792 * This condition is applied to all ADC features, for efficiency
793 * and compatibility over all STM32 families. However, the different
794 * features can be set under different ADC state conditions
795 * (setting possible with ADC enabled without conversion on going,
796 * ADC enabled with conversion on going, ...)
797 * Each feature can be updated afterwards with a unitary function
798 * and potentially with ADC in a different state than disabled,
799 * refer to description of each function for setting
800 * conditioned to ADC state.
801 * @note After using this function, other features must be configured
802 * using LL unitary functions.
803 * The minimum configuration remaining to be done is:
804 * - Set ADC group regular or group injected sequencer:
805 * map channel on the selected sequencer rank.
806 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
807 * - Set ADC channel sampling time
808 * Refer to function LL_ADC_SetChannelSamplingTime();
809 * @param ADCx ADC instance
810 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
811 * @retval An ErrorStatus enumeration value:
812 * - SUCCESS: ADC registers are initialized
813 * - ERROR: ADC registers are not initialized
814 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,const LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)815 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
816 {
817 ErrorStatus status = SUCCESS;
818
819 /* Check the parameters */
820 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
821 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, pADC_RegInitStruct ->TriggerSource));
822 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct ->SequencerLength));
823 assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(pADC_RegInitStruct ->DataTransferMode));
824
825 if (pADC_RegInitStruct ->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
826 {
827 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct ->SequencerDiscont));
828
829 /* ADC group regular continuous mode and discontinuous mode */
830 /* can not be enabled simultaneously */
831 assert_param((pADC_RegInitStruct ->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
832 || (pADC_RegInitStruct ->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
833 }
834 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct ->ContinuousMode));
835 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct ->Overrun));
836
837 /* Note: Hardware constraint (refer to description of this function): */
838 /* ADC instance must be disabled. */
839 if (LL_ADC_IsEnabled(ADCx) == 0UL)
840 {
841 /* Configuration of ADC hierarchical scope: */
842 /* - ADC group regular */
843 /* - Set ADC group regular trigger source */
844 /* - Set ADC group regular sequencer length */
845 /* - Set ADC group regular sequencer discontinuous mode */
846 /* - Set ADC group regular continuous mode */
847 /* - Set ADC group regular conversion data transfer: no transfer or */
848 /* transfer by DMA, and DMA requests mode */
849 /* - Set ADC group regular overrun behavior */
850 /* Note: On this STM32 series, ADC trigger edge is set when starting */
851 /* ADC conversion. */
852 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
853 if (pADC_RegInitStruct ->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
854 {
855 MODIFY_REG(ADCx->CFGR1,
856 ADC_CFGR1_EXTSEL
857 | ADC_CFGR1_EXTEN
858 | ADC_CFGR1_DISCEN
859 | ADC_CFGR1_DISCNUM
860 | ADC_CFGR1_CONT
861 | ADC_CFGR1_DMNGT
862 | ADC_CFGR1_OVRMOD
863 ,
864 pADC_RegInitStruct ->TriggerSource
865 | pADC_RegInitStruct ->SequencerDiscont
866 | pADC_RegInitStruct ->ContinuousMode
867 | pADC_RegInitStruct ->DataTransferMode
868 | pADC_RegInitStruct ->Overrun
869 );
870 }
871 else
872 {
873 MODIFY_REG(ADCx->CFGR1,
874 ADC_CFGR1_EXTSEL
875 | ADC_CFGR1_EXTEN
876 | ADC_CFGR1_DISCEN
877 | ADC_CFGR1_DISCNUM
878 | ADC_CFGR1_CONT
879 | ADC_CFGR1_DMNGT
880 | ADC_CFGR1_OVRMOD
881 ,
882 pADC_RegInitStruct ->TriggerSource
883 | LL_ADC_REG_SEQ_DISCONT_DISABLE
884 | pADC_RegInitStruct ->ContinuousMode
885 | pADC_RegInitStruct ->DataTransferMode
886 | pADC_RegInitStruct ->Overrun
887 );
888 }
889
890 /* Set ADC group regular sequencer length and scan direction */
891 LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct ->SequencerLength);
892 }
893 else
894 {
895 /* Initialization error: ADC instance is not disabled. */
896 status = ERROR;
897 }
898 return status;
899 }
900
901 /**
902 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
903 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
904 * whose fields will be set to default values.
905 * @retval None
906 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)907 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
908 {
909 /* Set ADC_REG_InitStruct fields to default values */
910 /* Set fields of ADC group regular */
911 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
912 /* setting of trigger source to SW start. */
913 pADC_RegInitStruct ->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
914 pADC_RegInitStruct ->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
915 pADC_RegInitStruct ->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
916 pADC_RegInitStruct ->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
917 pADC_RegInitStruct ->DataTransferMode = LL_ADC_REG_DR_TRANSFER;
918 pADC_RegInitStruct ->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
919 }
920
921 /**
922 * @brief Initialize some features of ADC group injected.
923 * @note These parameters have an impact on ADC scope: ADC group injected.
924 * Refer to corresponding unitary functions into
925 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
926 * (functions with prefix "INJ").
927 * @note The setting of these parameters by function @ref LL_ADC_Init()
928 * is conditioned to ADC state:
929 * ADC instance must be disabled.
930 * This condition is applied to all ADC features, for efficiency
931 * and compatibility over all STM32 families. However, the different
932 * features can be set under different ADC state conditions
933 * (setting possible with ADC enabled without conversion on going,
934 * ADC enabled with conversion on going, ...)
935 * Each feature can be updated afterwards with a unitary function
936 * and potentially with ADC in a different state than disabled,
937 * refer to description of each function for setting
938 * conditioned to ADC state.
939 * @note After using this function, other features must be configured
940 * using LL unitary functions.
941 * The minimum configuration remaining to be done is:
942 * - Set ADC group injected sequencer:
943 * map channel on the selected sequencer rank.
944 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
945 * - Set ADC channel sampling time
946 * Refer to function LL_ADC_SetChannelSamplingTime();
947 * @param ADCx ADC instance
948 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
949 * @retval An ErrorStatus enumeration value:
950 * - SUCCESS: ADC registers are initialized
951 * - ERROR: ADC registers are not initialized
952 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,const LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)953 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
954 {
955 ErrorStatus status = SUCCESS;
956
957 /* Check the parameters */
958 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
959 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, pADC_InjInitStruct->TriggerSource));
960 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength));
961 if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
962 {
963 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont));
964 }
965 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto));
966
967 /* Note: Hardware constraint (refer to description of this function): */
968 /* ADC instance must be disabled. */
969 if (LL_ADC_IsEnabled(ADCx) == 0UL)
970 {
971 /* Configuration of ADC hierarchical scope: */
972 /* - ADC group injected */
973 /* - Set ADC group injected trigger source */
974 /* - Set ADC group injected sequencer length */
975 /* - Set ADC group injected sequencer discontinuous mode */
976 /* - Set ADC group injected conversion trigger: independent or */
977 /* from ADC group regular */
978 /* Note: On this STM32 series, ADC trigger edge is set when starting */
979 /* ADC conversion. */
980 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
981 if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
982 {
983 MODIFY_REG(ADCx->CFGR1,
984 ADC_CFGR1_JDISCEN
985 | ADC_CFGR1_JAUTO
986 ,
987 pADC_InjInitStruct->SequencerDiscont
988 | pADC_InjInitStruct->TrigAuto
989 );
990 }
991 else
992 {
993 MODIFY_REG(ADCx->CFGR1,
994 ADC_CFGR1_JDISCEN
995 | ADC_CFGR1_JAUTO
996 ,
997 LL_ADC_REG_SEQ_DISCONT_DISABLE
998 | pADC_InjInitStruct->TrigAuto
999 );
1000 }
1001
1002 MODIFY_REG(ADCx->JSQR,
1003 ADC_JSQR_JEXTSEL
1004 | ADC_JSQR_JEXTEN
1005 | ADC_JSQR_JL
1006 ,
1007 pADC_InjInitStruct->TriggerSource
1008 | pADC_InjInitStruct->SequencerLength
1009 );
1010 }
1011 else
1012 {
1013 /* Initialization error: ADC instance is not disabled. */
1014 status = ERROR;
1015 }
1016 return status;
1017 }
1018
1019 /**
1020 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1021 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1022 * whose fields will be set to default values.
1023 * @retval None
1024 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)1025 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
1026 {
1027 /* Set ADC_INJ_InitStruct fields to default values */
1028 /* Set fields of ADC group injected */
1029 pADC_InjInitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1030 pADC_InjInitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1031 pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1032 pADC_InjInitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1033 }
1034
1035 /**
1036 * @}
1037 */
1038
1039 /**
1040 * @}
1041 */
1042
1043 /**
1044 * @}
1045 */
1046
1047 #endif /* ADC1 || ADC2 */
1048
1049 /**
1050 * @}
1051 */
1052
1053 #endif /* USE_FULL_LL_DRIVER */
1054
