1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL SYSTEM driver contains a set of generic APIs that can be
23 used by user:
24 (+) Some of the FLASH features need to be handled in the SYSTEM file.
25 (+) Access to DBGCMU registers
26 (+) Access to SYSCFG registers
27 @endverbatim
28 */
29
30 /* Define to prevent recursive inclusion -------------------------------------*/
31 #ifndef STM32N6xx_LL_SYSTEM_H
32 #define STM32N6xx_LL_SYSTEM_H
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 /* Includes ------------------------------------------------------------------*/
39 #include "stm32n6xx.h"
40
41 /** @addtogroup STM32N6xx_LL_Driver
42 * @{
43 */
44
45 #if defined (SYSCFG) || defined (DBGMCU)
46
47 /** @defgroup SYSTEM_LL SYSTEM
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53
54 /* Private constants ---------------------------------------------------------*/
55 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
56 * @{
57 */
58
59 /** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection
60 * @{
61 */
62 #define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell (available in the SYSCFG_CCVR)*/
63 #define LL_SYSCFG_VDD_REGISTER_CODE SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)*/
64 /**
65 * @}
66 */
67
68 /* Private macros ------------------------------------------------------------*/
69
70 /* Exported types ------------------------------------------------------------*/
71 /* Exported constants --------------------------------------------------------*/
72 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
73 * @{
74 */
75
76 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
77 * @{
78 */
79 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA6 SYSCFG_CFGR1_PA6_FMP /*!< Enable Fast Mode Plus on PA6 */
80 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA7 SYSCFG_CFGR1_PA7_FMP /*!< Enable Fast Mode Plus on PA7 */
81 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA15 SYSCFG_CFGR1_PA15_FMP /*!< Enable Fast Mode Plus on PA15 */
82 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB3 SYSCFG_CFGR1_PB3_FMP /*!< Enable Fast Mode Plus on PB3 */
83 /**
84 * @}
85 */
86
87 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
88 * @{
89 */
90 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
91 with Break Input of TIM1/16/17 */
92 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
93 with TIM1/16/17 Break Input and also
94 the PVDE and PLS bits of the Power Control Interface */
95 #define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM ECC double error signal
96 with Break Input of TIM1/16/17 */
97 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM33
98 with Break Input of TIM1/16/17 */
99 /**
100 * @}
101 */
102
103 /** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes
104 * @note Only available when system implements security (TZEN=1)
105 * @{
106 */
107 #define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */
108 #define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */
109 #define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */
110 #define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */
111 #define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */
112 #define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */
113 /**
114 * @}
115 */
116
117 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
118 * @{
119 */
120 #define LL_DBGMCU_DBTRGIN 0U /*!< DBTRGIO connected to DBTRGIN */
121 #define LL_DBGMCU_DBTRGOUT DBGMCU_CR_DBTRGOEN /*!< DBTRGIO connected to DBTRGOUT */
122 /**
123 * @}
124 */
125
126 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
127 * @{
128 */
129 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2_STOP
130 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3_STOP /*!< TIM3 stop in debug */
131 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4_STOP /*!< TIM4 stop in debug */
132 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5_STOP /*!< TIM5 stop in debug */
133 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6_STOP /*!< TIM6 stop in debug */
134 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7_STOP /*!< TIM7 stop in debug */
135 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12_STOP /*!< TIM12 stop in debug */
136 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13_STOP /*!< TIM13 stop in debug */
137 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14_STOP /*!< TIM14 stop in debug */
138 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP /*!< LPTIM1 stop in debug */
139 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1LFZ1_DBG_WWDG1_STOP /*!< WWDG1 stop in debug */
140 #define LL_DBGMCU_APB1_GRP1_TIM10_STOP DBGMCU_APB1LFZ1_DBG_TIM10_STOP /*!< TIM10 stop in debug */
141 #define LL_DBGMCU_APB1_GRP1_TIM11_STOP DBGMCU_APB1LFZ1_DBG_TIM11_STOP /*!< TIM11 stop in debug */
142 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout stop in debug */
143 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout stop in debug */
144 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3_STOP /*!< I2C3 SMBUS timeout stop in debug */
145 #define LL_DBGMCU_APB1_GRP1_I3C1_STOP DBGMCU_APB1LFZ1_DBG_I3C1_STOP /*!< I3C1 SMBUS timeout stop in debug */
146 #define LL_DBGMCU_APB1_GRP1_I3C2_STOP DBGMCU_APB1LFZ1_DBG_I3C2_STOP /*!< I3C2 SMBUS timeout stop in debug */
147 /**
148 * @}
149 */
150
151 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
152 * @{
153 */
154 #define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN_STOP /*!< FDCAN stop in debug */
155 /**
156 * @}
157 */
158
159 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
160 * @{
161 */
162 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1_STOP /*!< TIM1 stop in debug */
163 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8_STOP /*!< TIM8 stop in debug */
164 #define LL_DBGMCU_APB2_GRP1_TIM18_STOP DBGMCU_APB2FZ1_DBG_TIM18_STOP /*!< TIM18 stop in debug */
165 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15_STOP /*!< TIM15 stop in debug */
166 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16_STOP /*!< TIM16 stop in debug */
167 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17_STOP /*!< TIM17 stop in debug */
168 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2FZ1_DBG_TIM9_STOP /*!< TIM9 stop in debug */
169 /**
170 * @}
171 */
172
173 /** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
174 * @{
175 */
176 #define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4_STOP /*!< I2C4 stop in debug */
177 #define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2_STOP /*!< LPTIM2 stop in debug */
178 #define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3_STOP /*!< LPTIM3 stop in debug */
179 #define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4_STOP /*!< LPTIM4 stop in debug */
180 #define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5_STOP /*!< LPTIM5 stop in debug */
181 #define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC_STOP /*!< RTC stop in debug */
182 #define LL_DBGMCU_APB4_GRP1_IWDG_STOP DBGMCU_APB4FZ1_DBG_IWDG_STOP /*!< IWDG stop in debug */
183 /**
184 * @}
185 */
186
187 /** @defgroup SYSTEM_LL_EC_APB5_GRP1_STOP_IP DBGMCU APB5 GRP1 STOP IP
188 * @{
189 */
190 #define LL_DBGMCU_APB5_GRP1_GFXTIM_STOP DBGMCU_APB5FZ1_DBG_GFXTIM_STOP /*!< GFXTIM stop in debug */
191 /**
192 * @}
193 */
194
195 /** @defgroup SYSTEM_LL_EC_AHB1_GRP1_STOP_IP DBGMCU AHB1 GRP1 STOP IP
196 * @{
197 */
198 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP /*!< GPDMA1_CH0 suspend in debug */
199 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP /*!< GPDMA1_CH1 suspend in debug */
200 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP /*!< GPDMA1_CH2 suspend in debug */
201 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP /*!< GPDMA1_CH3 suspend in debug */
202 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP /*!< GPDMA1_CH4 suspend in debug */
203 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP /*!< GPDMA1_CH5 suspend in debug */
204 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP /*!< GPDMA1_CH6 suspend in debug */
205 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP /*!< GPDMA1_CH7 suspend in debug */
206 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP /*!< GPDMA1_CH8 suspend in debug */
207 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP /*!< GPDMA1_CH9 suspend in debug */
208 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP /*!< GPDMA1_CH10 suspend in debug */
209 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP /*!< GPDMA1_CH11 suspend in debug */
210 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP /*!< GPDMA1_CH12 suspend in debug */
211 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP /*!< GPDMA1_CH13 suspend in debug */
212 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP /*!< GPDMA1_CH14 suspend in debug */
213 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP /*!< GPDMA1_CH15 suspend in debug */
214 /**
215 * @}
216 */
217
218 /** @defgroup SYSTEM_LL_EC_AHB5_GRP1_STOP_IP DBGMCU AHB5 GRP1 STOP IP
219 * @{
220 */
221 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP /*!< HPDMA1_CH0 suspend in debug */
222 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP /*!< HPDMA1_CH1 suspend in debug */
223 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP /*!< HPDMA1_CH2 suspend in debug */
224 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP /*!< HPDMA1_CH3 suspend in debug */
225 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP /*!< HPDMA1_CH4 suspend in debug */
226 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP /*!< HPDMA1_CH5 suspend in debug */
227 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP /*!< HPDMA1_CH6 suspend in debug */
228 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP /*!< HPDMA1_CH7 suspend in debug */
229 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP /*!< HPDMA1_CH8 suspend in debug */
230 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP /*!< HPDMA1_CH9 suspend in debug */
231 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP /*!< HPDMA1_CH10 suspend in debug */
232 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP /*!< HPDMA1_CH11 suspend in debug */
233 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP /*!< HPDMA1_CH12 suspend in debug */
234 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP /*!< HPDMA1_CH13 suspend in debug */
235 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP /*!< HPDMA1_CH14 suspend in debug */
236 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP /*!< HPDMA1_CH15 suspend in debug */
237 #define LL_DBGMCU_AHB5_GRP1_NPU_STOP DBGMCU_AHB5FZ1_NPU_DBG_FREEZE /*!< NPU stop in debug mode */
238 /**
239 * @}
240 */
241
242 /* Exported macro ------------------------------------------------------------*/
243
244 /* Exported functions --------------------------------------------------------*/
245 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
246 * @{
247 */
248
249
250 #if defined (CPU_IN_SECURE_STATE)
251 /**
252 * @brief Returns the device identifier
253 * @note The BSEC clock must be enabled before calling this function
254 * Returned Device ID can be
255 * 0x00006200 for STM32N645xx
256 * 0x00006000 for STM32N655xx
257 * 0x00002200 for STM32N647xx
258 * 0x00002000 for STM32N657xx
259 * 0xffffffff if an error occurs
260 * @retval Device identifier
261 */
LL_GetDeviceID(void)262 __STATIC_INLINE uint32_t LL_GetDeviceID(void)
263 {
264 return (uint32_t)(READ_REG(BSEC->FVRw[9]));
265 }
266
267
268 /**
269 * @brief Returns the device revision identifier
270 * @note Returned Revision ID can be
271 * 0x00000100 for Cut1.0
272 * 0x00000101 for Cut1.1
273 * 0x00000200 for Cut2.0
274 * @retval Device revision identifier
275 */
LL_GetRevisionID(void)276 __STATIC_INLINE uint32_t LL_GetRevisionID(void)
277 {
278 return *(uint32_t *)(REVID_BASE);
279 }
280 #endif /* CPU_IN_SECURE_STATE */
281
282 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
283 * @{
284 */
285
286 /**
287 * @brief Enable the Debug Module during SLEEP mode
288 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
289 * @retval None
290 */
LL_DBGMCU_EnableDBGSleepMode(void)291 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
292 {
293 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
294 }
295
296 /**
297 * @brief Disable the Debug Module during SLEEP mode
298 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
299 * @retval None
300 */
LL_DBGMCU_DisableDBGSleepMode(void)301 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
302 {
303 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
304 }
305
306 /**
307 * @brief Enable the Debug Module during STOP mode
308 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
309 * @retval None
310 */
LL_DBGMCU_EnableDBGStopMode(void)311 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
312 {
313 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
314 }
315
316 /**
317 * @brief Disable the Debug Module during STOP mode
318 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
319 * @retval None
320 */
LL_DBGMCU_DisableDBGStopMode(void)321 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
322 {
323 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
324 }
325
326 /**
327 * @brief Enable the Debug Module during STANDBY mode
328 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
329 * @retval None
330 */
LL_DBGMCU_EnableDBGStandbyMode(void)331 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
332 {
333 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
334 }
335
336 /**
337 * @brief Disable the Debug Module during STANDBY mode
338 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
339 * @retval None
340 */
LL_DBGMCU_DisableDBGStandbyMode(void)341 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
342 {
343 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
344 }
345
346 /**
347 * @brief Enable the Debug clock through software
348 * @rmtoll DBGMCU_CR DBGCLKEN LL_DBGMCU_EnableDBGClock
349 * @retval None
350 */
LL_DBGMCU_EnableDBGClock(void)351 __STATIC_INLINE void LL_DBGMCU_EnableDBGClock(void)
352 {
353 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBGCLKEN);
354 }
355
356 /**
357 * @brief Disable the Debug clock through software
358 * @rmtoll DBGMCU_CR DBGCLKEN LL_DBGMCU_DisableDBGClock
359 * @retval None
360 */
LL_DBGMCU_DisableDBGClock(void)361 __STATIC_INLINE void LL_DBGMCU_DisableDBGClock(void)
362 {
363 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBGCLKEN);
364 }
365
366 /**
367 * @brief Enable the TPIU export clock enable through software
368 * @rmtoll DBGMCU_CR TRACECLKEN LL_DBGMCU_EnableTPIUExportClock
369 * @retval None
370 */
LL_DBGMCU_EnableTPIUExportClock(void)371 __STATIC_INLINE void LL_DBGMCU_EnableTPIUExportClock(void)
372 {
373 SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN);
374 }
375
376 /**
377 * @brief Disable the TPIU export clock enable through software
378 * @rmtoll DBGMCU_CR TRACECLKEN LL_DBGMCU_DisableTPIUExportClock
379 * @retval None
380 */
LL_DBGMCU_DisableTPIUExportClock(void)381 __STATIC_INLINE void LL_DBGMCU_DisableTPIUExportClock(void)
382 {
383 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN);
384 }
385
386 /**
387 * @brief Set DBTRGIO connection control
388 * @rmtoll DBGMCU_CR DBTRGOEN LL_DBGMCU_SetDBTRGIOConnectionControl
389 * @param ConfigDBTRGIO This parameter can be one of the following values:
390 * @arg @ref LL_DBGMCU_DBTRGIN
391 * @arg @ref LL_DBGMCU_DBTRGOUT
392 * @retval None
393 */
LL_DBGMCU_SetDBTRGIOConnectionControl(uint32_t ConfigDBTRGIO)394 __STATIC_INLINE void LL_DBGMCU_SetDBTRGIOConnectionControl(uint32_t ConfigDBTRGIO)
395 {
396 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBTRGOEN, ConfigDBTRGIO);
397 }
398
399 /**
400 * @brief Get DBTRGIO connection control
401 * @rmtoll DBGMCU_CR DBTRGOEN LL_DBGMCU_GetDBTRGIOConnectionControl
402 * @retval Returned value can be one of the following values:
403 * @arg @ref LL_DBGMCU_DBTRGIN
404 * @arg @ref LL_DBGMCU_DBTRGOUT
405 */
LL_DBGMCU_GetDBTRGIOConnectionControl(void)406 __STATIC_INLINE uint32_t LL_DBGMCU_GetDBTRGIOConnectionControl(void)
407 {
408 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBTRGOEN));
409 }
410
411 /**
412 * @brief Enable TSGEN halt
413 * @rmtoll DBGMCU_CR HLT_TSGEN_EN LL_DBGMCU_EnableTSGENHalt
414 * @retval None
415 */
LL_DBGMCU_EnableTSGENHalt(void)416 __STATIC_INLINE void LL_DBGMCU_EnableTSGENHalt(void)
417 {
418 SET_BIT(DBGMCU->CR, DBGMCU_CR_HLT_TSGEN_EN);
419 }
420
421 /**
422 * @brief Disable TSGEN halt
423 * @rmtoll DBGMCU_CR HLT_TSGEN_EN LL_DBGMCU_DisableTSGENHalt
424 * @retval None
425 */
LL_DBGMCU_DisableTSGENHalt(void)426 __STATIC_INLINE void LL_DBGMCU_DisableTSGENHalt(void)
427 {
428 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_HLT_TSGEN_EN);
429 }
430
431 /**
432 * @brief Freeze APB1 peripherals (group1 peripherals)
433 * @rmtoll DBGMCU_APB1LFZ1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
434 * @param Periphs This parameter can be a combination of the following values:
435 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
436 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
437 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
438 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
439 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
440 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
441 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
442 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
443 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
444 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
445 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
446 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM10_STOP
447 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM11_STOP
448 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
449 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
450 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
451 * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP
452 * @arg @ref LL_DBGMCU_APB1_GRP1_I3C2_STOP
453 * @retval None
454 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)455 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
456 {
457 SET_BIT(DBGMCU->APB1LFZ1, Periphs);
458 }
459
460 /**
461 * @brief Unfreeze APB1 peripherals (group1 peripherals)
462 * @rmtoll DBGMCU_APB1LFZ DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
463 * @param Periphs This parameter can be a combination of the following values:
464 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
465 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
466 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
467 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
468 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
469 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
470 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
471 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
472 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
473 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
474 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
475 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM10_STOP
476 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM11_STOP
477 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
478 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
479 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
480 * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP
481 * @arg @ref LL_DBGMCU_APB1_GRP1_I3C2_STOP
482 * @retval None
483 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)484 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
485 {
486 CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
487 }
488
489 /**
490 * @brief Freeze APB1 peripherals (group2 peripherals)
491 * @rmtoll DBGMCU_APB1HFZ1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
492 * @param Periphs This parameter can be a combination of the following values:
493 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
494 * @retval None
495 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)496 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
497 {
498 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
499 }
500
501 /**
502 * @brief Unfreeze APB1 peripherals (group2 peripherals)
503 * @rmtoll DBGMCU_APB1HFZ1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
504 * @param Periphs This parameter can be a combination of the following values:
505 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
506 * @retval None
507 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)508 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
509 {
510 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
511 }
512
513 /**
514 * @brief Freeze APB2 peripherals
515 * @rmtoll DBGMCU_APB2FZ1 DBG_TIMx_STOP LL_DBGMCU_APB2_FreezePeriph
516 * @param Periphs This parameter can be a combination of the following values:
517 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
518 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
519 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM18_STOP
520 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
521 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
522 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
523 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
524 * @retval None
525 */
LL_DBGMCU_APB2_FreezePeriph(uint32_t Periphs)526 __STATIC_INLINE void LL_DBGMCU_APB2_FreezePeriph(uint32_t Periphs)
527 {
528 SET_BIT(DBGMCU->APB2FZ1, Periphs);
529 }
530
531 /**
532 * @brief Unfreeze APB2 peripherals
533 * @rmtoll DBGMCU_APB2FZ1 DBG_TIMx_STOP LL_DBGMCU_APB2_UnFreezePeriph
534 * @param Periphs This parameter can be a combination of the following values:
535 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
536 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
537 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM18_STOP
538 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
539 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
540 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
541 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
542 * @retval None
543 */
LL_DBGMCU_APB2_UnFreezePeriph(uint32_t Periphs)544 __STATIC_INLINE void LL_DBGMCU_APB2_UnFreezePeriph(uint32_t Periphs)
545 {
546 SET_BIT(DBGMCU->APB2FZ1, Periphs);
547 }
548
549 /**
550 * @brief Freeze APB4 peripherals
551 * @rmtoll DBGMCU_APB4FZ1 DBG_TIMx_STOP LL_DBGMCU_APB4_FreezePeriph
552 * @param Periphs This parameter can be a combination of the following values:
553 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
554 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
555 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
556 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
557 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
558 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
559 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP
560 * @retval None
561 */
LL_DBGMCU_APB4_FreezePeriph(uint32_t Periphs)562 __STATIC_INLINE void LL_DBGMCU_APB4_FreezePeriph(uint32_t Periphs)
563 {
564 SET_BIT(DBGMCU->APB4FZ1, Periphs);
565 }
566
567 /**
568 * @brief Unreeze APB4 peripherals
569 * @rmtoll DBGMCU_APB4FZ1 DBG_TIMx_STOP LL_DBGMCU_APB4_UnFreezePeriph
570 * @param Periphs This parameter can be a combination of the following values:
571 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
572 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
573 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
574 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
575 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
576 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
577 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP
578 * @retval None
579 */
LL_DBGMCU_APB4_UnFreezePeriph(uint32_t Periphs)580 __STATIC_INLINE void LL_DBGMCU_APB4_UnFreezePeriph(uint32_t Periphs)
581 {
582 SET_BIT(DBGMCU->APB4FZ1, Periphs);
583 }
584
585 /**
586 * @brief Freeze APB5 peripherals
587 * @rmtoll DBGMCU_APB5FZ1 DBG_TIMx_STOP LL_DBGMCU_APB5_FreezePeriph
588 * @param Periphs This parameter can be a combination of the following values:
589 * @arg @ref LL_DBGMCU_APB5_GRP1_GFXTIM_STOP
590 * @retval None
591 */
LL_DBGMCU_APB5_FreezePeriph(uint32_t Periphs)592 __STATIC_INLINE void LL_DBGMCU_APB5_FreezePeriph(uint32_t Periphs)
593 {
594 SET_BIT(DBGMCU->APB5FZ1, Periphs);
595 }
596
597 /**
598 * @brief Unreeze APB5 peripherals
599 * @rmtoll DBGMCU_APB5FZ1 DBG_TIMx_STOP LL_DBGMCU_APB5_UnFreezePeriph
600 * @param Periphs This parameter can be a combination of the following values:
601 * @arg @ref LL_DBGMCU_APB5_GRP1_GFXTIM_STOP
602 * @retval None
603 */
LL_DBGMCU_APB5_UnFreezePeriph(uint32_t Periphs)604 __STATIC_INLINE void LL_DBGMCU_APB5_UnFreezePeriph(uint32_t Periphs)
605 {
606 SET_BIT(DBGMCU->APB5FZ1, Periphs);
607 }
608
609 /**
610 * @brief Freeze AHB1 peripherals
611 * @rmtoll DBGMCU_AHB1FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB1_FreezePeriph
612 * @param Periphs This parameter can be a combination of the following values:
613 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP
614 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP
615 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP
616 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP
617 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP
618 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP
619 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP
620 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP
621 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP
622 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP
623 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP
624 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP
625 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP
626 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP
627 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP
628 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP
629 * @retval None
630 */
LL_DBGMCU_AHB1_FreezePeriph(uint32_t Periphs)631 __STATIC_INLINE void LL_DBGMCU_AHB1_FreezePeriph(uint32_t Periphs)
632 {
633 SET_BIT(DBGMCU->AHB1FZ1, Periphs);
634 }
635
636 /**
637 * @brief Unreeze AHB1 peripherals
638 * @rmtoll DBGMCU_AHB1FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB1_UnFreezePeriph
639 * @param Periphs This parameter can be a combination of the following values:
640 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP
641 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP
642 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP
643 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP
644 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP
645 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP
646 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP
647 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP
648 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP
649 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP
650 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP
651 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP
652 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP
653 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP
654 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP
655 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP
656 * @retval None
657 */
LL_DBGMCU_AHB1_UnFreezePeriph(uint32_t Periphs)658 __STATIC_INLINE void LL_DBGMCU_AHB1_UnFreezePeriph(uint32_t Periphs)
659 {
660 SET_BIT(DBGMCU->AHB1FZ1, Periphs);
661 }
662
663 /**
664 * @brief Freeze AHB5 peripherals
665 * @rmtoll DBGMCU_AHB5FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB5_FreezePeriph
666 * @param Periphs This parameter can be a combination of the following values:
667 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP
668 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP
669 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP
670 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP
671 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP
672 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP
673 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP
674 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP
675 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP
676 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP
677 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP
678 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP
679 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP
680 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP
681 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP
682 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP
683 * @arg @ref LL_DBGMCU_AHB5_GRP1_NPU_STOP
684 * @retval None
685 */
LL_DBGMCU_AHB5_FreezePeriph(uint32_t Periphs)686 __STATIC_INLINE void LL_DBGMCU_AHB5_FreezePeriph(uint32_t Periphs)
687 {
688 SET_BIT(DBGMCU->AHB5FZ1, Periphs);
689 }
690
691 /**
692 * @brief Unreeze AHB5 peripherals
693 * @rmtoll DBGMCU_AHB5FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB5_UnFreezePeriph
694 * @param Periphs This parameter can be a combination of the following values:
695 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP
696 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP
697 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP
698 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP
699 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP
700 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP
701 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP
702 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP
703 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP
704 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP
705 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP
706 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP
707 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP
708 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP
709 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP
710 * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP
711 * @arg @ref LL_DBGMCU_AHB5_GRP1_NPU_STOP
712 * @retval None
713 */
LL_DBGMCU_AHB5_UnFreezePeriph(uint32_t Periphs)714 __STATIC_INLINE void LL_DBGMCU_AHB5_UnFreezePeriph(uint32_t Periphs)
715 {
716 SET_BIT(DBGMCU->AHB5FZ1, Periphs);
717 }
718
719
720 /**
721 * @}
722 */
723
724 #endif /* defined (SYSCFG) || defined (DBGMCU) */
725
726 /**
727 * @}
728 */
729
730 /**
731 * @}
732 */
733
734 /**
735 * @}
736 */
737
738 /**
739 * @}
740 */
741
742 /**
743 * @}
744 */
745
746 #ifdef __cplusplus
747 }
748 #endif
749
750 #endif /* STM32N6xx_LL_SYSTEM_H */
751
