1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32N6xx_LL_LPTIM_H
21 #define STM32N6xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32n6xx.h"
29
30 /** @addtogroup STM32N6xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
43 * @{
44 */
45
46 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
47 {
48 0U, /* CC1P */
49 16U /* CC2P */
50 };
51
52 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
53 {
54 0U, /* IC1F */
55 16U /* IC2F */
56 };
57
58 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
59 {
60 0U, /* IC1PSC */
61 16U /* IC2PSC */
62 };
63
64 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
65 {
66 0U, /* CC1SEL */
67 16U /* CC2SEL */
68 };
69
70 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
71 {
72 LPTIM_CCMR1_CC1E_Pos, /* CC1E */
73 LPTIM_CCMR1_CC2E_Pos /* CC2E */
74 };
75
76 static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] =
77 {
78 {2, 7, 9, 13},
79 {3, 5, 6, 8},
80 {2, 3, 4, 5},
81 {2, 2, 3, 3},
82 {2, 2, 2, 2},
83 {2, 2, 2, 2},
84 {2, 2, 2, 2},
85 {2, 2, 2, 2}
86
87 };
88
89 /**
90 * @}
91 */
92
93 /* Private constants ---------------------------------------------------------*/
94
95 /* Private macros ------------------------------------------------------------*/
96 #if defined(USE_FULL_LL_DRIVER)
97 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
98 * @{
99 */
100 /**
101 * @}
102 */
103 #endif /*USE_FULL_LL_DRIVER*/
104
105 /* Exported types ------------------------------------------------------------*/
106 #if defined(USE_FULL_LL_DRIVER)
107 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
108 * @{
109 */
110
111 /**
112 * @brief LPTIM Init structure definition
113 */
114 typedef struct
115 {
116 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
117 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
118
119 This feature can be modified afterwards using unitary
120 function @ref LL_LPTIM_SetClockSource().*/
121
122 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
123 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
124
125 This feature can be modified afterwards using using unitary
126 function @ref LL_LPTIM_SetPrescaler().*/
127
128 uint32_t Waveform; /*!< Specifies the waveform shape.
129 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
130
131 This feature can be modified afterwards using unitary
132 function @ref LL_LPTIM_SetWaveform().*/
133 } LL_LPTIM_InitTypeDef;
134
135 /**
136 * @}
137 */
138 #endif /* USE_FULL_LL_DRIVER */
139
140 /* Exported constants --------------------------------------------------------*/
141 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
142 * @{
143 */
144
145 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
146 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
147 * @{
148 */
149 #define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */
150 #define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */
151 #define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */
152 #define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */
153 #define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */
154 #define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */
155 #define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */
156 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
157 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
158 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
159 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
160 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
161 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
162 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
163 /**
164 * @}
165 */
166
167 /** @defgroup LPTIM_LL_EC_IT IT Defines
168 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
169 * @{
170 */
171 #define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */
172 #define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */
173 #define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */
174 #define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */
175 #define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */
176 #define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */
177 #define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */
178 #define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */
179 #define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */
180 #define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */
181 #define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */
182 #define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */
183 #define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */
184 /**
185 * @}
186 */
187
188 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
189 * @{
190 */
191 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
192 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
193 /**
194 * @}
195 */
196
197 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
198 * @{
199 */
200 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
201 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
202 /**
203 * @}
204 */
205
206 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
207 * @{
208 */
209 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
210 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
211 /**
212 * @}
213 */
214
215 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
216 * @{
217 */
218 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
219 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
220 /**
221 * @}
222 */
223
224 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
225 * @{
226 */
227 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers*/
228 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CCMR1_CC1P_0 /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers*/
229 /**
230 * @}
231 */
232
233 /** @defgroup TIM_LL_EC_CHANNEL Channel
234 * @{
235 */
236 #define LL_LPTIM_CHANNEL_CH1 0x00000000U /*!< LPTIM input/output channel 1 */
237 #define LL_LPTIM_CHANNEL_CH2 0x00000001U /*!< LPTIM input/output channel 2 */
238 /**
239 * @}
240 */
241
242 /** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler
243 * @{
244 */
245 #define LL_LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */
246 #define LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
247 #define LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
248 #define LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */
249 /**
250 * @}
251 */
252
253 /** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter
254 * @{
255 */
256 #define LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */
257 #define LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
258 #define LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
259 #define LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
260 /**
261 * @}
262 */
263
264 /** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY Input Capture Polarity
265 * @{
266 */
267 #define LL_LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */
268 #define LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */
269 #define LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */
270 /**
271 * @}
272 */
273 /** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection Input Capture selection
274 * @{
275 */
276 #define LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL /*!< Select PWM mode */
277 #define LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL /*!< Select Input Capture mode*/
278 /**
279 * @}
280 */
281
282 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
283 * @{
284 */
285 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
286 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
287 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
288 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
289 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
290 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
291 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
292 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
293 /**
294 * @}
295 */
296
297 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
298 * @{
299 */
300 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
301 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
302 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
303 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
304 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
305 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
306 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_A (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI2 FS A output */
307 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to SAI2 FS B output */
308 #define LL_LPTIM_TRIG_SOURCE_LPTIM2_CH1 LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to LPTIM2 Channel 1 */
309 #define LL_LPTIM_TRIG_SOURCE_LPTIM3_CH1 LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to LPTIM3 Channel 1 */
310 #define LL_LPTIM_TRIG_SOURCE_LPTIM4_OUT (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPTIM4 Output */
311 #define LL_LPTIM_TRIG_SOURCE_LPTIM5_OUT LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to LPTIM5 Output */
312 /**
313 * @}
314 */
315
316 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
317 * @{
318 */
319 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
320 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
321 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
322 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
323 /**
324 * @}
325 */
326
327 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
328 * @{
329 */
330 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
331 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
332 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
333 /**
334 * @}
335 */
336
337 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
338 * @{
339 */
340 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
341 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
342 /**
343 * @}
344 */
345
346 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
347 * @{
348 */
349 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
350 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
351 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
352 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
353 /**
354 * @}
355 */
356
357 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
358 * @{
359 */
360 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
361 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
362 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
363 /**
364 * @}
365 */
366
367 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
368 * @{
369 */
370 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
371 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
372 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
373 /**
374 * @}
375 */
376
377 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
378 * @{
379 */
380 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and LPTIM3 */
381 /**
382 * @}
383 */
384
385 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
386 * @{
387 */
388 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and LPTIM3 */
389 /**
390 * @}
391 */
392
393 /** @defgroup LPTIM_EC_LPTIM1_IC1_RMP LPTIM1 Input Ch1 Remap
394 * @{
395 */
396 #define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
397 /**
398 * @}
399 */
400
401 /** @defgroup LPTIM_EC_LPTIM1_IC2_RMP LPTIM1 Input Ch2 Remap
402 * @{
403 */
404 #define LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
405 #define LL_LPTIM_LPTIM1_IC2_RMP_LSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to LSI */
406 #define LL_LPTIM_LPTIM1_IC2_RMP_LSE LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to LSE */
407 /**
408 * @}
409 */
410
411 /** @defgroup LPTIM_EC_LPTIM2_IC1_RMP LPTIM2 Input Ch1 Remap
412 * @{
413 */
414 #define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
415 #define LL_LPTIM_LPTIM2_IC1_RMP_I3C1_IBIACK LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to I3C1 IBI ACK */
416 /**
417 * @}
418 */
419
420 /** @defgroup LPTIM_EC_LPTIM2_IC2_RMP LPTIM2 Input Ch2 Remap
421 * @{
422 */
423 #define LL_LPTIM_LPTIM2_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
424 #define LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024 LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to HSI/1024 */
425 #define LL_LPTIM_LPTIM2_IC2_RMP_MSI_128 LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to MSI/128 */
426 #define LL_LPTIM_LPTIM2_IC2_RMP_I3C2_IBIACK (LPTIM_CFGR2_IC2SEL_1 | LPTIM_CFGR2_IC2SEL_0) /*!< IC2 connected to I3C2 IBI ACK */
427 /**
428 * @}
429 */
430
431 /** @defgroup LPTIM_EC_LPTIM3_IC1_RMP LPTIM3 Input Ch1 Remap
432 * @{
433 */
434 #define LL_LPTIM_LPTIM3_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
435 #define LL_LPTIM_LPTIM3_IC1_RMP_I3C1_IBIACK LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to I3C1 IBI ACK */
436 /**
437 * @}
438 */
439
440 /** @defgroup LPTIM_EC_LPTIM3_IC2_RMP LPTIM3 Input Ch2 Remap
441 * @{
442 */
443
444 #define LL_LPTIM_LPTIM3_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
445 #define LL_LPTIM_LPTIM3_IC2_RMP_I3C2_IBIACK LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to I3C2 IBI ACK */
446 /**
447 * @}
448 */
449
450
451 /**
452 * @}
453 */
454
455 /* Exported macro ------------------------------------------------------------*/
456 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
457 * @{
458 */
459
460 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
461 * @{
462 */
463
464 /**
465 * @brief Write a value in LPTIM register
466 * @param __INSTANCE__ LPTIM Instance
467 * @param __REG__ Register to be written
468 * @param __VALUE__ Value to be written in the register
469 * @retval None
470 */
471 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
472
473 /**
474 * @brief Read a value in LPTIM register
475 * @param __INSTANCE__ LPTIM Instance
476 * @param __REG__ Register to be read
477 * @retval Register value
478 */
479 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
480
481 /**
482 * @brief LPTimer Input Capture Get Offset(in counter step unit)
483 * @note The real capture value corresponding to the input capture trigger can be calculated using
484 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
485 * The Offset value is depending on the glitch filter value for the channel
486 * and the value of the prescaler for the kernel clock.
487 * Please check Errata Sheet V1_8 for more details under "variable latency
488 * on input capture channel" section.
489 * @param __PSC__ This parameter can be one of the following values:
490 * @arg @ref LL_LPTIM_PRESCALER_DIV1
491 * @arg @ref LL_LPTIM_PRESCALER_DIV2
492 * @arg @ref LL_LPTIM_PRESCALER_DIV4
493 * @arg @ref LL_LPTIM_PRESCALER_DIV8
494 * @arg @ref LL_LPTIM_PRESCALER_DIV16
495 * @arg @ref LL_LPTIM_PRESCALER_DIV32
496 * @arg @ref LL_LPTIM_PRESCALER_DIV64
497 * @arg @ref LL_LPTIM_PRESCALER_DIV128
498 * @param __FLT__ This parameter can be one of the following values:
499 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
500 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
501 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
502 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
503 * @retval offset value
504 */
505 #define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\
506 [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\
507 [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]
508 /**
509 * @}
510 */
511
512 /**
513 * @}
514 */
515
516 /* Exported functions --------------------------------------------------------*/
517 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
518 * @{
519 */
520
521 /** Legacy definitions for compatibility purpose
522 @cond 0
523 */
524 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
525 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
526 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
527 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
528 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
529 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
530 /**
531 @endcond
532 */
533
534 #if defined(USE_FULL_LL_DRIVER)
535 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
536 * @{
537 */
538
539 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
540 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
541 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
542 /**
543 * @}
544 */
545 #endif /* USE_FULL_LL_DRIVER */
546
547 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
548 * @{
549 */
550
551 /**
552 * @brief Enable the LPTIM instance
553 * @note After setting the ENABLE bit, a delay of two counter clock is needed
554 * before the LPTIM instance is actually enabled.
555 * @rmtoll CR ENABLE LL_LPTIM_Enable
556 * @param LPTIMx Low-Power Timer instance
557 * @retval None
558 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)559 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
560 {
561 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
562 }
563
564 /**
565 * @brief Disable the LPTIM instance
566 * @rmtoll CR ENABLE LL_LPTIM_Disable
567 * @param LPTIMx Low-Power Timer instance
568 * @retval None
569 */
LL_LPTIM_Disable(LPTIM_TypeDef * LPTIMx)570 __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
571 {
572 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
573 }
574
575 /**
576 * @brief Indicates whether the LPTIM instance is enabled.
577 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
578 * @param LPTIMx Low-Power Timer instance
579 * @retval State of bit (1 or 0).
580 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)581 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
582 {
583 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
584 }
585
586 /**
587 * @brief Starts the LPTIM counter in the desired mode.
588 * @note LPTIM instance must be enabled before starting the counter.
589 * @note It is possible to change on the fly from One Shot mode to
590 * Continuous mode.
591 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
592 * CR SNGSTRT LL_LPTIM_StartCounter
593 * @param LPTIMx Low-Power Timer instance
594 * @param OperatingMode This parameter can be one of the following values:
595 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
596 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
597 * @retval None
598 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)599 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
600 {
601 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
602 }
603
604 /**
605 * @brief Enable reset after read.
606 * @note After calling this function any read access to LPTIM_CNT
607 * register will asynchronously reset the LPTIM_CNT register content.
608 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
609 * @param LPTIMx Low-Power Timer instance
610 * @retval None
611 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)612 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
613 {
614 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
615 }
616
617 /**
618 * @brief Disable reset after read.
619 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
620 * @param LPTIMx Low-Power Timer instance
621 * @retval None
622 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)623 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
624 {
625 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
626 }
627
628 /**
629 * @brief Indicate whether the reset after read feature is enabled.
630 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
631 * @param LPTIMx Low-Power Timer instance
632 * @retval State of bit (1 or 0).
633 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)634 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
635 {
636 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
637 }
638
639 /**
640 * @brief Reset of the LPTIM_CNT counter register (synchronous).
641 * @note Due to the synchronous nature of this reset, it only takes
642 * place after a synchronization delay of 3 LPTIM core clock cycles
643 * (LPTIM core clock may be different from APB clock).
644 * @note COUNTRST is automatically cleared by hardware
645 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
646 * @param LPTIMx Low-Power Timer instance
647 * @retval None
648 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)649 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
650 {
651 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
652 }
653
654 /**
655 * @brief Set the LPTIM registers update mode (enable/disable register preload)
656 * @note This function must be called when the LPTIM instance is disabled.
657 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
658 * @param LPTIMx Low-Power Timer instance
659 * @param UpdateMode This parameter can be one of the following values:
660 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
661 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
662 * @retval None
663 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)664 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
665 {
666 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
667 }
668
669 /**
670 * @brief Get the LPTIM registers update mode
671 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
672 * @param LPTIMx Low-Power Timer instance
673 * @retval Returned value can be one of the following values:
674 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
675 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
676 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)677 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
678 {
679 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
680 }
681
682 /**
683 * @brief Set the auto reload value
684 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
685 * @note After a write to the LPTIMx_ARR register a new write operation to the
686 * same register can only be performed when the previous write operation
687 * is completed. Any successive write before the ARROK flag is set, will
688 * lead to unpredictable results.
689 * @note autoreload value be strictly greater than the compare value.
690 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
691 * @param LPTIMx Low-Power Timer instance
692 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
693 * @retval None
694 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)695 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
696 {
697 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
698 }
699
700 /**
701 * @brief Get actual auto reload value
702 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
703 * @param LPTIMx Low-Power Timer instance
704 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
705 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)706 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
707 {
708 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
709 }
710
711 /**
712 * @brief Set the repetition value
713 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
714 * @rmtoll RCR REP LL_LPTIM_SetRepetition
715 * @param LPTIMx Low-Power Timer instance
716 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
717 * @retval None
718 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)719 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
720 {
721 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
722 }
723
724 /**
725 * @brief Get the repetition value
726 * @rmtoll RCR REP LL_LPTIM_GetRepetition
727 * @param LPTIMx Low-Power Timer instance
728 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
729 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)730 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
731 {
732 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
733 }
734
735 /**
736 * @brief Enable capture/compare channel.
737 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n
738 * CCMR1 CC2E LL_LPTIM_CC_EnableChannel
739 * @param LPTIMx LPTimer instance
740 * @param Channel This parameter can be one of the following values:
741 * @arg @ref LL_LPTIM_CHANNEL_CH1
742 * @arg @ref LL_LPTIM_CHANNEL_CH2
743 * @retval None
744 */
LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)745 __STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
746 {
747 SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
748 }
749
750 /**
751 * @brief Disable capture/compare channel.
752 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n
753 * CCMR1 CC2E LL_LPTIM_CC_DisableChannel
754 * @param LPTIMx LPTimer instance
755 * @param Channel This parameter can be one of the following values:
756 * @arg @ref LL_LPTIM_CHANNEL_CH1
757 * @arg @ref LL_LPTIM_CHANNEL_CH2
758 * @retval None
759 */
LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)760 __STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
761 {
762 CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
763 }
764
765 /**
766 * @brief Indicate whether channel is enabled.
767 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n
768 * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel
769 * @param LPTIMx LPTimer instance
770 * @param Channel This parameter can be one of the following values:
771 * @arg @ref LL_LPTIM_CHANNEL_CH1
772 * @arg @ref LL_LPTIM_CHANNEL_CH2
773 * @retval State of bit (1 or 0).
774 */
LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)775 __STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
776 {
777 return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \
778 (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
779
780 }
781
782 /**
783 * @brief Set the compare value
784 * @note After a write to the LPTIMx_CCR1 register a new write operation to the
785 * same register can only be performed when the previous write operation
786 * is completed. Any successive write before the CMP1OK flag is set, will
787 * lead to unpredictable results.
788 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1
789 * @param LPTIMx Low-Power Timer instance
790 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
791 * @retval None
792 */
LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)793 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
794 {
795 MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
796 }
797
798 /**
799 * @brief Get actual compare value
800 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1
801 * @param LPTIMx Low-Power Timer instance
802 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
803 */
LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef * LPTIMx)804 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx)
805 {
806 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
807 }
808
809 /**
810 * @brief Set the compare value
811 * @note After a write to the LPTIMx_CCR2 register a new write operation to the
812 * same register can only be performed when the previous write operation
813 * is completed. Any successive write before the CMP2OK flag is set, will
814 * lead to unpredictable results.
815 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2
816 * @param LPTIMx Low-Power Timer instance
817 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
818 * @retval None
819 */
LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)820 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
821 {
822 MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
823 }
824
825 /**
826 * @brief Get actual compare value
827 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2
828 * @param LPTIMx Low-Power Timer instance
829 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
830 */
LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef * LPTIMx)831 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx)
832 {
833 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
834 }
835
836 /**
837 * @brief Get actual counter value
838 * @note When the LPTIM instance is running with an asynchronous clock, reading
839 * the LPTIMx_CNT register may return unreliable values. So in this case
840 * it is necessary to perform two consecutive read accesses and verify
841 * that the two returned values are identical.
842 * @rmtoll CNT CNT LL_LPTIM_GetCounter
843 * @param LPTIMx Low-Power Timer instance
844 * @retval Counter value
845 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)846 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
847 {
848 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
849 }
850
851 /**
852 * @brief Set the counter mode (selection of the LPTIM counter clock source).
853 * @note The counter mode can be set only when the LPTIM instance is disabled.
854 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
855 * @param LPTIMx Low-Power Timer instance
856 * @param CounterMode This parameter can be one of the following values:
857 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
858 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
859 * @retval None
860 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)861 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
862 {
863 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
864 }
865
866 /**
867 * @brief Get the counter mode
868 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
869 * @param LPTIMx Low-Power Timer instance
870 * @retval Returned value can be one of the following values:
871 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
872 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
873 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)874 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
875 {
876 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
877 }
878
879 /**
880 * @brief Set waveform shape
881 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
882 * @param LPTIMx Low-Power Timer instance
883 * @param Waveform This parameter can be one of the following values:
884 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
885 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
886 * @retval None
887 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)888 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
889 {
890 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
891 }
892
893 /**
894 * @brief Get actual waveform shape
895 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
896 * @param LPTIMx Low-Power Timer instance
897 * @retval Returned value can be one of the following values:
898 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
899 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
900 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)901 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
902 {
903 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
904 }
905
906 /**
907 * @brief Set the polarity of an output channel.
908 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n
909 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n
910 * @param LPTIMx Low-Power Timer instance
911 * @param Channel This parameter can be one of the following values:
912 * @arg @ref LL_LPTIM_CHANNEL_CH1
913 * @arg @ref LL_LPTIM_CHANNEL_CH2
914 * @param Polarity This parameter can be one of the following values:
915 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
916 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
917 * @retval None
918 */
LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)919 __STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
920 {
921 if ((LPTIMx == LPTIM4) || (LPTIMx == LPTIM5))
922 {
923 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, ((Polarity >> LPTIM_CCMR1_CC1P_Pos) << LPTIM_CFGR_WAVPOL_Pos));
924 }
925 else
926 {
927 MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
928 (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
929 }
930 }
931
932 /**
933 * @brief Get the polarity of an output channel.
934 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n
935 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n
936 * @param LPTIMx Low-Power Timer instance
937 * @param Channel This parameter can be one of the following values:
938 * @arg @ref LL_LPTIM_CHANNEL_CH1
939 * @arg @ref LL_LPTIM_CHANNEL_CH2
940 * @retval Returned value can be one of the following values:
941 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
942 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
943 */
LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)944 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
945 {
946 if ((LPTIMx == LPTIM4) || (LPTIMx == LPTIM5))
947 {
948 return (uint32_t)((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL) >> LPTIM_CFGR_WAVPOL_Pos) << LPTIM_CCMR1_CC1P_Pos);
949 }
950 else
951 {
952 return (uint32_t)(READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]) >> \
953 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
954 }
955 }
956
957 /**
958 * @brief Set actual prescaler division ratio.
959 * @note This function must be called when the LPTIM instance is disabled.
960 * @note When the LPTIM is configured to be clocked by an internal clock source
961 * and the LPTIM counter is configured to be updated by active edges
962 * detected on the LPTIM external Input1, the internal clock provided to
963 * the LPTIM must be not be prescaled.
964 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
965 * @param LPTIMx Low-Power Timer instance
966 * @param Prescaler This parameter can be one of the following values:
967 * @arg @ref LL_LPTIM_PRESCALER_DIV1
968 * @arg @ref LL_LPTIM_PRESCALER_DIV2
969 * @arg @ref LL_LPTIM_PRESCALER_DIV4
970 * @arg @ref LL_LPTIM_PRESCALER_DIV8
971 * @arg @ref LL_LPTIM_PRESCALER_DIV16
972 * @arg @ref LL_LPTIM_PRESCALER_DIV32
973 * @arg @ref LL_LPTIM_PRESCALER_DIV64
974 * @arg @ref LL_LPTIM_PRESCALER_DIV128
975 * @retval None
976 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)977 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
978 {
979 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
980 }
981
982 /**
983 * @brief Get actual prescaler division ratio.
984 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
985 * @param LPTIMx Low-Power Timer instance
986 * @retval Returned value can be one of the following values:
987 * @arg @ref LL_LPTIM_PRESCALER_DIV1
988 * @arg @ref LL_LPTIM_PRESCALER_DIV2
989 * @arg @ref LL_LPTIM_PRESCALER_DIV4
990 * @arg @ref LL_LPTIM_PRESCALER_DIV8
991 * @arg @ref LL_LPTIM_PRESCALER_DIV16
992 * @arg @ref LL_LPTIM_PRESCALER_DIV32
993 * @arg @ref LL_LPTIM_PRESCALER_DIV64
994 * @arg @ref LL_LPTIM_PRESCALER_DIV128
995 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)996 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
997 {
998 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
999 }
1000
1001 /**
1002 * @brief Set LPTIM input 1 source (default GPIO).
1003 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
1004 * @param LPTIMx Low-Power Timer instance
1005 * @param Src This parameter can be one of the following values:
1006 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
1007 * @retval None
1008 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1009 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1010 {
1011 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
1012 }
1013
1014 /**
1015 * @brief Set LPTIM input 2 source (default GPIO).
1016 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
1017 * @param LPTIMx Low-Power Timer instance
1018 * @param Src This parameter can be one of the following values:
1019 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
1020 * @retval None
1021 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1022 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1023 {
1024 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
1025 }
1026
1027 /**
1028 * @brief Set LPTIM input source (default GPIO).
1029 * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap
1030 * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap
1031 * @param LPTIMx Low-Power Timer instance
1032 * @param Src This parameter can be one of the following values:
1033 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
1034 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
1035 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI
1036 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE
1037 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
1038 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_I3C1_IBIACK
1039 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
1040 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024
1041 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSI_128
1042 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_I3C2_IBIACK
1043 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO
1044 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_I3C1_IBIACK
1045 * @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_GPIO
1046 * @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_I3C2_IBIACK
1047 * @retval None
1048 */
LL_LPTIM_SetRemap(LPTIM_TypeDef * LPTIMx,uint32_t Src)1049 __STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1050 {
1051 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src);
1052 }
1053
1054 /**
1055 * @brief Set the polarity of IC channel 1.
1056 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n
1057 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n
1058 * @param LPTIMx Low-Power Timer instance
1059 * @param Channel This parameter can be one of the following values:
1060 * @arg @ref LL_LPTIM_CHANNEL_CH1
1061 * @arg @ref LL_LPTIM_CHANNEL_CH2
1062 * @param Polarity This parameter can be one of the following values:
1063 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1064 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1065 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1066 * @retval None
1067 */
LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)1068 __STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
1069 {
1070 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel],
1071 Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1072 }
1073
1074 /**
1075 * @brief Get the polarity of IC channels.
1076 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n
1077 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n
1078 * @param LPTIMx Low-Power Timer instance
1079 * @param Channel This parameter can be one of the following values:
1080 * @arg @ref LL_LPTIM_CHANNEL_CH1
1081 * @arg @ref LL_LPTIM_CHANNEL_CH2
1082 * @retval Returned value can be one of the following values:
1083 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1084 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1085 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1086 */
LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1087 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1088 {
1089 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \
1090 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1091
1092 }
1093
1094 /**
1095 * @brief Set the filter of IC channels.
1096 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n
1097 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n
1098 * @param LPTIMx Low-Power Timer instance
1099 * @param Channel This parameter can be one of the following values:
1100 * @arg @ref LL_LPTIM_CHANNEL_CH1
1101 * @arg @ref LL_LPTIM_CHANNEL_CH2
1102 * @param Filter This parameter can be one of the following values:
1103 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1104 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1105 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1106 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1107 * @retval None
1108 */
LL_LPTIM_IC_SetFilter(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Filter)1109 __STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
1110 {
1111 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel],
1112 Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1113 }
1114
1115 /**
1116 * @brief Get the filter of IC channels.
1117 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n
1118 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n
1119 * @param LPTIMx Low-Power Timer instance
1120 * @param Channel This parameter can be one of the following values:
1121 * @arg @ref LL_LPTIM_CHANNEL_CH1
1122 * @arg @ref LL_LPTIM_CHANNEL_CH2
1123 * @retval Returned value can be one of the following values:
1124 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1125 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1126 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1127 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1128 */
LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1129 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1130 {
1131 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \
1132 LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1133 }
1134
1135 /**
1136 * @brief Set the prescaler of IC channels.
1137 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n
1138 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n
1139 * @param LPTIMx Low-Power Timer instance
1140 * @param Channel This parameter can be one of the following values:
1141 * @arg @ref LL_LPTIM_CHANNEL_CH1
1142 * @arg @ref LL_LPTIM_CHANNEL_CH2
1143 * @param Prescaler This parameter can be one of the following values:
1144 * @arg @ref LL_LPTIM_ICPSC_DIV1
1145 * @arg @ref LL_LPTIM_ICPSC_DIV2
1146 * @arg @ref LL_LPTIM_ICPSC_DIV4
1147 * @arg @ref LL_LPTIM_ICPSC_DIV8
1148 * @retval None
1149 */
LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Prescaler)1150 __STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
1151 {
1152 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
1153 Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1154 }
1155
1156 /**
1157 * @brief Get the prescaler of IC channels.
1158 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n
1159 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n
1160 * @param LPTIMx Low-Power Timer instance
1161 * @param Channel This parameter can be one of the following values:
1162 * @arg @ref LL_LPTIM_CHANNEL_CH1
1163 * @arg @ref LL_LPTIM_CHANNEL_CH2
1164 * @retval Returned value can be one of the following values:
1165 * @arg @ref LL_LPTIM_ICPSC_DIV1
1166 * @arg @ref LL_LPTIM_ICPSC_DIV2
1167 * @arg @ref LL_LPTIM_ICPSC_DIV4
1168 * @arg @ref LL_LPTIM_ICPSC_DIV8
1169 */
LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1170 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1171 {
1172 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \
1173 LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1174 }
1175
1176 /**
1177 * @brief Set the Channel Mode.
1178 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n
1179 * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode
1180 * @param LPTIMx Low-Power Timer instance
1181 * @param Channel This parameter can be one of the following values:
1182 * @arg @ref LL_LPTIM_CHANNEL_CH1
1183 * @arg @ref LL_LPTIM_CHANNEL_CH2
1184 * @param CCMode This parameter can be one of the following values:
1185 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1186 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1187 * @retval None
1188 */
LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t CCMode)1189 __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
1190 {
1191 SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1192 }
1193
1194 /**
1195 * @brief Get the Channel Mode.
1196 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n
1197 * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode
1198 * @param LPTIMx Low-Power Timer instance
1199 * @param Channel This parameter can be one of the following values:
1200 * @arg @ref LL_LPTIM_CHANNEL_CH1
1201 * @arg @ref LL_LPTIM_CHANNEL_CH2
1202 * @retval Returned value can be one of the following values:
1203 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1204 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1205 */
LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1206 __STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1207 {
1208 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \
1209 LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1210 }
1211
1212 /**
1213 * @brief Get captured value for input channel 1.
1214 * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1
1215 * @note The real capture value corresponding to the input capture trigger can be calculated using
1216 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1217 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1218 * @param LPTIMx Low-Power Timer instance
1219 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1220 */
LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef * LPTIMx)1221 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx)
1222 {
1223 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
1224 }
1225
1226 /**
1227 * @brief Get captured value for input channel 2.
1228 * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2
1229 * @note The real capture value corresponding to the input capture trigger can be calculated using
1230 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1231 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1232 * @param LPTIMx Low-Power Timer instance
1233 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1234 */
LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef * LPTIMx)1235 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx)
1236 {
1237 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
1238 }
1239
1240 /**
1241 * @}
1242 */
1243
1244 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
1245 * @{
1246 */
1247
1248 /**
1249 * @brief Enable the timeout function
1250 * @note This function must be called when the LPTIM instance is disabled.
1251 * @note The first trigger event will start the timer, any successive trigger
1252 * event will reset the counter and the timer will restart.
1253 * @note The timeout value corresponds to the compare value; if no trigger
1254 * occurs within the expected time frame, the MCU is waked-up by the
1255 * compare match event.
1256 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
1257 * @param LPTIMx Low-Power Timer instance
1258 * @retval None
1259 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)1260 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
1261 {
1262 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1263 }
1264
1265 /**
1266 * @brief Disable the timeout function
1267 * @note This function must be called when the LPTIM instance is disabled.
1268 * @note A trigger event arriving when the timer is already started will be
1269 * ignored.
1270 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
1271 * @param LPTIMx Low-Power Timer instance
1272 * @retval None
1273 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)1274 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
1275 {
1276 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1277 }
1278
1279 /**
1280 * @brief Indicate whether the timeout function is enabled.
1281 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
1282 * @param LPTIMx Low-Power Timer instance
1283 * @retval State of bit (1 or 0).
1284 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)1285 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
1286 {
1287 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
1288 }
1289
1290 /**
1291 * @brief Start the LPTIM counter
1292 * @note This function must be called when the LPTIM instance is disabled.
1293 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
1294 * @param LPTIMx Low-Power Timer instance
1295 * @retval None
1296 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)1297 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
1298 {
1299 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
1300 }
1301
1302 /**
1303 * @brief Configure the external trigger used as a trigger event for the LPTIM.
1304 * @note This function must be called when the LPTIM instance is disabled.
1305 * @note An internal clock source must be present when a digital filter is
1306 * required for the trigger.
1307 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
1308 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
1309 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
1310 * @param LPTIMx Low-Power Timer instance
1311 * @param Source This parameter can be one of the following values:
1312 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1313 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1314 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1315 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1316 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1317 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
1318 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A
1319 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B
1320 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2_CH1
1321 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3_CH1
1322 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4_OUT
1323 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5_OUT
1324 * @param Filter This parameter can be one of the following values:
1325 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1326 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1327 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1328 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1329 * @param Polarity This parameter can be one of the following values:
1330 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1331 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1332 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1333 * @retval None
1334 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)1335 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
1336 {
1337 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
1338 }
1339
1340 /**
1341 * @brief Get actual external trigger source.
1342 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
1343 * @param LPTIMx Low-Power Timer instance
1344 * @retval Returned value can be one of the following values:
1345 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1346 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1347 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1348 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1349 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1350 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
1351 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A
1352 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B
1353 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2_CH1
1354 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3_CH1
1355 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4_OUT
1356 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5_OUT
1357 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)1358 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
1359 {
1360 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
1361 }
1362
1363 /**
1364 * @brief Get actual external trigger filter.
1365 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
1366 * @param LPTIMx Low-Power Timer instance
1367 * @retval Returned value can be one of the following values:
1368 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1369 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1370 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1371 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1372 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)1373 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
1374 {
1375 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
1376 }
1377
1378 /**
1379 * @brief Get actual external trigger polarity.
1380 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
1381 * @param LPTIMx Low-Power Timer instance
1382 * @retval Returned value can be one of the following values:
1383 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1384 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1385 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1386 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)1387 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
1388 {
1389 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
1390 }
1391
1392 /**
1393 * @}
1394 */
1395
1396 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
1397 * @{
1398 */
1399
1400 /**
1401 * @brief Set the source of the clock used by the LPTIM instance.
1402 * @note This function must be called when the LPTIM instance is disabled.
1403 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
1404 * @param LPTIMx Low-Power Timer instance
1405 * @param ClockSource This parameter can be one of the following values:
1406 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1407 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1408 * @retval None
1409 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)1410 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
1411 {
1412 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
1413 }
1414
1415 /**
1416 * @brief Get actual LPTIM instance clock source.
1417 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
1418 * @param LPTIMx Low-Power Timer instance
1419 * @retval Returned value can be one of the following values:
1420 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1421 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1422 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)1423 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
1424 {
1425 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
1426 }
1427
1428 /**
1429 * @brief Configure the active edge or edges used by the counter when
1430 the LPTIM is clocked by an external clock source.
1431 * @note This function must be called when the LPTIM instance is disabled.
1432 * @note When both external clock signal edges are considered active ones,
1433 * the LPTIM must also be clocked by an internal clock source with a
1434 * frequency equal to at least four times the external clock frequency.
1435 * @note An internal clock source must be present when a digital filter is
1436 * required for external clock.
1437 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
1438 * CFGR CKPOL LL_LPTIM_ConfigClock
1439 * @param LPTIMx Low-Power Timer instance
1440 * @param ClockFilter This parameter can be one of the following values:
1441 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1442 * @arg @ref LL_LPTIM_CLK_FILTER_2
1443 * @arg @ref LL_LPTIM_CLK_FILTER_4
1444 * @arg @ref LL_LPTIM_CLK_FILTER_8
1445 * @param ClockPolarity This parameter can be one of the following values:
1446 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1447 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1448 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1449 * @retval None
1450 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)1451 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
1452 {
1453 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
1454 }
1455
1456 /**
1457 * @brief Get actual clock polarity
1458 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
1459 * @param LPTIMx Low-Power Timer instance
1460 * @retval Returned value can be one of the following values:
1461 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1462 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1463 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1464 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)1465 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
1466 {
1467 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1468 }
1469
1470 /**
1471 * @brief Get actual clock digital filter
1472 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
1473 * @param LPTIMx Low-Power Timer instance
1474 * @retval Returned value can be one of the following values:
1475 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1476 * @arg @ref LL_LPTIM_CLK_FILTER_2
1477 * @arg @ref LL_LPTIM_CLK_FILTER_4
1478 * @arg @ref LL_LPTIM_CLK_FILTER_8
1479 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1480 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1481 {
1482 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1483 }
1484
1485 /**
1486 * @}
1487 */
1488
1489 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1490 * @{
1491 */
1492
1493 /**
1494 * @brief Configure the encoder mode.
1495 * @note This function must be called when the LPTIM instance is disabled.
1496 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1497 * @param LPTIMx Low-Power Timer instance
1498 * @param EncoderMode This parameter can be one of the following values:
1499 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1500 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1501 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1502 * @retval None
1503 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1504 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1505 {
1506 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1507 }
1508
1509 /**
1510 * @brief Get actual encoder mode.
1511 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1512 * @param LPTIMx Low-Power Timer instance
1513 * @retval Returned value can be one of the following values:
1514 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1515 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1516 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1517 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1518 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1519 {
1520 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1521 }
1522
1523 /**
1524 * @brief Enable the encoder mode
1525 * @note This function must be called when the LPTIM instance is disabled.
1526 * @note In this mode the LPTIM instance must be clocked by an internal clock
1527 * source. Also, the prescaler division ratio must be equal to 1.
1528 * @note LPTIM instance must be configured in continuous mode prior enabling
1529 * the encoder mode.
1530 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1531 * @param LPTIMx Low-Power Timer instance
1532 * @retval None
1533 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1534 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1535 {
1536 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1537 }
1538
1539 /**
1540 * @brief Disable the encoder mode
1541 * @note This function must be called when the LPTIM instance is disabled.
1542 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1543 * @param LPTIMx Low-Power Timer instance
1544 * @retval None
1545 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1546 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1547 {
1548 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1549 }
1550
1551 /**
1552 * @brief Indicates whether the LPTIM operates in encoder mode.
1553 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1554 * @param LPTIMx Low-Power Timer instance
1555 * @retval State of bit (1 or 0).
1556 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1557 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1558 {
1559 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1560 }
1561
1562 /**
1563 * @}
1564 */
1565
1566 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1567 * @{
1568 */
1569
1570 /**
1571 * @brief Clear the compare match flag for channel 1 (CC1CF)
1572 * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1
1573 * @param LPTIMx Low-Power Timer instance
1574 * @retval None
1575 */
LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef * LPTIMx)1576 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx)
1577 {
1578 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
1579 }
1580
1581 /**
1582 * @brief Inform application whether a capture/compare interrupt has occurred for channel 1.
1583 * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1
1584 * @param LPTIMx Low-Power Timer instance
1585 * @retval State of bit (1 or 0).
1586 */
LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef * LPTIMx)1587 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx)
1588 {
1589 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
1590 }
1591
1592 /**
1593 * @brief Clear the compare match flag for channel 2 (CC2CF)
1594 * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2
1595 * @param LPTIMx Low-Power Timer instance
1596 * @retval None
1597 */
LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef * LPTIMx)1598 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx)
1599 {
1600 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
1601 }
1602
1603 /**
1604 * @brief Inform application whether a capture/compare interrupt has occurred for channel 2.
1605 * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2
1606 * @param LPTIMx Low-Power Timer instance
1607 * @retval State of bit (1 or 0).
1608 */
LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef * LPTIMx)1609 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx)
1610 {
1611 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
1612 }
1613
1614 /**
1615 * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
1616 * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O
1617 * @param LPTIMx Low-Power Timer instance
1618 * @retval None
1619 */
LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef * LPTIMx)1620 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx)
1621 {
1622 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
1623 }
1624
1625 /**
1626 * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1.
1627 * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O
1628 * @param LPTIMx Low-Power Timer instance
1629 * @retval State of bit (1 or 0).
1630 */
LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef * LPTIMx)1631 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx)
1632 {
1633 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
1634 }
1635
1636 /**
1637 * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
1638 * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O
1639 * @param LPTIMx Low-Power Timer instance
1640 * @retval None
1641 */
LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef * LPTIMx)1642 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx)
1643 {
1644 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
1645 }
1646
1647 /**
1648 * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2.
1649 * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O
1650 * @param LPTIMx Low-Power Timer instance
1651 * @retval State of bit (1 or 0).
1652 */
LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef * LPTIMx)1653 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx)
1654 {
1655 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
1656 }
1657 /**
1658 * @brief Clear the autoreload match flag (ARRMCF)
1659 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1660 * @param LPTIMx Low-Power Timer instance
1661 * @retval None
1662 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1663 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1664 {
1665 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1666 }
1667
1668 /**
1669 * @brief Inform application whether a autoreload match interrupt has occurred.
1670 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1671 * @param LPTIMx Low-Power Timer instance
1672 * @retval State of bit (1 or 0).
1673 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1674 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1675 {
1676 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1677 }
1678
1679 /**
1680 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1681 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1682 * @param LPTIMx Low-Power Timer instance
1683 * @retval None
1684 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1685 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1686 {
1687 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1688 }
1689
1690 /**
1691 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1692 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1693 * @param LPTIMx Low-Power Timer instance
1694 * @retval State of bit (1 or 0).
1695 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1696 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1697 {
1698 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1699 }
1700
1701 /**
1702 * @brief Clear the compare register update interrupt flag (CMP1OKCF).
1703 * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK
1704 * @param LPTIMx Low-Power Timer instance
1705 * @retval None
1706 */
LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef * LPTIMx)1707 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
1708 {
1709 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
1710 }
1711
1712 /**
1713 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
1714 completed. If so, a new one can be initiated.
1715 * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK
1716 * @param LPTIMx Low-Power Timer instance
1717 * @retval State of bit (1 or 0).
1718 */
LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef * LPTIMx)1719 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx)
1720 {
1721 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
1722 }
1723
1724 /**
1725 * @brief Clear the compare register update interrupt flag (CMP2OKCF).
1726 * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK
1727 * @param LPTIMx Low-Power Timer instance
1728 * @retval None
1729 */
LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef * LPTIMx)1730 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
1731 {
1732 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
1733 }
1734
1735 /**
1736 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
1737 completed. If so, a new one can be initiated.
1738 * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK
1739 * @param LPTIMx Low-Power Timer instance
1740 * @retval State of bit (1 or 0).
1741 */
LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef * LPTIMx)1742 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx)
1743 {
1744 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
1745 }
1746
1747 /**
1748 * @brief Clear the interrupt register update interrupt flag (DIEROKCF).
1749 * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK
1750 * @param LPTIMx Low-Power Timer instance
1751 * @retval None
1752 */
LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef * LPTIMx)1753 __STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
1754 {
1755 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
1756 }
1757
1758 /**
1759 * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
1760 completed. If so, a new one can be initiated.
1761 * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK
1762 * @param LPTIMx Low-Power Timer instance
1763 * @retval State of bit (1 or 0).
1764 */
LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef * LPTIMx)1765 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx)
1766 {
1767 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
1768 }
1769
1770 /**
1771 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1772 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1773 * @param LPTIMx Low-Power Timer instance
1774 * @retval None
1775 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1776 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1777 {
1778 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1779 }
1780
1781 /**
1782 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1783 completed. If so, a new one can be initiated.
1784 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1785 * @param LPTIMx Low-Power Timer instance
1786 * @retval State of bit (1 or 0).
1787 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1788 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1789 {
1790 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1791 }
1792
1793 /**
1794 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1795 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1796 * @param LPTIMx Low-Power Timer instance
1797 * @retval None
1798 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1799 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1800 {
1801 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1802 }
1803
1804 /**
1805 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1806 operates in encoder mode).
1807 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1808 * @param LPTIMx Low-Power Timer instance
1809 * @retval State of bit (1 or 0).
1810 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1811 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1812 {
1813 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1814 }
1815
1816 /**
1817 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1818 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1819 * @param LPTIMx Low-Power Timer instance
1820 * @retval None
1821 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1822 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1823 {
1824 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1825 }
1826
1827 /**
1828 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1829 operates in encoder mode).
1830 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1831 * @param LPTIMx Low-Power Timer instance
1832 * @retval State of bit (1 or 0).
1833 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1834 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1835 {
1836 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1837 }
1838
1839 /**
1840 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1841 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1842 * @param LPTIMx Low-Power Timer instance
1843 * @retval None
1844 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1845 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1846 {
1847 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1848 }
1849
1850 /**
1851 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
1852 completed; If so, a new one can be initiated.
1853 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1854 * @param LPTIMx Low-Power Timer instance
1855 * @retval State of bit (1 or 0).
1856 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)1857 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
1858 {
1859 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1860 }
1861
1862 /**
1863 * @brief Clear the update event flag (UECF).
1864 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1865 * @param LPTIMx Low-Power Timer instance
1866 * @retval None
1867 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1868 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1869 {
1870 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1871 }
1872
1873 /**
1874 * @brief Informs application whether the LPTIMx update event has occurred.
1875 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1876 * @param LPTIMx Low-Power Timer instance
1877 * @retval State of bit (1 or 0).
1878 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)1879 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
1880 {
1881 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1882 }
1883
1884 /**
1885 * @}
1886 */
1887
1888 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1889 * @{
1890 */
1891 /**
1892 * @brief Enable capture/compare 1 interrupt (CC1IE).
1893 * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1
1894 * @param LPTIMx Low-Power Timer instance
1895 * @retval None
1896 */
LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef * LPTIMx)1897 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
1898 {
1899 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1900 }
1901
1902 /**
1903 * @brief Disable capture/compare 1 interrupt (CC1IE).
1904 * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1
1905 * @param LPTIMx Low-Power Timer instance
1906 * @retval None
1907 */
LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef * LPTIMx)1908 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
1909 {
1910 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1911 }
1912
1913 /**
1914 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
1915 * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1
1916 * @param LPTIMx Low-Power Timer instance
1917 * @retval State of bit (1 or 0).
1918 */
LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef * LPTIMx)1919 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx)
1920 {
1921 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
1922 }
1923
1924 /**
1925 * @brief Enable capture/compare 1 interrupt (CC2IE).
1926 * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2
1927 * @param LPTIMx Low-Power Timer instance
1928 * @retval None
1929 */
LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef * LPTIMx)1930 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
1931 {
1932 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1933 }
1934
1935 /**
1936 * @brief Disable capture/compare 2 interrupt (CC2IE).
1937 * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2
1938 * @param LPTIMx Low-Power Timer instance
1939 * @retval None
1940 */
LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef * LPTIMx)1941 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
1942 {
1943 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1944 }
1945
1946 /**
1947 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
1948 * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2
1949 * @param LPTIMx Low-Power Timer instance
1950 * @retval State of bit (1 or 0).
1951 */
LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef * LPTIMx)1952 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx)
1953 {
1954 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
1955 }
1956
1957 /**
1958 * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE).
1959 * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O
1960 * @param LPTIMx Low-Power Timer instance
1961 * @retval None
1962 */
LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef * LPTIMx)1963 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
1964 {
1965 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
1966 }
1967
1968 /**
1969 * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE).
1970 * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O
1971 * @param LPTIMx Low-Power Timer instance
1972 * @retval None
1973 */
LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef * LPTIMx)1974 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
1975 {
1976 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
1977 }
1978
1979 /**
1980 * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled.
1981 * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O
1982 * @param LPTIMx Low-Power Timer instance
1983 * @retval State of bit (1 or 0).
1984 */
LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef * LPTIMx)1985 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx)
1986 {
1987 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
1988 }
1989
1990 /**
1991 * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE).
1992 * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O
1993 * @param LPTIMx Low-Power Timer instance
1994 * @retval None
1995 */
LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef * LPTIMx)1996 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
1997 {
1998 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
1999 }
2000
2001 /**
2002 * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE).
2003 * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O
2004 * @param LPTIMx Low-Power Timer instance
2005 * @retval None
2006 */
LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef * LPTIMx)2007 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2008 {
2009 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2010 }
2011
2012 /**
2013 * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled.
2014 * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O
2015 * @param LPTIMx Low-Power Timer instance
2016 * @retval State of bit (1 or 0).
2017 */
LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef * LPTIMx)2018 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx)
2019 {
2020 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
2021 }
2022
2023 /**
2024 * @brief Enable autoreload match interrupt (ARRMIE).
2025 * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM
2026 * @param LPTIMx Low-Power Timer instance
2027 * @retval None
2028 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)2029 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2030 {
2031 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2032 }
2033
2034 /**
2035 * @brief Disable autoreload match interrupt (ARRMIE).
2036 * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM
2037 * @param LPTIMx Low-Power Timer instance
2038 * @retval None
2039 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)2040 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2041 {
2042 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2043 }
2044
2045 /**
2046 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
2047 * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
2048 * @param LPTIMx Low-Power Timer instance
2049 * @retval State of bit (1 or 0).
2050 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)2051 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
2052 {
2053 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
2054 }
2055
2056 /**
2057 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
2058 * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
2059 * @param LPTIMx Low-Power Timer instance
2060 * @retval None
2061 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2062 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2063 {
2064 SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2065 }
2066
2067 /**
2068 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
2069 * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
2070 * @param LPTIMx Low-Power Timer instance
2071 * @retval None
2072 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2073 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2074 {
2075 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2076 }
2077
2078 /**
2079 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
2080 * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
2081 * @param LPTIMx Low-Power Timer instance
2082 * @retval State of bit (1 or 0).
2083 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)2084 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
2085 {
2086 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
2087 }
2088
2089 /**
2090 * @brief Enable compare register write completed interrupt (CMP1OKIE).
2091 * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK
2092 * @param LPTIMx Low-Power Timer instance
2093 * @retval None
2094 */
LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2095 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2096 {
2097 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2098 }
2099
2100 /**
2101 * @brief Disable compare register write completed interrupt (CMP1OKIE).
2102 * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK
2103 * @param LPTIMx Low-Power Timer instance
2104 * @retval None
2105 */
LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2106 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2107 {
2108 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2109 }
2110
2111 /**
2112 * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
2113 * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK
2114 * @param LPTIMx Low-Power Timer instance
2115 * @retval State of bit (1 or 0).
2116 */
LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef * LPTIMx)2117 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx)
2118 {
2119 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
2120 }
2121
2122 /**
2123 * @brief Enable compare register write completed interrupt (CMP2OKIE).
2124 * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK
2125 * @param LPTIMx Low-Power Timer instance
2126 * @retval None
2127 */
LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2128 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2129 {
2130 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2131 }
2132
2133 /**
2134 * @brief Disable compare register write completed interrupt (CMP2OKIE).
2135 * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK
2136 * @param LPTIMx Low-Power Timer instance
2137 * @retval None
2138 */
LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2139 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2140 {
2141 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2142 }
2143
2144 /**
2145 * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
2146 * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK
2147 * @param LPTIMx Low-Power Timer instance
2148 * @retval State of bit (1 or 0).
2149 */
LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef * LPTIMx)2150 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx)
2151 {
2152 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
2153 }
2154
2155 /**
2156 * @brief Enable autoreload register write completed interrupt (ARROKIE).
2157 * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK
2158 * @param LPTIMx Low-Power Timer instance
2159 * @retval None
2160 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)2161 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2162 {
2163 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2164 }
2165
2166 /**
2167 * @brief Disable autoreload register write completed interrupt (ARROKIE).
2168 * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK
2169 * @param LPTIMx Low-Power Timer instance
2170 * @retval None
2171 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)2172 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2173 {
2174 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2175 }
2176
2177 /**
2178 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
2179 * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
2180 * @param LPTIMx Low-Power Timer instance
2181 * @retval State of bit(1 or 0).
2182 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)2183 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
2184 {
2185 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
2186 }
2187
2188 /**
2189 * @brief Enable direction change to up interrupt (UPIE).
2190 * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP
2191 * @param LPTIMx Low-Power Timer instance
2192 * @retval None
2193 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)2194 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
2195 {
2196 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2197 }
2198
2199 /**
2200 * @brief Disable direction change to up interrupt (UPIE).
2201 * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP
2202 * @param LPTIMx Low-Power Timer instance
2203 * @retval None
2204 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)2205 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
2206 {
2207 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2208 }
2209
2210 /**
2211 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
2212 * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP
2213 * @param LPTIMx Low-Power Timer instance
2214 * @retval State of bit(1 or 0).
2215 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)2216 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
2217 {
2218 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
2219 }
2220
2221 /**
2222 * @brief Enable direction change to down interrupt (DOWNIE).
2223 * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN
2224 * @param LPTIMx Low-Power Timer instance
2225 * @retval None
2226 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)2227 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2228 {
2229 SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2230 }
2231
2232 /**
2233 * @brief Disable direction change to down interrupt (DOWNIE).
2234 * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN
2235 * @param LPTIMx Low-Power Timer instance
2236 * @retval None
2237 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)2238 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2239 {
2240 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2241 }
2242
2243 /**
2244 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
2245 * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
2246 * @param LPTIMx Low-Power Timer instance
2247 * @retval State of bit(1 or 0).
2248 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)2249 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
2250 {
2251 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
2252 }
2253
2254 /**
2255 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
2256 * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK
2257 * @param LPTIMx Low-Power Timer instance
2258 * @retval None
2259 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)2260 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2261 {
2262 SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2263 }
2264
2265 /**
2266 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
2267 * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK
2268 * @param LPTIMx Low-Power Timer instance
2269 * @retval None
2270 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)2271 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2272 {
2273 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2274 }
2275
2276 /**
2277 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
2278 * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
2279 * @param LPTIMx Low-Power Timer instance
2280 * @retval State of bit(1 or 0).
2281 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)2282 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
2283 {
2284 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
2285 }
2286
2287 /**
2288 * @brief Enable update event interrupt (UEIE).
2289 * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE
2290 * @param LPTIMx Low-Power Timer instance
2291 * @retval None
2292 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)2293 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
2294 {
2295 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2296 }
2297
2298 /**
2299 * @brief Disable update event interrupt (UEIE).
2300 * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE
2301 * @param LPTIMx Low-Power Timer instance
2302 * @retval None
2303 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)2304 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
2305 {
2306 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2307 }
2308
2309 /**
2310 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
2311 * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE
2312 * @param LPTIMx Low-Power Timer instance
2313 *@ retval State of bit(1 or 0).
2314 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)2315 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
2316 {
2317 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
2318 }
2319 /**
2320 * @}
2321 */
2322
2323
2324 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
2325 * @{
2326 */
2327 /**
2328 * @brief Enable update DMA request.
2329 * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE
2330 * @param LPTIMx Low-Power Timer instance
2331 * @retval None
2332 */
LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2333 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2334 {
2335 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2336 }
2337
2338 /**
2339 * @brief Disable update DMA request.
2340 * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE
2341 * @param LPTIMx Low-Power Timer instance
2342 * @retval None
2343 */
LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2344 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2345 {
2346 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2347 }
2348
2349 /**
2350 * @brief Indicates whether the update DMA request is enabled.
2351 * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE
2352 * @param LPTIMx Low-Power Timer instance
2353 * @retval State of bit (1 or 0).
2354 */
LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef * LPTIMx)2355 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx)
2356 {
2357 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
2358 }
2359
2360 /**
2361 * @brief Enable capture/compare 1 DMA request (CC1DE).
2362 * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1
2363 * @param LPTIMx Low-Power Timer instance
2364 * @retval None
2365 */
LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2366 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2367 {
2368 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2369 }
2370
2371 /**
2372 * @brief Disable capture/compare 1 DMA request (CC1DE).
2373 * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1
2374 * @param LPTIMx Low-Power Timer instance
2375 * @retval None
2376 */
LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2377 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2378 {
2379 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2380 }
2381
2382 /**
2383 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
2384 * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1
2385 * @param LPTIMx Low-Power Timer instance
2386 * @retval State of bit (1 or 0).
2387 */
LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef * LPTIMx)2388 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx)
2389 {
2390 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
2391 }
2392
2393 /**
2394 * @brief Enable capture/compare 2 DMA request (CC2DE).
2395 * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2
2396 * @param LPTIMx Low-Power Timer instance
2397 * @retval None
2398 */
LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2399 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2400 {
2401 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2402 }
2403
2404 /**
2405 * @brief Disable capture/compare 2 DMA request (CC2DE).
2406 * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2
2407 * @param LPTIMx Low-Power Timer instance
2408 * @retval None
2409 */
LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2410 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2411 {
2412 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2413 }
2414
2415 /**
2416 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
2417 * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2
2418 * @param LPTIMx Low-Power Timer instance
2419 * @retval State of bit (1 or 0).
2420 */
LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef * LPTIMx)2421 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx)
2422 {
2423 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
2424 }
2425
2426 /**
2427 * @}
2428 */
2429 /**
2430 * @}
2431 */
2432
2433 /**
2434 * @}
2435 */
2436
2437 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
2438
2439 /**
2440 * @}
2441 */
2442
2443 #ifdef __cplusplus
2444 }
2445 #endif
2446
2447 #endif /* STM32N6xx_LL_LPTIM_H */
2448
