1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_icache.h
4 * @author MCD Application Team
5 * @brief Header file of ICACHE LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion ------------------------------------*/
20 #ifndef STM32N6xx_LL_ICACHE_H
21 #define STM32N6xx_LL_ICACHE_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes -----------------------------------------------------------------*/
28 #include "stm32n6xx.h"
29
30 /** @addtogroup STM32N6xx_LL_Driver
31 * @{
32 */
33
34 #if defined(ICACHE)
35
36 /** @defgroup ICACHE_LL ICACHE
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45
46 /* Exported constants -------------------------------------------------------*/
47 /** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants
48 * @{
49 */
50
51 /** @defgroup ICACHE_LL_EC_WaysSelection Ways selection
52 * @{
53 */
54 #define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
55 #define LL_ICACHE_4WAYS ICACHE_CR_WAYSEL /*!< 4-ways set associative cache (default) */
56 /**
57 * @}
58 */
59
60 /** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type
61 * @{
62 */
63 #define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */
64 #define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */
65 #define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */
66 /**
67 * @}
68 */
69
70 /** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines
71 * @brief Flags defines which can be used with LL_ICACHE_ReadReg function
72 * @{
73 */
74 #define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */
75 #define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */
76 #define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */
77 /**
78 * @}
79 */
80
81 /** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
82 * @brief Flags defines which can be used with LL_ICACHE_WriteReg function
83 * @{
84 */
85 #define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */
86 #define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */
87 /**
88 * @}
89 */
90
91 /** @defgroup ICACHE_LL_EC_IT IT Defines
92 * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions
93 * @{
94 */
95 #define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
96 #define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */
97 /**
98 * @}
99 */
100
101
102 /**
103 * @}
104 */
105
106 /* Exported macros ----------------------------------------------------------*/
107 /** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros
108 * @{
109 */
110
111 /** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros
112 * @{
113 */
114
115 /**
116 * @brief Write a value in ICACHE register
117 * @param __REG__ Register to be written
118 * @param __VALUE__ Value to be written in the register
119 * @retval None
120 */
121 #define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__))
122
123 /**
124 * @brief Read a value in ICACHE register
125 * @param __REG__ Register to be read
126 * @retval Register value
127 */
128 #define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__)
129 /**
130 * @}
131 */
132
133 /**
134 * @}
135 */
136
137 /* Exported functions --------------------------------------------------------*/
138 /** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions
139 * @{
140 */
141
142 /** @defgroup ICACHE_LL_EF_Configuration Configuration
143 * @{
144 */
145
146 /**
147 * @brief Enable the ICACHE.
148 * @rmtoll CR EN LL_ICACHE_Enable
149 * @retval None
150 */
LL_ICACHE_Enable(void)151 __STATIC_INLINE void LL_ICACHE_Enable(void)
152 {
153 SET_BIT(ICACHE->CR, ICACHE_CR_EN);
154 }
155
156 /**
157 * @brief Disable the ICACHE.
158 * @rmtoll CR EN LL_ICACHE_Disable
159 * @retval None
160 */
LL_ICACHE_Disable(void)161 __STATIC_INLINE void LL_ICACHE_Disable(void)
162 {
163 CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
164 }
165
166 /**
167 * @brief Return if ICACHE is enabled or not.
168 * @rmtoll CR EN LL_ICACHE_IsEnabled
169 * @retval State of bit (1 or 0).
170 */
LL_ICACHE_IsEnabled(void)171 __STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void)
172 {
173 return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL);
174 }
175
176 /**
177 * @brief Select the ICACHE operating mode.
178 * @rmtoll CR WAYSEL LL_ICACHE_SetMode
179 * @param Mode This parameter can be one of the following values:
180 * @arg @ref LL_ICACHE_1WAY
181 * @arg @ref LL_ICACHE_4WAYS
182 * @retval None
183 */
LL_ICACHE_SetMode(uint32_t Mode)184 __STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode)
185 {
186 MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode);
187 }
188
189 /**
190 * @brief Get the selected ICACHE operating mode.
191 * @rmtoll CR WAYSEL LL_ICACHE_GetMode
192 * @retval Returned value can be one of the following values:
193 * @arg @ref LL_ICACHE_1WAY
194 * @arg @ref LL_ICACHE_4WAYS
195 */
LL_ICACHE_GetMode(void)196 __STATIC_INLINE uint32_t LL_ICACHE_GetMode(void)
197 {
198 return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL));
199 }
200
201 /**
202 * @brief Invalidate the ICACHE.
203 * @note Until the BSYEND flag is set, the cache is bypassed.
204 * @rmtoll CR CACHEINV LL_ICACHE_Invalidate
205 * @retval None
206 */
LL_ICACHE_Invalidate(void)207 __STATIC_INLINE void LL_ICACHE_Invalidate(void)
208 {
209 SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
210 }
211
212 /**
213 * @}
214 */
215
216 /** @defgroup ICACHE_LL_EF_Monitors Monitors
217 * @{
218 */
219
220 /**
221 * @brief Enable the hit/miss monitor(s).
222 * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors
223 * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors
224 * @param Monitors This parameter can be one or a combination of the following values:
225 * @arg @ref LL_ICACHE_MONITOR_HIT
226 * @arg @ref LL_ICACHE_MONITOR_MISS
227 * @arg @ref LL_ICACHE_MONITOR_ALL
228 * @retval None
229 */
LL_ICACHE_EnableMonitors(uint32_t Monitors)230 __STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors)
231 {
232 SET_BIT(ICACHE->CR, Monitors);
233 }
234
235 /**
236 * @brief Disable the hit/miss monitor(s).
237 * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors
238 * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors
239 * @param Monitors This parameter can be one or a combination of the following values:
240 * @arg @ref LL_ICACHE_MONITOR_HIT
241 * @arg @ref LL_ICACHE_MONITOR_MISS
242 * @arg @ref LL_ICACHE_MONITOR_ALL
243 * @retval None
244 */
LL_ICACHE_DisableMonitors(uint32_t Monitors)245 __STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors)
246 {
247 CLEAR_BIT(ICACHE->CR, Monitors);
248 }
249
250 /**
251 * @brief Check if the monitor(s) is(are) enabled or disabled.
252 * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors
253 * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors
254 * @param Monitors This parameter can be one or a combination of the following values:
255 * @arg @ref LL_ICACHE_MONITOR_HIT
256 * @arg @ref LL_ICACHE_MONITOR_MISS
257 * @arg @ref LL_ICACHE_MONITOR_ALL
258 * @retval State of parameter value (1 or 0).
259 */
LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)260 __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)
261 {
262 return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL);
263 }
264
265 /**
266 * @brief Reset the hit/miss monitor(s).
267 * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors
268 * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors
269 * @param Monitors This parameter can be one or a combination of the following values:
270 * @arg @ref LL_ICACHE_MONITOR_HIT
271 * @arg @ref LL_ICACHE_MONITOR_MISS
272 * @arg @ref LL_ICACHE_MONITOR_ALL
273 * @retval None
274 */
LL_ICACHE_ResetMonitors(uint32_t Monitors)275 __STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors)
276 {
277 /* Reset */
278 SET_BIT(ICACHE->CR, (Monitors << 2U));
279 /* Release reset */
280 CLEAR_BIT(ICACHE->CR, (Monitors << 2U));
281 }
282
283 /**
284 * @brief Get the Hit monitor.
285 * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap.
286 * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor
287 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
288 */
LL_ICACHE_GetHitMonitor(void)289 __STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void)
290 {
291 return (ICACHE->HMONR);
292 }
293
294 /**
295 * @brief Get the Miss monitor.
296 * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap.
297 * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor
298 * @retval Value between Min_Data=0 and Max_Data=0xFFFF
299 */
LL_ICACHE_GetMissMonitor(void)300 __STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void)
301 {
302 return (ICACHE->MMONR);
303 }
304
305 /**
306 * @}
307 */
308
309 /** @defgroup ICACHE_LL_EF_IT_Management IT_Management
310 * @{
311 */
312
313 /**
314 * @brief Enable BSYEND interrupt.
315 * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND
316 * @retval None
317 */
LL_ICACHE_EnableIT_BSYEND(void)318 __STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void)
319 {
320 SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
321 }
322
323 /**
324 * @brief Disable BSYEND interrupt.
325 * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND
326 * @retval None
327 */
LL_ICACHE_DisableIT_BSYEND(void)328 __STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void)
329 {
330 CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
331 }
332
333 /**
334 * @brief Check if the BSYEND Interrupt is enabled or disabled.
335 * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND
336 * @retval State of bit (1 or 0).
337 */
LL_ICACHE_IsEnabledIT_BSYEND(void)338 __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void)
339 {
340 return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL);
341 }
342
343 /**
344 * @brief Enable ERR interrupt.
345 * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR
346 * @retval None
347 */
LL_ICACHE_EnableIT_ERR(void)348 __STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void)
349 {
350 SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
351 }
352
353 /**
354 * @brief Disable ERR interrupt.
355 * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR
356 * @retval None
357 */
LL_ICACHE_DisableIT_ERR(void)358 __STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void)
359 {
360 CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
361 }
362
363 /**
364 * @brief Check if the ERR Interrupt is enabled or disabled.
365 * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR
366 * @retval State of bit (1 or 0).
367 */
LL_ICACHE_IsEnabledIT_ERR(void)368 __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void)
369 {
370 return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL);
371 }
372
373 /**
374 * @}
375 */
376
377 /** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management
378 * @{
379 */
380
381 /**
382 * @brief Indicate the status of an ongoing operation flag.
383 * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY
384 * @retval State of bit (1 or 0).
385 */
LL_ICACHE_IsActiveFlag_BUSY(void)386 __STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void)
387 {
388 return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL);
389 }
390
391 /**
392 * @brief Indicate the status of an operation end flag.
393 * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND
394 * @retval State of bit (1 or 0).
395 */
LL_ICACHE_IsActiveFlag_BSYEND(void)396 __STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void)
397 {
398 return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL);
399 }
400
401 /**
402 * @brief Indicate the status of an error flag.
403 * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR
404 * @retval State of bit (1 or 0).
405 */
LL_ICACHE_IsActiveFlag_ERR(void)406 __STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void)
407 {
408 return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL);
409 }
410
411 /**
412 * @brief Clear busy end of operation flag.
413 * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND
414 * @retval None
415 */
LL_ICACHE_ClearFlag_BSYEND(void)416 __STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void)
417 {
418 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
419 }
420
421 /**
422 * @brief Clear error flag.
423 * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR
424 * @retval None
425 */
LL_ICACHE_ClearFlag_ERR(void)426 __STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void)
427 {
428 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
429 }
430
431 /**
432 * @}
433 */
434
435 /**
436 * @}
437 */
438
439 /**
440 * @}
441 */
442
443 #endif /* ICACHE */
444
445 /**
446 * @}
447 */
448
449 #ifdef __cplusplus
450 }
451 #endif
452
453 #endif /* STM32N6xx_LL_ICACHE_H */
454
