1 /** 2 ********************************************************************************************************************** 3 * @file stm32n6xx_hal_i3c.h 4 * @author MCD Application Team 5 * @brief Header file of I3C HAL module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ********************************************************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 20 #ifndef STM32N6xx_HAL_I3C_H 21 #define STM32N6xx_HAL_I3C_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 28 /* Includes ----------------------------------------------------------------------------------------------------------*/ 29 #include "stm32n6xx_hal_def.h" 30 #include "stm32n6xx_ll_i3c.h" 31 32 /** @addtogroup STM32N6xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup I3C 37 * @{ 38 */ 39 40 /* Exported types ----------------------------------------------------------------------------------------------------*/ 41 /** @defgroup I3C_Exported_Types I3C Exported Types 42 * @{ 43 */ 44 /** @defgroup I3C_Init_Structure_definition I3C Init Structure definition 45 * @brief I3C Init Structure definition 46 * @{ 47 */ 48 typedef struct 49 { 50 LL_I3C_CtrlBusConfTypeDef CtrlBusCharacteristic; /*!< Specifies the I3C controller bus characteristic configuration 51 when Controller mode */ 52 53 LL_I3C_TgtBusConfTypeDef TgtBusCharacteristic; /*!< Specifies the I3C target bus characteristic configuration 54 when Target mode */ 55 56 } I3C_InitTypeDef; 57 /** 58 * @} 59 */ 60 61 /** @defgroup I3C_FIFO_Config_Structure_definition I3C FIFO Configuration Structure definition 62 * @brief I3C FIFO configuration structure definition 63 * @{ 64 */ 65 typedef struct 66 { 67 uint32_t RxFifoThreshold; /*!< Specifies the I3C Rx FIFO threshold level. 68 This parameter must be a value of @ref I3C_RX_FIFO_THRESHOLD */ 69 70 uint32_t TxFifoThreshold; /*!< Specifies the I3C Tx FIFO threshold level. 71 This parameter must be a value of @ref I3C_TX_FIFO_THRESHOLD */ 72 73 uint32_t ControlFifo; /*!< Specifies the I3C control FIFO enable/disable state. 74 This parameter is configured only with controller mode and it 75 must be a value of @ref I3C_CONTROL_FIFO_STATE */ 76 77 uint32_t StatusFifo; /*!< Specifies the I3C status FIFO enable/disable state. 78 This parameter is configured only with controller mode and it 79 must be a value of @ref I3C_STATUS_FIFO_STATE */ 80 } I3C_FifoConfTypeDef; 81 /** 82 * @} 83 */ 84 85 /** @defgroup I3C_Controller_Config_Structure_definition I3C Controller Configuration Structure definition 86 * @brief I3C controller configuration structure definition 87 * @{ 88 */ 89 typedef struct 90 { 91 uint8_t DynamicAddr; /*!< Specifies the dynamic address of the controller when goes in target mode. 92 This parameter must be a number between Min_Data=0x00 and Max_Data=0x7F */ 93 94 uint8_t StallTime; /*!< Specifies the controller clock stall time in number of kernel clock cycles. 95 This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF */ 96 97 FunctionalState HotJoinAllowed; /*!< Specifies the Enable/Disable state of the controller Hot Join acknowledgement 98 when receiving a hot join request from target. 99 This parameter can be set to ENABLE or DISABLE */ 100 101 FunctionalState ACKStallState; /*!< Specifies the Enable/Disable state of the controller clock stall 102 on the ACK phase. 103 This parameter can be set to ENABLE or DISABLE */ 104 105 FunctionalState CCCStallState; /*!< Specifies the Enable/Disable state of the controller clock stall on the 106 T bit phase of a CCC communication to allow the target to decode command. 107 This parameter can be set to ENABLE or DISABLE */ 108 109 FunctionalState TxStallState; /*!< Specifies the Enable/Disable state of the controller clock stall on 110 parity phase of data to allow the target to read received data. 111 This parameter can be set to ENABLE or DISABLE */ 112 113 FunctionalState RxStallState; /*!< Specifies the Enable/Disable state of the controller clock stall on the T bit 114 phase of data enable to allow the target to prepare data to be sent. 115 This parameter can be set to ENABLE or DISABLE */ 116 117 FunctionalState HighKeeperSDA; /*!< Specifies the Enable/Disable state of the controller SDA high keeper. 118 This parameter can be set to ENABLE or DISABLE */ 119 } I3C_CtrlConfTypeDef; 120 /** 121 * @} 122 */ 123 124 /** @defgroup I3C_Target_Config_Structure_definition I3C Target Configuration Structure definition 125 * @brief I3C target configuration structure definition 126 * @{ 127 */ 128 typedef struct 129 { 130 uint8_t Identifier; /*!< Specifies the target characteristic ID (MIPI named reference DCR). 131 This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF */ 132 133 uint8_t MIPIIdentifier; /*!< Specifies the bits [12-15] of the 48-provisioned ID 134 (MIPI named reference PID), other 48-provisioned ID are hardcoded. 135 This parameter must be a number between Min_Data=0x00 and Max_Data=0x0F */ 136 137 FunctionalState CtrlRoleRequest; /*!< Specifies the Enable/Disable state of the target authorization request 138 for a second master Chip. 139 This parameter can be set to ENABLE or DISABLE */ 140 141 FunctionalState HotJoinRequest; /*!< Specifies the Enable/Disable state of the target hot join 142 authorization request. 143 This parameter can be set to ENABLE or DISABLE */ 144 145 FunctionalState IBIRequest; /*!< Specifies the Enable/Disable state of the target in Band Interrupt 146 authorization request. 147 This parameter can be set to ENABLE or DISABLE */ 148 149 FunctionalState IBIPayload; /*!< Specifies the Enable/Disable state of sending data payload after 150 an accepted IBI. 151 This parameter can be set to ENABLE or DISABLE */ 152 153 uint32_t IBIPayloadSize; /*!< Specifies the I3C target payload data size. 154 This parameter must be a value of @ref I3C_PAYLOAD_SIZE */ 155 156 uint16_t MaxReadDataSize; /*!< Specifies the numbers of data bytes that the target can read at maximum. 157 This parameter must be a number between Min_Data=0x00 and Max_Data=0xFFFF */ 158 159 uint16_t MaxWriteDataSize; /*!< Specifies the numbers of data bytes that the target can write at maximum. 160 This parameter must be a number between Min_Data=0x00 and Max_Data=0xFFFF */ 161 162 FunctionalState CtrlCapability; /*!< Specifies the Enable/Disable state of the target controller capability. 163 This parameter can be set to ENABLE or DISABLE */ 164 165 FunctionalState GroupAddrCapability; /*!< Specifies the Enable/Disable state of the target support of group address 166 after a controller role hand-off. 167 This parameter can be set to ENABLE or DISABLE */ 168 169 uint32_t DataTurnAroundDuration; /*!< Specifies the I3C target clock-to-data turnaround time. 170 This parameter must be a value of @ref I3C_TURNAROUND_TIME_TSCO */ 171 172 uint8_t MaxReadTurnAround; /*!< Specifies the target maximum read turnaround byte. 173 This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF */ 174 175 uint32_t MaxDataSpeed; /*!< Specifies the I3C target returned GETMXDS CCC format. 176 This parameter must be a value of @ref I3C_GETMXDS_FORMAT */ 177 178 FunctionalState MaxSpeedLimitation; /*!< Specifies the Enable/Disable state of the target max data speed limitation. 179 This parameter can be set to ENABLE or DISABLE */ 180 181 uint32_t HandOffActivityState; /*!< Specifies the I3C target activity state when becoming controller. 182 This parameter must be a value of @ref I3C_HANDOFF_ACTIVITY_STATE */ 183 184 FunctionalState HandOffDelay; /*!< Specifies the Enable/Disable state of the target need of delay to process 185 the controller role hand-off. 186 This parameter can be set to ENABLE or DISABLE */ 187 188 FunctionalState PendingReadMDB; /*!< Specifies the Enable/Disable state of the transmission of a mandatory 189 data bytes indicating a pending read notification for GETCAPR CCC command. 190 This parameter can be set to ENABLE or DISABLE */ 191 } I3C_TgtConfTypeDef; 192 /** 193 * @} 194 */ 195 196 /** @defgroup I3C_Device_Config_Structure_definition I3C Device Configuration Structure definition 197 * @brief I3C device configuration structure definition 198 * @{ 199 */ 200 typedef struct 201 { 202 uint8_t DeviceIndex; /*!< Specifies the index value of the device in the DEVRx register. 203 This parameter must be a number between Min_Data=1 and Max_Data=4 */ 204 205 uint8_t TargetDynamicAddr; /*!< Specifies the dynamic address of the target x (1 to 4) connected on the bus. 206 This parameter must be a number between Min_Data=0x00 and Max_Data=0x7F */ 207 208 FunctionalState IBIAck; /*!< Specifies the Enable/Disable state of the controller's ACK when receiving 209 an IBI from a target x (1 to 4) connected on the bus. 210 This parameter can be set to ENABLE or DISABLE */ 211 212 FunctionalState IBIPayload; /*!< Specifies the Enable/Disable state of the controller's receiving IBI payload 213 after acknowledging an IBI requested from a target x (1 to 4) connected 214 on the bus. 215 This parameter can be set to ENABLE or DISABLE */ 216 217 FunctionalState CtrlRoleReqAck; /*!< Specifies the Enable/Disable state of the controller's ACK when receiving 218 a control request from a target x (1 to 4) connected on the bus. 219 This parameter can be set to ENABLE or DISABLE */ 220 221 FunctionalState CtrlStopTransfer; /*!< Specifies the Enable/Disable state of the controller's stop transfer after 222 receiving an IBI request from a target x (1 to 4) connected on the bus. 223 This parameter can be set to ENABLE or DISABLE */ 224 225 } I3C_DeviceConfTypeDef; 226 /** 227 * @} 228 */ 229 230 /** @defgroup I3C_mode_structure_definition I3C mode structure definition 231 * @brief I3C Mode structure definition 232 * @{ 233 */ 234 typedef enum 235 { 236 HAL_I3C_MODE_NONE = 0x00U, /*!< No I3C communication on going */ 237 HAL_I3C_MODE_CONTROLLER = 0x01U, /*!< I3C communication is in controller Mode */ 238 HAL_I3C_MODE_TARGET = 0x02U, /*!< I3C communication is in target Mode */ 239 240 } HAL_I3C_ModeTypeDef; 241 /** 242 * @} 243 */ 244 245 /** @defgroup HAL_state_structure_definition HAL state structure definition 246 * @brief HAL State structure definition 247 * @{ 248 */ 249 typedef enum 250 { 251 HAL_I3C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ 252 HAL_I3C_STATE_READY = 0x10U, /*!< Peripheral Initialized and ready for use */ 253 HAL_I3C_STATE_BUSY = 0x20U, /*!< An internal process is ongoing */ 254 HAL_I3C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ 255 HAL_I3C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ 256 HAL_I3C_STATE_BUSY_TX_RX = 0x23U, /*!< Data Multiple Transfer process is ongoing */ 257 HAL_I3C_STATE_BUSY_DAA = 0x24U, /*!< Dynamic address assignment process is ongoing */ 258 HAL_I3C_STATE_LISTEN = 0x30U, /*!< Listen process is ongoing */ 259 HAL_I3C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ 260 HAL_I3C_STATE_ERROR = 0xE0U, /*!< Error */ 261 262 } HAL_I3C_StateTypeDef; 263 /** 264 * @} 265 */ 266 267 /** @defgroup I3C_CCCInfoTypeDef_Structure_definition I3C CCCInfoTypeDef Structure definition 268 * @brief I3C CCCInfoTypeDef Structure definition 269 * @{ 270 */ 271 typedef struct 272 { 273 uint32_t DynamicAddrValid; /*!< I3C target Dynamic Address Valid (updated during ENTDAA/RSTDAA/SETNEWDA CCC) 274 This parameter can be Valid=1U or Not Valid=0U */ 275 uint32_t DynamicAddr; /*!< I3C target Dynamic Address (updated during ENTDAA/RSTDAA/SETNEWDA CCC) */ 276 uint32_t MaxWriteLength; /*!< I3C target Maximum Write Length (updated during SETMWL CCC) */ 277 uint32_t MaxReadLength; /*!< I3C target Maximum Read Length (updated during SETMRL CCC) */ 278 uint32_t ResetAction; /*!< I3C target Reset Action level (updated during RSTACT CCC) */ 279 uint32_t ActivityState; /*!< I3C target Activity State (updated during ENTASx CCC) */ 280 uint32_t HotJoinAllowed; /*!< I3C target Hot Join (updated during ENEC/DISEC CCC) 281 This parameter can be Allowed=1U or Not Allowed=0U */ 282 uint32_t InBandAllowed; /*!< I3C target In Band Interrupt (updated during ENEC/DISEC CCC) 283 This parameter can be Allowed=1U or Not Allowed=0U */ 284 uint32_t CtrlRoleAllowed; /*!< I3C target Controller Role Request (updated during ENEC/DISEC CCC) 285 This parameter can be Allowed=1U or Not Allowed=0U */ 286 uint32_t IBICRTgtAddr; /*!< I3C controller receive Target Address during IBI or Controller Role Request event*/ 287 uint32_t IBITgtNbPayload; /*!< I3C controller get Number of Data Payload after an IBI event */ 288 uint32_t IBITgtPayload; /*!< I3C controller receive IBI Payload after an IBI event */ 289 290 } I3C_CCCInfoTypeDef; 291 /** 292 * @} 293 */ 294 295 /** @defgroup I3C_ControlTypeDef_Structure_definition I3C ControlTypeDef Structure definition 296 * @brief I3C ControlTypeDef Structure definition 297 * @{ 298 */ 299 typedef struct 300 { 301 uint32_t *pBuffer; /*!< Pointer to the buffer containing the control or status register values */ 302 uint32_t Size; /*!< The size of pBuffer in words */ 303 304 } I3C_ControlTypeDef; 305 /** 306 * @} 307 */ 308 309 /** @defgroup I3C_DataTypeDef_Structure_definition I3C DataTypeDef Structure definition 310 * @brief I3C DataTypeDef Structure definition 311 * @{ 312 */ 313 typedef struct 314 { 315 uint8_t *pBuffer; /*!< Pointer to the buffer containing all data values to transfer */ 316 uint32_t Size; /*!< The size of pBuffer in bytes */ 317 318 } I3C_DataTypeDef; 319 320 /** 321 * @} 322 */ 323 324 /** @defgroup I3C_CCCTypeDef_Structure_definition I3C CCCTypeDef Structure definition 325 * @brief I3C CCCTypeDef Structure definition 326 * @{ 327 */ 328 typedef struct 329 { 330 uint8_t TargetAddr; /*!< Dynamic or Static target Address */ 331 uint8_t CCC; /*!< CCC value code */ 332 I3C_DataTypeDef CCCBuf; /*!< Contain size of associated data and size of defining byte if any. 333 Contain pointer to CCC associated data */ 334 uint32_t Direction; /*!< CCC read and/or write direction message */ 335 336 } I3C_CCCTypeDef; 337 /** 338 * @} 339 */ 340 341 /** @defgroup I3C_BCRTypeDef_Structure_definition I3C BCRTypeDef Structure definition 342 * @brief I3C BCRTypeDef Structure definition 343 * @{ 344 */ 345 typedef struct 346 { 347 FunctionalState MaxDataSpeedLimitation; /*!< Max data speed limitation */ 348 FunctionalState IBIRequestCapable; /*!< IBI request capable */ 349 FunctionalState IBIPayload; /*!< IBI payload data */ 350 FunctionalState OfflineCapable; /*!< Offline capable */ 351 FunctionalState VirtualTargetSupport; /*!< Virtual target support */ 352 FunctionalState AdvancedCapabilities; /*!< Advanced capabilities */ 353 FunctionalState DeviceRole; /*!< Device role */ 354 355 } I3C_BCRTypeDef; 356 /** 357 * @} 358 */ 359 360 /** @defgroup I3C_PIDTypeDef_Structure_definition I3C PIDTypeDef Structure definition 361 * @brief I3C_PIDTypeDef Structure definition 362 * @{ 363 */ 364 typedef struct 365 { 366 uint16_t MIPIMID; /*!< MIPI Manufacturer ID */ 367 uint8_t IDTSEL; /*!< Provisioned ID Type Selector */ 368 uint16_t PartID; /*!< Part ID device vendor to define */ 369 uint8_t MIPIID; /*!< Instance ID */ 370 371 } I3C_PIDTypeDef; 372 /** 373 * @} 374 */ 375 376 /** @defgroup I3C_ENTDAAPayloadTypeDef_Structure_definition I3C ENTDAAPayloadTypeDef Structure definition 377 * @brief I3C ENTDAAPayloadTypeDef Structure definition 378 * @{ 379 */ 380 typedef struct 381 { 382 I3C_BCRTypeDef BCR; /*!< Bus Characteristics Register */ 383 uint32_t DCR; /*!< Device Characteristics Register */ 384 I3C_PIDTypeDef PID; /*!< Provisioned ID */ 385 386 } I3C_ENTDAAPayloadTypeDef; 387 /** 388 * @} 389 */ 390 391 /** @defgroup I3C_PrivateTypeDef_Structure_definition I3C PrivateTypeDef Structure definition 392 * @brief I3C PrivateTypeDef Structure definition 393 * @{ 394 */ 395 typedef struct 396 { 397 uint8_t TargetAddr; /*!< Dynamic or Static target Address */ 398 I3C_DataTypeDef TxBuf; /*!< Buffer structure containing the data to transmit (little endian) */ 399 I3C_DataTypeDef RxBuf; /*!< Buffer structure containing the data to receive (little endian) */ 400 uint32_t Direction; /*!< Read and/or write message */ 401 402 } I3C_PrivateTypeDef; 403 /** 404 * @} 405 */ 406 407 /** @defgroup I3C_XferTypeDef_Structure_definition I3C XferTypeDef Structure definition 408 * @brief I3C XferTypeDef Structure definition 409 * @{ 410 */ 411 typedef struct 412 { 413 I3C_ControlTypeDef CtrlBuf; /*!< Buffer structure containing the control register values */ 414 I3C_ControlTypeDef StatusBuf; /*!< Buffer structure containing the status register values */ 415 I3C_DataTypeDef TxBuf; /*!< Buffer structure containing the data to transmit */ 416 I3C_DataTypeDef RxBuf; /*!< Buffer structure containing the data to receive */ 417 418 } I3C_XferTypeDef; 419 /** 420 * @} 421 */ 422 423 /** @defgroup I3C_handle_Structure_definition I3C handle Structure definition 424 * @brief I3C handle Structure definition 425 * @{ 426 */ 427 typedef struct __I3C_HandleTypeDef 428 { 429 I3C_TypeDef *Instance; /*!< I3C registers base address */ 430 431 I3C_InitTypeDef Init; /*!< I3C communication parameters */ 432 433 HAL_I3C_ModeTypeDef Mode; /*!< I3C communication mode. 434 This parameter must be a value of 435 @ref I3C_mode_structure_definition */ 436 437 I3C_XferTypeDef *pXferData; /*!< I3C transfer buffers pointer */ 438 439 const I3C_CCCTypeDef *pCCCDesc; /*!< I3C CCC descriptor pointer */ 440 441 const I3C_PrivateTypeDef *pPrivateDesc; /*!< I3C private transfer descriptor pointer */ 442 443 uint32_t ControlXferCount; /*!< I3C counter indicating the remaining 444 control data bytes to write in 445 the control register */ 446 447 uint32_t RxXferCount; /*!< I3C counter indicating the remaining 448 data bytes to receive */ 449 450 uint32_t TxXferCount; /*!< I3C counter indicating the remaining 451 data bytes to transmit */ 452 453 #if defined(HAL_DMA_MODULE_ENABLED) 454 DMA_HandleTypeDef *hdmacr; /*!< I3C control DMA handle parameters */ 455 456 DMA_HandleTypeDef *hdmatx; /*!< I3C Tx DMA handle parameters */ 457 458 DMA_HandleTypeDef *hdmarx; /*!< I3C Rx DMA handle parameters */ 459 460 DMA_HandleTypeDef *hdmasr; /*!< I3C status DMA handle parameters */ 461 #endif /* HAL_DMA_MODULE_ENABLED */ 462 463 HAL_LockTypeDef Lock; /*!< I3C locking object */ 464 465 __IO HAL_I3C_StateTypeDef State; /*!< I3C communication state */ 466 467 __IO HAL_I3C_StateTypeDef PreviousState; /*!< I3C communication previous state */ 468 469 __IO uint32_t ErrorCode; /*!< I3C Error code */ 470 471 HAL_StatusTypeDef(*XferISR)(struct __I3C_HandleTypeDef *hi3c, 472 uint32_t itMasks); /*!< I3C transfer IRQ handler function pointer */ 473 474 void(*ptrTxFunc)(struct __I3C_HandleTypeDef *hi3c); /*!< I3C transmit function pointer */ 475 476 void(*ptrRxFunc)(struct __I3C_HandleTypeDef *hi3c); /*!< I3C receive function pointer */ 477 478 #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) 479 480 void (* CtrlTxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 481 /*!< I3C Controller private data and CCC Tx Transfer complete callback */ 482 483 void (* CtrlRxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 484 /*!< I3C Controller private data and CCC Rx Transfer completed callback */ 485 486 void (* CtrlMultipleXferCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 487 /*!< I3C Controller multiple Direct CCC, I3C private or I2C Transfer completed callback */ 488 489 void (* CtrlDAACpltCallback)(struct __I3C_HandleTypeDef *hi3c); 490 /*!< I3C Controller Dynamic Address Assignment completed callback */ 491 492 void (* TgtReqDynamicAddrCallback)(struct __I3C_HandleTypeDef *hi3c, uint64_t targetPayload); 493 /*!< I3C Controller request dynamic address callback during Dynamic Address Assignment processus */ 494 495 void (* TgtTxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 496 /*!< I3C Target private data Tx Transfer completed callback */ 497 498 void (* TgtRxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 499 /*!< I3C Target private data Rx Transfer completed callback */ 500 501 void (* TgtHotJoinCallback)(struct __I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress); 502 /*!< I3C Target Hot-Join callback */ 503 504 void (* NotifyCallback)(struct __I3C_HandleTypeDef *hi3c, uint32_t eventId); 505 /*!< I3C Target or Controller asynchronous events callback */ 506 507 void (* ErrorCallback)(struct __I3C_HandleTypeDef *hi3c); 508 /*!< I3C Error callback */ 509 510 void (* AbortCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 511 /*!< I3C Abort complete callback */ 512 513 void (* MspInitCallback)(struct __I3C_HandleTypeDef *hi3c); 514 /*!< I3C Msp Init callback */ 515 516 void (* MspDeInitCallback)(struct __I3C_HandleTypeDef *hi3c); 517 /*!< I3C Msp DeInit callback */ 518 519 #endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ 520 521 } I3C_HandleTypeDef; 522 /** 523 * @} 524 */ 525 526 #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) 527 /** @defgroup HAL_I3C_Callback_ID_definition I3C callback ID definition 528 * @brief HAL I3C callback ID definition 529 * @{ 530 */ 531 typedef enum 532 { 533 /*!< I3C Controller Tx Transfer completed callback ID */ 534 HAL_I3C_CTRL_TX_COMPLETE_CB_ID = 0x00U, 535 /*!< I3C Controller Rx Transfer completed callback ID */ 536 HAL_I3C_CTRL_RX_COMPLETE_CB_ID = 0x01U, 537 /*!< I3C Controller Multiple Transfer completed callback ID */ 538 HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID = 0x02U, 539 /*!< I3C Controller Dynamic Address Assignment completed callback ID */ 540 HAL_I3C_CTRL_DAA_COMPLETE_CB_ID = 0x03U, 541 /*!< I3C Controller request dynamic address completed callback ID */ 542 HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID = 0x04U, 543 /*!< I3C Target Tx Transfer completed callback ID */ 544 HAL_I3C_TGT_TX_COMPLETE_CB_ID = 0x05U, 545 /*!< I3C Target Rx Transfer completed callback ID */ 546 HAL_I3C_TGT_RX_COMPLETE_CB_ID = 0x06U, 547 /*!< I3C Target Hot-join notification callback ID */ 548 HAL_I3C_TGT_HOTJOIN_CB_ID = 0x07U, 549 /*!< I3C Target or Controller receive notification callback ID */ 550 HAL_I3C_NOTIFY_CB_ID = 0x08U, 551 /*!< I3C Error callback ID */ 552 HAL_I3C_ERROR_CB_ID = 0x09U, 553 /*!< I3C Abort callback ID */ 554 HAL_I3C_ABORT_CB_ID = 0x0AU, 555 /*!< I3C Msp Init callback ID */ 556 HAL_I3C_MSPINIT_CB_ID = 0x0BU, 557 /*!< I3C Msp DeInit callback ID */ 558 HAL_I3C_MSPDEINIT_CB_ID = 0x0CU 559 560 } HAL_I3C_CallbackIDTypeDef; 561 /** 562 * @} 563 */ 564 565 /** @defgroup HAL_I3C_Callback_Pointer_definition I3C callback Pointer definition 566 * @brief HAL I3C callback pointer definition 567 * @{ 568 */ 569 typedef void (*pI3C_CallbackTypeDef)(I3C_HandleTypeDef *hi3c); 570 typedef void (*pI3C_NotifyCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint32_t notifyId); 571 typedef void (*pI3C_TgtHotJoinCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress); 572 typedef void (*pI3C_TgtReqDynamicAddrCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint64_t targetPayload); 573 /** 574 * @} 575 */ 576 #endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ 577 578 /** 579 * @} 580 */ 581 582 /* Exported constants ------------------------------------------------------------------------------------------------*/ 583 /** @defgroup I3C_Exported_Constants I3C Exported Constants 584 * @{ 585 */ 586 587 /** @defgroup HAL_I3C_Notification_ID_definition I3C Notification ID definition 588 * @brief HAL I3C Notification ID definition 589 * @{ 590 */ 591 592 #define EVENT_ID_GETACCCR (0x00000001U) 593 /*!< I3C target complete controller-role hand-off (direct GETACCR CCC) event */ 594 #define EVENT_ID_IBIEND (0x00000002U) 595 /*!< I3C target IBI end process event */ 596 #define EVENT_ID_DAU (0x00000004U) 597 /*!< I3C target receive a dynamic address update (ENTDAA/RSTDAA/SETNEWDA CCC) event */ 598 #define EVENT_ID_GETx (0x00000008U) 599 /*!< I3C target receive any direct GETxxx CCC event */ 600 #define EVENT_ID_GETSTATUS (0x00000010U) 601 /*!< I3C target receive get status command (direct GETSTATUS CCC) event */ 602 #define EVENT_ID_SETMWL (0x00000020U) 603 /*!< I3C target receive maximum write length update (direct SETMWL CCC) event */ 604 #define EVENT_ID_SETMRL (0x00000040U) 605 /*!< I3C target receive maximum read length update(direct SETMRL CCC) event */ 606 #define EVENT_ID_RSTACT (0x00000080U) 607 /*!< I3C target detect reset pattern (broadcast or direct RSTACT CCC) event */ 608 #define EVENT_ID_ENTASx (0x00000100U) 609 /*!< I3C target receive activity state update (direct or broadcast ENTASx) event */ 610 #define EVENT_ID_ENEC_DISEC (0x00000200U) 611 /*!< I3C target receive a direct or broadcast ENEC/DISEC CCC event */ 612 #define EVENT_ID_DEFTGTS (0x00000400U) 613 /*!< I3C target receive a broadcast DEFTGTS CCC event */ 614 #define EVENT_ID_DEFGRPA (0x00000800U) 615 /*!< I3C target receive a group addressing (broadcast DEFGRPA CCC) event */ 616 #define EVENT_ID_WKP (0x00001000U) 617 /*!< I3C target wakeup event */ 618 #define EVENT_ID_IBI (0x00002000U) 619 /*!< I3C controller receive IBI event */ 620 #define EVENT_ID_CR (0x00004000U) 621 /*!< I3C controller controller-role request event */ 622 #define EVENT_ID_HJ (0x00008000U) 623 /*!< I3C controller hot-join event */ 624 /** 625 * @} 626 */ 627 628 /** @defgroup I3C_OPTION_DEFINITION OPTION DEFINITION 629 * @note HAL I3C option value coding follow below described bitmap: 630 * b31 631 * 0 : message end type restart 632 * 1 : message end type stop 633 * b30-b29-b28-b27 634 * 0010 : I3C private message 635 * 0011 : direct CCC message 636 * 0110 : broadcast CCC message 637 * 0100 : I2C private message 638 * b4 639 * 0 : message without arbitration header 640 * 1 : message with arbitration header 641 * b0 642 * 0 : message without defining byte 643 * 1 : message with defining byte 644 * 645 * other bits (not used) 646 * @{ 647 */ 648 #define I3C_DIRECT_WITH_DEFBYTE_RESTART (0x18000001U) /*!< Restart between each Direct Command then Stop 649 request for last command. 650 Each Command have an associated defining byte */ 651 #define I3C_DIRECT_WITH_DEFBYTE_STOP (0x98000001U) /*!< Stop between each Direct Command. 652 Each Command have an associated defining byte */ 653 #define I3C_DIRECT_WITHOUT_DEFBYTE_RESTART (0x18000000U) /*!< Restart between each Direct Command then Stop 654 request for last command. 655 Each Command have not an associated defining byte */ 656 #define I3C_DIRECT_WITHOUT_DEFBYTE_STOP (0x98000000U) /*!< Stop between each Direct Command. 657 Each Command have not an associated defining byte */ 658 #define I3C_BROADCAST_WITH_DEFBYTE_RESTART (0x30000001U) /*!< Restart between each Broadcast Command then Stop 659 request for last command. 660 Each Command have an associated defining byte */ 661 #define I3C_BROADCAST_WITH_DEFBYTE_STOP (0xB0000001U) /*!< Stop between each Broadcast Command. 662 Each Command have an associated defining byte */ 663 #define I3C_BROADCAST_WITHOUT_DEFBYTE_RESTART (0x30000000U) /*!< Restart between each Broadcast Command then Stop 664 request for last command. 665 Each Command have not an associated defining byte */ 666 #define I3C_BROADCAST_WITHOUT_DEFBYTE_STOP (0xB0000000U) /*!< Stop between each Broadcast Command. 667 Each Command have not an associated defining byte */ 668 #define I3C_PRIVATE_WITH_ARB_RESTART (0x10000000U) /*!< Restart between each I3C Private message then Stop 669 request for last message. 670 Each Message start with an arbitration header after 671 start bit condition */ 672 #define I3C_PRIVATE_WITH_ARB_STOP (0x90000000U) /*!< Stop between each I3C Private message. 673 Each Message start with an arbitration header after 674 start bit condition */ 675 #define I3C_PRIVATE_WITHOUT_ARB_RESTART (0x10000004U) /*!< Restart between each I3C message then Stop request 676 for last message. 677 Each Message start with Target address after start 678 bit condition */ 679 #define I3C_PRIVATE_WITHOUT_ARB_STOP (0x90000004U) /*!< Stop between each I3C Private message. 680 Each Message start with Target address after 681 start bit condition */ 682 #define I2C_PRIVATE_WITH_ARB_RESTART (0x20000000U) /*!< Restart between each I2C Private message then Stop 683 request for last message. 684 Each Message start with an arbitration header after 685 start bit condition */ 686 #define I2C_PRIVATE_WITH_ARB_STOP (0xA0000000U) /*!< Stop between each I2C Private message. 687 Each Message start with an arbitration header after 688 start bit condition */ 689 #define I2C_PRIVATE_WITHOUT_ARB_RESTART (0x20000004U) /*!< Restart between each I2C message then Stop request 690 for last message. 691 Each Message start with Target address after start 692 bit condition */ 693 #define I2C_PRIVATE_WITHOUT_ARB_STOP (0xA0000004U) /*!< Stop between each I2C Private message. 694 Each Message start with Target address after start 695 bit condition */ 696 /** 697 * @} 698 */ 699 700 /** @defgroup I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION I3C DYNAMIC ADDRESS OPTION DEFINITION 701 * @{ 702 */ 703 #define I3C_RSTDAA_THEN_ENTDAA (0x00000001U) /*!< Initiate a RSTDAA before a ENTDAA procedure */ 704 #define I3C_ONLY_ENTDAA (0x00000002U) /*!< Initiate a ENTDAA without RSTDAA */ 705 /** 706 * @} 707 */ 708 709 /** @defgroup I3C_ERROR_CODE_DEFINITION ERROR CODE DEFINITION 710 * @{ 711 */ 712 #define HAL_I3C_ERROR_NONE (0x00000000U) /*!< No error */ 713 714 #define HAL_I3C_ERROR_CE0 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE0) /*!< Controller detected an illegally 715 formatted CCC */ 716 #define HAL_I3C_ERROR_CE1 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE1) /*!< Controller detected that transmitted data 717 on the bus is different than expected */ 718 #define HAL_I3C_ERROR_CE2 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE2) /*!< Controller detected that broadcast address 719 7'h7E has been nacked */ 720 #define HAL_I3C_ERROR_CE3 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE3) /*!< Controller detected that new Controller 721 did not drive the bus after 722 Controller-role handoff */ 723 #define HAL_I3C_ERROR_TE0 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE0) /*!< Target detected an invalid broadcast 724 address */ 725 #define HAL_I3C_ERROR_TE1 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE1) /*!< Target detected an invalid CCC Code */ 726 #define HAL_I3C_ERROR_TE2 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE2) /*!< Target detected a parity error during 727 a write data */ 728 #define HAL_I3C_ERROR_TE3 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE3) /*!< Target detected a parity error on assigned 729 address during dynamic address 730 arbitration */ 731 #define HAL_I3C_ERROR_TE4 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE4) /*!< Target detected 7'h7E missing after Restart 732 during Dynamic Address Assignment 733 procedure */ 734 #define HAL_I3C_ERROR_TE5 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE5) /*!< Target detected an illegally 735 formatted CCC */ 736 #define HAL_I3C_ERROR_TE6 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE6) /*!< Target detected that transmitted data on 737 the bus is different than expected */ 738 #define HAL_I3C_ERROR_DATA_HAND_OFF (I3C_SER_DERR) /*!< I3C data error during controller-role hand-off process */ 739 #define HAL_I3C_ERROR_DATA_NACK (I3C_SER_DNACK) /*!< I3C data not acknowledged error */ 740 #define HAL_I3C_ERROR_ADDRESS_NACK (I3C_SER_ANACK) /*!< I3C address not acknowledged error */ 741 #define HAL_I3C_ERROR_COVR (I3C_SER_COVR) /*!< I3C S FIFO Over-Run or C FIFO Under-Run error */ 742 #define HAL_I3C_ERROR_DOVR (I3C_SER_DOVR) /*!< I3C Rx FIFO Over-Run or Tx FIFO Under-Run error */ 743 #define HAL_I3C_ERROR_STALL (I3C_SER_STALL) /*!< I3C SCL stall error */ 744 #define HAL_I3C_ERROR_DMA (0x00010000U) /*!< DMA transfer error */ 745 #define HAL_I3C_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ 746 #define HAL_I3C_ERROR_DMA_PARAM (0x00040000U) /*!< DMA Parameter Error */ 747 #define HAL_I3C_ERROR_INVALID_PARAM (0x00080000U) /*!< Invalid Parameters error */ 748 #define HAL_I3C_ERROR_SIZE (0x00100000U) /*!< I3C size management error */ 749 #define HAL_I3C_ERROR_NOT_ALLOWED (0x00200000U) /*!< I3C operation is not allowed */ 750 #define HAL_I3C_ERROR_DYNAMIC_ADDR (0x00400000U) /*!< I3C dynamic address error */ 751 752 #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) 753 #define HAL_I3C_ERROR_INVALID_CALLBACK (0x00800000U) /*!< Invalid Callback error */ 754 #endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ 755 /** 756 * @} 757 */ 758 759 /** @defgroup I3C_SDA_HOLD_TIME SDA HOLD TIME 760 * @{ 761 */ 762 #define HAL_I3C_SDA_HOLD_TIME_0_5 LL_I3C_SDA_HOLD_TIME_0_5 /*!< SDA hold time equal to 0.5 x ti3cclk */ 763 #define HAL_I3C_SDA_HOLD_TIME_1_5 LL_I3C_SDA_HOLD_TIME_1_5 /*!< SDA hold time equal to 1.5 x ti3cclk */ 764 /** 765 * @} 766 */ 767 768 /** @defgroup I3C_OWN_ACTIVITY_STATE OWN ACTIVITY STATE 769 * @{ 770 */ 771 #define HAL_I3C_OWN_ACTIVITY_STATE_0 LL_I3C_OWN_ACTIVITY_STATE_0 /*!< Own Controller Activity state 0 */ 772 #define HAL_I3C_OWN_ACTIVITY_STATE_1 LL_I3C_OWN_ACTIVITY_STATE_1 /*!< Own Controller Activity state 1 */ 773 #define HAL_I3C_OWN_ACTIVITY_STATE_2 LL_I3C_OWN_ACTIVITY_STATE_2 /*!< Own Controller Activity state 2 */ 774 #define HAL_I3C_OWN_ACTIVITY_STATE_3 LL_I3C_OWN_ACTIVITY_STATE_3 /*!< Own Controller Activity state 3 */ 775 /** 776 * @} 777 */ 778 779 /** @defgroup I3C_RX_FIFO_THRESHOLD RX FIFO THRESHOLD 780 * @{ 781 */ 782 #define HAL_I3C_RXFIFO_THRESHOLD_1_4 LL_I3C_RXFIFO_THRESHOLD_1_4 /*!< Rx Fifo Threshold is 1 byte */ 783 #define HAL_I3C_RXFIFO_THRESHOLD_4_4 LL_I3C_RXFIFO_THRESHOLD_4_4 /*!< Rx Fifo Threshold is 4 bytes */ 784 /** 785 * @} 786 */ 787 788 /** @defgroup I3C_TX_FIFO_THRESHOLD TX FIFO THRESHOLD 789 * @{ 790 */ 791 #define HAL_I3C_TXFIFO_THRESHOLD_1_4 LL_I3C_TXFIFO_THRESHOLD_1_4 /*!< Tx Fifo Threshold is 1 byte */ 792 #define HAL_I3C_TXFIFO_THRESHOLD_4_4 LL_I3C_TXFIFO_THRESHOLD_4_4 /*!< Tx Fifo Threshold is 4 bytes */ 793 /** 794 * @} 795 */ 796 797 /** @defgroup I3C_CONTROL_FIFO_STATE CONTROL FIFO STATE 798 * @{ 799 */ 800 #define HAL_I3C_CONTROLFIFO_DISABLE 0x00000000U /*!< Control FIFO mode disable */ 801 #define HAL_I3C_CONTROLFIFO_ENABLE I3C_CFGR_TMODE /*!< Control FIFO mode enable */ 802 /** 803 * @} 804 */ 805 806 /** @defgroup I3C_STATUS_FIFO_STATE STATUS FIFO STATE 807 * @{ 808 */ 809 #define HAL_I3C_STATUSFIFO_DISABLE 0x00000000U /*!< Status FIFO mode disable */ 810 #define HAL_I3C_STATUSFIFO_ENABLE I3C_CFGR_SMODE /*!< Status FIFO mode enable */ 811 /** 812 * @} 813 */ 814 815 /** @defgroup I3C_DIRECTION DIRECTION 816 * @{ 817 */ 818 #define HAL_I3C_DIRECTION_WRITE LL_I3C_DIRECTION_WRITE /*!< Write transfer */ 819 #define HAL_I3C_DIRECTION_READ LL_I3C_DIRECTION_READ /*!< Read transfer */ 820 #define HAL_I3C_DIRECTION_BOTH (LL_I3C_DIRECTION_READ | 1U) /*!< Read and Write transfer */ 821 /** 822 * @} 823 */ 824 825 /** @defgroup I3C_PAYLOAD_SIZE PAYLOAD SIZE 826 * @{ 827 */ 828 #define HAL_I3C_PAYLOAD_EMPTY LL_I3C_PAYLOAD_EMPTY /*!< Empty payload, no additional data after IBI acknowledge */ 829 #define HAL_I3C_PAYLOAD_1_BYTE LL_I3C_PAYLOAD_1_BYTE /*!< One additional data byte after IBI acknowledge */ 830 #define HAL_I3C_PAYLOAD_2_BYTES LL_I3C_PAYLOAD_2_BYTES /*!< Two additional data bytes after IBI acknowledge */ 831 #define HAL_I3C_PAYLOAD_3_BYTES LL_I3C_PAYLOAD_3_BYTES /*!< Three additional data bytes after IBI acknowledge */ 832 #define HAL_I3C_PAYLOAD_4_BYTES LL_I3C_PAYLOAD_4_BYTES /*!< Four additional data bytes after IBI acknowledge */ 833 /** 834 * @} 835 */ 836 837 /** @defgroup I3C_HANDOFF_ACTIVITY_STATE HANDOFF ACTIVITY STATE 838 * @{ 839 */ 840 #define HAL_I3C_HANDOFF_ACTIVITY_STATE_0 LL_I3C_HANDOFF_ACTIVITY_STATE_0 /*!< Activity state 0 after handoff */ 841 #define HAL_I3C_HANDOFF_ACTIVITY_STATE_1 LL_I3C_HANDOFF_ACTIVITY_STATE_1 /*!< Activity state 1 after handoff */ 842 #define HAL_I3C_HANDOFF_ACTIVITY_STATE_2 LL_I3C_HANDOFF_ACTIVITY_STATE_2 /*!< Activity state 2 after handoff */ 843 #define HAL_I3C_HANDOFF_ACTIVITY_STATE_3 LL_I3C_HANDOFF_ACTIVITY_STATE_3 /*!< Activity state 3 after handoff */ 844 /** 845 * @} 846 */ 847 848 /** @defgroup I3C_GETMXDS_FORMAT GETMXDS FORMAT 849 * @{ 850 */ 851 #define HAL_I3C_GETMXDS_FORMAT_1 LL_I3C_GETMXDS_FORMAT_1 /*!< GETMXDS CCC Format 1 is used, no MaxRdTurn 852 field in response */ 853 #define HAL_I3C_GETMXDS_FORMAT_2_LSB LL_I3C_GETMXDS_FORMAT_2_LSB /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field 854 in response, LSB = RDTURN[7:0] */ 855 #define HAL_I3C_GETMXDS_FORMAT_2_MID LL_I3C_GETMXDS_FORMAT_2_MID /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field 856 in response, Middle byte = RDTURN[7:0] */ 857 #define HAL_I3C_GETMXDS_FORMAT_2_MSB LL_I3C_GETMXDS_FORMAT_2_MSB /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field 858 in response, MSB = RDTURN[7:0] */ 859 /** 860 * @} 861 */ 862 863 /** @defgroup I3C_TURNAROUND_TIME_TSCO TURNAROUND TIME TSCO 864 * @{ 865 */ 866 #define HAL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS 867 /*!< clock-to-data turnaround time tSCO <= 12ns */ 868 #define HAL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS 869 /*!< clock-to-data turnaround time tSCO > 12ns */ 870 /** 871 * @} 872 */ 873 874 /** @defgroup I3C_COMMON_INTERRUPT I3C COMMON INTERRUPT 875 * @{ 876 */ 877 #define HAL_I3C_IT_TXFNFIE LL_I3C_IER_TXFNFIE /*!< Tx FIFO not full interrupt enable */ 878 #define HAL_I3C_IT_RXFNEIE LL_I3C_IER_RXFNEIE /*!< Rx FIFO not empty interrupt enable */ 879 #define HAL_I3C_IT_FCIE LL_I3C_IER_FCIE /*!< Frame complete interrupt enable */ 880 #define HAL_I3C_IT_ERRIE LL_I3C_IER_ERRIE /*!< Error interrupt enable */ 881 #define HAL_I3C_ALL_COMMON_ITS (uint32_t)(LL_I3C_IER_TXFNFIE | LL_I3C_IER_RXFNEIE | \ 882 LL_I3C_IER_FCIE | LL_I3C_IER_ERRIE) 883 /** 884 * @} 885 */ 886 887 /** @defgroup I3C_TARGET_INTERRUPT I3C TARGET INTERRUPT 888 * @{ 889 */ 890 #define HAL_I3C_IT_IBIENDIE LL_I3C_IER_IBIENDIE /*!< IBI end interrupt enable */ 891 #define HAL_I3C_IT_CRUPDIE LL_I3C_IER_CRUPDIE /*!< controller-role update interrupt enable */ 892 #define HAL_I3C_IT_WKPIE LL_I3C_IER_WKPIE /*!< wakeup interrupt enable */ 893 #define HAL_I3C_IT_GETIE LL_I3C_IER_GETIE /*!< GETxxx CCC interrupt enable */ 894 #define HAL_I3C_IT_STAIE LL_I3C_IER_STAIE /*!< GETSTATUS CCC interrupt enable */ 895 #define HAL_I3C_IT_DAUPDIE LL_I3C_IER_DAUPDIE /*!< ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable */ 896 #define HAL_I3C_IT_MWLUPDIE LL_I3C_IER_MWLUPDIE /*!< SETMWL CCC interrupt enable */ 897 #define HAL_I3C_IT_MRLUPDIE LL_I3C_IER_MRLUPDIE /*!< SETMRL CCC interrupt enable */ 898 #define HAL_I3C_IT_RSTIE LL_I3C_IER_RSTIE /*!< reset pattern interrupt enable */ 899 #define HAL_I3C_IT_ASUPDIE LL_I3C_IER_ASUPDIE /*!< ENTASx CCC interrupt enable */ 900 #define HAL_I3C_IT_INTUPDIE LL_I3C_IER_INTUPDIE /*!< ENEC/DISEC CCC interrupt enable */ 901 #define HAL_I3C_IT_DEFIE (LL_I3C_IER_DEFIE | LL_I3C_IER_RXFNEIE) 902 /*!< DEFTGTS CCC interrupt enable */ 903 #define HAL_I3C_IT_GRPIE (LL_I3C_IER_GRPIE | LL_I3C_IER_RXFNEIE) 904 /*!< DEFGRPA CCC interrupt enable */ 905 #define HAL_I3C_ALL_TGT_ITS (uint32_t)(LL_I3C_IER_IBIENDIE | LL_I3C_IER_CRUPDIE | LL_I3C_IER_WKPIE | \ 906 LL_I3C_IER_GETIE | LL_I3C_IER_STAIE | LL_I3C_IER_DAUPDIE | \ 907 LL_I3C_IER_MWLUPDIE | LL_I3C_IER_MRLUPDIE | LL_I3C_IER_RSTIE | \ 908 LL_I3C_IER_ASUPDIE | LL_I3C_IER_INTUPDIE | LL_I3C_IER_DEFIE | \ 909 LL_I3C_IER_GRPIE) 910 /** 911 * @} 912 */ 913 914 /** @defgroup I3C_CONTROLLER_INTERRUPT I3C CONTROLLER INTERRUPT 915 * @{ 916 */ 917 #define HAL_I3C_IT_CFNFIE LL_I3C_IER_CFNFIE /*!< Control FIFO not full interrupt enable */ 918 #define HAL_I3C_IT_SFNEIE LL_I3C_IER_SFNEIE /*!< Status FIFO not empty interrupt enable */ 919 #define HAL_I3C_IT_HJIE LL_I3C_IER_HJIE /*!< Hot-join interrupt enable */ 920 #define HAL_I3C_IT_CRIE LL_I3C_IER_CRIE /*!< Controller-role request interrupt enable */ 921 #define HAL_I3C_IT_IBIIE LL_I3C_IER_IBIIE /*!< IBI request interrupt enable */ 922 #define HAL_I3C_IT_RXTGTENDIE LL_I3C_IER_RXTGTENDIE /*!< Target-initiated read end interrupt enable */ 923 #define HAL_I3C_ALL_CTRL_ITS (uint32_t)(LL_I3C_IER_CFNFIE | LL_I3C_IER_SFNEIE | LL_I3C_IER_HJIE | \ 924 LL_I3C_IER_CRIE | LL_I3C_IER_IBIIE | LL_I3C_IER_RXTGTENDIE) 925 /** 926 * @} 927 */ 928 929 /** @defgroup I3C_FLAGS I3C FLAGS 930 * @{ 931 */ 932 #define HAL_I3C_FLAG_CFEF LL_I3C_EVR_CFEF /*!< Control FIFO not empty flag */ 933 #define HAL_I3C_FLAG_TXFEF LL_I3C_EVR_TXFEF /*!< Tx FIFO empty flag */ 934 #define HAL_I3C_FLAG_CFNFF LL_I3C_EVR_CFNFF /*!< Control FIFO not full flag */ 935 #define HAL_I3C_FLAG_SFNEF LL_I3C_EVR_SFNEF /*!< Status FIFO not empty flag */ 936 #define HAL_I3C_FLAG_TXFNFF LL_I3C_EVR_TXFNFF /*!< Tx FIFO not full flag */ 937 #define HAL_I3C_FLAG_RXFNEF LL_I3C_EVR_RXFNEF /*!< Rx FIFO not empty flag */ 938 #define HAL_I3C_FLAG_RXLASTF LL_I3C_EVR_RXLASTF /*!< Last read data byte/word flag */ 939 #define HAL_I3C_FLAG_TXLASTF LL_I3C_EVR_TXLASTF /*!< Last written data byte/word flag */ 940 #define HAL_I3C_FLAG_FCF LL_I3C_EVR_FCF /*!< Frame complete flag */ 941 #define HAL_I3C_FLAG_RXTGTENDF LL_I3C_EVR_RXTGTENDF /*!< Target-initiated read end flag */ 942 #define HAL_I3C_FLAG_ERRF LL_I3C_EVR_ERRF /*!< Error flag */ 943 #define HAL_I3C_FLAG_IBIF LL_I3C_EVR_IBIF /*!< IBI request flag */ 944 #define HAL_I3C_FLAG_IBIENDF LL_I3C_EVR_IBIENDF /*!< IBI end flag */ 945 #define HAL_I3C_FLAG_CRF LL_I3C_EVR_CRF /*!< Controller-role request flag */ 946 #define HAL_I3C_FLAG_CRUPDF LL_I3C_EVR_CRUPDF /*!< Controller-role update flag */ 947 #define HAL_I3C_FLAG_HJF LL_I3C_EVR_HJF /*!< Hot-join flag */ 948 #define HAL_I3C_FLAG_WKPF LL_I3C_EVR_WKPF /*!< Wakeup flag */ 949 #define HAL_I3C_FLAG_GETF LL_I3C_EVR_GETF /*!< GETxxx CCC flag */ 950 #define HAL_I3C_FLAG_STAF LL_I3C_EVR_STAF /*!< Format 1 GETSTATUS CCC flag */ 951 #define HAL_I3C_FLAG_DAUPDF LL_I3C_EVR_DAUPDF /*!< ENTDAA/RSTDAA/SETNEWDA CCC flag */ 952 #define HAL_I3C_FLAG_MWLUPDF LL_I3C_EVR_MWLUPDF /*!< SETMWL CCC flag */ 953 #define HAL_I3C_FLAG_MRLUPDF LL_I3C_EVR_MRLUPDF /*!< SETMRL CCC flag */ 954 #define HAL_I3C_FLAG_RSTF LL_I3C_EVR_RSTF /*!< Reset pattern flag */ 955 #define HAL_I3C_FLAG_ASUPDF LL_I3C_EVR_ASUPDF /*!< ENTASx CCC flag */ 956 #define HAL_I3C_FLAG_INTUPDF LL_I3C_EVR_INTUPDF /*!< ENEC/DISEC CCC flag */ 957 #define HAL_I3C_FLAG_DEFF LL_I3C_EVR_DEFF /*!< DEFTGTS CCC flag */ 958 #define HAL_I3C_FLAG_GRPF LL_I3C_EVR_GRPF /*!< DEFGRPA CCC flag */ 959 /** 960 * @} 961 */ 962 963 /** @defgroup I3C_BCR_IN_PAYLOAD I3C BCR IN PAYLOAD 964 * @{ 965 */ 966 #define HAL_I3C_BCR_IN_PAYLOAD_SHIFT 48 /*!< BCR field in target payload */ 967 /** 968 * @} 969 */ 970 971 /** @defgroup I3C_PATTERN_CONFIGURATION I3C PATTERN CONFIGURATION 972 * @{ 973 */ 974 #define HAL_I3C_TARGET_RESET_PATTERN 0x00000001U /*!< Target reset pattern */ 975 #define HAL_I3C_HDR_EXIT_PATTERN 0x00000002U /*!< HDR exit pattern */ 976 /** 977 * @} 978 */ 979 980 /** @defgroup I3C_RESET_PATTERN RESET PATTERN 981 * @{ 982 */ 983 #define HAL_I3C_RESET_PATTERN_DISABLE 0x00000000U 984 /*!< Standard STOP condition emitted at the end of a frame */ 985 #define HAL_I3C_RESET_PATTERN_ENABLE I3C_CFGR_RSTPTRN 986 /*!< Reset pattern is inserted before the STOP condition of any emitted frame */ 987 /** 988 * @} 989 */ 990 991 /** 992 * @} 993 */ 994 995 /* Exported macros ---------------------------------------------------------------------------------------------------*/ 996 /** @defgroup I3C_Exported_Macros I3C Exported Macros 997 * @{ 998 */ 999 1000 /** @brief Reset I3C handle state. 1001 * @param __HANDLE__ specifies the I3C Handle. 1002 * @retval None 1003 */ 1004 #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1) 1005 #define __HAL_I3C_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1006 (__HANDLE__)->State = HAL_I3C_STATE_RESET; \ 1007 (__HANDLE__)->MspInitCallback = NULL; \ 1008 (__HANDLE__)->MspDeInitCallback = NULL; \ 1009 } while(0) 1010 #else 1011 #define __HAL_I3C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I3C_STATE_RESET) 1012 #endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ 1013 1014 /** @brief Enable the specified I3C interrupt. 1015 * @param __HANDLE__ specifies the I3C Handle. 1016 * @param __INTERRUPT__ specifies the interrupt source to enable. 1017 * This parameter can be one value or a combination of the following group's values: 1018 * @arg @ref I3C_CONTROLLER_INTERRUPT 1019 * @arg @ref I3C_TARGET_INTERRUPT 1020 * @arg @ref I3C_COMMON_INTERRUPT 1021 * @retval None 1022 */ 1023 #define __HAL_I3C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 1024 1025 /** @brief Disable the specified I3C interrupt. 1026 * @param __HANDLE__ specifies the I3C Handle. 1027 * @param __INTERRUPT__ specifies the interrupt source to disable. 1028 * This parameter can be one value or a combination of the following group's values: 1029 * @arg @ref I3C_CONTROLLER_INTERRUPT 1030 * @arg @ref I3C_TARGET_INTERRUPT 1031 * @arg @ref I3C_COMMON_INTERRUPT 1032 * @retval None 1033 */ 1034 #define __HAL_I3C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 1035 1036 /** @brief Check whether the specified I3C flag is set or not. 1037 * @param __HANDLE__ specifies the I3C Handle. 1038 * @param __FLAG__ specifies the flag to check. 1039 * This parameter can be one value of the group @arg @ref I3C_FLAGS values. 1040 * @retval The new state of __FLAG__ (SET or RESET). 1041 */ 1042 #define __HAL_I3C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->EVR) &\ 1043 (__FLAG__)) == (__FLAG__)) ? SET : RESET) 1044 1045 /** @brief Get Bus Characterics in payload (64bits) receive during ENTDAA procedure. 1046 * @param __PAYLOAD__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. 1047 * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF. 1048 * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF. 1049 */ 1050 #define __HAL_I3C_GET_BCR(__PAYLOAD__) (((uint32_t)((uint64_t)(__PAYLOAD__) >> HAL_I3C_BCR_IN_PAYLOAD_SHIFT)) & \ 1051 I3C_BCR_BCR) 1052 1053 /** @brief Check IBI request capabilities. 1054 * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. 1055 * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. 1056 * @retval The state of IBI request capabilities (ENABLE or DISABLE). 1057 */ 1058 #define __HAL_I3C_GET_IBI_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR1_Msk) >> I3C_BCR_BCR1_Pos) == 1U) \ 1059 ? ENABLE : DISABLE) 1060 1061 /** @brief Check IBI additional data byte capabilities. 1062 * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. 1063 * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. 1064 * @retval The state of IBI additional data byte capabilities (ENABLE or DISABLE). 1065 */ 1066 #define __HAL_I3C_GET_IBI_PAYLOAD(__BCR__) (((((__BCR__) & I3C_BCR_BCR2_Msk) >> I3C_BCR_BCR2_Pos) == 1U) \ 1067 ? ENABLE : DISABLE) 1068 1069 /** @brief Check Controller role request capabilities. 1070 * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. 1071 * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. 1072 * @retval The state of Controller role request capabilities (ENABLE or DISABLE). 1073 */ 1074 #define __HAL_I3C_GET_CR_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR6_Msk) >> I3C_BCR_BCR6_Pos) == 1U) \ 1075 ? ENABLE : DISABLE) 1076 1077 /** 1078 * @} 1079 */ 1080 1081 /* Exported functions ------------------------------------------------------------------------------------------------*/ 1082 /** @addtogroup I3C_Exported_Functions 1083 * @{ 1084 */ 1085 1086 /** @addtogroup I3C_Exported_Functions_Group1 Initialization and de-initialization functions. 1087 * @{ 1088 */ 1089 HAL_StatusTypeDef HAL_I3C_Init(I3C_HandleTypeDef *hi3c); 1090 HAL_StatusTypeDef HAL_I3C_DeInit(I3C_HandleTypeDef *hi3c); 1091 void HAL_I3C_MspInit(I3C_HandleTypeDef *hi3c); 1092 void HAL_I3C_MspDeInit(I3C_HandleTypeDef *hi3c); 1093 /** 1094 * @} 1095 */ 1096 1097 /** @addtogroup I3C_Exported_Functions_Group2 Interrupt and callback functions. 1098 * @{ 1099 */ 1100 #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) 1101 HAL_StatusTypeDef HAL_I3C_RegisterCallback(I3C_HandleTypeDef *hi3c, 1102 HAL_I3C_CallbackIDTypeDef callbackID, 1103 pI3C_CallbackTypeDef pCallback); 1104 HAL_StatusTypeDef HAL_I3C_RegisterNotifyCallback(I3C_HandleTypeDef *hi3c, 1105 pI3C_NotifyCallbackTypeDef pNotifyCallback); 1106 HAL_StatusTypeDef HAL_I3C_RegisterTgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c, 1107 pI3C_TgtReqDynamicAddrCallbackTypeDef pTgtReqAddrCallback); 1108 HAL_StatusTypeDef HAL_I3C_RegisterTgtHotJoinCallback(I3C_HandleTypeDef *hi3c, 1109 pI3C_TgtHotJoinCallbackTypeDef pTgtHotJoinCallback); 1110 HAL_StatusTypeDef HAL_I3C_UnRegisterCallback(I3C_HandleTypeDef *hi3c, HAL_I3C_CallbackIDTypeDef callbackID); 1111 #endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ 1112 1113 HAL_StatusTypeDef HAL_I3C_ActivateNotification(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, 1114 uint32_t interruptMask); 1115 HAL_StatusTypeDef HAL_I3C_DeactivateNotification(I3C_HandleTypeDef *hi3c, uint32_t interruptMask); 1116 void HAL_I3C_CtrlTxCpltCallback(I3C_HandleTypeDef *hi3c); 1117 void HAL_I3C_CtrlRxCpltCallback(I3C_HandleTypeDef *hi3c); 1118 void HAL_I3C_CtrlMultipleXferCpltCallback(I3C_HandleTypeDef *hi3c); 1119 void HAL_I3C_CtrlDAACpltCallback(I3C_HandleTypeDef *hi3c); 1120 void HAL_I3C_TgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c, uint64_t targetPayload); 1121 void HAL_I3C_TgtTxCpltCallback(I3C_HandleTypeDef *hi3c); 1122 void HAL_I3C_TgtRxCpltCallback(I3C_HandleTypeDef *hi3c); 1123 void HAL_I3C_TgtHotJoinCallback(I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress); 1124 void HAL_I3C_NotifyCallback(I3C_HandleTypeDef *hi3c, uint32_t eventId); 1125 void HAL_I3C_AbortCpltCallback(I3C_HandleTypeDef *hi3c); 1126 void HAL_I3C_ErrorCallback(I3C_HandleTypeDef *hi3c); 1127 void HAL_I3C_ER_IRQHandler(I3C_HandleTypeDef *hi3c); 1128 void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c); 1129 /** 1130 * @} 1131 */ 1132 1133 /** @addtogroup I3C_Exported_Functions_Group3 Configuration functions. 1134 * @{ 1135 */ 1136 HAL_StatusTypeDef HAL_I3C_Ctrl_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c, 1137 const LL_I3C_CtrlBusConfTypeDef *pConfig); 1138 HAL_StatusTypeDef HAL_I3C_Tgt_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c, 1139 const LL_I3C_TgtBusConfTypeDef *pConfig); 1140 HAL_StatusTypeDef HAL_I3C_SetConfigFifo(I3C_HandleTypeDef *hi3c, const I3C_FifoConfTypeDef *pConfig); 1141 HAL_StatusTypeDef HAL_I3C_Ctrl_Config(I3C_HandleTypeDef *hi3c, const I3C_CtrlConfTypeDef *pConfig); 1142 HAL_StatusTypeDef HAL_I3C_Tgt_Config(I3C_HandleTypeDef *hi3c, const I3C_TgtConfTypeDef *pConfig); 1143 HAL_StatusTypeDef HAL_I3C_Ctrl_ConfigBusDevices(I3C_HandleTypeDef *hi3c, 1144 const I3C_DeviceConfTypeDef *pDesc, 1145 uint8_t nbDevice); 1146 HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef *hi3c, 1147 const I3C_CCCTypeDef *pCCCDesc, 1148 const I3C_PrivateTypeDef *pPrivateDesc, 1149 I3C_XferTypeDef *pXferData, 1150 uint8_t nbFrame, 1151 uint32_t option); 1152 HAL_StatusTypeDef HAL_I3C_Ctrl_SetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t resetPattern); 1153 HAL_StatusTypeDef HAL_I3C_Ctrl_GetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t *pResetPattern); 1154 /** 1155 * @} 1156 */ 1157 1158 /** @addtogroup I3C_Exported_Functions_Group4 FIFO Management functions. 1159 * @{ 1160 */ 1161 HAL_StatusTypeDef HAL_I3C_FlushAllFifo(I3C_HandleTypeDef *hi3c); 1162 HAL_StatusTypeDef HAL_I3C_FlushTxFifo(I3C_HandleTypeDef *hi3c); 1163 HAL_StatusTypeDef HAL_I3C_FlushRxFifo(I3C_HandleTypeDef *hi3c); 1164 HAL_StatusTypeDef HAL_I3C_FlushControlFifo(I3C_HandleTypeDef *hi3c); 1165 HAL_StatusTypeDef HAL_I3C_FlushStatusFifo(I3C_HandleTypeDef *hi3c); 1166 HAL_StatusTypeDef HAL_I3C_ClearConfigFifo(I3C_HandleTypeDef *hi3c); 1167 HAL_StatusTypeDef HAL_I3C_GetConfigFifo(I3C_HandleTypeDef *hi3c, I3C_FifoConfTypeDef *pConfig); 1168 /** 1169 * @} 1170 */ 1171 1172 /** @addtogroup I3C_Exported_Functions_Group5 Controller operational functions. 1173 * @{ 1174 */ 1175 /* Controller transmit direct write or a broadcast CCC command APIs */ 1176 HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC(I3C_HandleTypeDef *hi3c, 1177 I3C_XferTypeDef *pXferData, 1178 uint32_t timeout); 1179 HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_IT(I3C_HandleTypeDef *hi3c, 1180 I3C_XferTypeDef *pXferData); 1181 HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_DMA(I3C_HandleTypeDef *hi3c, 1182 I3C_XferTypeDef *pXferData); 1183 1184 /* Controller transmit direct read CCC command APIs */ 1185 HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC(I3C_HandleTypeDef *hi3c, 1186 I3C_XferTypeDef *pXferData, 1187 uint32_t timeout); 1188 HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_IT(I3C_HandleTypeDef *hi3c, 1189 I3C_XferTypeDef *pXferData); 1190 HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_DMA(I3C_HandleTypeDef *hi3c, 1191 I3C_XferTypeDef *pXferData); 1192 1193 /* Controller private write APIs */ 1194 HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit(I3C_HandleTypeDef *hi3c, 1195 I3C_XferTypeDef *pXferData, 1196 uint32_t timeout); 1197 HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_IT(I3C_HandleTypeDef *hi3c, 1198 I3C_XferTypeDef *pXferData); 1199 HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_DMA(I3C_HandleTypeDef *hi3c, 1200 I3C_XferTypeDef *pXferData); 1201 1202 /* Controller private read APIs */ 1203 HAL_StatusTypeDef HAL_I3C_Ctrl_Receive(I3C_HandleTypeDef *hi3c, 1204 I3C_XferTypeDef *pXferData, 1205 uint32_t timeout); 1206 HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_IT(I3C_HandleTypeDef *hi3c, 1207 I3C_XferTypeDef *pXferData); 1208 HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_DMA(I3C_HandleTypeDef *hi3c, 1209 I3C_XferTypeDef *pXferData); 1210 1211 /* Controller multiple Direct CCC Command, I3C private or I2C transfer APIs */ 1212 HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_IT(I3C_HandleTypeDef *hi3c, 1213 I3C_XferTypeDef *pXferData); 1214 HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_DMA(I3C_HandleTypeDef *hi3c, 1215 I3C_XferTypeDef *pXferData); 1216 1217 /* Controller assign dynamic address APIs */ 1218 HAL_StatusTypeDef HAL_I3C_Ctrl_SetDynAddr(I3C_HandleTypeDef *hi3c, uint8_t devAddress); 1219 HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign_IT(I3C_HandleTypeDef *hi3c, uint32_t dynOption); 1220 HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef *hi3c, 1221 uint64_t *target_payload, 1222 uint32_t dynOption, 1223 uint32_t timeout); 1224 /* Controller check device ready APIs */ 1225 HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI3C_Ready(I3C_HandleTypeDef *hi3c, 1226 uint8_t devAddress, 1227 uint32_t trials, 1228 uint32_t timeout); 1229 HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c, 1230 uint8_t devAddress, 1231 uint32_t trials, 1232 uint32_t timeout); 1233 /* Controller arbitration APIs */ 1234 HAL_StatusTypeDef HAL_I3C_Ctrl_GenerateArbitration(I3C_HandleTypeDef *hi3c, uint32_t timeout); 1235 1236 /** 1237 * @} 1238 */ 1239 1240 /** @addtogroup I3C_Exported_Functions_Group6 Target operational functions. 1241 * @{ 1242 */ 1243 HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout); 1244 HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); 1245 HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); 1246 HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout); 1247 HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); 1248 HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); 1249 HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq(I3C_HandleTypeDef *hi3c, uint32_t timeout); 1250 HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq_IT(I3C_HandleTypeDef *hi3c); 1251 HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq(I3C_HandleTypeDef *hi3c, uint8_t *pAddress, uint32_t timeout); 1252 HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq_IT(I3C_HandleTypeDef *hi3c); 1253 HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq(I3C_HandleTypeDef *hi3c, const uint8_t *pPayload, 1254 uint8_t payloadSize, uint32_t timeout); 1255 HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq_IT(I3C_HandleTypeDef *hi3c, const uint8_t *pPayload, uint8_t payloadSize); 1256 /** 1257 * @} 1258 */ 1259 1260 /** @addtogroup I3C_Exported_Functions_Group7 Generic and Common functions. 1261 * @{ 1262 */ 1263 HAL_StatusTypeDef HAL_I3C_Abort_IT(I3C_HandleTypeDef *hi3c); 1264 HAL_I3C_StateTypeDef HAL_I3C_GetState(const I3C_HandleTypeDef *hi3c); 1265 HAL_I3C_ModeTypeDef HAL_I3C_GetMode(const I3C_HandleTypeDef *hi3c); 1266 uint32_t HAL_I3C_GetError(const I3C_HandleTypeDef *hi3c); 1267 HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c, 1268 uint32_t notifyId, 1269 I3C_CCCInfoTypeDef *pCCCInfo); 1270 HAL_StatusTypeDef HAL_I3C_Get_ENTDAA_Payload_Info(I3C_HandleTypeDef *hi3c, 1271 uint64_t ENTDAA_payload, 1272 I3C_ENTDAAPayloadTypeDef *pENTDAA_payload); 1273 /** 1274 * @} 1275 */ 1276 1277 /** 1278 * @} 1279 */ 1280 1281 /* Private constants -------------------------------------------------------------------------------------------------*/ 1282 /** @defgroup I3C_Private_Constants I3C Private Constants 1283 * @{ 1284 */ 1285 1286 /** 1287 * @} 1288 */ 1289 1290 /* Private macros ----------------------------------------------------------------------------------------------------*/ 1291 /** @defgroup I3C_Private_Macro I3C Private Macros 1292 * @{ 1293 */ 1294 #define IS_I3C_MODE(__MODE__) (((__MODE__) == HAL_I3C_MODE_NONE) || \ 1295 ((__MODE__) == HAL_I3C_MODE_CONTROLLER) || \ 1296 ((__MODE__) == HAL_I3C_MODE_TARGET)) 1297 1298 #define IS_I3C_INTERRUPTMASK(__MODE__, __ITMASK__) (((__MODE__) == HAL_I3C_MODE_CONTROLLER) ? \ 1299 ((((__ITMASK__) & HAL_I3C_ALL_CTRL_ITS) != 0x0U) || \ 1300 (((__ITMASK__) & HAL_I3C_ALL_COMMON_ITS) != 0x0U)) : \ 1301 ((((__ITMASK__) & HAL_I3C_ALL_TGT_ITS) != 0x0U) || \ 1302 (((__ITMASK__) & HAL_I3C_ALL_COMMON_ITS) != 0x0U))) 1303 1304 #define IS_I3C_ENTDAA_OPTION(__OPTION__) (((__OPTION__) == I3C_RSTDAA_THEN_ENTDAA) || \ 1305 ((__OPTION__) == I3C_ONLY_ENTDAA)) 1306 1307 #define IS_I3C_SDAHOLDTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_0_5) || \ 1308 ((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_1_5)) 1309 1310 #define IS_I3C_WAITTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_0) || \ 1311 ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_1) || \ 1312 ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_2) || \ 1313 ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_3)) 1314 1315 #define IS_I3C_TXFIFOTHRESHOLD_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_TXFIFO_THRESHOLD_1_4) || \ 1316 ((__VALUE__) == HAL_I3C_TXFIFO_THRESHOLD_4_4)) 1317 1318 #define IS_I3C_RXFIFOTHRESHOLD_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_RXFIFO_THRESHOLD_1_4) || \ 1319 ((__VALUE__) == HAL_I3C_RXFIFO_THRESHOLD_4_4)) 1320 1321 #define IS_I3C_CONTROLFIFOSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_CONTROLFIFO_DISABLE) || \ 1322 ((__VALUE__) == HAL_I3C_CONTROLFIFO_ENABLE)) 1323 1324 #define IS_I3C_STATUSFIFOSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_STATUSFIFO_DISABLE) || \ 1325 ((__VALUE__) == HAL_I3C_STATUSFIFO_ENABLE)) 1326 1327 #define IS_I3C_DEVICE_VALUE(__VALUE__) (((__VALUE__) >= 1U) && ((__VALUE__) <= 4U)) 1328 1329 #define IS_I3C_DYNAMICADDRESS_VALUE(__VALUE__) ((__VALUE__) <= 0x7FU) 1330 1331 #define IS_I3C_FUNCTIONALSTATE_VALUE(__VALUE__) (((__VALUE__) == DISABLE) || \ 1332 ((__VALUE__) == ENABLE)) 1333 1334 #define IS_I3C_HANDOFFACTIVITYSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_0) || \ 1335 ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_1) || \ 1336 ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_2) || \ 1337 ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_3)) 1338 1339 #define IS_I3C_TSCOTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS) || \ 1340 ((__VALUE__) == HAL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS)) 1341 1342 #define IS_I3C_MAXSPEEDDATA_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_1 ) || \ 1343 ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_LSB) || \ 1344 ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_MID) || \ 1345 ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_MSB)) 1346 1347 #define IS_I3C_IBIPAYLOADSIZE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_PAYLOAD_EMPTY ) || \ 1348 ((__VALUE__) == HAL_I3C_PAYLOAD_1_BYTE ) || \ 1349 ((__VALUE__) == HAL_I3C_PAYLOAD_2_BYTES) || \ 1350 ((__VALUE__) == HAL_I3C_PAYLOAD_3_BYTES) || \ 1351 ((__VALUE__) == HAL_I3C_PAYLOAD_4_BYTES)) 1352 1353 #define IS_I3C_MIPIIDENTIFIER_VALUE(__VALUE__) ((__VALUE__) <= 0x0FU) 1354 1355 #define IS_I3C_MAXREADTURNARROUND_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU) 1356 1357 #define I3C_CHECK_IT_SOURCE(__IER__, __IT__) ((((__IER__) & (__IT__)) == (__IT__)) ? SET : RESET) 1358 1359 #define I3C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 1360 1361 #define IS_I3C_DMASOURCEBYTE_VALUE(__VALUE__) ((__VALUE__) == DMA_SRC_DATAWIDTH_BYTE) 1362 1363 #define IS_I3C_DMASOURCEWORD_VALUE(__VALUE__) ((__VALUE__) == DMA_SRC_DATAWIDTH_WORD) 1364 1365 #define IS_I3C_DMADESTINATIONBYTE_VALUE(__VALUE__) ((__VALUE__) == DMA_DEST_DATAWIDTH_BYTE) 1366 1367 #define IS_I3C_DMADESTINATIONWORD_VALUE(__VALUE__) ((__VALUE__) == DMA_DEST_DATAWIDTH_WORD) 1368 1369 #define I3C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) 1370 #define IS_I3C_RESET_PATTERN(__RSTPTRN__) (((__RSTPTRN__) == HAL_I3C_RESET_PATTERN_ENABLE) || \ 1371 ((__RSTPTRN__) == HAL_I3C_RESET_PATTERN_DISABLE)) 1372 /** 1373 * @} 1374 */ 1375 1376 /* Private functions -------------------------------------------------------------------------------------------------*/ 1377 /** @defgroup I3C_Private_Functions I3C Private Functions 1378 * @{ 1379 */ 1380 /* Private functions are defined in stm32n6xx_hal_i3c.c file */ 1381 /** 1382 * @} 1383 */ 1384 1385 /** 1386 * @} 1387 */ 1388 1389 /** 1390 * @} 1391 */ 1392 1393 #ifdef __cplusplus 1394 } 1395 #endif 1396 1397 #endif /* STM32N6xx_HAL_I3C_H */ 1398
