1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_HAL_CORTEX_H 21 #define STM32N6xx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 /** @addtogroup STM32N6xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @brief CORTEX HAL module driver 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 41 * @{ 42 */ 43 44 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 45 * @brief MPU Region initialization structure 46 * @{ 47 */ 48 typedef struct 49 { 50 uint8_t Enable; /*!< Specifies the status of the region. 51 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 52 uint8_t Number; /*!< Specifies the number of the region to protect. 53 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 54 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 55 uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ 56 uint8_t AttributesIndex; /*!< Specifies the memory attributes index. 57 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 58 uint8_t AccessPermission; /*!< Specifies the region access permission type. 59 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 60 uint8_t DisableExec; /*!< Specifies the instruction access status. 61 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 62 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 63 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 64 } MPU_Region_InitTypeDef; 65 /** 66 * @} 67 */ 68 69 /** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes Initialization Structure Definition 70 * @{ 71 */ 72 typedef struct 73 { 74 uint8_t Number; /*!< Specifies the number of the memory attributes to configure. 75 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 76 77 uint8_t Attributes; /*!< Specifies the memory attributes vue. 78 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ 79 80 } MPU_Attributes_InitTypeDef; 81 /** 82 * @} 83 */ 84 85 /** 86 * @} 87 */ 88 89 /* Exported constants --------------------------------------------------------*/ 90 91 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 92 * @{ 93 */ 94 95 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 96 * @{ 97 */ 98 #define NVIC_PRIORITYGROUP_0 7U /*!< 0 bit for pre-emption priority, 99 4 bits for subpriority */ 100 #define NVIC_PRIORITYGROUP_1 6U /*!< 1 bit for pre-emption priority, 101 3 bits for subpriority */ 102 #define NVIC_PRIORITYGROUP_2 5U /*!< 2 bits for pre-emption priority, 103 2 bits for subpriority */ 104 #define NVIC_PRIORITYGROUP_3 4U /*!< 3 bits for pre-emption priority, 105 1 bit for subpriority */ 106 #define NVIC_PRIORITYGROUP_4 3U /*!< 4 bits for pre-emption priority, 107 0 bit for subpriority */ 108 /** 109 * @} 110 */ 111 112 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 113 * @{ 114 */ 115 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0U 116 #define SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk 117 118 /** 119 * @} 120 */ 121 122 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 123 * @{ 124 */ 125 #define MPU_HFNMI_PRIVDEF_NONE 0U 126 #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk 127 #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk 128 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 129 /** 130 * @} 131 */ 132 133 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 134 * @{ 135 */ 136 #define MPU_REGION_ENABLE 1U 137 #define MPU_REGION_DISABLE 0U 138 /** 139 * @} 140 */ 141 142 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 143 * @{ 144 */ 145 #define MPU_INSTRUCTION_ACCESS_ENABLE 0U 146 #define MPU_INSTRUCTION_ACCESS_DISABLE 1U 147 /** 148 * @} 149 */ 150 151 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 152 * @{ 153 */ 154 #define MPU_ACCESS_NOT_SHAREABLE 0U 155 #define MPU_ACCESS_OUTER_SHAREABLE 2U 156 #define MPU_ACCESS_INNER_SHAREABLE 3U 157 /** 158 * @} 159 */ 160 161 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 162 * @{ 163 */ 164 #define MPU_REGION_PRIV_RW 0U 165 #define MPU_REGION_ALL_RW 1U 166 #define MPU_REGION_PRIV_RO 2U 167 #define MPU_REGION_ALL_RO 3U 168 /** 169 * @} 170 */ 171 172 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 173 * @{ 174 */ 175 #define MPU_REGION_NUMBER0 0U 176 #define MPU_REGION_NUMBER1 1U 177 #define MPU_REGION_NUMBER2 2U 178 #define MPU_REGION_NUMBER3 3U 179 #define MPU_REGION_NUMBER4 4U 180 #define MPU_REGION_NUMBER5 5U 181 #define MPU_REGION_NUMBER6 6U 182 #define MPU_REGION_NUMBER7 7U 183 #define MPU_REGION_NUMBER8 8U 184 #define MPU_REGION_NUMBER9 9U 185 #define MPU_REGION_NUMBER10 10U 186 #define MPU_REGION_NUMBER11 11U 187 #define MPU_REGION_NUMBER12 12U 188 #define MPU_REGION_NUMBER13 13U 189 #define MPU_REGION_NUMBER14 14U 190 #define MPU_REGION_NUMBER15 15U 191 /** 192 * @} 193 */ 194 195 /** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number 196 * @{ 197 */ 198 #define MPU_ATTRIBUTES_NUMBER0 0U 199 #define MPU_ATTRIBUTES_NUMBER1 1U 200 #define MPU_ATTRIBUTES_NUMBER2 2U 201 #define MPU_ATTRIBUTES_NUMBER3 3U 202 #define MPU_ATTRIBUTES_NUMBER4 4U 203 #define MPU_ATTRIBUTES_NUMBER5 5U 204 #define MPU_ATTRIBUTES_NUMBER6 6U 205 #define MPU_ATTRIBUTES_NUMBER7 7U 206 /** 207 * @} 208 */ 209 210 /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes 211 * @{ 212 */ 213 214 /* Device memory attributes */ 215 #define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ 216 #define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ 217 #define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ 218 #define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ 219 220 /* Normal Memory attributes */ 221 /* Note that these attributes need to be set for both inner AND outer attributes. 222 These defines should be used with the INNER_OUTER macro if they are the same for inner and outer. */ 223 /* - Non-cacheable memory attribute*/ 224 #define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ 225 226 /* - Cacheable memory attributes*/ 227 #define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ 228 #define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ 229 230 #define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ 231 #define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ 232 233 #define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ 234 #define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ 235 #define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ 236 #define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ 237 /** 238 * @} 239 */ 240 241 /** 242 * @} 243 */ 244 245 /* Exported macros -----------------------------------------------------------*/ 246 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 247 * @{ 248 */ 249 250 /** @defgroup CORTEX_MPU_Normal_Memory_Attributes CORTEX MPU Normal Memory Attributes 251 * @{ 252 */ 253 /* __ATTR__ being a combination of MPU Normal memory attributes */ 254 #define OUTER(__ATTR__) ((__ATTR__) << 4U) 255 #define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) 256 /** 257 * @} 258 */ 259 260 /** 261 * @} 262 */ 263 264 /* Exported functions --------------------------------------------------------*/ 265 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 266 * @{ 267 */ 268 269 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 270 * @brief Initialization and Configuration functions 271 * @{ 272 */ 273 /* Initialization and Configuration functions *****************************/ 274 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 275 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 276 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 277 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 278 void HAL_NVIC_SystemReset(void); 279 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 280 /** 281 * @} 282 */ 283 284 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 285 * @brief Cortex control functions 286 * @{ 287 */ 288 /* Peripheral Control functions ***********************************************/ 289 uint32_t HAL_NVIC_GetPriorityGrouping(void); 290 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, 291 uint32_t *pPreemptPriority, uint32_t *pSubPriority); 292 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 293 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 294 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 295 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 296 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 297 void HAL_SYSTICK_IRQHandler(void); 298 void HAL_SYSTICK_Callback(void); 299 void HAL_CORTEX_ClearEvent(void); 300 void HAL_MPU_Enable(uint32_t MPU_Control); 301 void HAL_MPU_Disable(void); 302 void HAL_MPU_EnableRegion(uint32_t RegionNumber); 303 void HAL_MPU_DisableRegion(uint32_t RegionNumber); 304 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit); 305 void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit); 306 #ifdef MPU_NS 307 void HAL_MPU_Enable_NS(uint32_t MPU_Control); 308 void HAL_MPU_Disable_NS(void); 309 void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber); 310 void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber); 311 void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *pMPU_RegionInit); 312 void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit); 313 #endif /* MPU_NS */ 314 /** 315 * @} 316 */ 317 318 /** 319 * @} 320 */ 321 322 /* Private types -------------------------------------------------------------*/ 323 /* Private variables ---------------------------------------------------------*/ 324 /* Private constants ---------------------------------------------------------*/ 325 /* Private macros ------------------------------------------------------------*/ 326 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 327 * @{ 328 */ 329 #define IS_NVIC_PRIORITY_INTERRUPT(__IT__) (((__IT__) > HardFault_IRQn) && ((__IT__) != DebugMonitor_IRQn)) 330 331 #define IS_NVIC_PRIORITY_GROUP(__GROUP__) (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \ 332 ((__GROUP__) == NVIC_PRIORITYGROUP_1) || \ 333 ((__GROUP__) == NVIC_PRIORITYGROUP_2) || \ 334 ((__GROUP__) == NVIC_PRIORITYGROUP_3) || \ 335 ((__GROUP__) == NVIC_PRIORITYGROUP_4)) 336 337 #define IS_NVIC_PREEMPTION_PRIORITY(__PRIO__, __PRIOGRP__) (((__PRIO__) < (1UL << __NVIC_PRIO_BITS)) && \ 338 ((__PRIO__) < (1UL << (7U - (__PRIOGRP__))))) 339 340 #define IS_NVIC_SUB_PRIORITY(__PRIO__, __PRIOGRP__) (((__PRIOGRP__) < (7U - __NVIC_PRIO_BITS)) ? \ 341 ((__PRIO__) < 1U): \ 342 ((__PRIO__) < (1UL << ((__PRIOGRP__) - (7U - __NVIC_PRIO_BITS))))) 343 344 #define IS_NVIC_DEVICE_IRQ(__IRQ__) ((__IRQ__) > SysTick_IRQn) 345 346 #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ 347 ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 348 349 #define IS_MPU_REGION_ENABLE(__STATE__) (((__STATE__) == MPU_REGION_ENABLE) || \ 350 ((__STATE__) == MPU_REGION_DISABLE)) 351 352 #define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 353 ((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE)) 354 355 #define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_OUTER_SHAREABLE) || \ 356 ((__STATE__) == MPU_ACCESS_INNER_SHAREABLE) || \ 357 ((__STATE__) == MPU_ACCESS_NOT_SHAREABLE)) 358 359 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_PRIV_RW) || \ 360 ((__TYPE__) == MPU_REGION_ALL_RW) || \ 361 ((__TYPE__) == MPU_REGION_PRIV_RO) || \ 362 ((__TYPE__) == MPU_REGION_ALL_RO)) 363 364 #define IS_MPU_REGION_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_REGION_NUMBER0) || \ 365 ((__NUMBER__) == MPU_REGION_NUMBER1) || \ 366 ((__NUMBER__) == MPU_REGION_NUMBER2) || \ 367 ((__NUMBER__) == MPU_REGION_NUMBER3) || \ 368 ((__NUMBER__) == MPU_REGION_NUMBER4) || \ 369 ((__NUMBER__) == MPU_REGION_NUMBER5) || \ 370 ((__NUMBER__) == MPU_REGION_NUMBER6) || \ 371 ((__NUMBER__) == MPU_REGION_NUMBER7) || \ 372 ((__NUMBER__) == MPU_REGION_NUMBER8) || \ 373 ((__NUMBER__) == MPU_REGION_NUMBER9) || \ 374 ((__NUMBER__) == MPU_REGION_NUMBER10) || \ 375 ((__NUMBER__) == MPU_REGION_NUMBER11) || \ 376 ((__NUMBER__) == MPU_REGION_NUMBER12) || \ 377 ((__NUMBER__) == MPU_REGION_NUMBER13) || \ 378 ((__NUMBER__) == MPU_REGION_NUMBER14) || \ 379 ((__NUMBER__) == MPU_REGION_NUMBER15)) 380 381 #define IS_MPU_ATTRIBUTES_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_ATTRIBUTES_NUMBER0) || \ 382 ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER1) || \ 383 ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER2) || \ 384 ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER3) || \ 385 ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER4) || \ 386 ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER5) || \ 387 ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER6) || \ 388 ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER7)) 389 390 391 /** 392 * @} 393 */ 394 395 /** 396 * @} 397 */ 398 399 /** 400 * @} 401 */ 402 403 #ifdef __cplusplus 404 } 405 #endif 406 407 #endif /* STM32N6xx_HAL_CORTEX_H */ 408
