1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_cacheaxi.h 4 * @author MCD Application Team 5 * @brief Header file of CACHEAXI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion ------------------------------------*/ 20 #ifndef STM32N6xx_HAL_CACHEAXI_H 21 #define STM32N6xx_HAL_CACHEAXI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes -----------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 /** @addtogroup STM32N6xx_HAL_Driver 31 * @{ 32 */ 33 34 #if defined (CACHEAXI) 35 /** @addtogroup CACHEAXI 36 * @{ 37 */ 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup CACHEAXI_Exported_Types CACHEAXI Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief HAL State structures definition 46 */ 47 typedef enum 48 { 49 HAL_CACHEAXI_STATE_RESET = 0x00U, /*!< CACHEAXI not yet initialized or disabled */ 50 HAL_CACHEAXI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 51 HAL_CACHEAXI_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 52 HAL_CACHEAXI_STATE_TIMEOUT = 0x05U, /*!< Timeout state */ 53 HAL_CACHEAXI_STATE_ERROR = 0x06U, /*!< CACHEAXI state error */ 54 } HAL_CACHEAXI_StateTypeDef; 55 56 /** @defgroup CACHEAXI_Configuration_Structure_definition CACHEAXI Configuration Structure definition 57 * @brief CACHEAXI Configuration Structure definition 58 * @{ 59 */ 60 #if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1) 61 typedef struct __CACHEAXI_HandleTypeDef 62 #else 63 typedef struct 64 #endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */ 65 { 66 CACHEAXI_TypeDef *Instance; /*!< CACHEAXI register base address. */ 67 __IO HAL_CACHEAXI_StateTypeDef State; 68 __IO uint32_t ErrorCode; 69 70 #if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1) 71 void (* ErrorCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi); 72 void (* CleanByAddrCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi); 73 void (* InvalidateCompleteCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi); 74 void (* CleanAndInvalidateByAddrCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi); 75 76 void (* MspInitCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi); 77 void (* MspDeInitCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi); 78 #endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */ 79 } CACHEAXI_HandleTypeDef; 80 81 #if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1) 82 /** 83 * @brief HAL CACHEAXI Callback ID enumeration definition 84 */ 85 typedef enum 86 { 87 HAL_CACHEAXI_CLEAN_BY_ADDRESS_CB_ID = 0x00U, /*!< CACHEAXI Clean By Address callback ID */ 88 HAL_CACHEAXI_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID = 0x01U, /*!< CACHEAXI Clean And Invalidate By Address callback ID */ 89 HAL_CACHEAXI_INVALIDATE_COMPLETE_CB_ID = 0x02U, /*!< CACHEAXI Invalidate Complete ID */ 90 HAL_CACHEAXI_ERROR_CB_ID = 0x03U, /*!< CACHEAXI Error callback ID */ 91 92 HAL_CACHEAXI_MSPINIT_CB_ID = 0x04U, /*!< CACHEAXI Msp Init callback ID */ 93 HAL_CACHEAXI_MSPDEINIT_CB_ID = 0x05U /*!< CACHEAXI Msp DeInit callback ID */ 94 } HAL_CACHEAXI_CallbackIDTypeDef; 95 96 /** 97 * @brief HAL CACHEAXI Callback pointer definition 98 */ 99 /*!< Pointer to a CACHEAXI common callback function */ 100 typedef void (*pCACHEAXI_CallbackTypeDef)(CACHEAXI_HandleTypeDef *hcacheaxi); 101 102 #endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */ 103 104 /** 105 * @} 106 */ 107 108 /** 109 * @} 110 */ 111 112 /* Exported constants -------------------------------------------------------*/ 113 /** @defgroup CACHEAXI_Exported_Constants CACHEAXI Exported Constants 114 * @{ 115 */ 116 117 /** @defgroup CACHEAXI_Error_Code CACHEAXI Error Code 118 * @{ 119 */ 120 #define HAL_CACHEAXI_ERROR_NONE 0x00000000U /*!< No error */ 121 #define HAL_CACHEAXI_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ 122 #define HAL_CACHEAXI_ERROR_EVICTION_CLEAN 0x00000020U /*!< Eviction or clean operation write-back error */ 123 #define HAL_CACHEAXI_ERROR_INVALID_OPERATION 0x00000040U /*!< Invalid operation */ 124 #if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1) 125 #define HAL_CACHEAXI_ERROR_INVALID_CALLBACK 0x00000080U /*!< Invalid callback error */ 126 #endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */ 127 128 /** 129 * @} 130 */ 131 132 /** @defgroup CACHEAXI_Monitor_Type Monitor type 133 * @{ 134 */ 135 #define CACHEAXI_MONITOR_READ_HIT CACHEAXI_CR1_RHITMEN /*!< Read Hit monitoring */ 136 #define CACHEAXI_MONITOR_READ_MISS CACHEAXI_CR1_RMISSMEN /*!< Read Miss monitoring */ 137 #define CACHEAXI_MONITOR_WRITE_HIT CACHEAXI_CR1_WHITMEN /*!< Write Hit monitoring */ 138 #define CACHEAXI_MONITOR_WRITE_MISS CACHEAXI_CR1_WMISSMEN /*!< Write Miss monitoring */ 139 #define CACHEAXI_MONITOR_READALLOC_MISS CACHEAXI_CR1_RAMMEN /*!< Read-allocate Miss monitoring */ 140 #define CACHEAXI_MONITOR_WRITEALLOC_MISS CACHEAXI_CR1_WAMMEN /*!< Write-allocate Miss monitoring */ 141 #define CACHEAXI_MONITOR_WRITETHROUGH CACHEAXI_CR1_WTMEN /*!< Write-through monitoring */ 142 #define CACHEAXI_MONITOR_EVICTION CACHEAXI_CR1_EVIMEN /*!< Eviction monitoring */ 143 #define CACHEAXI_MONITOR_ALL (CACHEAXI_CR1_RHITMEN | CACHEAXI_CR1_RMISSMEN | \ 144 CACHEAXI_CR1_WHITMEN | CACHEAXI_CR1_WMISSMEN | \ 145 CACHEAXI_CR1_RAMMEN | CACHEAXI_CR1_WAMMEN | \ 146 CACHEAXI_CR1_WTMEN | CACHEAXI_CR1_EVIMEN ) 147 /** 148 * @} 149 */ 150 151 /** @defgroup CACHEAXI_Interrupts Interrupts 152 * @{ 153 */ 154 #define CACHEAXI_IT_BUSYEND CACHEAXI_IER_BSYENDIE /*!< Busy end interrupt */ 155 #define CACHEAXI_IT_ERROR CACHEAXI_IER_ERRIE /*!< Cache error interrupt */ 156 #define CACHEAXI_IT_CMDEND CACHEAXI_IER_CMDENDIE /*!< Command end interrupt */ 157 /** 158 * @} 159 */ 160 161 /** @defgroup CACHEAXI_Flags Flags 162 * @{ 163 */ 164 #define CACHEAXI_FLAG_BUSY CACHEAXI_SR_BUSYF /*!< Busy flag */ 165 #define CACHEAXI_FLAG_BUSYEND CACHEAXI_SR_BSYENDF /*!< Busy end flag */ 166 #define CACHEAXI_FLAG_ERROR CACHEAXI_SR_ERRF /*!< Cache error flag */ 167 #define CACHEAXI_FLAG_BUSYCMD CACHEAXI_SR_BUSYCMDF /*!< Busy command flag */ 168 #define CACHEAXI_FLAG_CMDEND CACHEAXI_SR_CMDENDF /*!< Command end flag */ 169 /** 170 * @} 171 */ 172 173 /** 174 * @} 175 */ 176 177 /* Exported macros ----------------------------------------------------------*/ 178 /** @defgroup CACHEAXI_Exported_Macros CACHEAXI Exported Macros 179 * @{ 180 */ 181 182 /** @brief Enable CACHEAXI interrupts. 183 * @param __HANDLE__ specifies the CACHEAXI handle. 184 * @param __INTERRUPT__ specifies the CACHEAXI interrupt sources to be enabled. 185 * This parameter can be any combination of the following values: 186 * @arg @ref CACHEAXI_IT_BUSYEND Busy end interrupt 187 * @arg @ref CACHEAXI_IT_ERROR Cache error interrupt 188 * @arg @ref CACHEAXI_IT_CMDEND Cache Command end interrupt 189 * @retval None 190 */ 191 #define __HAL_CACHEAXI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) 192 193 /** @brief Disable CACHEAXI interrupts. 194 * @param __HANDLE__ specifies the CACHEAXI handle. 195 * @param __INTERRUPT__ specifies the CACHEAXI interrupt sources to be disabled. 196 * This parameter can be any combination of the following values: 197 * @arg @ref CACHEAXI_IT_BUSYEND Busy end interrupt 198 * @arg @ref CACHEAXI_IT_ERROR Cache error interrupt 199 * @arg @ref CACHEAXI_IT_CMDEND Cache Command end interrupt 200 * @retval None 201 */ 202 #define __HAL_CACHEAXI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) 203 204 /** @brief Check whether the specified CACHEAXI interrupt source is enabled or not. 205 * @param __HANDLE__ specifies the CACHEAXI handle. 206 * @param __INTERRUPT__ specifies the CACHEAXI interrupt source to check. 207 * This parameter can be any combination of the following values: 208 * @arg @ref CACHEAXI_IT_BUSYEND Busy end interrupt 209 * @arg @ref CACHEAXI_IT_ERROR Cache error interrupt 210 * @arg @ref CACHEAXI_IT_CMDEND Cache Command end interrupt 211 * 212 * @retval The state of __INTERRUPT__ (SET or RESET). 213 */ 214 #define __HAL_CACHEAXI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 215 ((READ_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 216 217 /** @brief Check whether the selected CACHEAXI flag is set or not. 218 * @param __HANDLE__ specifies the CACHEAXI handle. 219 * @param __FLAG__ specifies the flag to check. 220 * This parameter can be one of the following values: 221 * @arg @ref CACHEAXI_FLAG_BUSY Busy flag 222 * @arg @ref CACHEAXI_FLAG_BUSYEND Busy end flag 223 * @arg @ref CACHEAXI_FLAG_ERROR Cache error flag 224 * @arg @ref CACHEAXI_FLAG_BUSYCMD Cache Busy command flag 225 * @arg @ref CACHEAXI_FLAG_CMDEND Cache command end flag 226 * @retval The state of __FLAG__ (0 or 1). 227 */ 228 #define __HAL_CACHEAXI_GET_FLAG(__HANDLE__, __FLAG__) \ 229 ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? 1U : 0U) 230 231 /** @brief Clear the selected CACHEAXI flags. 232 * @param __HANDLE__ specifies the CACHEAXI handle. 233 * @param __FLAG__ specifies the CACHEAXI flags to clear. 234 * This parameter can be any combination of the following values: 235 * @arg @ref CACHEAXI_FLAG_BUSYEND Busy end flag 236 * @arg @ref CACHEAXI_FLAG_ERROR Cache error flag 237 * @arg @ref CACHEAXI_FLAG_CMDEND Cache command end flag 238 */ 239 #define __HAL_CACHEAXI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 240 241 /** 242 * @} 243 */ 244 245 /* Exported functions -------------------------------------------------------*/ 246 /** @defgroup CACHEAXI_Exported_Functions CACHEAXI Exported Functions 247 * @brief CACHEAXI Exported functions 248 * @{ 249 */ 250 251 /** @defgroup CACHEAXI_Exported_Functions_Group1 Initialization and De-Initialization Functions 252 * @brief Initialization and De-Initialization Functions 253 * @{ 254 */ 255 HAL_StatusTypeDef HAL_CACHEAXI_Init(CACHEAXI_HandleTypeDef *hcacheaxi); 256 HAL_StatusTypeDef HAL_CACHEAXI_DeInit(CACHEAXI_HandleTypeDef *hcacheaxi); 257 void HAL_CACHEAXI_MspInit(CACHEAXI_HandleTypeDef *hcacheaxi); 258 void HAL_CACHEAXI_MspDeInit(CACHEAXI_HandleTypeDef *hcacheaxi); 259 /** 260 * @} 261 */ 262 263 /** @defgroup CACHEAXI_Exported_Functions_Group2 I/O Operation Functions 264 * @brief I/O Operation Functions 265 * @{ 266 */ 267 /* Peripheral Control functions ***/ 268 HAL_StatusTypeDef HAL_CACHEAXI_Enable(CACHEAXI_HandleTypeDef *hcacheaxi); 269 HAL_StatusTypeDef HAL_CACHEAXI_Disable(CACHEAXI_HandleTypeDef *hcacheaxi); 270 uint32_t HAL_CACHEAXI_IsEnabled(const CACHEAXI_HandleTypeDef *hcacheaxi); 271 272 /*** Cache maintenance in blocking mode (Polling) ***/ 273 HAL_StatusTypeDef HAL_CACHEAXI_Invalidate(CACHEAXI_HandleTypeDef *hcacheaxi); 274 HAL_StatusTypeDef HAL_CACHEAXI_CleanByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr, 275 uint32_t dSize); 276 HAL_StatusTypeDef HAL_CACHEAXI_CleanInvalidByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr, 277 uint32_t dSize); 278 279 /*** Cache maintenance in non-blocking mode (Interrupt) ***/ 280 HAL_StatusTypeDef HAL_CACHEAXI_Invalidate_IT(CACHEAXI_HandleTypeDef *hcacheaxi); 281 HAL_StatusTypeDef HAL_CACHEAXI_CleanByAddr_IT(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr, 282 uint32_t dSize); 283 HAL_StatusTypeDef HAL_CACHEAXI_CleanInvalidByAddr_IT(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr, 284 uint32_t dSize); 285 286 /*** IRQHandler and Callbacks ***/ 287 void HAL_CACHEAXI_IRQHandler(CACHEAXI_HandleTypeDef *hcacheaxi); 288 void HAL_CACHEAXI_ErrorCallback(CACHEAXI_HandleTypeDef *hcacheaxi); 289 void HAL_CACHEAXI_CleanByAddrCallback(CACHEAXI_HandleTypeDef *hcacheaxi); 290 void HAL_CACHEAXI_InvalidateCompleteCallback(CACHEAXI_HandleTypeDef *hcacheaxi); 291 void HAL_CACHEAXI_CleanAndInvalidateByAddrCallback(CACHEAXI_HandleTypeDef *hcacheaxi); 292 293 #if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1) 294 /* Callbacks Register/UnRegister functions ***/ 295 HAL_StatusTypeDef HAL_CACHEAXI_RegisterCallback(CACHEAXI_HandleTypeDef *hcacheaxi, 296 HAL_CACHEAXI_CallbackIDTypeDef CallbackID, 297 pCACHEAXI_CallbackTypeDef pCallback); 298 HAL_StatusTypeDef HAL_CACHEAXI_UnRegisterCallback(CACHEAXI_HandleTypeDef *hcacheaxi, 299 HAL_CACHEAXI_CallbackIDTypeDef CallbackID); 300 #endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */ 301 302 /*** Performance instruction cache monitoring functions ***/ 303 uint32_t HAL_CACHEAXI_Monitor_GetReadHitValue(const CACHEAXI_HandleTypeDef *hcacheaxi); 304 uint32_t HAL_CACHEAXI_Monitor_GetReadMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi); 305 uint32_t HAL_CACHEAXI_Monitor_GetWriteHitValue(const CACHEAXI_HandleTypeDef *hcacheaxi); 306 uint32_t HAL_CACHEAXI_Monitor_GetWriteMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi); 307 uint32_t HAL_CACHEAXI_Monitor_GetReadAllocMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi); 308 uint32_t HAL_CACHEAXI_Monitor_GetWriteAllocMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi); 309 uint32_t HAL_CACHEAXI_Monitor_GetWriteThroughValue(const CACHEAXI_HandleTypeDef *hcacheaxi); 310 uint32_t HAL_CACHEAXI_Monitor_GetEvictionValue(const CACHEAXI_HandleTypeDef *hcacheaxi); 311 HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Reset(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType); 312 HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Start(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType); 313 HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Stop(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType); 314 /** 315 * @} 316 */ 317 318 /** @defgroup CACHEAXI_Exported_Functions_Group3 State and Error Functions 319 * @brief State and Error Functions 320 * @{ 321 */ 322 HAL_CACHEAXI_StateTypeDef HAL_CACHEAXI_GetState(const CACHEAXI_HandleTypeDef *hcacheaxi); 323 uint32_t HAL_CACHEAXI_GetError(const CACHEAXI_HandleTypeDef *hcacheaxi); 324 /** 325 * @} 326 */ 327 328 /** 329 * @} 330 */ 331 332 333 /* Private types -------------------------------------------------------------*/ 334 /* Private variables ---------------------------------------------------------*/ 335 /* Private constants ---------------------------------------------------------*/ 336 /* Private macros ------------------------------------------------------------*/ 337 /* Private functions ---------------------------------------------------------*/ 338 339 /** 340 * @} 341 */ 342 343 #endif /* CACHEAXI */ 344 /** 345 * @} 346 */ 347 348 #ifdef __cplusplus 349 } 350 #endif 351 352 #endif /* STM32N6xx_HAL_CACHEAXI_H */ 353
