1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_ipcc.h 4 * @author MCD Application Team 5 * @brief Header file of Mailbox HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_HAL_IPCC_H 21 #define STM32MP1xx_HAL_IPCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 31 /** @addtogroup STM32MP1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @defgroup IPCC IPCC 36 * @brief IPCC HAL module driver 37 * @{ 38 */ 39 40 /* Exported constants --------------------------------------------------------*/ 41 42 /** @defgroup IPCC_Exported_Constants IPCC Exported Constants 43 * @{ 44 */ 45 46 /** @defgroup IPCC_Channel IPCC Channel 47 * @{ 48 */ 49 #define IPCC_CHANNEL_1 0x00000000U 50 #define IPCC_CHANNEL_2 0x00000001U 51 #define IPCC_CHANNEL_3 0x00000002U 52 #define IPCC_CHANNEL_4 0x00000003U 53 #define IPCC_CHANNEL_5 0x00000004U 54 #define IPCC_CHANNEL_6 0x00000005U 55 /** 56 * @} 57 */ 58 59 /** 60 * @} 61 */ 62 63 /* Exported types ------------------------------------------------------------*/ 64 /** @defgroup IPCC_Exported_Types IPCC Exported Types 65 * @{ 66 */ 67 68 /** 69 * @brief HAL IPCC State structures definition 70 */ 71 typedef enum 72 { 73 HAL_IPCC_STATE_RESET = 0x00U, /*!< IPCC not yet initialized or disabled */ 74 HAL_IPCC_STATE_READY = 0x01U, /*!< IPCC initialized and ready for use */ 75 HAL_IPCC_STATE_BUSY = 0x02U /*!< IPCC internal processing is ongoing */ 76 } HAL_IPCC_StateTypeDef; 77 78 /** 79 * @brief IPCC channel direction structure definition 80 */ 81 typedef enum 82 { 83 IPCC_CHANNEL_DIR_TX = 0x00U, /*!< Channel direction Tx is used by an MCU to transmit */ 84 IPCC_CHANNEL_DIR_RX = 0x01U /*!< Channel direction Rx is used by an MCU to receive */ 85 } IPCC_CHANNELDirTypeDef; 86 87 /** 88 * @brief IPCC channel status structure definition 89 */ 90 typedef enum 91 { 92 IPCC_CHANNEL_STATUS_FREE = 0x00U, /*!< Means that a new msg can be posted on that channel */ 93 IPCC_CHANNEL_STATUS_OCCUPIED = 0x01U /*!< An MCU has posted a msg the other MCU hasn't retrieved */ 94 } IPCC_CHANNELStatusTypeDef; 95 96 /** 97 * @brief IPCC handle structure definition 98 */ 99 typedef struct __IPCC_HandleTypeDef 100 { 101 IPCC_TypeDef *Instance; /*!< IPCC registers base address */ 102 void (* ChannelCallbackRx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); /*!< Rx Callback registration table */ 103 void (* ChannelCallbackTx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); /*!< Tx Callback registration table */ 104 uint32_t callbackRequest; /*!< Store information about callback notification by channel */ 105 __IO HAL_IPCC_StateTypeDef State; /*!< IPCC State: initialized or not */ 106 } IPCC_HandleTypeDef; 107 108 /** 109 * @brief IPCC callback typedef 110 */ 111 typedef void ChannelCb(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); 112 113 /** 114 * @} 115 */ 116 117 /* Exported macros -----------------------------------------------------------*/ 118 /** @defgroup IPCC_Exported_Macros IPCC Exported Macros 119 * @{ 120 */ 121 122 /** 123 * @brief Enable the specified interrupt. 124 * @param __HANDLE__ specifies the IPCC Handle 125 * @param __CHDIRECTION__ specifies the channels Direction 126 * This parameter can be one of the following values: 127 * @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable 128 * @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable 129 */ 130 #if defined(CORE_CM4) 131 #define __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__) \ 132 (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \ 133 ((__HANDLE__)->Instance->C2CR |= IPCC_C2CR_RXOIE) : \ 134 ((__HANDLE__)->Instance->C2CR |= IPCC_C2CR_TXFIE)) 135 #else 136 #define __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__) \ 137 (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \ 138 ((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_RXOIE) : \ 139 ((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_TXFIE)) 140 #endif 141 142 /** 143 * @brief Disable the specified interrupt. 144 * @param __HANDLE__ specifies the IPCC Handle 145 * @param __CHDIRECTION__ specifies the channels Direction 146 * This parameter can be one of the following values: 147 * @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable 148 * @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable 149 */ 150 #if defined(CORE_CM4) 151 #define __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__) \ 152 (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \ 153 ((__HANDLE__)->Instance->C2CR &= ~IPCC_C2CR_RXOIE) : \ 154 ((__HANDLE__)->Instance->C2CR &= ~IPCC_C2CR_TXFIE)) 155 #else 156 #define __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__) \ 157 (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \ 158 ((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_RXOIE) : \ 159 ((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_TXFIE)) 160 #endif 161 162 /** 163 * @brief Mask the specified interrupt. 164 * @param __HANDLE__ specifies the IPCC Handle 165 * @param __CHDIRECTION__ specifies the channels Direction 166 * This parameter can be one of the following values: 167 * @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable 168 * @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable 169 * @param __CHINDEX__ specifies the channels number: 170 * This parameter can be one of the following values: 171 * @arg IPCC_CHANNEL_1: IPCC Channel 1 172 * @arg IPCC_CHANNEL_2: IPCC Channel 2 173 * @arg IPCC_CHANNEL_3: IPCC Channel 3 174 * @arg IPCC_CHANNEL_4: IPCC Channel 4 175 * @arg IPCC_CHANNEL_5: IPCC Channel 5 176 * @arg IPCC_CHANNEL_6: IPCC Channel 6 177 */ 178 #if defined(CORE_CM4) 179 #define __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \ 180 (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \ 181 ((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \ 182 ((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__)))) 183 #else 184 #define __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \ 185 (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \ 186 ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \ 187 ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__)))) 188 #endif 189 190 /** 191 * @brief Unmask the specified interrupt. 192 * @param __HANDLE__ specifies the IPCC Handle 193 * @param __CHDIRECTION__ specifies the channels Direction 194 * This parameter can be one of the following values: 195 * @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable 196 * @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable 197 * @param __CHINDEX__ specifies the channels number: 198 * This parameter can be one of the following values: 199 * @arg IPCC_CHANNEL_1: IPCC Channel 1 200 * @arg IPCC_CHANNEL_2: IPCC Channel 2 201 * @arg IPCC_CHANNEL_3: IPCC Channel 3 202 * @arg IPCC_CHANNEL_4: IPCC Channel 4 203 * @arg IPCC_CHANNEL_5: IPCC Channel 5 204 * @arg IPCC_CHANNEL_6: IPCC Channel 6 205 */ 206 #if defined(CORE_CM4) 207 #define __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \ 208 (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \ 209 ((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \ 210 ((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__)))) 211 #else 212 #define __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \ 213 (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \ 214 ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \ 215 ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__)))) 216 #endif 217 218 /** 219 * @} 220 */ 221 222 /* Exported functions --------------------------------------------------------*/ 223 /** @defgroup IPCC_Exported_Functions IPCC Exported Functions 224 * @{ 225 */ 226 227 /* Initialization and de-initialization functions *******************************/ 228 /** @defgroup IPCC_Exported_Functions_Group1 Initialization and deinitialization functions 229 * @{ 230 */ 231 HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc); 232 HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc); 233 void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc); 234 void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc); 235 /** 236 * @} 237 */ 238 239 /** @defgroup IPCC_Exported_Functions_Group2 Communication functions 240 * @{ 241 */ 242 /* IO operation functions *****************************************************/ 243 HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb); 244 HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); 245 IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); 246 HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); 247 /** 248 * @} 249 */ 250 251 /** @defgroup IPCC_Exported_Functions_Group3 Peripheral State and Error functions 252 * @{ 253 */ 254 /* Peripheral State and Error functions ****************************************/ 255 HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc); 256 /** 257 * @} 258 */ 259 260 /** @defgroup IPCC_IRQ_Handler_and_Callbacks Peripheral IRQ Handler and Callbacks 261 * @{ 262 */ 263 /* IRQHandler and Callbacks used in non blocking modes ************************/ 264 void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc); 265 void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc); 266 void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); 267 void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); 268 /** 269 * @} 270 */ 271 272 /** 273 * @} 274 */ 275 276 /** 277 * @} 278 */ 279 280 /** 281 * @} 282 */ 283 284 #ifdef __cplusplus 285 } 286 #endif 287 288 #endif /* STM32MP1xx_HAL_IPCC_H */ 289 290
