1 /**
2 ******************************************************************************
3 * @file system_stm32l5xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32l5xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * After each device reset the MSI (4 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32l5xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * This file configures the system clock as follows:
26 *=============================================================================
27 *-----------------------------------------------------------------------------
28 * System Clock source | MSI
29 *-----------------------------------------------------------------------------
30 * SYSCLK(Hz) | 4000000
31 *-----------------------------------------------------------------------------
32 * HCLK(Hz) | 4000000
33 *-----------------------------------------------------------------------------
34 * AHB Prescaler | 1
35 *-----------------------------------------------------------------------------
36 * APB1 Prescaler | 1
37 *-----------------------------------------------------------------------------
38 * APB2 Prescaler | 1
39 *-----------------------------------------------------------------------------
40 * PLL_SRC | No clock
41 *-----------------------------------------------------------------------------
42 * PLL_M | 1
43 *-----------------------------------------------------------------------------
44 * PLL_N | 8
45 *-----------------------------------------------------------------------------
46 * PLL_P | 7
47 *-----------------------------------------------------------------------------
48 * PLL_Q | 2
49 *-----------------------------------------------------------------------------
50 * PLL_R | 2
51 *-----------------------------------------------------------------------------
52 * PLLSAI1_SRC | NA
53 *-----------------------------------------------------------------------------
54 * PLLSAI1_M | NA
55 *-----------------------------------------------------------------------------
56 * PLLSAI1_N | NA
57 *-----------------------------------------------------------------------------
58 * PLLSAI1_P | NA
59 *-----------------------------------------------------------------------------
60 * PLLSAI1_Q | NA
61 *-----------------------------------------------------------------------------
62 * PLLSAI1_R | NA
63 *-----------------------------------------------------------------------------
64 * PLLSAI2_SRC | NA
65 *-----------------------------------------------------------------------------
66 * PLLSAI2_M | NA
67 *-----------------------------------------------------------------------------
68 * PLLSAI2_N | NA
69 *-----------------------------------------------------------------------------
70 * PLLSAI2_P | NA
71 *-----------------------------------------------------------------------------
72 * Require 48MHz for USB FS, | Disabled
73 * SDIO and RNG clock |
74 *-----------------------------------------------------------------------------
75 *=============================================================================
76 ******************************************************************************
77 * @attention
78 *
79 * Copyright (c) 2019 STMicroelectronics.
80 * All rights reserved.
81 *
82 * This software is licensed under terms that can be found in the LICENSE file
83 * in the root directory of this software component.
84 * If no LICENSE file comes with this software, it is provided AS-IS.
85 *
86 ******************************************************************************
87 */
88
89 /** @addtogroup CMSIS
90 * @{
91 */
92
93 /** @addtogroup STM32L5xx_System
94 * @{
95 */
96
97 /** @addtogroup STM32L5xx_System_Private_Includes
98 * @{
99 */
100
101 #include "stm32l5xx.h"
102
103 /**
104 * @}
105 */
106
107 /** @addtogroup STM32L5xx_System_Private_TypesDefinitions
108 * @{
109 */
110
111 /**
112 * @}
113 */
114
115 /** @addtogroup STM32L5xx_System_Private_Defines
116 * @{
117 */
118
119 #if !defined (HSE_VALUE)
120 #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
121 #endif /* HSE_VALUE */
122
123 #if !defined (MSI_VALUE)
124 #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
125 #endif /* MSI_VALUE */
126
127 #if !defined (HSI_VALUE)
128 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
129 #endif /* HSI_VALUE */
130
131 /* Note: Following vector table addresses must be defined in line with linker
132 configuration. */
133 /*!< Uncomment the following line if you need to relocate the vector table
134 anywhere in Flash or Sram, else the vector table is kept at the automatic
135 remap of boot address selected */
136 /* #define USER_VECT_TAB_ADDRESS */
137
138 #if defined(USER_VECT_TAB_ADDRESS)
139 /*!< Uncomment the following line if you need to relocate your vector Table
140 in Sram else user remap will be done in Flash. */
141 /* #define VECT_TAB_SRAM */
142
143 #if defined(VECT_TAB_SRAM)
144 #define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
145 This value must be a multiple of 0x200. */
146 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
147 This value must be a multiple of 0x200. */
148 #else
149 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
150 This value must be a multiple of 0x200. */
151 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
152 This value must be a multiple of 0x200. */
153 #endif /* VECT_TAB_SRAM */
154 #endif /* USER_VECT_TAB_ADDRESS */
155
156 /******************************************************************************/
157 /**
158 * @}
159 */
160
161 /** @addtogroup STM32L5xx_System_Private_Macros
162 * @{
163 */
164
165 /**
166 * @}
167 */
168
169 /** @addtogroup STM32L5xx_System_Private_Variables
170 * @{
171 */
172 /* The SystemCoreClock variable is updated in three ways:
173 1) by calling CMSIS function SystemCoreClockUpdate()
174 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
175 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
176 Note: If you use this function to configure the system clock; then there
177 is no need to call the 2 first functions listed above, since SystemCoreClock
178 variable is updated automatically.
179 */
180 uint32_t SystemCoreClock = 4000000U;
181
182 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
183 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
184 const uint32_t MSIRangeTable[16] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
185 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U, \
186 0U, 0U, 0U, 0U}; /* MISRAC-2012: 0U for unexpected value */
187 /**
188 * @}
189 */
190
191 /** @addtogroup STM32L5xx_System_Private_FunctionPrototypes
192 * @{
193 */
194
195 /**
196 * @}
197 */
198
199 /** @addtogroup STM32L5xx_System_Private_Functions
200 * @{
201 */
202
203 /**
204 * @brief Setup the microcontroller system.
205 * @retval None
206 */
207
SystemInit(void)208 void SystemInit(void)
209 {
210 /* Configure the Vector Table location -------------------------------------*/
211 #if defined(USER_VECT_TAB_ADDRESS)
212 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
213 #endif
214
215 /* FPU settings ------------------------------------------------------------*/
216 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
217 SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
218 #endif
219 }
220
221 /**
222 * @brief Update SystemCoreClock variable according to Clock Register Values.
223 * The SystemCoreClock variable contains the core clock (HCLK), it can
224 * be used by the user application to setup the SysTick timer or configure
225 * other parameters.
226 *
227 * @note Each time the core clock (HCLK) changes, this function must be called
228 * to update SystemCoreClock variable value. Otherwise, any configuration
229 * based on this variable will be incorrect.
230 *
231 * @note - The system frequency computed by this function is not the real
232 * frequency in the chip. It is calculated based on the predefined
233 * constant and the selected clock source:
234 *
235 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
236 *
237 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
238 *
239 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
240 *
241 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
242 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
243 *
244 * (*) MSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
245 * 4 MHz) but the real value may vary depending on the variations
246 * in voltage and temperature.
247 *
248 * (**) HSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
249 * 16 MHz) but the real value may vary depending on the variations
250 * in voltage and temperature.
251 *
252 * (***) HSE_VALUE is a constant defined in stm32l5xx_hal.h file (default value
253 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
254 * frequency of the crystal used. Otherwise, this function may
255 * have wrong result.
256 *
257 * - The result of this function could be not correct when using fractional
258 * value for HSE crystal.
259 *
260 * @retval None
261 */
SystemCoreClockUpdate(void)262 void SystemCoreClockUpdate(void)
263 {
264 uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
265
266 /* Get MSI Range frequency--------------------------------------------------*/
267 if((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
268 { /* MSISRANGE from RCC_CSR applies */
269 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
270 }
271 else
272 { /* MSIRANGE from RCC_CR applies */
273 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
274 }
275 /*MSI frequency range in HZ*/
276 msirange = MSIRangeTable[msirange];
277
278 /* Get SYSCLK source -------------------------------------------------------*/
279 switch (RCC->CFGR & RCC_CFGR_SWS)
280 {
281 case 0x00: /* MSI used as system clock source */
282 SystemCoreClock = msirange;
283 break;
284
285 case 0x04: /* HSI used as system clock source */
286 SystemCoreClock = HSI_VALUE;
287 break;
288
289 case 0x08: /* HSE used as system clock source */
290 SystemCoreClock = HSE_VALUE;
291 break;
292
293 case 0x0C: /* PLL used as system clock source */
294 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
295 SYSCLK = PLL_VCO / PLLR
296 */
297 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
298 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
299
300 switch (pllsource)
301 {
302 case 0x02: /* HSI used as PLL clock source */
303 pllvco = (HSI_VALUE / pllm);
304 break;
305
306 case 0x03: /* HSE used as PLL clock source */
307 pllvco = (HSE_VALUE / pllm);
308 break;
309
310 default: /* MSI used as PLL clock source */
311 pllvco = (msirange / pllm);
312 break;
313 }
314 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
315 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
316 SystemCoreClock = pllvco/pllr;
317 break;
318
319 default:
320 SystemCoreClock = msirange;
321 break;
322 }
323 /* Compute HCLK clock frequency --------------------------------------------*/
324 /* Get HCLK prescaler */
325 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
326 /* HCLK clock frequency */
327 SystemCoreClock >>= tmp;
328 }
329
330
331 /**
332 * @}
333 */
334
335 /**
336 * @}
337 */
338
339 /**
340 * @}
341 */
342
