1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L5xx_LL_DAC_H
21 #define STM32L5xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l5xx.h"
29
30 /** @addtogroup STM32L5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC1)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 /* - channel register offset of sample-and-hold sample time register SHSRx */
55 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
56 CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 2 */
59 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
60
61 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
62 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
63 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
64
65 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
66 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
67 DHR12Rx channel 1 (shifted left of 20 bits) */
68 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
69 DHR12Rx channel 1 (shifted left of 24 bits) */
70
71 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
72 DHR12Rx channel 1 (shifted left of 28 bits) */
73 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
74 DHR12Rx channel 1 (shifted left of 20 bits) */
75 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
76 DHR12Rx channel 1 (shifted left of 24 bits) */
77
78 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
79 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
80 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
81 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
82 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
83
84 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
85
86 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
87 DORx channel 2 (shifted left of 5 bits) */
88 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
89
90 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
91 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
92 SHSRx channel 2 (shifted left of 6 bits) */
93 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
94
95
96 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
97 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
98 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
99 to position 0 */
100 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
101 to position 0 */
102
103 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
104 channel 1 or 2 versus DHR12Rx channel 1
105 (shifted left of 28 bits) */
106 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
107 channel 1 or 2 versus DHR12Rx channel 1
108 (shifted left of 20 bits) */
109 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
110 channel 1 or 2 versus DHR12Rx channel 1
111 (shifted left of 24 bits) */
112 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
113 channel 1 or 2 versus DORx channel 1
114 (shifted left of 5 bits) */
115 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
116 channel 1 or 2 versus SHSRx channel 1
117 (shifted left of 6 bits) */
118
119 /* DAC registers bits positions */
120 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
121 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
122 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
123
124 /* Miscellaneous data */
125 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
126 bits (voltage range determined by analog voltage
127 references Vref+ and Vref-, refer to reference manual) */
128
129 /**
130 * @}
131 */
132
133
134 /* Private macros ------------------------------------------------------------*/
135 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
136 * @{
137 */
138
139 /**
140 * @brief Driver macro reserved for internal use: set a pointer to
141 * a register from a register basis from which an offset
142 * is applied.
143 * @param __REG__ Register basis from which the offset is applied.
144 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
145 * @retval Pointer to register address
146 */
147 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
148 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
149
150 /**
151 * @}
152 */
153
154
155 /* Exported types ------------------------------------------------------------*/
156 #if defined(USE_FULL_LL_DRIVER)
157 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
158 * @{
159 */
160
161 /**
162 * @brief Structure definition of some features of DAC instance.
163 */
164 typedef struct
165 {
166 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
167 internal (SW start) or from external peripheral
168 (timer event, external interrupt line).
169 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
170
171 This feature can be modified afterwards using unitary
172 function @ref LL_DAC_SetTriggerSource(). */
173
174 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
175 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
176
177 This feature can be modified afterwards using unitary
178 function @ref LL_DAC_SetWaveAutoGeneration(). */
179
180 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
181 If waveform automatic generation mode is set to noise, this parameter
182 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
183 If waveform automatic generation mode is set to triangle,
184 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
185 @note If waveform automatic generation mode is disabled,
186 this parameter is discarded.
187
188 This feature can be modified afterwards using unitary
189 function @ref LL_DAC_SetWaveNoiseLFSR(),
190 @ref LL_DAC_SetWaveTriangleAmplitude()
191 depending on the wave automatic generation selected. */
192
193 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
194 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
195
196 This feature can be modified afterwards using unitary
197 function @ref LL_DAC_SetOutputBuffer(). */
198
199 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
200 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
201
202 This feature can be modified afterwards using unitary
203 function @ref LL_DAC_SetOutputConnection(). */
204
205 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
206 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
207
208 This feature can be modified afterwards using unitary
209 function @ref LL_DAC_SetOutputMode(). */
210 } LL_DAC_InitTypeDef;
211
212 /**
213 * @}
214 */
215 #endif /* USE_FULL_LL_DRIVER */
216
217 /* Exported constants --------------------------------------------------------*/
218 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
219 * @{
220 */
221
222 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
223 * @brief Flags defines which can be used with LL_DAC_ReadReg function
224 * @{
225 */
226 /* DAC channel 1 flags */
227 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
228 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
229 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
230
231 /* DAC channel 2 flags */
232 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
233 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
234 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
235
236 /**
237 * @}
238 */
239
240 /** @defgroup DAC_LL_EC_IT DAC interruptions
241 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
242 * @{
243 */
244 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
245
246 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
247
248 /**
249 * @}
250 */
251
252 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
253 * @{
254 */
255 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
256 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
257 /**
258 * @}
259 */
260
261 /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
262 * @brief High frequency interface mode defines that can be used
263 * with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
264 * @{
265 */
266 #define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
267 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_CR_HFSEL) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
268 /**
269 * @}
270 */
271
272 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
273 * @{
274 */
275 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
276 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
277 /**
278 * @}
279 */
280
281 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
282 * @{
283 */
284 #define LL_DAC_TRIG_SOFTWARE 0x00000000UL /*!< DAC channel conversion trigger internal (SW start) */
285 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
286 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
287 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
288 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
289 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
290 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
291 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
292 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
293 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
294 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
295 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
296 /**
297 * @}
298 */
299
300 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
301 * @{
302 */
303 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
304 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
305 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
306 /**
307 * @}
308 */
309
310 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
311 * @{
312 */
313 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
314 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
315 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
316 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
317 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
318 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
319 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
320 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
321 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
322 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
323 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
324 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
325 /**
326 * @}
327 */
328
329 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
330 * @{
331 */
332 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
333 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
334 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
335 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
336 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
337 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
338 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
339 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
340 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
341 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
342 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
343 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
344 /**
345 * @}
346 */
347
348 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
349 * @{
350 */
351 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
352 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
353 /**
354 * @}
355 */
356
357 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
358 * @{
359 */
360 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
361 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
362 /**
363 * @}
364 */
365
366 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
367 * @{
368 */
369 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
370 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
371 /**
372 * @}
373 */
374
375 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
376 * @{
377 */
378 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
379 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
380 /**
381 * @}
382 */
383
384 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
385 * @{
386 */
387 /* List of DAC registers intended to be used (most commonly) with */
388 /* DMA transfer. */
389 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
390 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
391 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
392 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
393 /**
394 * @}
395 */
396
397 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
398 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
399 * not timeout values.
400 * For details on delays values, refer to descriptions in source code
401 * above each literal definition.
402 * @{
403 */
404
405 /* Delay for DAC channel voltage settling time from DAC channel startup */
406 /* (transition from disable to enable). */
407 /* Note: DAC channel startup time depends on board application environment: */
408 /* impedance connected to DAC channel output. */
409 /* The delay below is specified under conditions: */
410 /* - voltage maximum transition (lowest to highest value) */
411 /* - until voltage reaches final value +-1LSB */
412 /* - DAC channel output buffer enabled */
413 /* - load impedance of 5kOhm (min), 50pF (max) */
414 /* Literal set to maximum value (refer to device datasheet, */
415 /* parameter "tWAKEUP"). */
416 /* Unit: us */
417 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
418
419 /* Delay for DAC channel voltage settling time. */
420 /* Note: DAC channel startup time depends on board application environment: */
421 /* impedance connected to DAC channel output. */
422 /* The delay below is specified under conditions: */
423 /* - voltage maximum transition (lowest to highest value) */
424 /* - until voltage reaches final value +-1LSB */
425 /* - DAC channel output buffer enabled */
426 /* - load impedance of 5kOhm min, 50pF max */
427 /* Literal set to maximum value (refer to device datasheet, */
428 /* parameter "tSETTLING"). */
429 /* Unit: us */
430 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
431
432 /**
433 * @}
434 */
435
436 /**
437 * @}
438 */
439
440 /* Exported macro ------------------------------------------------------------*/
441 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
442 * @{
443 */
444
445 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
446 * @{
447 */
448
449 /**
450 * @brief Write a value in DAC register
451 * @param __INSTANCE__ DAC Instance
452 * @param __REG__ Register to be written
453 * @param __VALUE__ Value to be written in the register
454 * @retval None
455 */
456 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
457
458 /**
459 * @brief Read a value in DAC register
460 * @param __INSTANCE__ DAC Instance
461 * @param __REG__ Register to be read
462 * @retval Register value
463 */
464 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
465
466 /**
467 * @}
468 */
469
470 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
471 * @{
472 */
473
474 /**
475 * @brief Helper macro to get DAC channel number in decimal format
476 * from literals LL_DAC_CHANNEL_x.
477 * Example:
478 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
479 * will return decimal number "1".
480 * @note The input can be a value from functions where a channel
481 * number is returned.
482 * @param __CHANNEL__ This parameter can be one of the following values:
483 * @arg @ref LL_DAC_CHANNEL_1
484 * @arg @ref LL_DAC_CHANNEL_2
485 * @retval 1...2
486 */
487 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
488 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
489
490 /**
491 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
492 * from number in decimal format.
493 * Example:
494 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
495 * will return a data equivalent to "LL_DAC_CHANNEL_1".
496 * @note If the input parameter does not correspond to a DAC channel,
497 * this macro returns value '0'.
498 * @param __DECIMAL_NB__ 1...2
499 * @retval Returned value can be one of the following values:
500 * @arg @ref LL_DAC_CHANNEL_1
501 * @arg @ref LL_DAC_CHANNEL_2
502 */
503 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
504 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
505
506 /**
507 * @brief Helper macro to define the DAC conversion data full-scale digital
508 * value corresponding to the selected DAC resolution.
509 * @note DAC conversion data full-scale corresponds to voltage range
510 * determined by analog voltage references Vref+ and Vref-
511 * (refer to reference manual).
512 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
513 * @arg @ref LL_DAC_RESOLUTION_12B
514 * @arg @ref LL_DAC_RESOLUTION_8B
515 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
516 */
517 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
518 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
519
520 /**
521 * @brief Helper macro to calculate the DAC conversion data (unit: digital
522 * value) corresponding to a voltage (unit: mVolt).
523 * @note This helper macro is intended to provide input data in voltage
524 * rather than digital value,
525 * to be used with LL DAC functions such as
526 * @ref LL_DAC_ConvertData12RightAligned().
527 * @note Analog reference voltage (Vref+) must be either known from
528 * user board environment or can be calculated using ADC measurement
529 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
530 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
531 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
532 * (unit: mVolt).
533 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
534 * @arg @ref LL_DAC_RESOLUTION_12B
535 * @arg @ref LL_DAC_RESOLUTION_8B
536 * @retval DAC conversion data (unit: digital value)
537 */
538 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
539 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
540 / (__VREFANALOG_VOLTAGE__) \
541 )
542
543 /**
544 * @}
545 */
546
547 /**
548 * @}
549 */
550
551
552 /* Exported functions --------------------------------------------------------*/
553 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
554 * @{
555 */
556 /** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
557 * @{
558 */
559 /**
560 * @brief Set the high frequency interface mode for the selected DAC instance
561 * @rmtoll CR HFSEL LL_DAC_SetHighFrequencyMode
562 * @param DACx DAC instance
563 * @param HighFreqMode This parameter can be one of the following values:
564 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
565 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
566 * @retval None
567 */
LL_DAC_SetHighFrequencyMode(DAC_TypeDef * DACx,uint32_t HighFreqMode)568 __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
569 {
570 MODIFY_REG(DACx->CR, DAC_CR_HFSEL, HighFreqMode);
571 }
572
573 /**
574 * @brief Get the high frequency interface mode for the selected DAC instance
575 * @rmtoll CR HFSEL LL_DAC_GetHighFrequencyMode
576 * @param DACx DAC instance
577 * @retval Returned value can be one of the following values:
578 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
579 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
580 */
LL_DAC_GetHighFrequencyMode(const DAC_TypeDef * DACx)581 __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(const DAC_TypeDef *DACx)
582 {
583 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_HFSEL));
584 }
585 /**
586 * @}
587 */
588
589
590 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
591 * @{
592 */
593
594 /**
595 * @brief Set the operating mode for the selected DAC channel:
596 * calibration or normal operating mode.
597 * @rmtoll CR CEN1 LL_DAC_SetMode\n
598 * CR CEN2 LL_DAC_SetMode
599 * @param DACx DAC instance
600 * @param DAC_Channel This parameter can be one of the following values:
601 * @arg @ref LL_DAC_CHANNEL_1
602 * @arg @ref LL_DAC_CHANNEL_2
603 * @param ChannelMode This parameter can be one of the following values:
604 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
605 * @arg @ref LL_DAC_MODE_CALIBRATION
606 * @retval None
607 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)608 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
609 {
610 MODIFY_REG(DACx->CR,
611 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
612 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
613 }
614
615 /**
616 * @brief Get the operating mode for the selected DAC channel:
617 * calibration or normal operating mode.
618 * @rmtoll CR CEN1 LL_DAC_GetMode\n
619 * CR CEN2 LL_DAC_GetMode
620 * @param DACx DAC instance
621 * @param DAC_Channel This parameter can be one of the following values:
622 * @arg @ref LL_DAC_CHANNEL_1
623 * @arg @ref LL_DAC_CHANNEL_2
624 * @retval Returned value can be one of the following values:
625 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
626 * @arg @ref LL_DAC_MODE_CALIBRATION
627 */
LL_DAC_GetMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)628 __STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
629 {
630 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
631 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
632 );
633 }
634
635 /**
636 * @brief Set the offset trimming value for the selected DAC channel.
637 * Trimming has an impact when output buffer is enabled
638 * and is intended to replace factory calibration default values.
639 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
640 * CCR OTRIM2 LL_DAC_SetTrimmingValue
641 * @param DACx DAC instance
642 * @param DAC_Channel This parameter can be one of the following values:
643 * @arg @ref LL_DAC_CHANNEL_1
644 * @arg @ref LL_DAC_CHANNEL_2
645 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
646 * @retval None
647 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)648 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
649 {
650 MODIFY_REG(DACx->CCR,
651 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
652 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
653 }
654
655 /**
656 * @brief Get the offset trimming value for the selected DAC channel.
657 * Trimming has an impact when output buffer is enabled
658 * and is intended to replace factory calibration default values.
659 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
660 * CCR OTRIM2 LL_DAC_GetTrimmingValue
661 * @param DACx DAC instance
662 * @param DAC_Channel This parameter can be one of the following values:
663 * @arg @ref LL_DAC_CHANNEL_1
664 * @arg @ref LL_DAC_CHANNEL_2
665 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
666 */
LL_DAC_GetTrimmingValue(const DAC_TypeDef * DACx,uint32_t DAC_Channel)667 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
668 {
669 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
670 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
671 );
672 }
673
674 /**
675 * @brief Set the conversion trigger source for the selected DAC channel.
676 * @note For conversion trigger source to be effective, DAC trigger
677 * must be enabled using function @ref LL_DAC_EnableTrigger().
678 * @note To set conversion trigger source, DAC channel must be disabled.
679 * Otherwise, the setting is discarded.
680 * @note Availability of parameters of trigger sources from timer
681 * depends on timers availability on the selected device.
682 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
683 * CR TSEL2 LL_DAC_SetTriggerSource
684 * @param DACx DAC instance
685 * @param DAC_Channel This parameter can be one of the following values:
686 * @arg @ref LL_DAC_CHANNEL_1
687 * @arg @ref LL_DAC_CHANNEL_2
688 * @param TriggerSource This parameter can be one of the following values:
689 * @arg @ref LL_DAC_TRIG_SOFTWARE
690 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
691 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
692 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
693 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
694 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
695 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
696 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
697 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
698 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
699 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
700 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
701 * @retval None
702 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)703 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
704 {
705 MODIFY_REG(DACx->CR,
706 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
707 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
708 }
709
710 /**
711 * @brief Get the conversion trigger source for the selected DAC channel.
712 * @note For conversion trigger source to be effective, DAC trigger
713 * must be enabled using function @ref LL_DAC_EnableTrigger().
714 * @note Availability of parameters of trigger sources from timer
715 * depends on timers availability on the selected device.
716 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
717 * CR TSEL2 LL_DAC_GetTriggerSource
718 * @param DACx DAC instance
719 * @param DAC_Channel This parameter can be one of the following values:
720 * @arg @ref LL_DAC_CHANNEL_1
721 * @arg @ref LL_DAC_CHANNEL_2
722 * @retval Returned value can be one of the following values:
723 * @arg @ref LL_DAC_TRIG_SOFTWARE
724 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
725 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
726 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
727 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
728 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
729 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
730 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
731 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
732 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
733 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
734 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
735 */
LL_DAC_GetTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)736 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
737 {
738 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
739 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
740 );
741 }
742
743 /**
744 * @brief Set the waveform automatic generation mode
745 * for the selected DAC channel.
746 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
747 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
748 * @param DACx DAC instance
749 * @param DAC_Channel This parameter can be one of the following values:
750 * @arg @ref LL_DAC_CHANNEL_1
751 * @arg @ref LL_DAC_CHANNEL_2
752 * @param WaveAutoGeneration This parameter can be one of the following values:
753 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
754 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
755 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
756 * @retval None
757 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)758 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
759 {
760 MODIFY_REG(DACx->CR,
761 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
762 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
763 }
764
765 /**
766 * @brief Get the waveform automatic generation mode
767 * for the selected DAC channel.
768 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
769 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
770 * @param DACx DAC instance
771 * @param DAC_Channel This parameter can be one of the following values:
772 * @arg @ref LL_DAC_CHANNEL_1
773 * @arg @ref LL_DAC_CHANNEL_2
774 * @retval Returned value can be one of the following values:
775 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
776 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
777 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
778 */
LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef * DACx,uint32_t DAC_Channel)779 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
780 {
781 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
782 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
783 );
784 }
785
786 /**
787 * @brief Set the noise waveform generation for the selected DAC channel:
788 * Noise mode and parameters LFSR (linear feedback shift register).
789 * @note For wave generation to be effective, DAC channel
790 * wave generation mode must be enabled using
791 * function @ref LL_DAC_SetWaveAutoGeneration().
792 * @note This setting can be set when the selected DAC channel is disabled
793 * (otherwise, the setting operation is ignored).
794 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
795 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
796 * @param DACx DAC instance
797 * @param DAC_Channel This parameter can be one of the following values:
798 * @arg @ref LL_DAC_CHANNEL_1
799 * @arg @ref LL_DAC_CHANNEL_2
800 * @param NoiseLFSRMask This parameter can be one of the following values:
801 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
802 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
803 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
804 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
805 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
806 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
807 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
808 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
809 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
810 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
811 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
812 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
813 * @retval None
814 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)815 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
816 {
817 MODIFY_REG(DACx->CR,
818 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
819 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
820 }
821
822 /**
823 * @brief Get the noise waveform generation for the selected DAC channel:
824 * Noise mode and parameters LFSR (linear feedback shift register).
825 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
826 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
827 * @param DACx DAC instance
828 * @param DAC_Channel This parameter can be one of the following values:
829 * @arg @ref LL_DAC_CHANNEL_1
830 * @arg @ref LL_DAC_CHANNEL_2
831 * @retval Returned value can be one of the following values:
832 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
833 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
834 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
835 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
836 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
837 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
838 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
839 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
840 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
841 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
842 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
843 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
844 */
LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef * DACx,uint32_t DAC_Channel)845 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
846 {
847 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
848 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
849 );
850 }
851
852 /**
853 * @brief Set the triangle waveform generation for the selected DAC channel:
854 * triangle mode and amplitude.
855 * @note For wave generation to be effective, DAC channel
856 * wave generation mode must be enabled using
857 * function @ref LL_DAC_SetWaveAutoGeneration().
858 * @note This setting can be set when the selected DAC channel is disabled
859 * (otherwise, the setting operation is ignored).
860 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
861 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
862 * @param DACx DAC instance
863 * @param DAC_Channel This parameter can be one of the following values:
864 * @arg @ref LL_DAC_CHANNEL_1
865 * @arg @ref LL_DAC_CHANNEL_2
866 * @param TriangleAmplitude This parameter can be one of the following values:
867 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
868 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
869 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
870 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
871 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
872 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
873 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
874 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
875 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
876 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
877 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
878 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
879 * @retval None
880 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)881 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
882 uint32_t TriangleAmplitude)
883 {
884 MODIFY_REG(DACx->CR,
885 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
886 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
887 }
888
889 /**
890 * @brief Get the triangle waveform generation for the selected DAC channel:
891 * triangle mode and amplitude.
892 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
893 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
894 * @param DACx DAC instance
895 * @param DAC_Channel This parameter can be one of the following values:
896 * @arg @ref LL_DAC_CHANNEL_1
897 * @arg @ref LL_DAC_CHANNEL_2
898 * @retval Returned value can be one of the following values:
899 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
900 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
901 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
902 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
903 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
904 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
905 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
906 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
907 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
908 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
909 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
910 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
911 */
LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef * DACx,uint32_t DAC_Channel)912 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
913 {
914 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
915 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
916 );
917 }
918
919 /**
920 * @brief Set the output for the selected DAC channel.
921 * @note This function set several features:
922 * - mode normal or sample-and-hold
923 * - buffer
924 * - connection to GPIO or internal path.
925 * These features can also be set individually using
926 * dedicated functions:
927 * - @ref LL_DAC_SetOutputBuffer()
928 * - @ref LL_DAC_SetOutputMode()
929 * - @ref LL_DAC_SetOutputConnection()
930 * @note On this STM32 series, output connection depends on output mode
931 * (normal or sample and hold) and output buffer state.
932 * - if output connection is set to internal path and output buffer
933 * is enabled (whatever output mode):
934 * output connection is also connected to GPIO pin
935 * (both connections to GPIO pin and internal path).
936 * - if output connection is set to GPIO pin, output buffer
937 * is disabled, output mode set to sample and hold:
938 * output connection is also connected to internal path
939 * (both connections to GPIO pin and internal path).
940 * @note Mode sample-and-hold requires an external capacitor
941 * to be connected between DAC channel output and ground.
942 * Capacitor value depends on load on DAC channel output and
943 * sample-and-hold timings configured.
944 * As indication, capacitor typical value is 100nF
945 * (refer to device datasheet, parameter "CSH").
946 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
947 * CR MODE2 LL_DAC_ConfigOutput
948 * @param DACx DAC instance
949 * @param DAC_Channel This parameter can be one of the following values:
950 * @arg @ref LL_DAC_CHANNEL_1
951 * @arg @ref LL_DAC_CHANNEL_2
952 * @param OutputMode This parameter can be one of the following values:
953 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
954 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
955 * @param OutputBuffer This parameter can be one of the following values:
956 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
957 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
958 * @param OutputConnection This parameter can be one of the following values:
959 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
960 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
961 * @retval None
962 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)963 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
964 uint32_t OutputBuffer, uint32_t OutputConnection)
965 {
966 MODIFY_REG(DACx->MCR,
967 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
968 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
969 }
970
971 /**
972 * @brief Set the output mode normal or sample-and-hold
973 * for the selected DAC channel.
974 * @note Mode sample-and-hold requires an external capacitor
975 * to be connected between DAC channel output and ground.
976 * Capacitor value depends on load on DAC channel output and
977 * sample-and-hold timings configured.
978 * As indication, capacitor typical value is 100nF
979 * (refer to device datasheet, parameter "CSH").
980 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
981 * CR MODE2 LL_DAC_SetOutputMode
982 * @param DACx DAC instance
983 * @param DAC_Channel This parameter can be one of the following values:
984 * @arg @ref LL_DAC_CHANNEL_1
985 * @arg @ref LL_DAC_CHANNEL_2
986 * @param OutputMode This parameter can be one of the following values:
987 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
988 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
989 * @retval None
990 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)991 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
992 {
993 MODIFY_REG(DACx->MCR,
994 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
995 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
996 }
997
998 /**
999 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
1000 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
1001 * CR MODE2 LL_DAC_GetOutputMode
1002 * @param DACx DAC instance
1003 * @param DAC_Channel This parameter can be one of the following values:
1004 * @arg @ref LL_DAC_CHANNEL_1
1005 * @arg @ref LL_DAC_CHANNEL_2
1006 * @retval Returned value can be one of the following values:
1007 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1008 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1009 */
LL_DAC_GetOutputMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1010 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1011 {
1012 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1013 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1014 );
1015 }
1016
1017 /**
1018 * @brief Set the output buffer for the selected DAC channel.
1019 * @note On this STM32 series, when buffer is enabled, its offset can be
1020 * trimmed: factory calibration default values can be
1021 * replaced by user trimming values, using function
1022 * @ref LL_DAC_SetTrimmingValue().
1023 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
1024 * CR MODE2 LL_DAC_SetOutputBuffer
1025 * @param DACx DAC instance
1026 * @param DAC_Channel This parameter can be one of the following values:
1027 * @arg @ref LL_DAC_CHANNEL_1
1028 * @arg @ref LL_DAC_CHANNEL_2
1029 * @param OutputBuffer This parameter can be one of the following values:
1030 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1031 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1032 * @retval None
1033 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)1034 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1035 {
1036 MODIFY_REG(DACx->MCR,
1037 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1038 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1039 }
1040
1041 /**
1042 * @brief Get the output buffer state for the selected DAC channel.
1043 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
1044 * CR MODE2 LL_DAC_GetOutputBuffer
1045 * @param DACx DAC instance
1046 * @param DAC_Channel This parameter can be one of the following values:
1047 * @arg @ref LL_DAC_CHANNEL_1
1048 * @arg @ref LL_DAC_CHANNEL_2
1049 * @retval Returned value can be one of the following values:
1050 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1051 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1052 */
LL_DAC_GetOutputBuffer(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1053 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1054 {
1055 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1056 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1057 );
1058 }
1059
1060 /**
1061 * @brief Set the output connection for the selected DAC channel.
1062 * @note On this STM32 series, output connection depends on output mode (normal or
1063 * sample and hold) and output buffer state.
1064 * - if output connection is set to internal path and output buffer
1065 * is enabled (whatever output mode):
1066 * output connection is also connected to GPIO pin
1067 * (both connections to GPIO pin and internal path).
1068 * - if output connection is set to GPIO pin, output buffer
1069 * is disabled, output mode set to sample and hold:
1070 * output connection is also connected to internal path
1071 * (both connections to GPIO pin and internal path).
1072 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1073 * CR MODE2 LL_DAC_SetOutputConnection
1074 * @param DACx DAC instance
1075 * @param DAC_Channel This parameter can be one of the following values:
1076 * @arg @ref LL_DAC_CHANNEL_1
1077 * @arg @ref LL_DAC_CHANNEL_2
1078 * @param OutputConnection This parameter can be one of the following values:
1079 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1080 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1081 * @retval None
1082 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)1083 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1084 {
1085 MODIFY_REG(DACx->MCR,
1086 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1087 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1088 }
1089
1090 /**
1091 * @brief Get the output connection for the selected DAC channel.
1092 * @note On this STM32 series, output connection depends on output mode (normal or
1093 * sample and hold) and output buffer state.
1094 * - if output connection is set to internal path and output buffer
1095 * is enabled (whatever output mode):
1096 * output connection is also connected to GPIO pin
1097 * (both connections to GPIO pin and internal path).
1098 * - if output connection is set to GPIO pin, output buffer
1099 * is disabled, output mode set to sample and hold:
1100 * output connection is also connected to internal path
1101 * (both connections to GPIO pin and internal path).
1102 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1103 * CR MODE2 LL_DAC_GetOutputConnection
1104 * @param DACx DAC instance
1105 * @param DAC_Channel This parameter can be one of the following values:
1106 * @arg @ref LL_DAC_CHANNEL_1
1107 * @arg @ref LL_DAC_CHANNEL_2
1108 * @retval Returned value can be one of the following values:
1109 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1110 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1111 */
LL_DAC_GetOutputConnection(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1112 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1113 {
1114 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1115 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1116 );
1117 }
1118
1119 /**
1120 * @brief Set the sample-and-hold timing for the selected DAC channel:
1121 * sample time
1122 * @note Sample time must be set when DAC channel is disabled
1123 * or during DAC operation when DAC channel flag BWSTx is reset,
1124 * otherwise the setting is ignored.
1125 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1126 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1127 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1128 * @param DACx DAC instance
1129 * @param DAC_Channel This parameter can be one of the following values:
1130 * @arg @ref LL_DAC_CHANNEL_1
1131 * @arg @ref LL_DAC_CHANNEL_2
1132 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1133 * @retval None
1134 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1135 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1136 {
1137 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1138 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1139
1140 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1141 }
1142
1143 /**
1144 * @brief Get the sample-and-hold timing for the selected DAC channel:
1145 * sample time
1146 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1147 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1148 * @param DACx DAC instance
1149 * @param DAC_Channel This parameter can be one of the following values:
1150 * @arg @ref LL_DAC_CHANNEL_1
1151 * @arg @ref LL_DAC_CHANNEL_2
1152 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1153 */
LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1154 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1155 {
1156 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1157 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1158
1159 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1160 }
1161
1162 /**
1163 * @brief Set the sample-and-hold timing for the selected DAC channel:
1164 * hold time
1165 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1166 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1167 * @param DACx DAC instance
1168 * @param DAC_Channel This parameter can be one of the following values:
1169 * @arg @ref LL_DAC_CHANNEL_1
1170 * @arg @ref LL_DAC_CHANNEL_2
1171 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1172 * @retval None
1173 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1174 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1175 {
1176 MODIFY_REG(DACx->SHHR,
1177 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1178 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1179 }
1180
1181 /**
1182 * @brief Get the sample-and-hold timing for the selected DAC channel:
1183 * hold time
1184 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1185 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1186 * @param DACx DAC instance
1187 * @param DAC_Channel This parameter can be one of the following values:
1188 * @arg @ref LL_DAC_CHANNEL_1
1189 * @arg @ref LL_DAC_CHANNEL_2
1190 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1191 */
LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1192 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1193 {
1194 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1195 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1196 );
1197 }
1198
1199 /**
1200 * @brief Set the sample-and-hold timing for the selected DAC channel:
1201 * refresh time
1202 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1203 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1204 * @param DACx DAC instance
1205 * @param DAC_Channel This parameter can be one of the following values:
1206 * @arg @ref LL_DAC_CHANNEL_1
1207 * @arg @ref LL_DAC_CHANNEL_2
1208 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1209 * @retval None
1210 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1211 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1212 {
1213 MODIFY_REG(DACx->SHRR,
1214 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1215 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1216 }
1217
1218 /**
1219 * @brief Get the sample-and-hold timing for the selected DAC channel:
1220 * refresh time
1221 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1222 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1223 * @param DACx DAC instance
1224 * @param DAC_Channel This parameter can be one of the following values:
1225 * @arg @ref LL_DAC_CHANNEL_1
1226 * @arg @ref LL_DAC_CHANNEL_2
1227 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1228 */
LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1229 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1230 {
1231 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1232 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1233 );
1234 }
1235
1236 /**
1237 * @}
1238 */
1239
1240 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1241 * @{
1242 */
1243
1244 /**
1245 * @brief Enable DAC DMA transfer request of the selected channel.
1246 * @note To configure DMA source address (peripheral address),
1247 * use function @ref LL_DAC_DMA_GetRegAddr().
1248 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1249 * CR DMAEN2 LL_DAC_EnableDMAReq
1250 * @param DACx DAC instance
1251 * @param DAC_Channel This parameter can be one of the following values:
1252 * @arg @ref LL_DAC_CHANNEL_1
1253 * @arg @ref LL_DAC_CHANNEL_2
1254 * @retval None
1255 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1256 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1257 {
1258 SET_BIT(DACx->CR,
1259 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1260 }
1261
1262 /**
1263 * @brief Disable DAC DMA transfer request of the selected channel.
1264 * @note To configure DMA source address (peripheral address),
1265 * use function @ref LL_DAC_DMA_GetRegAddr().
1266 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1267 * CR DMAEN2 LL_DAC_DisableDMAReq
1268 * @param DACx DAC instance
1269 * @param DAC_Channel This parameter can be one of the following values:
1270 * @arg @ref LL_DAC_CHANNEL_1
1271 * @arg @ref LL_DAC_CHANNEL_2
1272 * @retval None
1273 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1274 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1275 {
1276 CLEAR_BIT(DACx->CR,
1277 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1278 }
1279
1280 /**
1281 * @brief Get DAC DMA transfer request state of the selected channel.
1282 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1283 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1284 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1285 * @param DACx DAC instance
1286 * @param DAC_Channel This parameter can be one of the following values:
1287 * @arg @ref LL_DAC_CHANNEL_1
1288 * @arg @ref LL_DAC_CHANNEL_2
1289 * @retval State of bit (1 or 0).
1290 */
LL_DAC_IsDMAReqEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1291 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1292 {
1293 return ((READ_BIT(DACx->CR,
1294 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1295 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1296 }
1297
1298 /**
1299 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1300 * DAC register address from DAC instance and a list of DAC registers
1301 * intended to be used (most commonly) with DMA transfer.
1302 * @note These DAC registers are data holding registers:
1303 * when DAC conversion is requested, DAC generates a DMA transfer
1304 * request to have data available in DAC data holding registers.
1305 * @note This macro is intended to be used with LL DMA driver, refer to
1306 * function "LL_DMA_ConfigAddresses()".
1307 * Example:
1308 * LL_DMA_ConfigAddresses(DMA1,
1309 * LL_DMA_CHANNEL_1,
1310 * (uint32_t)&< array or variable >,
1311 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
1312 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1313 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1314 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1315 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1316 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1317 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1318 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1319 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1320 * @param DACx DAC instance
1321 * @param DAC_Channel This parameter can be one of the following values:
1322 * @arg @ref LL_DAC_CHANNEL_1
1323 * @arg @ref LL_DAC_CHANNEL_2
1324 * @param Register This parameter can be one of the following values:
1325 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1326 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1327 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1328 * @retval DAC register address
1329 */
LL_DAC_DMA_GetRegAddr(const DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1330 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1331 {
1332 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1333 /* DAC channel selected. */
1334 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
1335 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1336 }
1337 /**
1338 * @}
1339 */
1340
1341 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1342 * @{
1343 */
1344
1345 /**
1346 * @brief Enable DAC selected channel.
1347 * @rmtoll CR EN1 LL_DAC_Enable\n
1348 * CR EN2 LL_DAC_Enable
1349 * @note After enable from off state, DAC channel requires a delay
1350 * for output voltage to reach accuracy +/- 1 LSB.
1351 * Refer to device datasheet, parameter "tWAKEUP".
1352 * @param DACx DAC instance
1353 * @param DAC_Channel This parameter can be one of the following values:
1354 * @arg @ref LL_DAC_CHANNEL_1
1355 * @arg @ref LL_DAC_CHANNEL_2
1356 * @retval None
1357 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1358 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1359 {
1360 SET_BIT(DACx->CR,
1361 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1362 }
1363
1364 /**
1365 * @brief Disable DAC selected channel.
1366 * @rmtoll CR EN1 LL_DAC_Disable\n
1367 * CR EN2 LL_DAC_Disable
1368 * @param DACx DAC instance
1369 * @param DAC_Channel This parameter can be one of the following values:
1370 * @arg @ref LL_DAC_CHANNEL_1
1371 * @arg @ref LL_DAC_CHANNEL_2
1372 * @retval None
1373 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1374 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1375 {
1376 CLEAR_BIT(DACx->CR,
1377 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1378 }
1379
1380 /**
1381 * @brief Get DAC enable state of the selected channel.
1382 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1383 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1384 * CR EN2 LL_DAC_IsEnabled
1385 * @param DACx DAC instance
1386 * @param DAC_Channel This parameter can be one of the following values:
1387 * @arg @ref LL_DAC_CHANNEL_1
1388 * @arg @ref LL_DAC_CHANNEL_2
1389 * @retval State of bit (1 or 0).
1390 */
LL_DAC_IsEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1391 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1392 {
1393 return ((READ_BIT(DACx->CR,
1394 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1395 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1396 }
1397
1398 /**
1399 * @brief Enable DAC trigger of the selected channel.
1400 * @note - If DAC trigger is disabled, DAC conversion is performed
1401 * automatically once the data holding register is updated,
1402 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1403 * @ref LL_DAC_ConvertData12RightAligned(), ...
1404 * - If DAC trigger is enabled, DAC conversion is performed
1405 * only when a hardware of software trigger event is occurring.
1406 * Select trigger source using
1407 * function @ref LL_DAC_SetTriggerSource().
1408 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1409 * CR TEN2 LL_DAC_EnableTrigger
1410 * @param DACx DAC instance
1411 * @param DAC_Channel This parameter can be one of the following values:
1412 * @arg @ref LL_DAC_CHANNEL_1
1413 * @arg @ref LL_DAC_CHANNEL_2
1414 * @retval None
1415 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1416 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1417 {
1418 SET_BIT(DACx->CR,
1419 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1420 }
1421
1422 /**
1423 * @brief Disable DAC trigger of the selected channel.
1424 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1425 * CR TEN2 LL_DAC_DisableTrigger
1426 * @param DACx DAC instance
1427 * @param DAC_Channel This parameter can be one of the following values:
1428 * @arg @ref LL_DAC_CHANNEL_1
1429 * @arg @ref LL_DAC_CHANNEL_2
1430 * @retval None
1431 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1432 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1433 {
1434 CLEAR_BIT(DACx->CR,
1435 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1436 }
1437
1438 /**
1439 * @brief Get DAC trigger state of the selected channel.
1440 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1441 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1442 * CR TEN2 LL_DAC_IsTriggerEnabled
1443 * @param DACx DAC instance
1444 * @param DAC_Channel This parameter can be one of the following values:
1445 * @arg @ref LL_DAC_CHANNEL_1
1446 * @arg @ref LL_DAC_CHANNEL_2
1447 * @retval State of bit (1 or 0).
1448 */
LL_DAC_IsTriggerEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1449 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1450 {
1451 return ((READ_BIT(DACx->CR,
1452 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1453 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1454 }
1455
1456 /**
1457 * @brief Trig DAC conversion by software for the selected DAC channel.
1458 * @note Preliminarily, DAC trigger must be set to software trigger
1459 * using function
1460 * @ref LL_DAC_Init()
1461 * @ref LL_DAC_SetTriggerSource()
1462 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1463 * and DAC trigger must be enabled using
1464 * function @ref LL_DAC_EnableTrigger().
1465 * @note For devices featuring DAC with 2 channels: this function
1466 * can perform a SW start of both DAC channels simultaneously.
1467 * Two channels can be selected as parameter.
1468 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1469 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1470 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1471 * @param DACx DAC instance
1472 * @param DAC_Channel This parameter can a combination of the following values:
1473 * @arg @ref LL_DAC_CHANNEL_1
1474 * @arg @ref LL_DAC_CHANNEL_2
1475 * @retval None
1476 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1477 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1478 {
1479 SET_BIT(DACx->SWTRIGR,
1480 (DAC_Channel & DAC_SWTR_CHX_MASK));
1481 }
1482
1483 /**
1484 * @brief Set the data to be loaded in the data holding register
1485 * in format 12 bits left alignment (LSB aligned on bit 0),
1486 * for the selected DAC channel.
1487 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1488 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1489 * @param DACx DAC instance
1490 * @param DAC_Channel This parameter can be one of the following values:
1491 * @arg @ref LL_DAC_CHANNEL_1
1492 * @arg @ref LL_DAC_CHANNEL_2
1493 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1494 * @retval None
1495 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1496 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1497 {
1498 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1499 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1500
1501 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1502 }
1503
1504 /**
1505 * @brief Set the data to be loaded in the data holding register
1506 * in format 12 bits left alignment (MSB aligned on bit 15),
1507 * for the selected DAC channel.
1508 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1509 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1510 * @param DACx DAC instance
1511 * @param DAC_Channel This parameter can be one of the following values:
1512 * @arg @ref LL_DAC_CHANNEL_1
1513 * @arg @ref LL_DAC_CHANNEL_2
1514 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1515 * @retval None
1516 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1517 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1518 {
1519 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1520 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1521
1522 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1523 }
1524
1525 /**
1526 * @brief Set the data to be loaded in the data holding register
1527 * in format 8 bits left alignment (LSB aligned on bit 0),
1528 * for the selected DAC channel.
1529 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1530 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1531 * @param DACx DAC instance
1532 * @param DAC_Channel This parameter can be one of the following values:
1533 * @arg @ref LL_DAC_CHANNEL_1
1534 * @arg @ref LL_DAC_CHANNEL_2
1535 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1536 * @retval None
1537 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1538 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1539 {
1540 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1541 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1542
1543 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1544 }
1545
1546
1547 /**
1548 * @brief Set the data to be loaded in the data holding register
1549 * in format 12 bits left alignment (LSB aligned on bit 0),
1550 * for both DAC channels.
1551 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1552 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1553 * @param DACx DAC instance
1554 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1555 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1556 * @retval None
1557 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1558 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1559 uint32_t DataChannel2)
1560 {
1561 MODIFY_REG(DACx->DHR12RD,
1562 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1563 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1564 }
1565
1566 /**
1567 * @brief Set the data to be loaded in the data holding register
1568 * in format 12 bits left alignment (MSB aligned on bit 15),
1569 * for both DAC channels.
1570 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1571 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1572 * @param DACx DAC instance
1573 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1574 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1575 * @retval None
1576 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1577 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1578 uint32_t DataChannel2)
1579 {
1580 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1581 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1582 /* the 4 LSB must be taken into account for the shift value. */
1583 MODIFY_REG(DACx->DHR12LD,
1584 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1585 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1586 }
1587
1588 /**
1589 * @brief Set the data to be loaded in the data holding register
1590 * in format 8 bits left alignment (LSB aligned on bit 0),
1591 * for both DAC channels.
1592 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1593 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1594 * @param DACx DAC instance
1595 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1596 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1597 * @retval None
1598 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1599 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1600 uint32_t DataChannel2)
1601 {
1602 MODIFY_REG(DACx->DHR8RD,
1603 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1604 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1605 }
1606
1607
1608 /**
1609 * @brief Retrieve output data currently generated for the selected DAC channel.
1610 * @note Whatever alignment and resolution settings
1611 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1612 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1613 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1614 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1615 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1616 * @param DACx DAC instance
1617 * @param DAC_Channel This parameter can be one of the following values:
1618 * @arg @ref LL_DAC_CHANNEL_1
1619 * @arg @ref LL_DAC_CHANNEL_2
1620 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1621 */
LL_DAC_RetrieveOutputData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1622 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1623 {
1624 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1625 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1626
1627 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1628 }
1629
1630 /**
1631 * @}
1632 */
1633
1634 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1635 * @{
1636 */
1637
1638 /**
1639 * @brief Get DAC calibration offset flag for DAC channel 1
1640 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1641 * @param DACx DAC instance
1642 * @retval State of bit (1 or 0).
1643 */
LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef * DACx)1644 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
1645 {
1646 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1647 }
1648
1649
1650 /**
1651 * @brief Get DAC calibration offset flag for DAC channel 2
1652 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
1653 * @param DACx DAC instance
1654 * @retval State of bit (1 or 0).
1655 */
LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef * DACx)1656 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
1657 {
1658 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1659 }
1660
1661
1662 /**
1663 * @brief Get DAC busy writing sample time flag for DAC channel 1
1664 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1665 * @param DACx DAC instance
1666 * @retval State of bit (1 or 0).
1667 */
LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef * DACx)1668 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
1669 {
1670 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1671 }
1672
1673 /**
1674 * @brief Get DAC busy writing sample time flag for DAC channel 2
1675 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
1676 * @param DACx DAC instance
1677 * @retval State of bit (1 or 0).
1678 */
LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef * DACx)1679 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
1680 {
1681 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1682 }
1683
1684
1685 /**
1686 * @brief Get DAC underrun flag for DAC channel 1
1687 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1688 * @param DACx DAC instance
1689 * @retval State of bit (1 or 0).
1690 */
LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef * DACx)1691 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
1692 {
1693 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1694 }
1695
1696
1697 /**
1698 * @brief Get DAC underrun flag for DAC channel 2
1699 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1700 * @param DACx DAC instance
1701 * @retval State of bit (1 or 0).
1702 */
LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef * DACx)1703 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
1704 {
1705 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1706 }
1707
1708
1709 /**
1710 * @brief Clear DAC underrun flag for DAC channel 1
1711 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1712 * @param DACx DAC instance
1713 * @retval None
1714 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1715 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1716 {
1717 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1718 }
1719
1720
1721 /**
1722 * @brief Clear DAC underrun flag for DAC channel 2
1723 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1724 * @param DACx DAC instance
1725 * @retval None
1726 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1727 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1728 {
1729 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1730 }
1731
1732
1733 /**
1734 * @}
1735 */
1736
1737 /** @defgroup DAC_LL_EF_IT_Management IT management
1738 * @{
1739 */
1740
1741 /**
1742 * @brief Enable DMA underrun interrupt for DAC channel 1
1743 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1744 * @param DACx DAC instance
1745 * @retval None
1746 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1747 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1748 {
1749 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1750 }
1751
1752
1753 /**
1754 * @brief Enable DMA underrun interrupt for DAC channel 2
1755 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1756 * @param DACx DAC instance
1757 * @retval None
1758 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1759 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1760 {
1761 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1762 }
1763
1764
1765 /**
1766 * @brief Disable DMA underrun interrupt for DAC channel 1
1767 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1768 * @param DACx DAC instance
1769 * @retval None
1770 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1771 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1772 {
1773 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1774 }
1775
1776
1777 /**
1778 * @brief Disable DMA underrun interrupt for DAC channel 2
1779 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1780 * @param DACx DAC instance
1781 * @retval None
1782 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1783 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1784 {
1785 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1786 }
1787
1788
1789 /**
1790 * @brief Get DMA underrun interrupt for DAC channel 1
1791 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1792 * @param DACx DAC instance
1793 * @retval State of bit (1 or 0).
1794 */
LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef * DACx)1795 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
1796 {
1797 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1798 }
1799
1800
1801 /**
1802 * @brief Get DMA underrun interrupt for DAC channel 2
1803 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1804 * @param DACx DAC instance
1805 * @retval State of bit (1 or 0).
1806 */
LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef * DACx)1807 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
1808 {
1809 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1810 }
1811
1812
1813 /**
1814 * @}
1815 */
1816
1817 #if defined(USE_FULL_LL_DRIVER)
1818 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1819 * @{
1820 */
1821
1822 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
1823 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
1824 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1825
1826 /**
1827 * @}
1828 */
1829 #endif /* USE_FULL_LL_DRIVER */
1830
1831 /**
1832 * @}
1833 */
1834
1835 /**
1836 * @}
1837 */
1838
1839 #endif /* DAC1 */
1840
1841 /**
1842 * @}
1843 */
1844
1845 #ifdef __cplusplus
1846 }
1847 #endif
1848
1849 #endif /* STM32L5xx_LL_DAC_H */
1850