1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_swpmi.h
4 * @author MCD Application Team
5 * @brief Header file of SWPMI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_SWPMI_H
21 #define STM32L4xx_LL_SWPMI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined(SWPMI1)
35
36 /** @defgroup SWPMI_LL SWPMI
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 #if defined(USE_FULL_LL_DRIVER)
45 /** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros
46 * @{
47 */
48 /**
49 * @}
50 */
51 #endif /*USE_FULL_LL_DRIVER*/
52
53 /* Exported types ------------------------------------------------------------*/
54 #if defined(USE_FULL_LL_DRIVER)
55 /** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure
56 * @{
57 */
58
59 /**
60 * @brief SWPMI Init structures definition
61 */
62 typedef struct
63 {
64 uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class.
65 This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS
66
67 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */
68
69 uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler.
70 This parameter must be a number between Min_Data=0 and Max_Data=63U.
71
72 The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER
73
74 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */
75
76 uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode.
77 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX
78
79 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */
80
81 uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode.
82 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX
83
84 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */
85 } LL_SWPMI_InitTypeDef;
86
87 /**
88 * @}
89 */
90 #endif /* USE_FULL_LL_DRIVER */
91
92 /* Exported constants --------------------------------------------------------*/
93 /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants
94 * @{
95 */
96
97 /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines
98 * @brief Flags defines which can be used with LL_SWPMI_WriteReg function
99 * @{
100 */
101 #define LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF /*!< Clear receive buffer full flag */
102 #define LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF /*!< Clear transmit buffer empty flag */
103 #define LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag */
104 #define LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag */
105 #define LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */
106 #define LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF /*!< Clear transfer complete flag */
107 #define LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF /*!< Clear slave resume flag */
108 /**
109 * @}
110 */
111
112 /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines
113 * @brief Flags defines which can be used with LL_SWPMI_ReadReg function
114 * @{
115 */
116 #define LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF /*!< Receive buffer full flag */
117 #define LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF /*!< Transmit buffer empty flag */
118 #define LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF /*!< Receive CRC error flag */
119 #define LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF /*!< Receive overrun error flag */
120 #define LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF /*!< Transmit underrun error flag */
121 #define LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE /*!< Receive data register not empty */
122 #define LL_SWPMI_ISR_TXE SWPMI_ISR_TXE /*!< Transmit data register empty */
123 #define LL_SWPMI_ISR_TCF SWPMI_ISR_TCF /*!< Transfer complete flag */
124 #define LL_SWPMI_ISR_SRF SWPMI_ISR_SRF /*!< Slave resume flag */
125 #define LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP /*!< SUSPEND flag */
126 #define LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF /*!< DEACTIVATED flag */
127 /**
128 * @}
129 */
130
131 /** @defgroup SWPMI_LL_EC_IT IT Defines
132 * @brief IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions
133 * @{
134 */
135 #define LL_SWPMI_IER_SRIE SWPMI_IER_SRIE /*!< Slave resume interrupt enable */
136 #define LL_SWPMI_IER_TCIE SWPMI_IER_TCIE /*!< Transmit complete interrupt enable */
137 #define LL_SWPMI_IER_TIE SWPMI_IER_TIE /*!< Transmit interrupt enable */
138 #define LL_SWPMI_IER_RIE SWPMI_IER_RIE /*!< Receive interrupt enable */
139 #define LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */
140 #define LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable */
141 #define LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable */
142 #define LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE /*!< Transmit buffer empty interrupt enable */
143 #define LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE /*!< Receive buffer full interrupt enable */
144 /**
145 * @}
146 */
147
148 /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX
149 * @{
150 */
151 #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for reception */
152 #define LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE /*!< Multi software buffermode for reception */
153 /**
154 * @}
155 */
156
157 /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX
158 * @{
159 */
160 #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for transmission */
161 #define LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE /*!< Multi software buffermode for transmission */
162 /**
163 * @}
164 */
165
166 /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS
167 * @{
168 */
169 #define LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000) /*!< SWPMI_IO uses directly VDD voltage to operate in class C */
170 #define LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */
171 /**
172 * @}
173 */
174
175 /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data
176 * @{
177 */
178 #define LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0 /*!< Get address of data register used for transmission */
179 #define LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1 /*!< Get address of data register used for reception */
180 /**
181 * @}
182 */
183
184 /**
185 * @}
186 */
187
188 /* Exported macro ------------------------------------------------------------*/
189 /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros
190 * @{
191 */
192
193 /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros
194 * @{
195 */
196
197 /**
198 * @brief Write a value in SWPMI register
199 * @param __INSTANCE__ SWPMI Instance
200 * @param __REG__ Register to be written
201 * @param __VALUE__ Value to be written in the register
202 * @retval None
203 */
204 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
205
206 /**
207 * @brief Read a value in SWPMI register
208 * @param __INSTANCE__ SWPMI Instance
209 * @param __REG__ Register to be read
210 * @retval Register value
211 */
212 #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
213 /**
214 * @}
215 */
216
217 /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros
218 * @{
219 */
220
221 /**
222 * @brief Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function)
223 * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
224 * @param __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)
225 * @param __FSWPCLK__ PCLK or HSI frequency (in Hz)
226 * @retval Bitrate prescaler (BRR register)
227 */
228 #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
229
230 /**
231 * @}
232 */
233
234 /**
235 * @}
236 */
237
238 /* Exported functions --------------------------------------------------------*/
239 /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions
240 * @{
241 */
242
243 /** @defgroup SWPMI_LL_EF_Configuration Configuration
244 * @{
245 */
246
247 /**
248 * @brief Set Reception buffering mode
249 * @note If Multi software buffer mode is chosen, RXDMA bits must also be set.
250 * @rmtoll CR RXMODE LL_SWPMI_SetReceptionMode
251 * @param SWPMIx SWPMI Instance
252 * @param RxBufferingMode This parameter can be one of the following values:
253 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
254 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
255 * @retval None
256 */
LL_SWPMI_SetReceptionMode(SWPMI_TypeDef * SWPMIx,uint32_t RxBufferingMode)257 __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
258 {
259 MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode);
260 }
261
262 /**
263 * @brief Get Reception buffering mode
264 * @rmtoll CR RXMODE LL_SWPMI_GetReceptionMode
265 * @param SWPMIx SWPMI Instance
266 * @retval Returned value can be one of the following values:
267 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
268 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
269 */
LL_SWPMI_GetReceptionMode(const SWPMI_TypeDef * SWPMIx)270 __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(const SWPMI_TypeDef *SWPMIx)
271 {
272 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));
273 }
274
275 /**
276 * @brief Set Transmission buffering mode
277 * @note If Multi software buffer mode is chosen, TXDMA bits must also be set.
278 * @rmtoll CR TXMODE LL_SWPMI_SetTransmissionMode
279 * @param SWPMIx SWPMI Instance
280 * @param TxBufferingMode This parameter can be one of the following values:
281 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
282 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
283 * @retval None
284 */
LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef * SWPMIx,uint32_t TxBufferingMode)285 __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
286 {
287 MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode);
288 }
289
290 /**
291 * @brief Get Transmission buffering mode
292 * @rmtoll CR TXMODE LL_SWPMI_GetTransmissionMode
293 * @param SWPMIx SWPMI Instance
294 * @retval Returned value can be one of the following values:
295 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
296 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
297 */
LL_SWPMI_GetTransmissionMode(const SWPMI_TypeDef * SWPMIx)298 __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(const SWPMI_TypeDef *SWPMIx)
299 {
300 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));
301 }
302
303 /**
304 * @brief Enable loopback mode
305 * @rmtoll CR LPBK LL_SWPMI_EnableLoopback
306 * @param SWPMIx SWPMI Instance
307 * @retval None
308 */
LL_SWPMI_EnableLoopback(SWPMI_TypeDef * SWPMIx)309 __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
310 {
311 SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
312 }
313
314 /**
315 * @brief Disable loopback mode
316 * @rmtoll CR LPBK LL_SWPMI_DisableLoopback
317 * @param SWPMIx SWPMI Instance
318 * @retval None
319 */
LL_SWPMI_DisableLoopback(SWPMI_TypeDef * SWPMIx)320 __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
321 {
322 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
323 }
324
325 /**
326 * @brief Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
327 * @note SWP bus stays in the ACTIVATED state as long as there is a communication
328 * with the slave, either in transmission or in reception. The SWP bus switches back
329 * to the SUSPENDED state as soon as there is no more transmission or reception
330 * activity, after 7 idle bits.
331 * @rmtoll CR SWPACT LL_SWPMI_Activate
332 * @param SWPMIx SWPMI Instance
333 * @retval None
334 */
LL_SWPMI_Activate(SWPMI_TypeDef * SWPMIx)335 __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
336 {
337 /* In order to activate SWP again, the software must clear DEACT bit*/
338 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
339
340 /* Set SWACT bit */
341 SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
342 }
343
344 /**
345 * @brief Check if Single wire protocol bus is in ACTIVATED state.
346 * @rmtoll CR SWPACT LL_SWPMI_Activate
347 * @param SWPMIx SWPMI Instance
348 * @retval State of bit (1 or 0).
349 */
LL_SWPMI_IsActivated(const SWPMI_TypeDef * SWPMIx)350 __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(const SWPMI_TypeDef *SWPMIx)
351 {
352 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL);
353 }
354
355 /**
356 * @brief Deactivate immediately Single wire protocol bus (immediate transition to
357 * DEACTIVATED state)
358 * @rmtoll CR SWPACT LL_SWPMI_Deactivate
359 * @param SWPMIx SWPMI Instance
360 * @retval None
361 */
LL_SWPMI_Deactivate(SWPMI_TypeDef * SWPMIx)362 __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
363 {
364 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
365 }
366
367 /**
368 * @brief Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED
369 * state if no resume from slave)
370 * @rmtoll CR DEACT LL_SWPMI_RequestDeactivation
371 * @param SWPMIx SWPMI Instance
372 * @retval None
373 */
LL_SWPMI_RequestDeactivation(SWPMI_TypeDef * SWPMIx)374 __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
375 {
376 SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
377 }
378
379 /**
380 * @brief Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)
381 * @rmtoll BRR BR LL_SWPMI_SetBitRatePrescaler
382 * @param SWPMIx SWPMI Instance
383 * @param BitRatePrescaler A number between Min_Data=0 and Max_Data=63U
384 * @retval None
385 */
LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef * SWPMIx,uint32_t BitRatePrescaler)386 __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
387 {
388 WRITE_REG(SWPMIx->BRR, BitRatePrescaler);
389 }
390
391 /**
392 * @brief Get Bitrate prescaler
393 * @rmtoll BRR BR LL_SWPMI_GetBitRatePrescaler
394 * @param SWPMIx SWPMI Instance
395 * @retval A number between Min_Data=0 and Max_Data=63U
396 */
LL_SWPMI_GetBitRatePrescaler(const SWPMI_TypeDef * SWPMIx)397 __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(const SWPMI_TypeDef *SWPMIx)
398 {
399 return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));
400 }
401
402 /**
403 * @brief Set SWP Voltage Class
404 * @rmtoll OR CLASS LL_SWPMI_SetVoltageClass
405 * @param SWPMIx SWPMI Instance
406 * @param VoltageClass This parameter can be one of the following values:
407 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
408 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
409 * @retval None
410 */
LL_SWPMI_SetVoltageClass(SWPMI_TypeDef * SWPMIx,uint32_t VoltageClass)411 __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
412 {
413 MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass);
414 }
415
416 /**
417 * @brief Get SWP Voltage Class
418 * @rmtoll OR CLASS LL_SWPMI_GetVoltageClass
419 * @param SWPMIx SWPMI Instance
420 * @retval Returned value can be one of the following values:
421 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
422 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
423 */
LL_SWPMI_GetVoltageClass(const SWPMI_TypeDef * SWPMIx)424 __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(const SWPMI_TypeDef *SWPMIx)
425 {
426 return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));
427 }
428
429 /**
430 * @}
431 */
432
433 /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management
434 * @{
435 */
436
437 /**
438 * @brief Check if the last word of the frame under reception has arrived in SWPMI_RDR.
439 * @rmtoll ISR RXBFF LL_SWPMI_IsActiveFlag_RXBF
440 * @param SWPMIx SWPMI Instance
441 * @retval State of bit (1 or 0).
442 */
LL_SWPMI_IsActiveFlag_RXBF(const SWPMI_TypeDef * SWPMIx)443 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(const SWPMI_TypeDef *SWPMIx)
444 {
445 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL);
446 }
447
448 /**
449 * @brief Check if Frame transmission buffer has been emptied
450 * @rmtoll ISR TXBEF LL_SWPMI_IsActiveFlag_TXBE
451 * @param SWPMIx SWPMI Instance
452 * @retval State of bit (1 or 0).
453 */
LL_SWPMI_IsActiveFlag_TXBE(const SWPMI_TypeDef * SWPMIx)454 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(const SWPMI_TypeDef *SWPMIx)
455 {
456 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL);
457 }
458
459 /**
460 * @brief Check if CRC error in reception has been detected
461 * @rmtoll ISR RXBERF LL_SWPMI_IsActiveFlag_RXBER
462 * @param SWPMIx SWPMI Instance
463 * @retval State of bit (1 or 0).
464 */
LL_SWPMI_IsActiveFlag_RXBER(const SWPMI_TypeDef * SWPMIx)465 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(const SWPMI_TypeDef *SWPMIx)
466 {
467 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL);
468 }
469
470 /**
471 * @brief Check if Overrun in reception has been detected
472 * @rmtoll ISR RXOVRF LL_SWPMI_IsActiveFlag_RXOVR
473 * @param SWPMIx SWPMI Instance
474 * @retval State of bit (1 or 0).
475 */
LL_SWPMI_IsActiveFlag_RXOVR(const SWPMI_TypeDef * SWPMIx)476 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(const SWPMI_TypeDef *SWPMIx)
477 {
478 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL);
479 }
480
481 /**
482 * @brief Check if underrun error in transmission has been detected
483 * @rmtoll ISR TXUNRF LL_SWPMI_IsActiveFlag_TXUNR
484 * @param SWPMIx SWPMI Instance
485 * @retval State of bit (1 or 0).
486 */
LL_SWPMI_IsActiveFlag_TXUNR(const SWPMI_TypeDef * SWPMIx)487 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(const SWPMI_TypeDef *SWPMIx)
488 {
489 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL);
490 }
491
492 /**
493 * @brief Check if Receive data register not empty (it means that Received data is ready
494 * to be read in the SWPMI_RDR register)
495 * @rmtoll ISR RXNE LL_SWPMI_IsActiveFlag_RXNE
496 * @param SWPMIx SWPMI Instance
497 * @retval State of bit (1 or 0).
498 */
LL_SWPMI_IsActiveFlag_RXNE(const SWPMI_TypeDef * SWPMIx)499 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(const SWPMI_TypeDef *SWPMIx)
500 {
501 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL);
502 }
503
504 /**
505 * @brief Check if Transmit data register is empty (it means that Data written in transmit
506 * data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
507 * @rmtoll ISR TXE LL_SWPMI_IsActiveFlag_TXE
508 * @param SWPMIx SWPMI Instance
509 * @retval State of bit (1 or 0).
510 */
LL_SWPMI_IsActiveFlag_TXE(const SWPMI_TypeDef * SWPMIx)511 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(const SWPMI_TypeDef *SWPMIx)
512 {
513 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL);
514 }
515
516 /**
517 * @brief Check if Both transmission and reception are completed and SWP is switched to
518 * the SUSPENDED state
519 * @rmtoll ISR TCF LL_SWPMI_IsActiveFlag_TC
520 * @param SWPMIx SWPMI Instance
521 * @retval State of bit (1 or 0).
522 */
LL_SWPMI_IsActiveFlag_TC(const SWPMI_TypeDef * SWPMIx)523 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(const SWPMI_TypeDef *SWPMIx)
524 {
525 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL);
526 }
527
528 /**
529 * @brief Check if a Resume by slave state has been detected during the SWP bus SUSPENDED
530 * state
531 * @rmtoll ISR SRF LL_SWPMI_IsActiveFlag_SR
532 * @param SWPMIx SWPMI Instance
533 * @retval State of bit (1 or 0).
534 */
LL_SWPMI_IsActiveFlag_SR(const SWPMI_TypeDef * SWPMIx)535 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(const SWPMI_TypeDef *SWPMIx)
536 {
537 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL);
538 }
539
540 /**
541 * @brief Check if SWP bus is in SUSPENDED or DEACTIVATED state
542 * @rmtoll ISR SUSP LL_SWPMI_IsActiveFlag_SUSP
543 * @param SWPMIx SWPMI Instance
544 * @retval State of bit (1 or 0).
545 */
LL_SWPMI_IsActiveFlag_SUSP(const SWPMI_TypeDef * SWPMIx)546 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(const SWPMI_TypeDef *SWPMIx)
547 {
548 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL);
549 }
550
551 /**
552 * @brief Check if SWP bus is in DEACTIVATED state
553 * @rmtoll ISR DEACTF LL_SWPMI_IsActiveFlag_DEACT
554 * @param SWPMIx SWPMI Instance
555 * @retval State of bit (1 or 0).
556 */
LL_SWPMI_IsActiveFlag_DEACT(const SWPMI_TypeDef * SWPMIx)557 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(const SWPMI_TypeDef *SWPMIx)
558 {
559 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL);
560 }
561
562 /**
563 * @brief Clear receive buffer full flag
564 * @rmtoll ICR CRXBFF LL_SWPMI_ClearFlag_RXBF
565 * @param SWPMIx SWPMI Instance
566 * @retval None
567 */
LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef * SWPMIx)568 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
569 {
570 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);
571 }
572
573 /**
574 * @brief Clear transmit buffer empty flag
575 * @rmtoll ICR CTXBEF LL_SWPMI_ClearFlag_TXBE
576 * @param SWPMIx SWPMI Instance
577 * @retval None
578 */
LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef * SWPMIx)579 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
580 {
581 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);
582 }
583
584 /**
585 * @brief Clear receive CRC error flag
586 * @rmtoll ICR CRXBERF LL_SWPMI_ClearFlag_RXBER
587 * @param SWPMIx SWPMI Instance
588 * @retval None
589 */
LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef * SWPMIx)590 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
591 {
592 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);
593 }
594
595 /**
596 * @brief Clear receive overrun error flag
597 * @rmtoll ICR CRXOVRF LL_SWPMI_ClearFlag_RXOVR
598 * @param SWPMIx SWPMI Instance
599 * @retval None
600 */
LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef * SWPMIx)601 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
602 {
603 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);
604 }
605
606 /**
607 * @brief Clear transmit underrun error flag
608 * @rmtoll ICR CTXUNRF LL_SWPMI_ClearFlag_TXUNR
609 * @param SWPMIx SWPMI Instance
610 * @retval None
611 */
LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef * SWPMIx)612 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
613 {
614 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);
615 }
616
617 /**
618 * @brief Clear transfer complete flag
619 * @rmtoll ICR CTCF LL_SWPMI_ClearFlag_TC
620 * @param SWPMIx SWPMI Instance
621 * @retval None
622 */
LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef * SWPMIx)623 __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
624 {
625 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);
626 }
627
628 /**
629 * @brief Clear slave resume flag
630 * @rmtoll ICR CSRF LL_SWPMI_ClearFlag_SR
631 * @param SWPMIx SWPMI Instance
632 * @retval None
633 */
LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef * SWPMIx)634 __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
635 {
636 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);
637 }
638
639 /**
640 * @}
641 */
642
643 /** @defgroup SWPMI_LL_EF_IT_Management IT_Management
644 * @{
645 */
646
647 /**
648 * @brief Enable Slave resume interrupt
649 * @rmtoll IER SRIE LL_SWPMI_EnableIT_SR
650 * @param SWPMIx SWPMI Instance
651 * @retval None
652 */
LL_SWPMI_EnableIT_SR(SWPMI_TypeDef * SWPMIx)653 __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
654 {
655 SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
656 }
657
658 /**
659 * @brief Enable Transmit complete interrupt
660 * @rmtoll IER TCIE LL_SWPMI_EnableIT_TC
661 * @param SWPMIx SWPMI Instance
662 * @retval None
663 */
LL_SWPMI_EnableIT_TC(SWPMI_TypeDef * SWPMIx)664 __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
665 {
666 SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
667 }
668
669 /**
670 * @brief Enable Transmit interrupt
671 * @rmtoll IER TIE LL_SWPMI_EnableIT_TX
672 * @param SWPMIx SWPMI Instance
673 * @retval None
674 */
LL_SWPMI_EnableIT_TX(SWPMI_TypeDef * SWPMIx)675 __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
676 {
677 SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);
678 }
679
680 /**
681 * @brief Enable Receive interrupt
682 * @rmtoll IER RIE LL_SWPMI_EnableIT_RX
683 * @param SWPMIx SWPMI Instance
684 * @retval None
685 */
LL_SWPMI_EnableIT_RX(SWPMI_TypeDef * SWPMIx)686 __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
687 {
688 SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);
689 }
690
691 /**
692 * @brief Enable Transmit underrun error interrupt
693 * @rmtoll IER TXUNRIE LL_SWPMI_EnableIT_TXUNR
694 * @param SWPMIx SWPMI Instance
695 * @retval None
696 */
LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef * SWPMIx)697 __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
698 {
699 SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
700 }
701
702 /**
703 * @brief Enable Receive overrun error interrupt
704 * @rmtoll IER RXOVRIE LL_SWPMI_EnableIT_RXOVR
705 * @param SWPMIx SWPMI Instance
706 * @retval None
707 */
LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef * SWPMIx)708 __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
709 {
710 SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
711 }
712
713 /**
714 * @brief Enable Receive CRC error interrupt
715 * @rmtoll IER RXBERIE LL_SWPMI_EnableIT_RXBER
716 * @param SWPMIx SWPMI Instance
717 * @retval None
718 */
LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef * SWPMIx)719 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
720 {
721 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
722 }
723
724 /**
725 * @brief Enable Transmit buffer empty interrupt
726 * @rmtoll IER TXBEIE LL_SWPMI_EnableIT_TXBE
727 * @param SWPMIx SWPMI Instance
728 * @retval None
729 */
LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef * SWPMIx)730 __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
731 {
732 SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
733 }
734
735 /**
736 * @brief Enable Receive buffer full interrupt
737 * @rmtoll IER RXBFIE LL_SWPMI_EnableIT_RXBF
738 * @param SWPMIx SWPMI Instance
739 * @retval None
740 */
LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef * SWPMIx)741 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
742 {
743 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
744 }
745
746 /**
747 * @brief Disable Slave resume interrupt
748 * @rmtoll IER SRIE LL_SWPMI_DisableIT_SR
749 * @param SWPMIx SWPMI Instance
750 * @retval None
751 */
LL_SWPMI_DisableIT_SR(SWPMI_TypeDef * SWPMIx)752 __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
753 {
754 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
755 }
756
757 /**
758 * @brief Disable Transmit complete interrupt
759 * @rmtoll IER TCIE LL_SWPMI_DisableIT_TC
760 * @param SWPMIx SWPMI Instance
761 * @retval None
762 */
LL_SWPMI_DisableIT_TC(SWPMI_TypeDef * SWPMIx)763 __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
764 {
765 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
766 }
767
768 /**
769 * @brief Disable Transmit interrupt
770 * @rmtoll IER TIE LL_SWPMI_DisableIT_TX
771 * @param SWPMIx SWPMI Instance
772 * @retval None
773 */
LL_SWPMI_DisableIT_TX(SWPMI_TypeDef * SWPMIx)774 __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
775 {
776 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);
777 }
778
779 /**
780 * @brief Disable Receive interrupt
781 * @rmtoll IER RIE LL_SWPMI_DisableIT_RX
782 * @param SWPMIx SWPMI Instance
783 * @retval None
784 */
LL_SWPMI_DisableIT_RX(SWPMI_TypeDef * SWPMIx)785 __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
786 {
787 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);
788 }
789
790 /**
791 * @brief Disable Transmit underrun error interrupt
792 * @rmtoll IER TXUNRIE LL_SWPMI_DisableIT_TXUNR
793 * @param SWPMIx SWPMI Instance
794 * @retval None
795 */
LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef * SWPMIx)796 __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
797 {
798 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
799 }
800
801 /**
802 * @brief Disable Receive overrun error interrupt
803 * @rmtoll IER RXOVRIE LL_SWPMI_DisableIT_RXOVR
804 * @param SWPMIx SWPMI Instance
805 * @retval None
806 */
LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef * SWPMIx)807 __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
808 {
809 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
810 }
811
812 /**
813 * @brief Disable Receive CRC error interrupt
814 * @rmtoll IER RXBERIE LL_SWPMI_DisableIT_RXBER
815 * @param SWPMIx SWPMI Instance
816 * @retval None
817 */
LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef * SWPMIx)818 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
819 {
820 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
821 }
822
823 /**
824 * @brief Disable Transmit buffer empty interrupt
825 * @rmtoll IER TXBEIE LL_SWPMI_DisableIT_TXBE
826 * @param SWPMIx SWPMI Instance
827 * @retval None
828 */
LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef * SWPMIx)829 __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
830 {
831 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
832 }
833
834 /**
835 * @brief Disable Receive buffer full interrupt
836 * @rmtoll IER RXBFIE LL_SWPMI_DisableIT_RXBF
837 * @param SWPMIx SWPMI Instance
838 * @retval None
839 */
LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef * SWPMIx)840 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
841 {
842 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
843 }
844
845 /**
846 * @brief Check if Slave resume interrupt is enabled
847 * @rmtoll IER SRIE LL_SWPMI_IsEnabledIT_SR
848 * @param SWPMIx SWPMI Instance
849 * @retval State of bit (1 or 0).
850 */
LL_SWPMI_IsEnabledIT_SR(const SWPMI_TypeDef * SWPMIx)851 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(const SWPMI_TypeDef *SWPMIx)
852 {
853 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL);
854 }
855
856 /**
857 * @brief Check if Transmit complete interrupt is enabled
858 * @rmtoll IER TCIE LL_SWPMI_IsEnabledIT_TC
859 * @param SWPMIx SWPMI Instance
860 * @retval State of bit (1 or 0).
861 */
LL_SWPMI_IsEnabledIT_TC(const SWPMI_TypeDef * SWPMIx)862 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(const SWPMI_TypeDef *SWPMIx)
863 {
864 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL);
865 }
866
867 /**
868 * @brief Check if Transmit interrupt is enabled
869 * @rmtoll IER TIE LL_SWPMI_IsEnabledIT_TX
870 * @param SWPMIx SWPMI Instance
871 * @retval State of bit (1 or 0).
872 */
LL_SWPMI_IsEnabledIT_TX(const SWPMI_TypeDef * SWPMIx)873 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(const SWPMI_TypeDef *SWPMIx)
874 {
875 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL);
876 }
877
878 /**
879 * @brief Check if Receive interrupt is enabled
880 * @rmtoll IER RIE LL_SWPMI_IsEnabledIT_RX
881 * @param SWPMIx SWPMI Instance
882 * @retval State of bit (1 or 0).
883 */
LL_SWPMI_IsEnabledIT_RX(const SWPMI_TypeDef * SWPMIx)884 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(const SWPMI_TypeDef *SWPMIx)
885 {
886 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL);
887 }
888
889 /**
890 * @brief Check if Transmit underrun error interrupt is enabled
891 * @rmtoll IER TXUNRIE LL_SWPMI_IsEnabledIT_TXUNR
892 * @param SWPMIx SWPMI Instance
893 * @retval State of bit (1 or 0).
894 */
LL_SWPMI_IsEnabledIT_TXUNR(const SWPMI_TypeDef * SWPMIx)895 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(const SWPMI_TypeDef *SWPMIx)
896 {
897 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL);
898 }
899
900 /**
901 * @brief Check if Receive overrun error interrupt is enabled
902 * @rmtoll IER RXOVRIE LL_SWPMI_IsEnabledIT_RXOVR
903 * @param SWPMIx SWPMI Instance
904 * @retval State of bit (1 or 0).
905 */
LL_SWPMI_IsEnabledIT_RXOVR(const SWPMI_TypeDef * SWPMIx)906 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(const SWPMI_TypeDef *SWPMIx)
907 {
908 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL);
909 }
910
911 /**
912 * @brief Check if Receive CRC error interrupt is enabled
913 * @rmtoll IER RXBERIE LL_SWPMI_IsEnabledIT_RXBER
914 * @param SWPMIx SWPMI Instance
915 * @retval State of bit (1 or 0).
916 */
LL_SWPMI_IsEnabledIT_RXBER(const SWPMI_TypeDef * SWPMIx)917 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(const SWPMI_TypeDef *SWPMIx)
918 {
919 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL);
920 }
921
922 /**
923 * @brief Check if Transmit buffer empty interrupt is enabled
924 * @rmtoll IER TXBEIE LL_SWPMI_IsEnabledIT_TXBE
925 * @param SWPMIx SWPMI Instance
926 * @retval State of bit (1 or 0).
927 */
LL_SWPMI_IsEnabledIT_TXBE(const SWPMI_TypeDef * SWPMIx)928 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(const SWPMI_TypeDef *SWPMIx)
929 {
930 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL);
931 }
932
933 /**
934 * @brief Check if Receive buffer full interrupt is enabled
935 * @rmtoll IER RXBFIE LL_SWPMI_IsEnabledIT_RXBF
936 * @param SWPMIx SWPMI Instance
937 * @retval State of bit (1 or 0).
938 */
LL_SWPMI_IsEnabledIT_RXBF(const SWPMI_TypeDef * SWPMIx)939 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(const SWPMI_TypeDef *SWPMIx)
940 {
941 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL);
942 }
943
944 /**
945 * @}
946 */
947
948 /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management
949 * @{
950 */
951
952 /**
953 * @brief Enable DMA mode for reception
954 * @rmtoll CR RXDMA LL_SWPMI_EnableDMAReq_RX
955 * @param SWPMIx SWPMI Instance
956 * @retval None
957 */
LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef * SWPMIx)958 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
959 {
960 SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
961 }
962
963 /**
964 * @brief Disable DMA mode for reception
965 * @rmtoll CR RXDMA LL_SWPMI_DisableDMAReq_RX
966 * @param SWPMIx SWPMI Instance
967 * @retval None
968 */
LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef * SWPMIx)969 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
970 {
971 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
972 }
973
974 /**
975 * @brief Check if DMA mode for reception is enabled
976 * @rmtoll CR RXDMA LL_SWPMI_IsEnabledDMAReq_RX
977 * @param SWPMIx SWPMI Instance
978 * @retval State of bit (1 or 0).
979 */
LL_SWPMI_IsEnabledDMAReq_RX(const SWPMI_TypeDef * SWPMIx)980 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(const SWPMI_TypeDef *SWPMIx)
981 {
982 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL);
983 }
984
985 /**
986 * @brief Enable DMA mode for transmission
987 * @rmtoll CR TXDMA LL_SWPMI_EnableDMAReq_TX
988 * @param SWPMIx SWPMI Instance
989 * @retval None
990 */
LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef * SWPMIx)991 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
992 {
993 SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
994 }
995
996 /**
997 * @brief Disable DMA mode for transmission
998 * @rmtoll CR TXDMA LL_SWPMI_DisableDMAReq_TX
999 * @param SWPMIx SWPMI Instance
1000 * @retval None
1001 */
LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef * SWPMIx)1002 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1003 {
1004 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
1005 }
1006
1007 /**
1008 * @brief Check if DMA mode for transmission is enabled
1009 * @rmtoll CR TXDMA LL_SWPMI_IsEnabledDMAReq_TX
1010 * @param SWPMIx SWPMI Instance
1011 * @retval State of bit (1 or 0).
1012 */
LL_SWPMI_IsEnabledDMAReq_TX(const SWPMI_TypeDef * SWPMIx)1013 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(const SWPMI_TypeDef *SWPMIx)
1014 {
1015 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL);
1016 }
1017
1018 /**
1019 * @brief Get the data register address used for DMA transfer
1020 * @rmtoll TDR TD LL_SWPMI_DMA_GetRegAddr\n
1021 * RDR RD LL_SWPMI_DMA_GetRegAddr
1022 * @param SWPMIx SWPMI Instance
1023 * @param Direction This parameter can be one of the following values:
1024 * @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT
1025 * @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE
1026 * @retval Address of data register
1027 */
LL_SWPMI_DMA_GetRegAddr(const SWPMI_TypeDef * SWPMIx,uint32_t Direction)1028 __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(const SWPMI_TypeDef *SWPMIx, uint32_t Direction)
1029 {
1030 uint32_t data_reg_addr;
1031
1032 if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)
1033 {
1034 /* return address of TDR register */
1035 data_reg_addr = (uint32_t)&(SWPMIx->TDR);
1036 }
1037 else
1038 {
1039 /* return address of RDR register */
1040 data_reg_addr = (uint32_t)&(SWPMIx->RDR);
1041 }
1042
1043 return data_reg_addr;
1044 }
1045
1046 /**
1047 * @}
1048 */
1049
1050 /** @defgroup SWPMI_LL_EF_Data_Management Data_Management
1051 * @{
1052 */
1053
1054 /**
1055 * @brief Retrieve number of data bytes present in payload of received frame
1056 * @rmtoll RFL RFL LL_SWPMI_GetReceiveFrameLength
1057 * @param SWPMIx SWPMI Instance
1058 * @retval Value between Min_Data=0x00 and Max_Data=0x1F
1059 */
LL_SWPMI_GetReceiveFrameLength(const SWPMI_TypeDef * SWPMIx)1060 __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(const SWPMI_TypeDef *SWPMIx)
1061 {
1062 return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));
1063 }
1064
1065 /**
1066 * @brief Transmit Data Register
1067 * @rmtoll TDR TD LL_SWPMI_TransmitData32
1068 * @param SWPMIx SWPMI Instance
1069 * @param TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1070 * @retval None
1071 */
LL_SWPMI_TransmitData32(SWPMI_TypeDef * SWPMIx,uint32_t TxData)1072 __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
1073 {
1074 WRITE_REG(SWPMIx->TDR, TxData);
1075 }
1076
1077 /**
1078 * @brief Receive Data Register
1079 * @rmtoll RDR RD LL_SWPMI_ReceiveData32
1080 * @param SWPMIx SWPMI Instance
1081 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1082 */
LL_SWPMI_ReceiveData32(SWPMI_TypeDef * SWPMIx)1083 __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
1084 {
1085 return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));
1086 }
1087
1088 /**
1089 * @brief Enable SWP Transceiver Bypass
1090 * @note The external interface for SWPMI is SWPMI_IO
1091 * (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
1092 * @rmtoll OR TBYP LL_SWPMI_EnableTXBypass
1093 * @param SWPMIx SWPMI Instance
1094 * @retval None
1095 */
LL_SWPMI_EnableTXBypass(SWPMI_TypeDef * SWPMIx)1096 __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
1097 {
1098 CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1099 }
1100
1101 /**
1102 * @brief Disable SWP Transceiver Bypass
1103 * @note SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate
1104 * function on GPIOs. This configuration is selected to connect an external transceiver
1105 * @rmtoll OR TBYP LL_SWPMI_DisableTXBypass
1106 * @param SWPMIx SWPMI Instance
1107 * @retval None
1108 */
LL_SWPMI_DisableTXBypass(SWPMI_TypeDef * SWPMIx)1109 __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
1110 {
1111 SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1112 }
1113
1114 /**
1115 * @}
1116 */
1117
1118 #if defined(USE_FULL_LL_DRIVER)
1119 /** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions
1120 * @{
1121 */
1122
1123 ErrorStatus LL_SWPMI_DeInit(const SWPMI_TypeDef *SWPMIx);
1124 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, const LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1125 void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1126
1127 /**
1128 * @}
1129 */
1130 #endif /*USE_FULL_LL_DRIVER*/
1131
1132 /**
1133 * @}
1134 */
1135
1136 /**
1137 * @}
1138 */
1139
1140 #endif /* SWPMI1 */
1141
1142 /**
1143 * @}
1144 */
1145
1146 #ifdef __cplusplus
1147 }
1148 #endif
1149
1150 #endif /* STM32L4xx_LL_SWPMI_H */
1151
