1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_rng.h
4 * @author MCD Application Team
5 * @brief Header file of RNG LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_RNG_H
21 #define STM32L4xx_LL_RNG_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (RNG)
35
36 /** @defgroup RNG_LL RNG
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private defines -----------------------------------------------------------*/
42 /** @defgroup RNG_LL_Private_Defines RNG Private Defines
43 * @{
44 */
45 /* Health test control register information to use in CCM algorithm */
46 #define LL_RNG_HTCFG 0x17590ABCU /*!< Magic number */
47 /**
48 * @}
49 */
50 /* Private variables ---------------------------------------------------------*/
51 /* Private constants ---------------------------------------------------------*/
52 /* Private macros ------------------------------------------------------------*/
53
54 /* Exported types ------------------------------------------------------------*/
55 #if defined(RNG_CR_CED)
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
58 * @{
59 */
60
61
62 /**
63 * @brief LL RNG Init Structure Definition
64 */
65 typedef struct
66 {
67 uint32_t ClockErrorDetection; /*!< Clock error detection.
68 This parameter can be one value of @ref RNG_LL_CED.
69 This parameter can be modified using unitary
70 functions @ref LL_RNG_EnableClkErrorDetect(). */
71 } LL_RNG_InitTypeDef;
72
73 /**
74 * @}
75 */
76 #endif /* USE_FULL_LL_DRIVER */
77 #endif /* RNG_CR_CED */
78 /* Exported constants --------------------------------------------------------*/
79 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
80 * @{
81 */
82
83 #if defined(RNG_CR_CED)
84 /** @defgroup RNG_LL_CED Clock Error Detection
85 * @{
86 */
87 #define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
88 #define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
89 /**
90 * @}
91 */
92 #endif /* RNG_CR_CED */
93
94 #if defined(RNG_CR_CONDRST)
95 /** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal
96 * programmable divider acting on the incoming RNG clock
97 * @{
98 */
99 #define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
100 #define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */
101 #define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */
102 #define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */
103 #define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */
104 #define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */
105 #define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */
106 #define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */
107 #define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */
108 #define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */
109 #define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */
110 #define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */
111 #define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */
112 #define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */
113 #define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */
114 #define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */
115 /**
116 * @}
117 */
118
119 /** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration
120 * @{
121 */
122 #define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/
123 #define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */
124
125 /* Legacy alias */
126 #define LL_RNG_NOTNIST_COMPLIANT LL_RNG_CUSTOM_NIST
127 /**
128 * @}
129 */
130
131 #endif /* RNG_CR_CONDRST */
132 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
133 * @brief Flags defines which can be used with LL_RNG_ReadReg function
134 * @{
135 */
136 #define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
137 #define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
138 #define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
139 #define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
140 #define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
141 /**
142 * @}
143 */
144
145 /** @defgroup RNG_LL_EC_IT IT Defines
146 * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
147 * @{
148 */
149 #define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
150 /**
151 * @}
152 */
153
154 /**
155 * @}
156 */
157
158 /* Exported macro ------------------------------------------------------------*/
159 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
160 * @{
161 */
162
163 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
164 * @{
165 */
166
167 /**
168 * @brief Write a value in RNG register
169 * @param __INSTANCE__ RNG Instance
170 * @param __REG__ Register to be written
171 * @param __VALUE__ Value to be written in the register
172 * @retval None
173 */
174 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
175
176 /**
177 * @brief Read a value in RNG register
178 * @param __INSTANCE__ RNG Instance
179 * @param __REG__ Register to be read
180 * @retval Register value
181 */
182 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
183 /**
184 * @}
185 */
186
187 /**
188 * @}
189 */
190
191
192 /* Exported functions --------------------------------------------------------*/
193 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
194 * @{
195 */
196 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
197 * @{
198 */
199
200 /**
201 * @brief Enable Random Number Generation
202 * @rmtoll CR RNGEN LL_RNG_Enable
203 * @param RNGx RNG Instance
204 * @retval None
205 */
LL_RNG_Enable(RNG_TypeDef * RNGx)206 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
207 {
208 SET_BIT(RNGx->CR, RNG_CR_RNGEN);
209 }
210
211 /**
212 * @brief Disable Random Number Generation
213 * @rmtoll CR RNGEN LL_RNG_Disable
214 * @param RNGx RNG Instance
215 * @retval None
216 */
LL_RNG_Disable(RNG_TypeDef * RNGx)217 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
218 {
219 CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
220 }
221
222 /**
223 * @brief Check if Random Number Generator is enabled
224 * @rmtoll CR RNGEN LL_RNG_IsEnabled
225 * @param RNGx RNG Instance
226 * @retval State of bit (1 or 0).
227 */
LL_RNG_IsEnabled(const RNG_TypeDef * RNGx)228 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
229 {
230 return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
231 }
232
233 #if defined(RNG_CR_CED)
234 /**
235 * @brief Enable Clock Error Detection
236 * @rmtoll CR CED LL_RNG_EnableClkErrorDetect
237 * @param RNGx RNG Instance
238 * @retval None
239 */
LL_RNG_EnableClkErrorDetect(RNG_TypeDef * RNGx)240 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
241 {
242 #if defined(RNG_CR_CONDRST)
243 MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST);
244 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
245 #else
246 CLEAR_BIT(RNGx->CR, RNG_CR_CED);
247 #endif /* RNG_CR_CONDRST*/
248 }
249
250 /**
251 * @brief Disable RNG Clock Error Detection
252 * @rmtoll CR CED LL_RNG_DisableClkErrorDetect
253 * @param RNGx RNG Instance
254 * @retval None
255 */
LL_RNG_DisableClkErrorDetect(RNG_TypeDef * RNGx)256 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
257 {
258 #if defined(RNG_CR_CONDRST)
259 MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST);
260 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
261 #else
262 SET_BIT(RNGx->CR, RNG_CR_CED);
263 #endif /* RNG_CR_CONDRST*/
264 }
265
266 /**
267 * @brief Check if RNG Clock Error Detection is enabled
268 * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
269 * @param RNGx RNG Instance
270 * @retval State of bit (1 or 0).
271 */
LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef * RNGx)272 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
273 {
274 return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
275 }
276
277 #if defined(RNG_CR_CONDRST)
278 /**
279 * @brief Set RNG Conditioning Soft Reset bit
280 * @rmtoll CR CONDRST LL_RNG_SetConditioningResetBit
281 * @param RNGx RNG Instance
282 * @retval None
283 */
LL_RNG_SetConditioningResetBit(RNG_TypeDef * RNGx)284 __STATIC_INLINE void LL_RNG_SetConditioningResetBit(RNG_TypeDef *RNGx)
285 {
286 SET_BIT(RNGx->CR, RNG_CR_CONDRST);
287 }
288
289 /**
290 * @brief Reset RNG Conditioning Soft Reset bit
291 * @rmtoll CR CONDRST LL_RNG_ResetConditioningResetBit
292 * @param RNGx RNG Instance
293 * @retval None
294 */
LL_RNG_ResetConditioningResetBit(RNG_TypeDef * RNGx)295 __STATIC_INLINE void LL_RNG_ResetConditioningResetBit(RNG_TypeDef *RNGx)
296 {
297 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
298 }
299
300 /**
301 * @brief Check if RNG Conditioning Soft Reset bit is set
302 * @rmtoll CR CONDRST LL_RNG_IsResetConditioningBitSet
303 * @param RNGx RNG Instance
304 * @retval State of bit (1 or 0).
305 */
LL_RNG_IsResetConditioningBitSet(RNG_TypeDef * RNGx)306 __STATIC_INLINE uint32_t LL_RNG_IsResetConditioningBitSet(RNG_TypeDef *RNGx)
307 {
308 return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
309 }
310
311 /**
312 * @brief Enable RNG Config Lock
313 * @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock
314 * @param RNGx RNG Instance
315 * @retval None
316 */
LL_RNG_ConfigLock(RNG_TypeDef * RNGx)317 __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
318 {
319 SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
320 }
321
322 /**
323 * @brief Check if RNG Config Lock is enabled
324 * @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked
325 * @param RNGx RNG Instance
326 * @retval State of bit (1 or 0).
327 */
LL_RNG_IsConfigLocked(RNG_TypeDef * RNGx)328 __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
329 {
330 return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
331 }
332
333 /**
334 * @brief Enable NIST Compliance
335 * @rmtoll CR NISTC LL_RNG_EnableNistCompliance
336 * @param RNGx RNG Instance
337 * @retval None
338 */
LL_RNG_EnableNistCompliance(RNG_TypeDef * RNGx)339 __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
340 {
341 MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST);
342 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
343 }
344
345 /**
346 * @brief Disable NIST Compliance
347 * @rmtoll CR NISTC LL_RNG_DisableNistCompliance
348 * @param RNGx RNG Instance
349 * @retval None
350 */
LL_RNG_DisableNistCompliance(RNG_TypeDef * RNGx)351 __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
352 {
353 MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST);
354 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
355 }
356
357 /**
358 * @brief Check if NIST Compliance is enabled
359 * @rmtoll CR NISTC LL_RNG_IsNistComplianceEnabled
360 * @param RNGx RNG Instance
361 * @retval State of bit (1 or 0).
362 */
LL_RNG_IsNistComplianceEnabled(RNG_TypeDef * RNGx)363 __STATIC_INLINE uint32_t LL_RNG_IsNistComplianceEnabled(RNG_TypeDef *RNGx)
364 {
365 return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
366 }
367
368 /**
369 * @brief Set RNG Config1 Configuration field value
370 * @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1
371 * @param RNGx RNG Instance
372 * @param Config1 Value between 0 and 0x3F
373 * @retval None
374 */
LL_RNG_SetConfig1(RNG_TypeDef * RNGx,uint32_t Config1)375 __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
376 {
377 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST);
378 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
379 }
380
381 /**
382 * @brief Get RNG Config1 Configuration field value
383 * @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1
384 * @param RNGx RNG Instance
385 * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
386 */
LL_RNG_GetConfig1(RNG_TypeDef * RNGx)387 __STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
388 {
389 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
390 }
391
392 /**
393 * @brief Set RNG Config2 Configuration field value
394 * @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2
395 * @param RNGx RNG Instance
396 * @param Config2 Value between 0 and 0x7
397 * @retval None
398 */
LL_RNG_SetConfig2(RNG_TypeDef * RNGx,uint32_t Config2)399 __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
400 {
401 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST);
402 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
403 }
404
405 /**
406 * @brief Get RNG Config2 Configuration field value
407 * @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2
408 * @param RNGx RNG Instance
409 * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
410 */
LL_RNG_GetConfig2(RNG_TypeDef * RNGx)411 __STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
412 {
413 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
414 }
415
416 /**
417 * @brief Set RNG Config3 Configuration field value
418 * @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3
419 * @param RNGx RNG Instance
420 * @param Config3 Value between 0 and 0xF
421 * @retval None
422 */
LL_RNG_SetConfig3(RNG_TypeDef * RNGx,uint32_t Config3)423 __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
424 {
425 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST);
426 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
427 }
428
429 /**
430 * @brief Get RNG Config3 Configuration field value
431 * @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3
432 * @param RNGx RNG Instance
433 * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
434 */
LL_RNG_GetConfig3(RNG_TypeDef * RNGx)435 __STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
436 {
437 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
438 }
439
440 /**
441 * @brief Set RNG Clock divider factor
442 * @rmtoll CR CLKDIV LL_RNG_SetClockDivider
443 * @param RNGx RNG Instance
444 * @param Divider can be one of the following values:
445 * @arg @ref LL_RNG_CLKDIV_BY_1
446 * @arg @ref LL_RNG_CLKDIV_BY_2
447 * @arg @ref LL_RNG_CLKDIV_BY_4
448 * @arg @ref LL_RNG_CLKDIV_BY_8
449 * @arg @ref LL_RNG_CLKDIV_BY_16
450 * @arg @ref LL_RNG_CLKDIV_BY_32
451 * @arg @ref LL_RNG_CLKDIV_BY_64
452 * @arg @ref LL_RNG_CLKDIV_BY_128
453 * @arg @ref LL_RNG_CLKDIV_BY_256
454 * @arg @ref LL_RNG_CLKDIV_BY_512
455 * @arg @ref LL_RNG_CLKDIV_BY_1024
456 * @arg @ref LL_RNG_CLKDIV_BY_2048
457 * @arg @ref LL_RNG_CLKDIV_BY_4096
458 * @arg @ref LL_RNG_CLKDIV_BY_8192
459 * @arg @ref LL_RNG_CLKDIV_BY_16384
460 * @arg @ref LL_RNG_CLKDIV_BY_32768
461 * @retval None
462 */
LL_RNG_SetClockDivider(RNG_TypeDef * RNGx,uint32_t Divider)463 __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
464 {
465 MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST);
466 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
467 }
468
469 /**
470 * @brief Get RNG Clock divider factor
471 * @rmtoll CR CLKDIV LL_RNG_GetClockDivider
472 * @param RNGx RNG Instance
473 * @retval Returned value can be one of the following values:
474 * @arg @ref LL_RNG_CLKDIV_BY_1
475 * @arg @ref LL_RNG_CLKDIV_BY_2
476 * @arg @ref LL_RNG_CLKDIV_BY_4
477 * @arg @ref LL_RNG_CLKDIV_BY_8
478 * @arg @ref LL_RNG_CLKDIV_BY_16
479 * @arg @ref LL_RNG_CLKDIV_BY_32
480 * @arg @ref LL_RNG_CLKDIV_BY_64
481 * @arg @ref LL_RNG_CLKDIV_BY_128
482 * @arg @ref LL_RNG_CLKDIV_BY_256
483 * @arg @ref LL_RNG_CLKDIV_BY_512
484 * @arg @ref LL_RNG_CLKDIV_BY_1024
485 * @arg @ref LL_RNG_CLKDIV_BY_2048
486 * @arg @ref LL_RNG_CLKDIV_BY_4096
487 * @arg @ref LL_RNG_CLKDIV_BY_8192
488 * @arg @ref LL_RNG_CLKDIV_BY_16384
489 * @arg @ref LL_RNG_CLKDIV_BY_32768
490 */
LL_RNG_GetClockDivider(RNG_TypeDef * RNGx)491 __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
492 {
493 return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
494 }
495 #endif /* RNG_CR_CONDRST */
496 #endif /* RNG_CR_CED */
497 /**
498 * @}
499 */
500
501 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
502 * @{
503 */
504
505 /**
506 * @brief Indicate if the RNG Data ready Flag is set or not
507 * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
508 * @param RNGx RNG Instance
509 * @retval State of bit (1 or 0).
510 */
LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef * RNGx)511 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
512 {
513 return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
514 }
515
516 /**
517 * @brief Indicate if the Clock Error Current Status Flag is set or not
518 * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
519 * @param RNGx RNG Instance
520 * @retval State of bit (1 or 0).
521 */
LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef * RNGx)522 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
523 {
524 return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
525 }
526
527 /**
528 * @brief Indicate if the Seed Error Current Status Flag is set or not
529 * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
530 * @param RNGx RNG Instance
531 * @retval State of bit (1 or 0).
532 */
LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef * RNGx)533 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
534 {
535 return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
536 }
537
538 /**
539 * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
540 * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
541 * @param RNGx RNG Instance
542 * @retval State of bit (1 or 0).
543 */
LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef * RNGx)544 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
545 {
546 return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
547 }
548
549 /**
550 * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
551 * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
552 * @param RNGx RNG Instance
553 * @retval State of bit (1 or 0).
554 */
LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef * RNGx)555 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
556 {
557 return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
558 }
559
560 /**
561 * @brief Clear Clock Error interrupt Status (CEIS) Flag
562 * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
563 * @param RNGx RNG Instance
564 * @retval None
565 */
LL_RNG_ClearFlag_CEIS(RNG_TypeDef * RNGx)566 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
567 {
568 WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
569 }
570
571 /**
572 * @brief Clear Seed Error interrupt Status (SEIS) Flag
573 * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
574 * @param RNGx RNG Instance
575 * @retval None
576 */
LL_RNG_ClearFlag_SEIS(RNG_TypeDef * RNGx)577 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
578 {
579 WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
580 }
581
582 /**
583 * @}
584 */
585
586 /** @defgroup RNG_LL_EF_IT_Management IT Management
587 * @{
588 */
589
590 /**
591 * @brief Enable Random Number Generator Interrupt
592 * (applies for either Seed error, Clock Error or Data ready interrupts)
593 * @rmtoll CR IE LL_RNG_EnableIT
594 * @param RNGx RNG Instance
595 * @retval None
596 */
LL_RNG_EnableIT(RNG_TypeDef * RNGx)597 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
598 {
599 SET_BIT(RNGx->CR, RNG_CR_IE);
600 }
601
602 /**
603 * @brief Disable Random Number Generator Interrupt
604 * (applies for either Seed error, Clock Error or Data ready interrupts)
605 * @rmtoll CR IE LL_RNG_DisableIT
606 * @param RNGx RNG Instance
607 * @retval None
608 */
LL_RNG_DisableIT(RNG_TypeDef * RNGx)609 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
610 {
611 CLEAR_BIT(RNGx->CR, RNG_CR_IE);
612 }
613
614 /**
615 * @brief Check if Random Number Generator Interrupt is enabled
616 * (applies for either Seed error, Clock Error or Data ready interrupts)
617 * @rmtoll CR IE LL_RNG_IsEnabledIT
618 * @param RNGx RNG Instance
619 * @retval State of bit (1 or 0).
620 */
LL_RNG_IsEnabledIT(const RNG_TypeDef * RNGx)621 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
622 {
623 return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
624 }
625
626 /**
627 * @}
628 */
629
630 /** @defgroup RNG_LL_EF_Data_Management Data Management
631 * @{
632 */
633
634 /**
635 * @brief Return32-bit Random Number value
636 * @rmtoll DR RNDATA LL_RNG_ReadRandData32
637 * @param RNGx RNG Instance
638 * @retval Generated 32-bit random value
639 */
LL_RNG_ReadRandData32(const RNG_TypeDef * RNGx)640 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
641 {
642 return (uint32_t)(READ_REG(RNGx->DR));
643 }
644
645 /**
646 * @}
647 */
648
649 #if defined(RNG_VER_3_2) || defined (RNG_VER_3_1)
650 /** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
651 * @{
652 */
653
654 /**
655 * @brief Set RNG Health Test Control
656 * @rmtoll HTCR HTCFG LL_RNG_SetHealthconfiguration
657 * @param RNGx RNG Instance
658 * @param HTCFG can be values of 32 bits
659 * @retval None
660 */
LL_RNG_SetHealthconfiguration(RNG_TypeDef * RNGx,uint32_t HTCFG)661 __STATIC_INLINE void LL_RNG_SetHealthconfiguration(RNG_TypeDef *RNGx, uint32_t HTCFG)
662 {
663 WRITE_REG(RNGx->HTCR, HTCFG);
664 }
665
666 /**
667 * @brief Get RNG Health Test Control
668 * @rmtoll HTCR HTCFG LL_RNG_GetHealthconfiguration
669 * @param RNGx RNG Instance
670 * @retval Return 32-bit RNG Health Test configuration
671 */
LL_RNG_GetHealthconfiguration(RNG_TypeDef * RNGx)672 __STATIC_INLINE uint32_t LL_RNG_GetHealthconfiguration(RNG_TypeDef *RNGx)
673 {
674 return (uint32_t)READ_REG(RNGx->HTCR);
675 }
676
677 /**
678 * @}
679 */
680 #endif /* RNG_VER_3_2 || RNG_VER_3_1 */
681 #if defined(USE_FULL_LL_DRIVER)
682 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
683 * @{
684 */
685 #if defined(RNG_CR_CED)
686 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct);
687 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
688 #endif /* RNG_CR_CED */
689 ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
690
691 /**
692 * @}
693 */
694 #endif /* USE_FULL_LL_DRIVER */
695
696 /**
697 * @}
698 */
699
700 /**
701 * @}
702 */
703
704 #endif /* RNG */
705
706 /**
707 * @}
708 */
709
710 #ifdef __cplusplus
711 }
712 #endif
713
714 #endif /* __STM32L4xx_LL_RNG_H */
715
