1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2016 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
88 Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
142 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
143 (+) TriggerCallback : TIM Trigger Callback.
144 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
145 (+) IC_CaptureCallback : TIM Input Capture Callback.
146 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
147 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
148 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
149 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
150 (+) ErrorCallback : TIM Error Callback.
151
152 [..]
153 By default, after the Init and when the state is HAL_TIM_STATE_RESET
154 all interrupt callbacks are set to the corresponding weak functions:
155 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
156
157 [..]
158 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
159 functionalities in the Init / DeInit only when these callbacks are null
160 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
161 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
162
163 [..]
164 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
165 Exception done MspInit / MspDeInit that can be registered / unregistered
166 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
167 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
168 In that case first register the MspInit/MspDeInit user callbacks
169 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
170
171 [..]
172 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
173 not defined, the callback registration feature is not available and all callbacks
174 are set to the corresponding weak functions.
175
176 @endverbatim
177 ******************************************************************************
178 */
179
180 /* Includes ------------------------------------------------------------------*/
181 #include "stm32l1xx_hal.h"
182
183 /** @addtogroup STM32L1xx_HAL_Driver
184 * @{
185 */
186
187 /** @defgroup TIM TIM
188 * @brief TIM HAL module driver
189 * @{
190 */
191
192 #ifdef HAL_TIM_MODULE_ENABLED
193
194 /* Private typedef -----------------------------------------------------------*/
195 /* Private define ------------------------------------------------------------*/
196 /* Private macros ------------------------------------------------------------*/
197 /* Private variables ---------------------------------------------------------*/
198 /* Private function prototypes -----------------------------------------------*/
199 /** @addtogroup TIM_Private_Functions
200 * @{
201 */
202 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
203 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
204 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
205 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
206 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
207 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
208 uint32_t TIM_ICFilter);
209 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
210 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
211 uint32_t TIM_ICFilter);
212 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
213 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
214 uint32_t TIM_ICFilter);
215 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
216 uint32_t TIM_ICFilter);
217 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
218 static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
219 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
220 static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
221 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
222 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
223 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
224 static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
225 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
226 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
227 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
228 const TIM_SlaveConfigTypeDef *sSlaveConfig);
229 /**
230 * @}
231 */
232 /* Exported functions --------------------------------------------------------*/
233
234 /** @defgroup TIM_Exported_Functions TIM Exported Functions
235 * @{
236 */
237
238 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
239 * @brief Time Base functions
240 *
241 @verbatim
242 ==============================================================================
243 ##### Time Base functions #####
244 ==============================================================================
245 [..]
246 This section provides functions allowing to:
247 (+) Initialize and configure the TIM base.
248 (+) De-initialize the TIM base.
249 (+) Start the Time Base.
250 (+) Stop the Time Base.
251 (+) Start the Time Base and enable interrupt.
252 (+) Stop the Time Base and disable interrupt.
253 (+) Start the Time Base and enable DMA transfer.
254 (+) Stop the Time Base and disable DMA transfer.
255
256 @endverbatim
257 * @{
258 */
259 /**
260 * @brief Initializes the TIM Time base Unit according to the specified
261 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
262 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
263 * requires a timer reset to avoid unexpected direction
264 * due to DIR bit readonly in center aligned mode.
265 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
266 * @param htim TIM Base handle
267 * @retval HAL status
268 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)269 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
270 {
271 /* Check the TIM handle allocation */
272 if (htim == NULL)
273 {
274 return HAL_ERROR;
275 }
276
277 /* Check the parameters */
278 assert_param(IS_TIM_INSTANCE(htim->Instance));
279 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
280 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
281 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
282 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
283
284 if (htim->State == HAL_TIM_STATE_RESET)
285 {
286 /* Allocate lock resource and initialize it */
287 htim->Lock = HAL_UNLOCKED;
288
289 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
290 /* Reset interrupt callbacks to legacy weak callbacks */
291 TIM_ResetCallback(htim);
292
293 if (htim->Base_MspInitCallback == NULL)
294 {
295 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
296 }
297 /* Init the low level hardware : GPIO, CLOCK, NVIC */
298 htim->Base_MspInitCallback(htim);
299 #else
300 /* Init the low level hardware : GPIO, CLOCK, NVIC */
301 HAL_TIM_Base_MspInit(htim);
302 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
303 }
304
305 /* Set the TIM state */
306 htim->State = HAL_TIM_STATE_BUSY;
307
308 /* Set the Time Base configuration */
309 TIM_Base_SetConfig(htim->Instance, &htim->Init);
310
311 /* Initialize the DMA burst operation state */
312 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
313
314 /* Initialize the TIM channels state */
315 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
316
317 /* Initialize the TIM state*/
318 htim->State = HAL_TIM_STATE_READY;
319
320 return HAL_OK;
321 }
322
323 /**
324 * @brief DeInitializes the TIM Base peripheral
325 * @param htim TIM Base handle
326 * @retval HAL status
327 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)328 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
329 {
330 /* Check the parameters */
331 assert_param(IS_TIM_INSTANCE(htim->Instance));
332
333 htim->State = HAL_TIM_STATE_BUSY;
334
335 /* Disable the TIM Peripheral Clock */
336 __HAL_TIM_DISABLE(htim);
337
338 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
339 if (htim->Base_MspDeInitCallback == NULL)
340 {
341 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
342 }
343 /* DeInit the low level hardware */
344 htim->Base_MspDeInitCallback(htim);
345 #else
346 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
347 HAL_TIM_Base_MspDeInit(htim);
348 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
349
350 /* Change the DMA burst operation state */
351 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
352
353 /* Change the TIM channels state */
354 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
355
356 /* Change TIM state */
357 htim->State = HAL_TIM_STATE_RESET;
358
359 /* Release Lock */
360 __HAL_UNLOCK(htim);
361
362 return HAL_OK;
363 }
364
365 /**
366 * @brief Initializes the TIM Base MSP.
367 * @param htim TIM Base handle
368 * @retval None
369 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)370 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
371 {
372 /* Prevent unused argument(s) compilation warning */
373 UNUSED(htim);
374
375 /* NOTE : This function should not be modified, when the callback is needed,
376 the HAL_TIM_Base_MspInit could be implemented in the user file
377 */
378 }
379
380 /**
381 * @brief DeInitializes TIM Base MSP.
382 * @param htim TIM Base handle
383 * @retval None
384 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)385 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
386 {
387 /* Prevent unused argument(s) compilation warning */
388 UNUSED(htim);
389
390 /* NOTE : This function should not be modified, when the callback is needed,
391 the HAL_TIM_Base_MspDeInit could be implemented in the user file
392 */
393 }
394
395
396 /**
397 * @brief Starts the TIM Base generation.
398 * @param htim TIM Base handle
399 * @retval HAL status
400 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)401 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
402 {
403 uint32_t tmpsmcr;
404
405 /* Check the parameters */
406 assert_param(IS_TIM_INSTANCE(htim->Instance));
407
408 /* Check the TIM state */
409 if (htim->State != HAL_TIM_STATE_READY)
410 {
411 return HAL_ERROR;
412 }
413
414 /* Set the TIM state */
415 htim->State = HAL_TIM_STATE_BUSY;
416
417 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
418 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
419 {
420 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
421 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
422 {
423 __HAL_TIM_ENABLE(htim);
424 }
425 }
426 else
427 {
428 __HAL_TIM_ENABLE(htim);
429 }
430
431 /* Return function status */
432 return HAL_OK;
433 }
434
435 /**
436 * @brief Stops the TIM Base generation.
437 * @param htim TIM Base handle
438 * @retval HAL status
439 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)440 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
441 {
442 /* Check the parameters */
443 assert_param(IS_TIM_INSTANCE(htim->Instance));
444
445 /* Disable the Peripheral */
446 __HAL_TIM_DISABLE(htim);
447
448 /* Set the TIM state */
449 htim->State = HAL_TIM_STATE_READY;
450
451 /* Return function status */
452 return HAL_OK;
453 }
454
455 /**
456 * @brief Starts the TIM Base generation in interrupt mode.
457 * @param htim TIM Base handle
458 * @retval HAL status
459 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)460 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
461 {
462 uint32_t tmpsmcr;
463
464 /* Check the parameters */
465 assert_param(IS_TIM_INSTANCE(htim->Instance));
466
467 /* Check the TIM state */
468 if (htim->State != HAL_TIM_STATE_READY)
469 {
470 return HAL_ERROR;
471 }
472
473 /* Set the TIM state */
474 htim->State = HAL_TIM_STATE_BUSY;
475
476 /* Enable the TIM Update interrupt */
477 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
478
479 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
480 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
481 {
482 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
483 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
484 {
485 __HAL_TIM_ENABLE(htim);
486 }
487 }
488 else
489 {
490 __HAL_TIM_ENABLE(htim);
491 }
492
493 /* Return function status */
494 return HAL_OK;
495 }
496
497 /**
498 * @brief Stops the TIM Base generation in interrupt mode.
499 * @param htim TIM Base handle
500 * @retval HAL status
501 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)502 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
503 {
504 /* Check the parameters */
505 assert_param(IS_TIM_INSTANCE(htim->Instance));
506
507 /* Disable the TIM Update interrupt */
508 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
509
510 /* Disable the Peripheral */
511 __HAL_TIM_DISABLE(htim);
512
513 /* Set the TIM state */
514 htim->State = HAL_TIM_STATE_READY;
515
516 /* Return function status */
517 return HAL_OK;
518 }
519
520 /**
521 * @brief Starts the TIM Base generation in DMA mode.
522 * @param htim TIM Base handle
523 * @param pData The source Buffer address.
524 * @param Length The length of data to be transferred from memory to peripheral.
525 * @retval HAL status
526 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)527 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
528 {
529 uint32_t tmpsmcr;
530
531 /* Check the parameters */
532 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
533
534 /* Set the TIM state */
535 if (htim->State == HAL_TIM_STATE_BUSY)
536 {
537 return HAL_BUSY;
538 }
539 else if (htim->State == HAL_TIM_STATE_READY)
540 {
541 if ((pData == NULL) || (Length == 0U))
542 {
543 return HAL_ERROR;
544 }
545 else
546 {
547 htim->State = HAL_TIM_STATE_BUSY;
548 }
549 }
550 else
551 {
552 return HAL_ERROR;
553 }
554
555 /* Set the DMA Period elapsed callbacks */
556 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
557 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
558
559 /* Set the DMA error callback */
560 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
561
562 /* Enable the DMA channel */
563 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
564 Length) != HAL_OK)
565 {
566 /* Return error status */
567 return HAL_ERROR;
568 }
569
570 /* Enable the TIM Update DMA request */
571 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
572
573 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
574 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
575 {
576 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
577 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
578 {
579 __HAL_TIM_ENABLE(htim);
580 }
581 }
582 else
583 {
584 __HAL_TIM_ENABLE(htim);
585 }
586
587 /* Return function status */
588 return HAL_OK;
589 }
590
591 /**
592 * @brief Stops the TIM Base generation in DMA mode.
593 * @param htim TIM Base handle
594 * @retval HAL status
595 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)596 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
597 {
598 /* Check the parameters */
599 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
600
601 /* Disable the TIM Update DMA request */
602 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
603
604 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
605
606 /* Disable the Peripheral */
607 __HAL_TIM_DISABLE(htim);
608
609 /* Set the TIM state */
610 htim->State = HAL_TIM_STATE_READY;
611
612 /* Return function status */
613 return HAL_OK;
614 }
615
616 /**
617 * @}
618 */
619
620 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
621 * @brief TIM Output Compare functions
622 *
623 @verbatim
624 ==============================================================================
625 ##### TIM Output Compare functions #####
626 ==============================================================================
627 [..]
628 This section provides functions allowing to:
629 (+) Initialize and configure the TIM Output Compare.
630 (+) De-initialize the TIM Output Compare.
631 (+) Start the TIM Output Compare.
632 (+) Stop the TIM Output Compare.
633 (+) Start the TIM Output Compare and enable interrupt.
634 (+) Stop the TIM Output Compare and disable interrupt.
635 (+) Start the TIM Output Compare and enable DMA transfer.
636 (+) Stop the TIM Output Compare and disable DMA transfer.
637
638 @endverbatim
639 * @{
640 */
641 /**
642 * @brief Initializes the TIM Output Compare according to the specified
643 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
644 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
645 * requires a timer reset to avoid unexpected direction
646 * due to DIR bit readonly in center aligned mode.
647 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
648 * @param htim TIM Output Compare handle
649 * @retval HAL status
650 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)651 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
652 {
653 /* Check the TIM handle allocation */
654 if (htim == NULL)
655 {
656 return HAL_ERROR;
657 }
658
659 /* Check the parameters */
660 assert_param(IS_TIM_INSTANCE(htim->Instance));
661 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
662 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
663 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
664 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
665
666 if (htim->State == HAL_TIM_STATE_RESET)
667 {
668 /* Allocate lock resource and initialize it */
669 htim->Lock = HAL_UNLOCKED;
670
671 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
672 /* Reset interrupt callbacks to legacy weak callbacks */
673 TIM_ResetCallback(htim);
674
675 if (htim->OC_MspInitCallback == NULL)
676 {
677 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
678 }
679 /* Init the low level hardware : GPIO, CLOCK, NVIC */
680 htim->OC_MspInitCallback(htim);
681 #else
682 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
683 HAL_TIM_OC_MspInit(htim);
684 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
685 }
686
687 /* Set the TIM state */
688 htim->State = HAL_TIM_STATE_BUSY;
689
690 /* Init the base time for the Output Compare */
691 TIM_Base_SetConfig(htim->Instance, &htim->Init);
692
693 /* Initialize the DMA burst operation state */
694 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
695
696 /* Initialize the TIM channels state */
697 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
698
699 /* Initialize the TIM state*/
700 htim->State = HAL_TIM_STATE_READY;
701
702 return HAL_OK;
703 }
704
705 /**
706 * @brief DeInitializes the TIM peripheral
707 * @param htim TIM Output Compare handle
708 * @retval HAL status
709 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)710 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
711 {
712 /* Check the parameters */
713 assert_param(IS_TIM_INSTANCE(htim->Instance));
714
715 htim->State = HAL_TIM_STATE_BUSY;
716
717 /* Disable the TIM Peripheral Clock */
718 __HAL_TIM_DISABLE(htim);
719
720 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
721 if (htim->OC_MspDeInitCallback == NULL)
722 {
723 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
724 }
725 /* DeInit the low level hardware */
726 htim->OC_MspDeInitCallback(htim);
727 #else
728 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
729 HAL_TIM_OC_MspDeInit(htim);
730 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
731
732 /* Change the DMA burst operation state */
733 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
734
735 /* Change the TIM channels state */
736 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
737
738 /* Change TIM state */
739 htim->State = HAL_TIM_STATE_RESET;
740
741 /* Release Lock */
742 __HAL_UNLOCK(htim);
743
744 return HAL_OK;
745 }
746
747 /**
748 * @brief Initializes the TIM Output Compare MSP.
749 * @param htim TIM Output Compare handle
750 * @retval None
751 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)752 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
753 {
754 /* Prevent unused argument(s) compilation warning */
755 UNUSED(htim);
756
757 /* NOTE : This function should not be modified, when the callback is needed,
758 the HAL_TIM_OC_MspInit could be implemented in the user file
759 */
760 }
761
762 /**
763 * @brief DeInitializes TIM Output Compare MSP.
764 * @param htim TIM Output Compare handle
765 * @retval None
766 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)767 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
768 {
769 /* Prevent unused argument(s) compilation warning */
770 UNUSED(htim);
771
772 /* NOTE : This function should not be modified, when the callback is needed,
773 the HAL_TIM_OC_MspDeInit could be implemented in the user file
774 */
775 }
776
777 /**
778 * @brief Starts the TIM Output Compare signal generation.
779 * @param htim TIM Output Compare handle
780 * @param Channel TIM Channel to be enabled
781 * This parameter can be one of the following values:
782 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
783 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
784 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
785 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
786 * @retval HAL status
787 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)788 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
789 {
790 uint32_t tmpsmcr;
791
792 /* Check the parameters */
793 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
794
795 /* Check the TIM channel state */
796 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
797 {
798 return HAL_ERROR;
799 }
800
801 /* Set the TIM channel state */
802 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
803
804 /* Enable the Output compare channel */
805 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
806
807 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
808 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
809 {
810 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
811 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
812 {
813 __HAL_TIM_ENABLE(htim);
814 }
815 }
816 else
817 {
818 __HAL_TIM_ENABLE(htim);
819 }
820
821 /* Return function status */
822 return HAL_OK;
823 }
824
825 /**
826 * @brief Stops the TIM Output Compare signal generation.
827 * @param htim TIM Output Compare handle
828 * @param Channel TIM Channel to be disabled
829 * This parameter can be one of the following values:
830 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
831 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
832 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
833 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
834 * @retval HAL status
835 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)836 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
837 {
838 /* Check the parameters */
839 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
840
841 /* Disable the Output compare channel */
842 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
843
844 /* Disable the Peripheral */
845 __HAL_TIM_DISABLE(htim);
846
847 /* Set the TIM channel state */
848 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
849
850 /* Return function status */
851 return HAL_OK;
852 }
853
854 /**
855 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
856 * @param htim TIM Output Compare handle
857 * @param Channel TIM Channel to be enabled
858 * This parameter can be one of the following values:
859 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
860 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
861 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
862 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
863 * @retval HAL status
864 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)865 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
866 {
867 HAL_StatusTypeDef status = HAL_OK;
868 uint32_t tmpsmcr;
869
870 /* Check the parameters */
871 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
872
873 /* Check the TIM channel state */
874 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
875 {
876 return HAL_ERROR;
877 }
878
879 /* Set the TIM channel state */
880 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
881
882 switch (Channel)
883 {
884 case TIM_CHANNEL_1:
885 {
886 /* Enable the TIM Capture/Compare 1 interrupt */
887 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
888 break;
889 }
890
891 case TIM_CHANNEL_2:
892 {
893 /* Enable the TIM Capture/Compare 2 interrupt */
894 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
895 break;
896 }
897
898 case TIM_CHANNEL_3:
899 {
900 /* Enable the TIM Capture/Compare 3 interrupt */
901 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
902 break;
903 }
904
905 case TIM_CHANNEL_4:
906 {
907 /* Enable the TIM Capture/Compare 4 interrupt */
908 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
909 break;
910 }
911
912 default:
913 status = HAL_ERROR;
914 break;
915 }
916
917 if (status == HAL_OK)
918 {
919 /* Enable the Output compare channel */
920 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
921
922 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
923 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
924 {
925 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
926 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
927 {
928 __HAL_TIM_ENABLE(htim);
929 }
930 }
931 else
932 {
933 __HAL_TIM_ENABLE(htim);
934 }
935 }
936
937 /* Return function status */
938 return status;
939 }
940
941 /**
942 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
943 * @param htim TIM Output Compare handle
944 * @param Channel TIM Channel to be disabled
945 * This parameter can be one of the following values:
946 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
947 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
948 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
949 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
950 * @retval HAL status
951 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)952 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
953 {
954 HAL_StatusTypeDef status = HAL_OK;
955
956 /* Check the parameters */
957 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
958
959 switch (Channel)
960 {
961 case TIM_CHANNEL_1:
962 {
963 /* Disable the TIM Capture/Compare 1 interrupt */
964 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
965 break;
966 }
967
968 case TIM_CHANNEL_2:
969 {
970 /* Disable the TIM Capture/Compare 2 interrupt */
971 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
972 break;
973 }
974
975 case TIM_CHANNEL_3:
976 {
977 /* Disable the TIM Capture/Compare 3 interrupt */
978 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
979 break;
980 }
981
982 case TIM_CHANNEL_4:
983 {
984 /* Disable the TIM Capture/Compare 4 interrupt */
985 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
986 break;
987 }
988
989 default:
990 status = HAL_ERROR;
991 break;
992 }
993
994 if (status == HAL_OK)
995 {
996 /* Disable the Output compare channel */
997 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
998
999 /* Disable the Peripheral */
1000 __HAL_TIM_DISABLE(htim);
1001
1002 /* Set the TIM channel state */
1003 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1004 }
1005
1006 /* Return function status */
1007 return status;
1008 }
1009
1010 /**
1011 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1012 * @param htim TIM Output Compare handle
1013 * @param Channel TIM Channel to be enabled
1014 * This parameter can be one of the following values:
1015 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1016 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1017 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1018 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1019 * @param pData The source Buffer address.
1020 * @param Length The length of data to be transferred from memory to TIM peripheral
1021 * @retval HAL status
1022 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1023 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1024 uint16_t Length)
1025 {
1026 HAL_StatusTypeDef status = HAL_OK;
1027 uint32_t tmpsmcr;
1028
1029 /* Check the parameters */
1030 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1031
1032 /* Set the TIM channel state */
1033 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1034 {
1035 return HAL_BUSY;
1036 }
1037 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1038 {
1039 if ((pData == NULL) || (Length == 0U))
1040 {
1041 return HAL_ERROR;
1042 }
1043 else
1044 {
1045 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1046 }
1047 }
1048 else
1049 {
1050 return HAL_ERROR;
1051 }
1052
1053 switch (Channel)
1054 {
1055 case TIM_CHANNEL_1:
1056 {
1057 /* Set the DMA compare callbacks */
1058 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1059 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1060
1061 /* Set the DMA error callback */
1062 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1063
1064 /* Enable the DMA channel */
1065 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1066 Length) != HAL_OK)
1067 {
1068 /* Return error status */
1069 return HAL_ERROR;
1070 }
1071
1072 /* Enable the TIM Capture/Compare 1 DMA request */
1073 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1074 break;
1075 }
1076
1077 case TIM_CHANNEL_2:
1078 {
1079 /* Set the DMA compare callbacks */
1080 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1081 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1082
1083 /* Set the DMA error callback */
1084 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1085
1086 /* Enable the DMA channel */
1087 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1088 Length) != HAL_OK)
1089 {
1090 /* Return error status */
1091 return HAL_ERROR;
1092 }
1093
1094 /* Enable the TIM Capture/Compare 2 DMA request */
1095 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1096 break;
1097 }
1098
1099 case TIM_CHANNEL_3:
1100 {
1101 /* Set the DMA compare callbacks */
1102 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1103 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1104
1105 /* Set the DMA error callback */
1106 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1107
1108 /* Enable the DMA channel */
1109 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1110 Length) != HAL_OK)
1111 {
1112 /* Return error status */
1113 return HAL_ERROR;
1114 }
1115 /* Enable the TIM Capture/Compare 3 DMA request */
1116 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1117 break;
1118 }
1119
1120 case TIM_CHANNEL_4:
1121 {
1122 /* Set the DMA compare callbacks */
1123 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1124 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1125
1126 /* Set the DMA error callback */
1127 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1128
1129 /* Enable the DMA channel */
1130 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1131 Length) != HAL_OK)
1132 {
1133 /* Return error status */
1134 return HAL_ERROR;
1135 }
1136 /* Enable the TIM Capture/Compare 4 DMA request */
1137 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1138 break;
1139 }
1140
1141 default:
1142 status = HAL_ERROR;
1143 break;
1144 }
1145
1146 if (status == HAL_OK)
1147 {
1148 /* Enable the Output compare channel */
1149 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1150
1151 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1152 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1153 {
1154 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1155 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1156 {
1157 __HAL_TIM_ENABLE(htim);
1158 }
1159 }
1160 else
1161 {
1162 __HAL_TIM_ENABLE(htim);
1163 }
1164 }
1165
1166 /* Return function status */
1167 return status;
1168 }
1169
1170 /**
1171 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1172 * @param htim TIM Output Compare handle
1173 * @param Channel TIM Channel to be disabled
1174 * This parameter can be one of the following values:
1175 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1176 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1177 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1178 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1179 * @retval HAL status
1180 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1181 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1182 {
1183 HAL_StatusTypeDef status = HAL_OK;
1184
1185 /* Check the parameters */
1186 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1187
1188 switch (Channel)
1189 {
1190 case TIM_CHANNEL_1:
1191 {
1192 /* Disable the TIM Capture/Compare 1 DMA request */
1193 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1194 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1195 break;
1196 }
1197
1198 case TIM_CHANNEL_2:
1199 {
1200 /* Disable the TIM Capture/Compare 2 DMA request */
1201 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1202 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1203 break;
1204 }
1205
1206 case TIM_CHANNEL_3:
1207 {
1208 /* Disable the TIM Capture/Compare 3 DMA request */
1209 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1210 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1211 break;
1212 }
1213
1214 case TIM_CHANNEL_4:
1215 {
1216 /* Disable the TIM Capture/Compare 4 interrupt */
1217 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1218 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1219 break;
1220 }
1221
1222 default:
1223 status = HAL_ERROR;
1224 break;
1225 }
1226
1227 if (status == HAL_OK)
1228 {
1229 /* Disable the Output compare channel */
1230 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1231
1232 /* Disable the Peripheral */
1233 __HAL_TIM_DISABLE(htim);
1234
1235 /* Set the TIM channel state */
1236 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1237 }
1238
1239 /* Return function status */
1240 return status;
1241 }
1242
1243 /**
1244 * @}
1245 */
1246
1247 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1248 * @brief TIM PWM functions
1249 *
1250 @verbatim
1251 ==============================================================================
1252 ##### TIM PWM functions #####
1253 ==============================================================================
1254 [..]
1255 This section provides functions allowing to:
1256 (+) Initialize and configure the TIM PWM.
1257 (+) De-initialize the TIM PWM.
1258 (+) Start the TIM PWM.
1259 (+) Stop the TIM PWM.
1260 (+) Start the TIM PWM and enable interrupt.
1261 (+) Stop the TIM PWM and disable interrupt.
1262 (+) Start the TIM PWM and enable DMA transfer.
1263 (+) Stop the TIM PWM and disable DMA transfer.
1264
1265 @endverbatim
1266 * @{
1267 */
1268 /**
1269 * @brief Initializes the TIM PWM Time Base according to the specified
1270 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1271 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1272 * requires a timer reset to avoid unexpected direction
1273 * due to DIR bit readonly in center aligned mode.
1274 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1275 * @param htim TIM PWM handle
1276 * @retval HAL status
1277 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1278 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1279 {
1280 /* Check the TIM handle allocation */
1281 if (htim == NULL)
1282 {
1283 return HAL_ERROR;
1284 }
1285
1286 /* Check the parameters */
1287 assert_param(IS_TIM_INSTANCE(htim->Instance));
1288 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1289 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1290 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1291 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1292
1293 if (htim->State == HAL_TIM_STATE_RESET)
1294 {
1295 /* Allocate lock resource and initialize it */
1296 htim->Lock = HAL_UNLOCKED;
1297
1298 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1299 /* Reset interrupt callbacks to legacy weak callbacks */
1300 TIM_ResetCallback(htim);
1301
1302 if (htim->PWM_MspInitCallback == NULL)
1303 {
1304 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1305 }
1306 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1307 htim->PWM_MspInitCallback(htim);
1308 #else
1309 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1310 HAL_TIM_PWM_MspInit(htim);
1311 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1312 }
1313
1314 /* Set the TIM state */
1315 htim->State = HAL_TIM_STATE_BUSY;
1316
1317 /* Init the base time for the PWM */
1318 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1319
1320 /* Initialize the DMA burst operation state */
1321 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1322
1323 /* Initialize the TIM channels state */
1324 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1325
1326 /* Initialize the TIM state*/
1327 htim->State = HAL_TIM_STATE_READY;
1328
1329 return HAL_OK;
1330 }
1331
1332 /**
1333 * @brief DeInitializes the TIM peripheral
1334 * @param htim TIM PWM handle
1335 * @retval HAL status
1336 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1337 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1338 {
1339 /* Check the parameters */
1340 assert_param(IS_TIM_INSTANCE(htim->Instance));
1341
1342 htim->State = HAL_TIM_STATE_BUSY;
1343
1344 /* Disable the TIM Peripheral Clock */
1345 __HAL_TIM_DISABLE(htim);
1346
1347 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1348 if (htim->PWM_MspDeInitCallback == NULL)
1349 {
1350 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1351 }
1352 /* DeInit the low level hardware */
1353 htim->PWM_MspDeInitCallback(htim);
1354 #else
1355 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1356 HAL_TIM_PWM_MspDeInit(htim);
1357 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1358
1359 /* Change the DMA burst operation state */
1360 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1361
1362 /* Change the TIM channels state */
1363 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1364
1365 /* Change TIM state */
1366 htim->State = HAL_TIM_STATE_RESET;
1367
1368 /* Release Lock */
1369 __HAL_UNLOCK(htim);
1370
1371 return HAL_OK;
1372 }
1373
1374 /**
1375 * @brief Initializes the TIM PWM MSP.
1376 * @param htim TIM PWM handle
1377 * @retval None
1378 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1379 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1380 {
1381 /* Prevent unused argument(s) compilation warning */
1382 UNUSED(htim);
1383
1384 /* NOTE : This function should not be modified, when the callback is needed,
1385 the HAL_TIM_PWM_MspInit could be implemented in the user file
1386 */
1387 }
1388
1389 /**
1390 * @brief DeInitializes TIM PWM MSP.
1391 * @param htim TIM PWM handle
1392 * @retval None
1393 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1394 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1395 {
1396 /* Prevent unused argument(s) compilation warning */
1397 UNUSED(htim);
1398
1399 /* NOTE : This function should not be modified, when the callback is needed,
1400 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1401 */
1402 }
1403
1404 /**
1405 * @brief Starts the PWM signal generation.
1406 * @param htim TIM handle
1407 * @param Channel TIM Channels to be enabled
1408 * This parameter can be one of the following values:
1409 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1410 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1411 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1412 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1413 * @retval HAL status
1414 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1415 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1416 {
1417 uint32_t tmpsmcr;
1418
1419 /* Check the parameters */
1420 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1421
1422 /* Check the TIM channel state */
1423 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1424 {
1425 return HAL_ERROR;
1426 }
1427
1428 /* Set the TIM channel state */
1429 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1430
1431 /* Enable the Capture compare channel */
1432 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1433
1434 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1435 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1436 {
1437 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1438 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1439 {
1440 __HAL_TIM_ENABLE(htim);
1441 }
1442 }
1443 else
1444 {
1445 __HAL_TIM_ENABLE(htim);
1446 }
1447
1448 /* Return function status */
1449 return HAL_OK;
1450 }
1451
1452 /**
1453 * @brief Stops the PWM signal generation.
1454 * @param htim TIM PWM handle
1455 * @param Channel TIM Channels to be disabled
1456 * This parameter can be one of the following values:
1457 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1458 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1459 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1460 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1461 * @retval HAL status
1462 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1463 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1464 {
1465 /* Check the parameters */
1466 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1467
1468 /* Disable the Capture compare channel */
1469 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1470
1471 /* Disable the Peripheral */
1472 __HAL_TIM_DISABLE(htim);
1473
1474 /* Set the TIM channel state */
1475 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1476
1477 /* Return function status */
1478 return HAL_OK;
1479 }
1480
1481 /**
1482 * @brief Starts the PWM signal generation in interrupt mode.
1483 * @param htim TIM PWM handle
1484 * @param Channel TIM Channel to be enabled
1485 * This parameter can be one of the following values:
1486 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1487 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1488 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1489 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1490 * @retval HAL status
1491 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1492 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1493 {
1494 HAL_StatusTypeDef status = HAL_OK;
1495 uint32_t tmpsmcr;
1496
1497 /* Check the parameters */
1498 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1499
1500 /* Check the TIM channel state */
1501 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1502 {
1503 return HAL_ERROR;
1504 }
1505
1506 /* Set the TIM channel state */
1507 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1508
1509 switch (Channel)
1510 {
1511 case TIM_CHANNEL_1:
1512 {
1513 /* Enable the TIM Capture/Compare 1 interrupt */
1514 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1515 break;
1516 }
1517
1518 case TIM_CHANNEL_2:
1519 {
1520 /* Enable the TIM Capture/Compare 2 interrupt */
1521 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1522 break;
1523 }
1524
1525 case TIM_CHANNEL_3:
1526 {
1527 /* Enable the TIM Capture/Compare 3 interrupt */
1528 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1529 break;
1530 }
1531
1532 case TIM_CHANNEL_4:
1533 {
1534 /* Enable the TIM Capture/Compare 4 interrupt */
1535 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1536 break;
1537 }
1538
1539 default:
1540 status = HAL_ERROR;
1541 break;
1542 }
1543
1544 if (status == HAL_OK)
1545 {
1546 /* Enable the Capture compare channel */
1547 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1548
1549 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1550 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1551 {
1552 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1553 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1554 {
1555 __HAL_TIM_ENABLE(htim);
1556 }
1557 }
1558 else
1559 {
1560 __HAL_TIM_ENABLE(htim);
1561 }
1562 }
1563
1564 /* Return function status */
1565 return status;
1566 }
1567
1568 /**
1569 * @brief Stops the PWM signal generation in interrupt mode.
1570 * @param htim TIM PWM handle
1571 * @param Channel TIM Channels to be disabled
1572 * This parameter can be one of the following values:
1573 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1574 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1575 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1576 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1577 * @retval HAL status
1578 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1579 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1580 {
1581 HAL_StatusTypeDef status = HAL_OK;
1582
1583 /* Check the parameters */
1584 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1585
1586 switch (Channel)
1587 {
1588 case TIM_CHANNEL_1:
1589 {
1590 /* Disable the TIM Capture/Compare 1 interrupt */
1591 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1592 break;
1593 }
1594
1595 case TIM_CHANNEL_2:
1596 {
1597 /* Disable the TIM Capture/Compare 2 interrupt */
1598 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1599 break;
1600 }
1601
1602 case TIM_CHANNEL_3:
1603 {
1604 /* Disable the TIM Capture/Compare 3 interrupt */
1605 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1606 break;
1607 }
1608
1609 case TIM_CHANNEL_4:
1610 {
1611 /* Disable the TIM Capture/Compare 4 interrupt */
1612 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1613 break;
1614 }
1615
1616 default:
1617 status = HAL_ERROR;
1618 break;
1619 }
1620
1621 if (status == HAL_OK)
1622 {
1623 /* Disable the Capture compare channel */
1624 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1625
1626 /* Disable the Peripheral */
1627 __HAL_TIM_DISABLE(htim);
1628
1629 /* Set the TIM channel state */
1630 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1631 }
1632
1633 /* Return function status */
1634 return status;
1635 }
1636
1637 /**
1638 * @brief Starts the TIM PWM signal generation in DMA mode.
1639 * @param htim TIM PWM handle
1640 * @param Channel TIM Channels to be enabled
1641 * This parameter can be one of the following values:
1642 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1643 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1644 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1645 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1646 * @param pData The source Buffer address.
1647 * @param Length The length of data to be transferred from memory to TIM peripheral
1648 * @retval HAL status
1649 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1650 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1651 uint16_t Length)
1652 {
1653 HAL_StatusTypeDef status = HAL_OK;
1654 uint32_t tmpsmcr;
1655
1656 /* Check the parameters */
1657 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1658
1659 /* Set the TIM channel state */
1660 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1661 {
1662 return HAL_BUSY;
1663 }
1664 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1665 {
1666 if ((pData == NULL) || (Length == 0U))
1667 {
1668 return HAL_ERROR;
1669 }
1670 else
1671 {
1672 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1673 }
1674 }
1675 else
1676 {
1677 return HAL_ERROR;
1678 }
1679
1680 switch (Channel)
1681 {
1682 case TIM_CHANNEL_1:
1683 {
1684 /* Set the DMA compare callbacks */
1685 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1686 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1687
1688 /* Set the DMA error callback */
1689 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1690
1691 /* Enable the DMA channel */
1692 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1693 Length) != HAL_OK)
1694 {
1695 /* Return error status */
1696 return HAL_ERROR;
1697 }
1698
1699 /* Enable the TIM Capture/Compare 1 DMA request */
1700 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1701 break;
1702 }
1703
1704 case TIM_CHANNEL_2:
1705 {
1706 /* Set the DMA compare callbacks */
1707 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1708 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1709
1710 /* Set the DMA error callback */
1711 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1712
1713 /* Enable the DMA channel */
1714 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1715 Length) != HAL_OK)
1716 {
1717 /* Return error status */
1718 return HAL_ERROR;
1719 }
1720 /* Enable the TIM Capture/Compare 2 DMA request */
1721 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1722 break;
1723 }
1724
1725 case TIM_CHANNEL_3:
1726 {
1727 /* Set the DMA compare callbacks */
1728 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1729 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1730
1731 /* Set the DMA error callback */
1732 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1733
1734 /* Enable the DMA channel */
1735 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1736 Length) != HAL_OK)
1737 {
1738 /* Return error status */
1739 return HAL_ERROR;
1740 }
1741 /* Enable the TIM Output Capture/Compare 3 request */
1742 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1743 break;
1744 }
1745
1746 case TIM_CHANNEL_4:
1747 {
1748 /* Set the DMA compare callbacks */
1749 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1750 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1751
1752 /* Set the DMA error callback */
1753 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1754
1755 /* Enable the DMA channel */
1756 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1757 Length) != HAL_OK)
1758 {
1759 /* Return error status */
1760 return HAL_ERROR;
1761 }
1762 /* Enable the TIM Capture/Compare 4 DMA request */
1763 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1764 break;
1765 }
1766
1767 default:
1768 status = HAL_ERROR;
1769 break;
1770 }
1771
1772 if (status == HAL_OK)
1773 {
1774 /* Enable the Capture compare channel */
1775 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1776
1777 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1778 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1779 {
1780 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1781 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1782 {
1783 __HAL_TIM_ENABLE(htim);
1784 }
1785 }
1786 else
1787 {
1788 __HAL_TIM_ENABLE(htim);
1789 }
1790 }
1791
1792 /* Return function status */
1793 return status;
1794 }
1795
1796 /**
1797 * @brief Stops the TIM PWM signal generation in DMA mode.
1798 * @param htim TIM PWM handle
1799 * @param Channel TIM Channels to be disabled
1800 * This parameter can be one of the following values:
1801 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1802 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1803 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1804 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1805 * @retval HAL status
1806 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1807 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1808 {
1809 HAL_StatusTypeDef status = HAL_OK;
1810
1811 /* Check the parameters */
1812 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1813
1814 switch (Channel)
1815 {
1816 case TIM_CHANNEL_1:
1817 {
1818 /* Disable the TIM Capture/Compare 1 DMA request */
1819 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1820 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1821 break;
1822 }
1823
1824 case TIM_CHANNEL_2:
1825 {
1826 /* Disable the TIM Capture/Compare 2 DMA request */
1827 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1828 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1829 break;
1830 }
1831
1832 case TIM_CHANNEL_3:
1833 {
1834 /* Disable the TIM Capture/Compare 3 DMA request */
1835 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1836 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1837 break;
1838 }
1839
1840 case TIM_CHANNEL_4:
1841 {
1842 /* Disable the TIM Capture/Compare 4 interrupt */
1843 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1844 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1845 break;
1846 }
1847
1848 default:
1849 status = HAL_ERROR;
1850 break;
1851 }
1852
1853 if (status == HAL_OK)
1854 {
1855 /* Disable the Capture compare channel */
1856 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1857
1858 /* Disable the Peripheral */
1859 __HAL_TIM_DISABLE(htim);
1860
1861 /* Set the TIM channel state */
1862 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1863 }
1864
1865 /* Return function status */
1866 return status;
1867 }
1868
1869 /**
1870 * @}
1871 */
1872
1873 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1874 * @brief TIM Input Capture functions
1875 *
1876 @verbatim
1877 ==============================================================================
1878 ##### TIM Input Capture functions #####
1879 ==============================================================================
1880 [..]
1881 This section provides functions allowing to:
1882 (+) Initialize and configure the TIM Input Capture.
1883 (+) De-initialize the TIM Input Capture.
1884 (+) Start the TIM Input Capture.
1885 (+) Stop the TIM Input Capture.
1886 (+) Start the TIM Input Capture and enable interrupt.
1887 (+) Stop the TIM Input Capture and disable interrupt.
1888 (+) Start the TIM Input Capture and enable DMA transfer.
1889 (+) Stop the TIM Input Capture and disable DMA transfer.
1890
1891 @endverbatim
1892 * @{
1893 */
1894 /**
1895 * @brief Initializes the TIM Input Capture Time base according to the specified
1896 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1897 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1898 * requires a timer reset to avoid unexpected direction
1899 * due to DIR bit readonly in center aligned mode.
1900 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1901 * @param htim TIM Input Capture handle
1902 * @retval HAL status
1903 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1904 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1905 {
1906 /* Check the TIM handle allocation */
1907 if (htim == NULL)
1908 {
1909 return HAL_ERROR;
1910 }
1911
1912 /* Check the parameters */
1913 assert_param(IS_TIM_INSTANCE(htim->Instance));
1914 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1915 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1916 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1917 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1918
1919 if (htim->State == HAL_TIM_STATE_RESET)
1920 {
1921 /* Allocate lock resource and initialize it */
1922 htim->Lock = HAL_UNLOCKED;
1923
1924 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1925 /* Reset interrupt callbacks to legacy weak callbacks */
1926 TIM_ResetCallback(htim);
1927
1928 if (htim->IC_MspInitCallback == NULL)
1929 {
1930 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
1931 }
1932 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1933 htim->IC_MspInitCallback(htim);
1934 #else
1935 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1936 HAL_TIM_IC_MspInit(htim);
1937 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1938 }
1939
1940 /* Set the TIM state */
1941 htim->State = HAL_TIM_STATE_BUSY;
1942
1943 /* Init the base time for the input capture */
1944 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1945
1946 /* Initialize the DMA burst operation state */
1947 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1948
1949 /* Initialize the TIM channels state */
1950 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1951
1952 /* Initialize the TIM state*/
1953 htim->State = HAL_TIM_STATE_READY;
1954
1955 return HAL_OK;
1956 }
1957
1958 /**
1959 * @brief DeInitializes the TIM peripheral
1960 * @param htim TIM Input Capture handle
1961 * @retval HAL status
1962 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)1963 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1964 {
1965 /* Check the parameters */
1966 assert_param(IS_TIM_INSTANCE(htim->Instance));
1967
1968 htim->State = HAL_TIM_STATE_BUSY;
1969
1970 /* Disable the TIM Peripheral Clock */
1971 __HAL_TIM_DISABLE(htim);
1972
1973 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1974 if (htim->IC_MspDeInitCallback == NULL)
1975 {
1976 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
1977 }
1978 /* DeInit the low level hardware */
1979 htim->IC_MspDeInitCallback(htim);
1980 #else
1981 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1982 HAL_TIM_IC_MspDeInit(htim);
1983 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1984
1985 /* Change the DMA burst operation state */
1986 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1987
1988 /* Change the TIM channels state */
1989 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1990
1991 /* Change TIM state */
1992 htim->State = HAL_TIM_STATE_RESET;
1993
1994 /* Release Lock */
1995 __HAL_UNLOCK(htim);
1996
1997 return HAL_OK;
1998 }
1999
2000 /**
2001 * @brief Initializes the TIM Input Capture MSP.
2002 * @param htim TIM Input Capture handle
2003 * @retval None
2004 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2005 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2006 {
2007 /* Prevent unused argument(s) compilation warning */
2008 UNUSED(htim);
2009
2010 /* NOTE : This function should not be modified, when the callback is needed,
2011 the HAL_TIM_IC_MspInit could be implemented in the user file
2012 */
2013 }
2014
2015 /**
2016 * @brief DeInitializes TIM Input Capture MSP.
2017 * @param htim TIM handle
2018 * @retval None
2019 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2020 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2021 {
2022 /* Prevent unused argument(s) compilation warning */
2023 UNUSED(htim);
2024
2025 /* NOTE : This function should not be modified, when the callback is needed,
2026 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2027 */
2028 }
2029
2030 /**
2031 * @brief Starts the TIM Input Capture measurement.
2032 * @param htim TIM Input Capture handle
2033 * @param Channel TIM Channels to be enabled
2034 * This parameter can be one of the following values:
2035 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2036 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2037 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2038 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2039 * @retval HAL status
2040 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2041 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2042 {
2043 uint32_t tmpsmcr;
2044 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2045
2046 /* Check the parameters */
2047 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2048
2049 /* Check the TIM channel state */
2050 if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
2051 {
2052 return HAL_ERROR;
2053 }
2054
2055 /* Set the TIM channel state */
2056 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2057
2058 /* Enable the Input Capture channel */
2059 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2060
2061 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2062 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2063 {
2064 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2065 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2066 {
2067 __HAL_TIM_ENABLE(htim);
2068 }
2069 }
2070 else
2071 {
2072 __HAL_TIM_ENABLE(htim);
2073 }
2074
2075 /* Return function status */
2076 return HAL_OK;
2077 }
2078
2079 /**
2080 * @brief Stops the TIM Input Capture measurement.
2081 * @param htim TIM Input Capture handle
2082 * @param Channel TIM Channels to be disabled
2083 * This parameter can be one of the following values:
2084 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2085 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2086 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2087 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2088 * @retval HAL status
2089 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2090 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2091 {
2092 /* Check the parameters */
2093 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2094
2095 /* Disable the Input Capture channel */
2096 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2097
2098 /* Disable the Peripheral */
2099 __HAL_TIM_DISABLE(htim);
2100
2101 /* Set the TIM channel state */
2102 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2103
2104 /* Return function status */
2105 return HAL_OK;
2106 }
2107
2108 /**
2109 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2110 * @param htim TIM Input Capture handle
2111 * @param Channel TIM Channels to be enabled
2112 * This parameter can be one of the following values:
2113 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2114 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2115 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2116 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2117 * @retval HAL status
2118 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2119 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2120 {
2121 HAL_StatusTypeDef status = HAL_OK;
2122 uint32_t tmpsmcr;
2123
2124 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2125
2126 /* Check the parameters */
2127 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2128
2129 /* Check the TIM channel state */
2130 if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
2131 {
2132 return HAL_ERROR;
2133 }
2134
2135 /* Set the TIM channel state */
2136 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2137
2138 switch (Channel)
2139 {
2140 case TIM_CHANNEL_1:
2141 {
2142 /* Enable the TIM Capture/Compare 1 interrupt */
2143 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2144 break;
2145 }
2146
2147 case TIM_CHANNEL_2:
2148 {
2149 /* Enable the TIM Capture/Compare 2 interrupt */
2150 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2151 break;
2152 }
2153
2154 case TIM_CHANNEL_3:
2155 {
2156 /* Enable the TIM Capture/Compare 3 interrupt */
2157 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2158 break;
2159 }
2160
2161 case TIM_CHANNEL_4:
2162 {
2163 /* Enable the TIM Capture/Compare 4 interrupt */
2164 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2165 break;
2166 }
2167
2168 default:
2169 status = HAL_ERROR;
2170 break;
2171 }
2172
2173 if (status == HAL_OK)
2174 {
2175 /* Enable the Input Capture channel */
2176 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2177
2178 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2179 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2180 {
2181 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2182 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2183 {
2184 __HAL_TIM_ENABLE(htim);
2185 }
2186 }
2187 else
2188 {
2189 __HAL_TIM_ENABLE(htim);
2190 }
2191 }
2192
2193 /* Return function status */
2194 return status;
2195 }
2196
2197 /**
2198 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2199 * @param htim TIM Input Capture handle
2200 * @param Channel TIM Channels to be disabled
2201 * This parameter can be one of the following values:
2202 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2203 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2204 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2205 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2206 * @retval HAL status
2207 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2208 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2209 {
2210 HAL_StatusTypeDef status = HAL_OK;
2211
2212 /* Check the parameters */
2213 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2214
2215 switch (Channel)
2216 {
2217 case TIM_CHANNEL_1:
2218 {
2219 /* Disable the TIM Capture/Compare 1 interrupt */
2220 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2221 break;
2222 }
2223
2224 case TIM_CHANNEL_2:
2225 {
2226 /* Disable the TIM Capture/Compare 2 interrupt */
2227 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2228 break;
2229 }
2230
2231 case TIM_CHANNEL_3:
2232 {
2233 /* Disable the TIM Capture/Compare 3 interrupt */
2234 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2235 break;
2236 }
2237
2238 case TIM_CHANNEL_4:
2239 {
2240 /* Disable the TIM Capture/Compare 4 interrupt */
2241 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2242 break;
2243 }
2244
2245 default:
2246 status = HAL_ERROR;
2247 break;
2248 }
2249
2250 if (status == HAL_OK)
2251 {
2252 /* Disable the Input Capture channel */
2253 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2254
2255 /* Disable the Peripheral */
2256 __HAL_TIM_DISABLE(htim);
2257
2258 /* Set the TIM channel state */
2259 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2260 }
2261
2262 /* Return function status */
2263 return status;
2264 }
2265
2266 /**
2267 * @brief Starts the TIM Input Capture measurement in DMA mode.
2268 * @param htim TIM Input Capture handle
2269 * @param Channel TIM Channels to be enabled
2270 * This parameter can be one of the following values:
2271 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2272 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2273 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2274 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2275 * @param pData The destination Buffer address.
2276 * @param Length The length of data to be transferred from TIM peripheral to memory.
2277 * @retval HAL status
2278 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2279 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2280 {
2281 HAL_StatusTypeDef status = HAL_OK;
2282 uint32_t tmpsmcr;
2283
2284 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2285
2286 /* Check the parameters */
2287 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2288 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2289
2290 /* Set the TIM channel state */
2291 if (channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2292 {
2293 return HAL_BUSY;
2294 }
2295 if (channel_state == HAL_TIM_CHANNEL_STATE_READY)
2296 {
2297 if ((pData == NULL) || (Length == 0U))
2298 {
2299 return HAL_ERROR;
2300 }
2301 else
2302 {
2303 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2304 }
2305 }
2306 else
2307 {
2308 return HAL_ERROR;
2309 }
2310
2311 /* Enable the Input Capture channel */
2312 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2313
2314 switch (Channel)
2315 {
2316 case TIM_CHANNEL_1:
2317 {
2318 /* Set the DMA capture callbacks */
2319 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2320 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2321
2322 /* Set the DMA error callback */
2323 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2324
2325 /* Enable the DMA channel */
2326 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2327 Length) != HAL_OK)
2328 {
2329 /* Return error status */
2330 return HAL_ERROR;
2331 }
2332 /* Enable the TIM Capture/Compare 1 DMA request */
2333 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2334 break;
2335 }
2336
2337 case TIM_CHANNEL_2:
2338 {
2339 /* Set the DMA capture callbacks */
2340 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2341 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2342
2343 /* Set the DMA error callback */
2344 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2345
2346 /* Enable the DMA channel */
2347 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2348 Length) != HAL_OK)
2349 {
2350 /* Return error status */
2351 return HAL_ERROR;
2352 }
2353 /* Enable the TIM Capture/Compare 2 DMA request */
2354 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2355 break;
2356 }
2357
2358 case TIM_CHANNEL_3:
2359 {
2360 /* Set the DMA capture callbacks */
2361 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2362 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2363
2364 /* Set the DMA error callback */
2365 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2366
2367 /* Enable the DMA channel */
2368 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2369 Length) != HAL_OK)
2370 {
2371 /* Return error status */
2372 return HAL_ERROR;
2373 }
2374 /* Enable the TIM Capture/Compare 3 DMA request */
2375 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2376 break;
2377 }
2378
2379 case TIM_CHANNEL_4:
2380 {
2381 /* Set the DMA capture callbacks */
2382 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2383 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2384
2385 /* Set the DMA error callback */
2386 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2387
2388 /* Enable the DMA channel */
2389 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2390 Length) != HAL_OK)
2391 {
2392 /* Return error status */
2393 return HAL_ERROR;
2394 }
2395 /* Enable the TIM Capture/Compare 4 DMA request */
2396 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2397 break;
2398 }
2399
2400 default:
2401 status = HAL_ERROR;
2402 break;
2403 }
2404
2405 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2406 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2407 {
2408 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2409 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2410 {
2411 __HAL_TIM_ENABLE(htim);
2412 }
2413 }
2414 else
2415 {
2416 __HAL_TIM_ENABLE(htim);
2417 }
2418
2419 /* Return function status */
2420 return status;
2421 }
2422
2423 /**
2424 * @brief Stops the TIM Input Capture measurement in DMA mode.
2425 * @param htim TIM Input Capture handle
2426 * @param Channel TIM Channels to be disabled
2427 * This parameter can be one of the following values:
2428 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2429 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2430 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2431 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2432 * @retval HAL status
2433 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2434 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2435 {
2436 HAL_StatusTypeDef status = HAL_OK;
2437
2438 /* Check the parameters */
2439 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2440 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2441
2442 /* Disable the Input Capture channel */
2443 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2444
2445 switch (Channel)
2446 {
2447 case TIM_CHANNEL_1:
2448 {
2449 /* Disable the TIM Capture/Compare 1 DMA request */
2450 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2451 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2452 break;
2453 }
2454
2455 case TIM_CHANNEL_2:
2456 {
2457 /* Disable the TIM Capture/Compare 2 DMA request */
2458 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2459 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2460 break;
2461 }
2462
2463 case TIM_CHANNEL_3:
2464 {
2465 /* Disable the TIM Capture/Compare 3 DMA request */
2466 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2467 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2468 break;
2469 }
2470
2471 case TIM_CHANNEL_4:
2472 {
2473 /* Disable the TIM Capture/Compare 4 DMA request */
2474 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2475 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2476 break;
2477 }
2478
2479 default:
2480 status = HAL_ERROR;
2481 break;
2482 }
2483
2484 if (status == HAL_OK)
2485 {
2486 /* Disable the Peripheral */
2487 __HAL_TIM_DISABLE(htim);
2488
2489 /* Set the TIM channel state */
2490 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2491 }
2492
2493 /* Return function status */
2494 return status;
2495 }
2496 /**
2497 * @}
2498 */
2499
2500 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2501 * @brief TIM One Pulse functions
2502 *
2503 @verbatim
2504 ==============================================================================
2505 ##### TIM One Pulse functions #####
2506 ==============================================================================
2507 [..]
2508 This section provides functions allowing to:
2509 (+) Initialize and configure the TIM One Pulse.
2510 (+) De-initialize the TIM One Pulse.
2511 (+) Start the TIM One Pulse.
2512 (+) Stop the TIM One Pulse.
2513 (+) Start the TIM One Pulse and enable interrupt.
2514 (+) Stop the TIM One Pulse and disable interrupt.
2515 (+) Start the TIM One Pulse and enable DMA transfer.
2516 (+) Stop the TIM One Pulse and disable DMA transfer.
2517
2518 @endverbatim
2519 * @{
2520 */
2521 /**
2522 * @brief Initializes the TIM One Pulse Time Base according to the specified
2523 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2524 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2525 * requires a timer reset to avoid unexpected direction
2526 * due to DIR bit readonly in center aligned mode.
2527 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2528 * @note When the timer instance is initialized in One Pulse mode, timer
2529 * channels 1 and channel 2 are reserved and cannot be used for other
2530 * purpose.
2531 * @param htim TIM One Pulse handle
2532 * @param OnePulseMode Select the One pulse mode.
2533 * This parameter can be one of the following values:
2534 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2535 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2536 * @retval HAL status
2537 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2538 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2539 {
2540 /* Check the TIM handle allocation */
2541 if (htim == NULL)
2542 {
2543 return HAL_ERROR;
2544 }
2545
2546 /* Check the parameters */
2547 assert_param(IS_TIM_INSTANCE(htim->Instance));
2548 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2549 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2550 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2551 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2552 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2553
2554 if (htim->State == HAL_TIM_STATE_RESET)
2555 {
2556 /* Allocate lock resource and initialize it */
2557 htim->Lock = HAL_UNLOCKED;
2558
2559 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2560 /* Reset interrupt callbacks to legacy weak callbacks */
2561 TIM_ResetCallback(htim);
2562
2563 if (htim->OnePulse_MspInitCallback == NULL)
2564 {
2565 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2566 }
2567 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2568 htim->OnePulse_MspInitCallback(htim);
2569 #else
2570 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2571 HAL_TIM_OnePulse_MspInit(htim);
2572 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2573 }
2574
2575 /* Set the TIM state */
2576 htim->State = HAL_TIM_STATE_BUSY;
2577
2578 /* Configure the Time base in the One Pulse Mode */
2579 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2580
2581 /* Reset the OPM Bit */
2582 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2583
2584 /* Configure the OPM Mode */
2585 htim->Instance->CR1 |= OnePulseMode;
2586
2587 /* Initialize the DMA burst operation state */
2588 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2589
2590 /* Initialize the TIM channels state */
2591 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2592 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2593
2594 /* Initialize the TIM state*/
2595 htim->State = HAL_TIM_STATE_READY;
2596
2597 return HAL_OK;
2598 }
2599
2600 /**
2601 * @brief DeInitializes the TIM One Pulse
2602 * @param htim TIM One Pulse handle
2603 * @retval HAL status
2604 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2605 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2606 {
2607 /* Check the parameters */
2608 assert_param(IS_TIM_INSTANCE(htim->Instance));
2609
2610 htim->State = HAL_TIM_STATE_BUSY;
2611
2612 /* Disable the TIM Peripheral Clock */
2613 __HAL_TIM_DISABLE(htim);
2614
2615 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2616 if (htim->OnePulse_MspDeInitCallback == NULL)
2617 {
2618 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2619 }
2620 /* DeInit the low level hardware */
2621 htim->OnePulse_MspDeInitCallback(htim);
2622 #else
2623 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2624 HAL_TIM_OnePulse_MspDeInit(htim);
2625 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2626
2627 /* Change the DMA burst operation state */
2628 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2629
2630 /* Set the TIM channel state */
2631 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2632 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2633
2634 /* Change TIM state */
2635 htim->State = HAL_TIM_STATE_RESET;
2636
2637 /* Release Lock */
2638 __HAL_UNLOCK(htim);
2639
2640 return HAL_OK;
2641 }
2642
2643 /**
2644 * @brief Initializes the TIM One Pulse MSP.
2645 * @param htim TIM One Pulse handle
2646 * @retval None
2647 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2648 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2649 {
2650 /* Prevent unused argument(s) compilation warning */
2651 UNUSED(htim);
2652
2653 /* NOTE : This function should not be modified, when the callback is needed,
2654 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2655 */
2656 }
2657
2658 /**
2659 * @brief DeInitializes TIM One Pulse MSP.
2660 * @param htim TIM One Pulse handle
2661 * @retval None
2662 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2663 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2664 {
2665 /* Prevent unused argument(s) compilation warning */
2666 UNUSED(htim);
2667
2668 /* NOTE : This function should not be modified, when the callback is needed,
2669 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2670 */
2671 }
2672
2673 /**
2674 * @brief Starts the TIM One Pulse signal generation.
2675 * @note Though OutputChannel parameter is deprecated and ignored by the function
2676 * it has been kept to avoid HAL_TIM API compatibility break.
2677 * @note The pulse output channel is determined when calling
2678 * @ref HAL_TIM_OnePulse_ConfigChannel().
2679 * @param htim TIM One Pulse handle
2680 * @param OutputChannel See note above
2681 * @retval HAL status
2682 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2683 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2684 {
2685 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2686 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2687
2688 /* Prevent unused argument(s) compilation warning */
2689 UNUSED(OutputChannel);
2690
2691 /* Check the TIM channels state */
2692 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2693 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2694 {
2695 return HAL_ERROR;
2696 }
2697
2698 /* Set the TIM channels state */
2699 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2700 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2701
2702 /* Enable the Capture compare and the Input Capture channels
2703 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2704 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2705 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2706 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2707
2708 No need to enable the counter, it's enabled automatically by hardware
2709 (the counter starts in response to a stimulus and generate a pulse */
2710
2711 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2712 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2713
2714 /* Return function status */
2715 return HAL_OK;
2716 }
2717
2718 /**
2719 * @brief Stops the TIM One Pulse signal generation.
2720 * @note Though OutputChannel parameter is deprecated and ignored by the function
2721 * it has been kept to avoid HAL_TIM API compatibility break.
2722 * @note The pulse output channel is determined when calling
2723 * @ref HAL_TIM_OnePulse_ConfigChannel().
2724 * @param htim TIM One Pulse handle
2725 * @param OutputChannel See note above
2726 * @retval HAL status
2727 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2728 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2729 {
2730 /* Prevent unused argument(s) compilation warning */
2731 UNUSED(OutputChannel);
2732
2733 /* Disable the Capture compare and the Input Capture channels
2734 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2735 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2736 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2737 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2738
2739 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2740 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2741
2742 /* Disable the Peripheral */
2743 __HAL_TIM_DISABLE(htim);
2744
2745 /* Set the TIM channels state */
2746 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2747 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2748
2749 /* Return function status */
2750 return HAL_OK;
2751 }
2752
2753 /**
2754 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2755 * @note Though OutputChannel parameter is deprecated and ignored by the function
2756 * it has been kept to avoid HAL_TIM API compatibility break.
2757 * @note The pulse output channel is determined when calling
2758 * @ref HAL_TIM_OnePulse_ConfigChannel().
2759 * @param htim TIM One Pulse handle
2760 * @param OutputChannel See note above
2761 * @retval HAL status
2762 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2763 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2764 {
2765 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2766 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2767
2768 /* Prevent unused argument(s) compilation warning */
2769 UNUSED(OutputChannel);
2770
2771 /* Check the TIM channels state */
2772 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2773 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2774 {
2775 return HAL_ERROR;
2776 }
2777
2778 /* Set the TIM channels state */
2779 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2780 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2781
2782 /* Enable the Capture compare and the Input Capture channels
2783 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2784 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2785 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2786 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2787
2788 No need to enable the counter, it's enabled automatically by hardware
2789 (the counter starts in response to a stimulus and generate a pulse */
2790
2791 /* Enable the TIM Capture/Compare 1 interrupt */
2792 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2793
2794 /* Enable the TIM Capture/Compare 2 interrupt */
2795 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2796
2797 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2798 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2799
2800 /* Return function status */
2801 return HAL_OK;
2802 }
2803
2804 /**
2805 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2806 * @note Though OutputChannel parameter is deprecated and ignored by the function
2807 * it has been kept to avoid HAL_TIM API compatibility break.
2808 * @note The pulse output channel is determined when calling
2809 * @ref HAL_TIM_OnePulse_ConfigChannel().
2810 * @param htim TIM One Pulse handle
2811 * @param OutputChannel See note above
2812 * @retval HAL status
2813 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2814 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2815 {
2816 /* Prevent unused argument(s) compilation warning */
2817 UNUSED(OutputChannel);
2818
2819 /* Disable the TIM Capture/Compare 1 interrupt */
2820 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2821
2822 /* Disable the TIM Capture/Compare 2 interrupt */
2823 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2824
2825 /* Disable the Capture compare and the Input Capture channels
2826 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2827 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2828 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2829 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2830 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2831 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2832
2833 /* Disable the Peripheral */
2834 __HAL_TIM_DISABLE(htim);
2835
2836 /* Set the TIM channels state */
2837 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2838 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2839
2840 /* Return function status */
2841 return HAL_OK;
2842 }
2843
2844 /**
2845 * @}
2846 */
2847
2848 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2849 * @brief TIM Encoder functions
2850 *
2851 @verbatim
2852 ==============================================================================
2853 ##### TIM Encoder functions #####
2854 ==============================================================================
2855 [..]
2856 This section provides functions allowing to:
2857 (+) Initialize and configure the TIM Encoder.
2858 (+) De-initialize the TIM Encoder.
2859 (+) Start the TIM Encoder.
2860 (+) Stop the TIM Encoder.
2861 (+) Start the TIM Encoder and enable interrupt.
2862 (+) Stop the TIM Encoder and disable interrupt.
2863 (+) Start the TIM Encoder and enable DMA transfer.
2864 (+) Stop the TIM Encoder and disable DMA transfer.
2865
2866 @endverbatim
2867 * @{
2868 */
2869 /**
2870 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
2871 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2872 * requires a timer reset to avoid unexpected direction
2873 * due to DIR bit readonly in center aligned mode.
2874 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
2875 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
2876 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
2877 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
2878 * @note When the timer instance is initialized in Encoder mode, timer
2879 * channels 1 and channel 2 are reserved and cannot be used for other
2880 * purpose.
2881 * @param htim TIM Encoder Interface handle
2882 * @param sConfig TIM Encoder Interface configuration structure
2883 * @retval HAL status
2884 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)2885 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
2886 {
2887 uint32_t tmpsmcr;
2888 uint32_t tmpccmr1;
2889 uint32_t tmpccer;
2890
2891 /* Check the TIM handle allocation */
2892 if (htim == NULL)
2893 {
2894 return HAL_ERROR;
2895 }
2896
2897 /* Check the parameters */
2898 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2899 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2900 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2901 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2902 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2903 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2904 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2905 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
2906 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
2907 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2908 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2909 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2910 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2911 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2912
2913 if (htim->State == HAL_TIM_STATE_RESET)
2914 {
2915 /* Allocate lock resource and initialize it */
2916 htim->Lock = HAL_UNLOCKED;
2917
2918 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2919 /* Reset interrupt callbacks to legacy weak callbacks */
2920 TIM_ResetCallback(htim);
2921
2922 if (htim->Encoder_MspInitCallback == NULL)
2923 {
2924 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
2925 }
2926 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2927 htim->Encoder_MspInitCallback(htim);
2928 #else
2929 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2930 HAL_TIM_Encoder_MspInit(htim);
2931 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2932 }
2933
2934 /* Set the TIM state */
2935 htim->State = HAL_TIM_STATE_BUSY;
2936
2937 /* Reset the SMS and ECE bits */
2938 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
2939
2940 /* Configure the Time base in the Encoder Mode */
2941 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2942
2943 /* Get the TIMx SMCR register value */
2944 tmpsmcr = htim->Instance->SMCR;
2945
2946 /* Get the TIMx CCMR1 register value */
2947 tmpccmr1 = htim->Instance->CCMR1;
2948
2949 /* Get the TIMx CCER register value */
2950 tmpccer = htim->Instance->CCER;
2951
2952 /* Set the encoder Mode */
2953 tmpsmcr |= sConfig->EncoderMode;
2954
2955 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2956 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2957 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2958
2959 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2960 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2961 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2962 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
2963 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
2964
2965 /* Set the TI1 and the TI2 Polarities */
2966 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2967 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2968 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
2969
2970 /* Write to TIMx SMCR */
2971 htim->Instance->SMCR = tmpsmcr;
2972
2973 /* Write to TIMx CCMR1 */
2974 htim->Instance->CCMR1 = tmpccmr1;
2975
2976 /* Write to TIMx CCER */
2977 htim->Instance->CCER = tmpccer;
2978
2979 /* Initialize the DMA burst operation state */
2980 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2981
2982 /* Set the TIM channels state */
2983 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2984 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2985
2986 /* Initialize the TIM state*/
2987 htim->State = HAL_TIM_STATE_READY;
2988
2989 return HAL_OK;
2990 }
2991
2992
2993 /**
2994 * @brief DeInitializes the TIM Encoder interface
2995 * @param htim TIM Encoder Interface handle
2996 * @retval HAL status
2997 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)2998 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2999 {
3000 /* Check the parameters */
3001 assert_param(IS_TIM_INSTANCE(htim->Instance));
3002
3003 htim->State = HAL_TIM_STATE_BUSY;
3004
3005 /* Disable the TIM Peripheral Clock */
3006 __HAL_TIM_DISABLE(htim);
3007
3008 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3009 if (htim->Encoder_MspDeInitCallback == NULL)
3010 {
3011 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3012 }
3013 /* DeInit the low level hardware */
3014 htim->Encoder_MspDeInitCallback(htim);
3015 #else
3016 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3017 HAL_TIM_Encoder_MspDeInit(htim);
3018 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3019
3020 /* Change the DMA burst operation state */
3021 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3022
3023 /* Set the TIM channels state */
3024 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3025 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3026
3027 /* Change TIM state */
3028 htim->State = HAL_TIM_STATE_RESET;
3029
3030 /* Release Lock */
3031 __HAL_UNLOCK(htim);
3032
3033 return HAL_OK;
3034 }
3035
3036 /**
3037 * @brief Initializes the TIM Encoder Interface MSP.
3038 * @param htim TIM Encoder Interface handle
3039 * @retval None
3040 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3041 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3042 {
3043 /* Prevent unused argument(s) compilation warning */
3044 UNUSED(htim);
3045
3046 /* NOTE : This function should not be modified, when the callback is needed,
3047 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3048 */
3049 }
3050
3051 /**
3052 * @brief DeInitializes TIM Encoder Interface MSP.
3053 * @param htim TIM Encoder Interface handle
3054 * @retval None
3055 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3056 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3057 {
3058 /* Prevent unused argument(s) compilation warning */
3059 UNUSED(htim);
3060
3061 /* NOTE : This function should not be modified, when the callback is needed,
3062 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3063 */
3064 }
3065
3066 /**
3067 * @brief Starts the TIM Encoder Interface.
3068 * @param htim TIM Encoder Interface handle
3069 * @param Channel TIM Channels to be enabled
3070 * This parameter can be one of the following values:
3071 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3072 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3073 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3074 * @retval HAL status
3075 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3076 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3077 {
3078 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3079 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3080
3081 /* Check the parameters */
3082 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3083
3084 /* Set the TIM channel(s) state */
3085 if (Channel == TIM_CHANNEL_1)
3086 {
3087 if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3088 {
3089 return HAL_ERROR;
3090 }
3091 else
3092 {
3093 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3094 }
3095 }
3096 else if (Channel == TIM_CHANNEL_2)
3097 {
3098 if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3099 {
3100 return HAL_ERROR;
3101 }
3102 else
3103 {
3104 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3105 }
3106 }
3107 else
3108 {
3109 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3110 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3111 {
3112 return HAL_ERROR;
3113 }
3114 else
3115 {
3116 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3117 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3118 }
3119 }
3120
3121 /* Enable the encoder interface channels */
3122 switch (Channel)
3123 {
3124 case TIM_CHANNEL_1:
3125 {
3126 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3127 break;
3128 }
3129
3130 case TIM_CHANNEL_2:
3131 {
3132 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3133 break;
3134 }
3135
3136 default :
3137 {
3138 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3139 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3140 break;
3141 }
3142 }
3143 /* Enable the Peripheral */
3144 __HAL_TIM_ENABLE(htim);
3145
3146 /* Return function status */
3147 return HAL_OK;
3148 }
3149
3150 /**
3151 * @brief Stops the TIM Encoder Interface.
3152 * @param htim TIM Encoder Interface handle
3153 * @param Channel TIM Channels to be disabled
3154 * This parameter can be one of the following values:
3155 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3156 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3157 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3158 * @retval HAL status
3159 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3160 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3161 {
3162 /* Check the parameters */
3163 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3164
3165 /* Disable the Input Capture channels 1 and 2
3166 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3167 switch (Channel)
3168 {
3169 case TIM_CHANNEL_1:
3170 {
3171 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3172 break;
3173 }
3174
3175 case TIM_CHANNEL_2:
3176 {
3177 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3178 break;
3179 }
3180
3181 default :
3182 {
3183 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3184 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3185 break;
3186 }
3187 }
3188
3189 /* Disable the Peripheral */
3190 __HAL_TIM_DISABLE(htim);
3191
3192 /* Set the TIM channel(s) state */
3193 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3194 {
3195 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3196 }
3197 else
3198 {
3199 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3200 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3201 }
3202
3203 /* Return function status */
3204 return HAL_OK;
3205 }
3206
3207 /**
3208 * @brief Starts the TIM Encoder Interface in interrupt mode.
3209 * @param htim TIM Encoder Interface handle
3210 * @param Channel TIM Channels to be enabled
3211 * This parameter can be one of the following values:
3212 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3213 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3214 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3215 * @retval HAL status
3216 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3217 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3218 {
3219 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3220 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3221
3222 /* Check the parameters */
3223 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3224
3225 /* Set the TIM channel(s) state */
3226 if (Channel == TIM_CHANNEL_1)
3227 {
3228 if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3229 {
3230 return HAL_ERROR;
3231 }
3232 else
3233 {
3234 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3235 }
3236 }
3237 else if (Channel == TIM_CHANNEL_2)
3238 {
3239 if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3240 {
3241 return HAL_ERROR;
3242 }
3243 else
3244 {
3245 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3246 }
3247 }
3248 else
3249 {
3250 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3251 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3252 {
3253 return HAL_ERROR;
3254 }
3255 else
3256 {
3257 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3258 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3259 }
3260 }
3261
3262 /* Enable the encoder interface channels */
3263 /* Enable the capture compare Interrupts 1 and/or 2 */
3264 switch (Channel)
3265 {
3266 case TIM_CHANNEL_1:
3267 {
3268 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3269 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3270 break;
3271 }
3272
3273 case TIM_CHANNEL_2:
3274 {
3275 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3276 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3277 break;
3278 }
3279
3280 default :
3281 {
3282 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3283 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3284 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3285 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3286 break;
3287 }
3288 }
3289
3290 /* Enable the Peripheral */
3291 __HAL_TIM_ENABLE(htim);
3292
3293 /* Return function status */
3294 return HAL_OK;
3295 }
3296
3297 /**
3298 * @brief Stops the TIM Encoder Interface in interrupt mode.
3299 * @param htim TIM Encoder Interface handle
3300 * @param Channel TIM Channels to be disabled
3301 * This parameter can be one of the following values:
3302 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3303 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3304 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3305 * @retval HAL status
3306 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3307 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3308 {
3309 /* Check the parameters */
3310 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3311
3312 /* Disable the Input Capture channels 1 and 2
3313 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3314 if (Channel == TIM_CHANNEL_1)
3315 {
3316 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3317
3318 /* Disable the capture compare Interrupts 1 */
3319 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3320 }
3321 else if (Channel == TIM_CHANNEL_2)
3322 {
3323 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3324
3325 /* Disable the capture compare Interrupts 2 */
3326 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3327 }
3328 else
3329 {
3330 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3331 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3332
3333 /* Disable the capture compare Interrupts 1 and 2 */
3334 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3335 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3336 }
3337
3338 /* Disable the Peripheral */
3339 __HAL_TIM_DISABLE(htim);
3340
3341 /* Set the TIM channel(s) state */
3342 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3343 {
3344 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3345 }
3346 else
3347 {
3348 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3349 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3350 }
3351
3352 /* Return function status */
3353 return HAL_OK;
3354 }
3355
3356 /**
3357 * @brief Starts the TIM Encoder Interface in DMA mode.
3358 * @param htim TIM Encoder Interface handle
3359 * @param Channel TIM Channels to be enabled
3360 * This parameter can be one of the following values:
3361 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3362 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3363 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3364 * @param pData1 The destination Buffer address for IC1.
3365 * @param pData2 The destination Buffer address for IC2.
3366 * @param Length The length of data to be transferred from TIM peripheral to memory.
3367 * @retval HAL status
3368 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3369 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3370 uint32_t *pData2, uint16_t Length)
3371 {
3372 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3373 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3374
3375 /* Check the parameters */
3376 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3377
3378 /* Set the TIM channel(s) state */
3379 if (Channel == TIM_CHANNEL_1)
3380 {
3381 if (channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3382 {
3383 return HAL_BUSY;
3384 }
3385 else if (channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3386 {
3387 if ((pData1 == NULL) || (Length == 0U))
3388 {
3389 return HAL_ERROR;
3390 }
3391 else
3392 {
3393 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3394 }
3395 }
3396 else
3397 {
3398 return HAL_ERROR;
3399 }
3400 }
3401 else if (Channel == TIM_CHANNEL_2)
3402 {
3403 if (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3404 {
3405 return HAL_BUSY;
3406 }
3407 else if (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3408 {
3409 if ((pData2 == NULL) || (Length == 0U))
3410 {
3411 return HAL_ERROR;
3412 }
3413 else
3414 {
3415 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3416 }
3417 }
3418 else
3419 {
3420 return HAL_ERROR;
3421 }
3422 }
3423 else
3424 {
3425 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3426 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3427 {
3428 return HAL_BUSY;
3429 }
3430 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3431 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3432 {
3433 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3434 {
3435 return HAL_ERROR;
3436 }
3437 else
3438 {
3439 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3440 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3441 }
3442 }
3443 else
3444 {
3445 return HAL_ERROR;
3446 }
3447 }
3448
3449 switch (Channel)
3450 {
3451 case TIM_CHANNEL_1:
3452 {
3453 /* Set the DMA capture callbacks */
3454 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3455 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3456
3457 /* Set the DMA error callback */
3458 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3459
3460 /* Enable the DMA channel */
3461 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3462 Length) != HAL_OK)
3463 {
3464 /* Return error status */
3465 return HAL_ERROR;
3466 }
3467 /* Enable the TIM Input Capture DMA request */
3468 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3469
3470 /* Enable the Capture compare channel */
3471 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3472
3473 /* Enable the Peripheral */
3474 __HAL_TIM_ENABLE(htim);
3475
3476 break;
3477 }
3478
3479 case TIM_CHANNEL_2:
3480 {
3481 /* Set the DMA capture callbacks */
3482 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3483 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3484
3485 /* Set the DMA error callback */
3486 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3487 /* Enable the DMA channel */
3488 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3489 Length) != HAL_OK)
3490 {
3491 /* Return error status */
3492 return HAL_ERROR;
3493 }
3494 /* Enable the TIM Input Capture DMA request */
3495 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3496
3497 /* Enable the Capture compare channel */
3498 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3499
3500 /* Enable the Peripheral */
3501 __HAL_TIM_ENABLE(htim);
3502
3503 break;
3504 }
3505
3506 default:
3507 {
3508 /* Set the DMA capture callbacks */
3509 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3510 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3511
3512 /* Set the DMA error callback */
3513 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3514
3515 /* Enable the DMA channel */
3516 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3517 Length) != HAL_OK)
3518 {
3519 /* Return error status */
3520 return HAL_ERROR;
3521 }
3522
3523 /* Set the DMA capture callbacks */
3524 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3525 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3526
3527 /* Set the DMA error callback */
3528 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3529
3530 /* Enable the DMA channel */
3531 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3532 Length) != HAL_OK)
3533 {
3534 /* Return error status */
3535 return HAL_ERROR;
3536 }
3537
3538 /* Enable the TIM Input Capture DMA request */
3539 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3540 /* Enable the TIM Input Capture DMA request */
3541 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3542
3543 /* Enable the Capture compare channel */
3544 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3545 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3546
3547 /* Enable the Peripheral */
3548 __HAL_TIM_ENABLE(htim);
3549
3550 break;
3551 }
3552 }
3553
3554 /* Return function status */
3555 return HAL_OK;
3556 }
3557
3558 /**
3559 * @brief Stops the TIM Encoder Interface in DMA mode.
3560 * @param htim TIM Encoder Interface handle
3561 * @param Channel TIM Channels to be enabled
3562 * This parameter can be one of the following values:
3563 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3564 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3565 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3566 * @retval HAL status
3567 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3568 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3569 {
3570 /* Check the parameters */
3571 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3572
3573 /* Disable the Input Capture channels 1 and 2
3574 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3575 if (Channel == TIM_CHANNEL_1)
3576 {
3577 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3578
3579 /* Disable the capture compare DMA Request 1 */
3580 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3581 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3582 }
3583 else if (Channel == TIM_CHANNEL_2)
3584 {
3585 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3586
3587 /* Disable the capture compare DMA Request 2 */
3588 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3589 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3590 }
3591 else
3592 {
3593 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3594 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3595
3596 /* Disable the capture compare DMA Request 1 and 2 */
3597 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3598 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3599 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3600 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3601 }
3602
3603 /* Disable the Peripheral */
3604 __HAL_TIM_DISABLE(htim);
3605
3606 /* Set the TIM channel(s) state */
3607 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3608 {
3609 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3610 }
3611 else
3612 {
3613 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3614 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3615 }
3616
3617 /* Return function status */
3618 return HAL_OK;
3619 }
3620
3621 /**
3622 * @}
3623 */
3624 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3625 * @brief TIM IRQ handler management
3626 *
3627 @verbatim
3628 ==============================================================================
3629 ##### IRQ handler management #####
3630 ==============================================================================
3631 [..]
3632 This section provides Timer IRQ handler function.
3633
3634 @endverbatim
3635 * @{
3636 */
3637 /**
3638 * @brief This function handles TIM interrupts requests.
3639 * @param htim TIM handle
3640 * @retval None
3641 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3642 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3643 {
3644 /* Capture compare 1 event */
3645 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3646 {
3647 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3648 {
3649 {
3650 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3651 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3652
3653 /* Input capture event */
3654 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3655 {
3656 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3657 htim->IC_CaptureCallback(htim);
3658 #else
3659 HAL_TIM_IC_CaptureCallback(htim);
3660 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3661 }
3662 /* Output compare event */
3663 else
3664 {
3665 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3666 htim->OC_DelayElapsedCallback(htim);
3667 htim->PWM_PulseFinishedCallback(htim);
3668 #else
3669 HAL_TIM_OC_DelayElapsedCallback(htim);
3670 HAL_TIM_PWM_PulseFinishedCallback(htim);
3671 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3672 }
3673 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3674 }
3675 }
3676 }
3677 /* Capture compare 2 event */
3678 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3679 {
3680 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3681 {
3682 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3683 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3684 /* Input capture event */
3685 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3686 {
3687 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3688 htim->IC_CaptureCallback(htim);
3689 #else
3690 HAL_TIM_IC_CaptureCallback(htim);
3691 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3692 }
3693 /* Output compare event */
3694 else
3695 {
3696 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3697 htim->OC_DelayElapsedCallback(htim);
3698 htim->PWM_PulseFinishedCallback(htim);
3699 #else
3700 HAL_TIM_OC_DelayElapsedCallback(htim);
3701 HAL_TIM_PWM_PulseFinishedCallback(htim);
3702 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3703 }
3704 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3705 }
3706 }
3707 /* Capture compare 3 event */
3708 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3709 {
3710 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3711 {
3712 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3713 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3714 /* Input capture event */
3715 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3716 {
3717 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3718 htim->IC_CaptureCallback(htim);
3719 #else
3720 HAL_TIM_IC_CaptureCallback(htim);
3721 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3722 }
3723 /* Output compare event */
3724 else
3725 {
3726 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3727 htim->OC_DelayElapsedCallback(htim);
3728 htim->PWM_PulseFinishedCallback(htim);
3729 #else
3730 HAL_TIM_OC_DelayElapsedCallback(htim);
3731 HAL_TIM_PWM_PulseFinishedCallback(htim);
3732 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3733 }
3734 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3735 }
3736 }
3737 /* Capture compare 4 event */
3738 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3739 {
3740 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3741 {
3742 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3743 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3744 /* Input capture event */
3745 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3746 {
3747 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3748 htim->IC_CaptureCallback(htim);
3749 #else
3750 HAL_TIM_IC_CaptureCallback(htim);
3751 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3752 }
3753 /* Output compare event */
3754 else
3755 {
3756 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3757 htim->OC_DelayElapsedCallback(htim);
3758 htim->PWM_PulseFinishedCallback(htim);
3759 #else
3760 HAL_TIM_OC_DelayElapsedCallback(htim);
3761 HAL_TIM_PWM_PulseFinishedCallback(htim);
3762 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3763 }
3764 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3765 }
3766 }
3767 /* TIM Update event */
3768 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3769 {
3770 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3771 {
3772 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3773 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3774 htim->PeriodElapsedCallback(htim);
3775 #else
3776 HAL_TIM_PeriodElapsedCallback(htim);
3777 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3778 }
3779 }
3780 /* TIM Trigger detection event */
3781 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3782 {
3783 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3784 {
3785 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3786 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3787 htim->TriggerCallback(htim);
3788 #else
3789 HAL_TIM_TriggerCallback(htim);
3790 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3791 }
3792 }
3793 }
3794
3795 /**
3796 * @}
3797 */
3798
3799 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
3800 * @brief TIM Peripheral Control functions
3801 *
3802 @verbatim
3803 ==============================================================================
3804 ##### Peripheral Control functions #####
3805 ==============================================================================
3806 [..]
3807 This section provides functions allowing to:
3808 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3809 (+) Configure External Clock source.
3810 (+) Configure Master and the Slave synchronization.
3811 (+) Configure the DMA Burst Mode.
3812
3813 @endverbatim
3814 * @{
3815 */
3816
3817 /**
3818 * @brief Initializes the TIM Output Compare Channels according to the specified
3819 * parameters in the TIM_OC_InitTypeDef.
3820 * @param htim TIM Output Compare handle
3821 * @param sConfig TIM Output Compare configuration structure
3822 * @param Channel TIM Channels to configure
3823 * This parameter can be one of the following values:
3824 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3825 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3826 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3827 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3828 * @retval HAL status
3829 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3830 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
3831 const TIM_OC_InitTypeDef *sConfig,
3832 uint32_t Channel)
3833 {
3834 HAL_StatusTypeDef status = HAL_OK;
3835
3836 /* Check the parameters */
3837 assert_param(IS_TIM_CHANNELS(Channel));
3838 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
3839 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3840
3841 /* Process Locked */
3842 __HAL_LOCK(htim);
3843
3844 switch (Channel)
3845 {
3846 case TIM_CHANNEL_1:
3847 {
3848 /* Check the parameters */
3849 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3850
3851 /* Configure the TIM Channel 1 in Output Compare */
3852 TIM_OC1_SetConfig(htim->Instance, sConfig);
3853 break;
3854 }
3855
3856 case TIM_CHANNEL_2:
3857 {
3858 /* Check the parameters */
3859 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3860
3861 /* Configure the TIM Channel 2 in Output Compare */
3862 TIM_OC2_SetConfig(htim->Instance, sConfig);
3863 break;
3864 }
3865
3866 case TIM_CHANNEL_3:
3867 {
3868 /* Check the parameters */
3869 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3870
3871 /* Configure the TIM Channel 3 in Output Compare */
3872 TIM_OC3_SetConfig(htim->Instance, sConfig);
3873 break;
3874 }
3875
3876 case TIM_CHANNEL_4:
3877 {
3878 /* Check the parameters */
3879 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3880
3881 /* Configure the TIM Channel 4 in Output Compare */
3882 TIM_OC4_SetConfig(htim->Instance, sConfig);
3883 break;
3884 }
3885
3886 default:
3887 status = HAL_ERROR;
3888 break;
3889 }
3890
3891 __HAL_UNLOCK(htim);
3892
3893 return status;
3894 }
3895
3896 /**
3897 * @brief Initializes the TIM Input Capture Channels according to the specified
3898 * parameters in the TIM_IC_InitTypeDef.
3899 * @param htim TIM IC handle
3900 * @param sConfig TIM Input Capture configuration structure
3901 * @param Channel TIM Channel to configure
3902 * This parameter can be one of the following values:
3903 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3904 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3905 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3906 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3907 * @retval HAL status
3908 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)3909 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
3910 {
3911 HAL_StatusTypeDef status = HAL_OK;
3912
3913 /* Check the parameters */
3914 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3915 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
3916 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
3917 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
3918 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
3919
3920 /* Process Locked */
3921 __HAL_LOCK(htim);
3922
3923 if (Channel == TIM_CHANNEL_1)
3924 {
3925 /* TI1 Configuration */
3926 TIM_TI1_SetConfig(htim->Instance,
3927 sConfig->ICPolarity,
3928 sConfig->ICSelection,
3929 sConfig->ICFilter);
3930
3931 /* Reset the IC1PSC Bits */
3932 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3933
3934 /* Set the IC1PSC value */
3935 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
3936 }
3937 else if (Channel == TIM_CHANNEL_2)
3938 {
3939 /* TI2 Configuration */
3940 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3941
3942 TIM_TI2_SetConfig(htim->Instance,
3943 sConfig->ICPolarity,
3944 sConfig->ICSelection,
3945 sConfig->ICFilter);
3946
3947 /* Reset the IC2PSC Bits */
3948 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3949
3950 /* Set the IC2PSC value */
3951 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
3952 }
3953 else if (Channel == TIM_CHANNEL_3)
3954 {
3955 /* TI3 Configuration */
3956 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3957
3958 TIM_TI3_SetConfig(htim->Instance,
3959 sConfig->ICPolarity,
3960 sConfig->ICSelection,
3961 sConfig->ICFilter);
3962
3963 /* Reset the IC3PSC Bits */
3964 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
3965
3966 /* Set the IC3PSC value */
3967 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3968 }
3969 else if (Channel == TIM_CHANNEL_4)
3970 {
3971 /* TI4 Configuration */
3972 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3973
3974 TIM_TI4_SetConfig(htim->Instance,
3975 sConfig->ICPolarity,
3976 sConfig->ICSelection,
3977 sConfig->ICFilter);
3978
3979 /* Reset the IC4PSC Bits */
3980 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3981
3982 /* Set the IC4PSC value */
3983 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
3984 }
3985 else
3986 {
3987 status = HAL_ERROR;
3988 }
3989
3990 __HAL_UNLOCK(htim);
3991
3992 return status;
3993 }
3994
3995 /**
3996 * @brief Initializes the TIM PWM channels according to the specified
3997 * parameters in the TIM_OC_InitTypeDef.
3998 * @param htim TIM PWM handle
3999 * @param sConfig TIM PWM configuration structure
4000 * @param Channel TIM Channels to be configured
4001 * This parameter can be one of the following values:
4002 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4003 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4004 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4005 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4006 * @retval HAL status
4007 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4008 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4009 const TIM_OC_InitTypeDef *sConfig,
4010 uint32_t Channel)
4011 {
4012 HAL_StatusTypeDef status = HAL_OK;
4013
4014 /* Check the parameters */
4015 assert_param(IS_TIM_CHANNELS(Channel));
4016 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4017 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4018 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4019
4020 /* Process Locked */
4021 __HAL_LOCK(htim);
4022
4023 switch (Channel)
4024 {
4025 case TIM_CHANNEL_1:
4026 {
4027 /* Check the parameters */
4028 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4029
4030 /* Configure the Channel 1 in PWM mode */
4031 TIM_OC1_SetConfig(htim->Instance, sConfig);
4032
4033 /* Set the Preload enable bit for channel1 */
4034 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4035
4036 /* Configure the Output Fast mode */
4037 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4038 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4039 break;
4040 }
4041
4042 case TIM_CHANNEL_2:
4043 {
4044 /* Check the parameters */
4045 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4046
4047 /* Configure the Channel 2 in PWM mode */
4048 TIM_OC2_SetConfig(htim->Instance, sConfig);
4049
4050 /* Set the Preload enable bit for channel2 */
4051 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4052
4053 /* Configure the Output Fast mode */
4054 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4055 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4056 break;
4057 }
4058
4059 case TIM_CHANNEL_3:
4060 {
4061 /* Check the parameters */
4062 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4063
4064 /* Configure the Channel 3 in PWM mode */
4065 TIM_OC3_SetConfig(htim->Instance, sConfig);
4066
4067 /* Set the Preload enable bit for channel3 */
4068 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4069
4070 /* Configure the Output Fast mode */
4071 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4072 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4073 break;
4074 }
4075
4076 case TIM_CHANNEL_4:
4077 {
4078 /* Check the parameters */
4079 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4080
4081 /* Configure the Channel 4 in PWM mode */
4082 TIM_OC4_SetConfig(htim->Instance, sConfig);
4083
4084 /* Set the Preload enable bit for channel4 */
4085 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4086
4087 /* Configure the Output Fast mode */
4088 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4089 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4090 break;
4091 }
4092
4093 default:
4094 status = HAL_ERROR;
4095 break;
4096 }
4097
4098 __HAL_UNLOCK(htim);
4099
4100 return status;
4101 }
4102
4103 /**
4104 * @brief Initializes the TIM One Pulse Channels according to the specified
4105 * parameters in the TIM_OnePulse_InitTypeDef.
4106 * @param htim TIM One Pulse handle
4107 * @param sConfig TIM One Pulse configuration structure
4108 * @param OutputChannel TIM output channel to configure
4109 * This parameter can be one of the following values:
4110 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4111 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4112 * @param InputChannel TIM input Channel to configure
4113 * This parameter can be one of the following values:
4114 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4115 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4116 * @note To output a waveform with a minimum delay user can enable the fast
4117 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4118 * output is forced in response to the edge detection on TIx input,
4119 * without taking in account the comparison.
4120 * @retval HAL status
4121 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4122 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4123 uint32_t OutputChannel, uint32_t InputChannel)
4124 {
4125 HAL_StatusTypeDef status = HAL_OK;
4126 TIM_OC_InitTypeDef temp1;
4127
4128 /* Check the parameters */
4129 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4130 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4131
4132 if (OutputChannel != InputChannel)
4133 {
4134 /* Process Locked */
4135 __HAL_LOCK(htim);
4136
4137 htim->State = HAL_TIM_STATE_BUSY;
4138
4139 /* Extract the Output compare configuration from sConfig structure */
4140 temp1.OCMode = sConfig->OCMode;
4141 temp1.Pulse = sConfig->Pulse;
4142 temp1.OCPolarity = sConfig->OCPolarity;
4143
4144 switch (OutputChannel)
4145 {
4146 case TIM_CHANNEL_1:
4147 {
4148 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4149
4150 TIM_OC1_SetConfig(htim->Instance, &temp1);
4151 break;
4152 }
4153
4154 case TIM_CHANNEL_2:
4155 {
4156 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4157
4158 TIM_OC2_SetConfig(htim->Instance, &temp1);
4159 break;
4160 }
4161
4162 default:
4163 status = HAL_ERROR;
4164 break;
4165 }
4166
4167 if (status == HAL_OK)
4168 {
4169 switch (InputChannel)
4170 {
4171 case TIM_CHANNEL_1:
4172 {
4173 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4174
4175 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4176 sConfig->ICSelection, sConfig->ICFilter);
4177
4178 /* Reset the IC1PSC Bits */
4179 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4180
4181 /* Select the Trigger source */
4182 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4183 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4184
4185 /* Select the Slave Mode */
4186 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4187 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4188 break;
4189 }
4190
4191 case TIM_CHANNEL_2:
4192 {
4193 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4194
4195 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4196 sConfig->ICSelection, sConfig->ICFilter);
4197
4198 /* Reset the IC2PSC Bits */
4199 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4200
4201 /* Select the Trigger source */
4202 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4203 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4204
4205 /* Select the Slave Mode */
4206 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4207 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4208 break;
4209 }
4210
4211 default:
4212 status = HAL_ERROR;
4213 break;
4214 }
4215 }
4216
4217 htim->State = HAL_TIM_STATE_READY;
4218
4219 __HAL_UNLOCK(htim);
4220
4221 return status;
4222 }
4223 else
4224 {
4225 return HAL_ERROR;
4226 }
4227 }
4228
4229 /**
4230 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4231 * @param htim TIM handle
4232 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4233 * This parameter can be one of the following values:
4234 * @arg TIM_DMABASE_CR1
4235 * @arg TIM_DMABASE_CR2
4236 * @arg TIM_DMABASE_SMCR
4237 * @arg TIM_DMABASE_DIER
4238 * @arg TIM_DMABASE_SR
4239 * @arg TIM_DMABASE_EGR
4240 * @arg TIM_DMABASE_CCMR1
4241 * @arg TIM_DMABASE_CCMR2
4242 * @arg TIM_DMABASE_CCER
4243 * @arg TIM_DMABASE_CNT
4244 * @arg TIM_DMABASE_PSC
4245 * @arg TIM_DMABASE_ARR
4246 * @arg TIM_DMABASE_CCR1
4247 * @arg TIM_DMABASE_CCR2
4248 * @arg TIM_DMABASE_CCR3
4249 * @arg TIM_DMABASE_CCR4
4250 * @arg TIM_DMABASE_OR
4251 * @param BurstRequestSrc TIM DMA Request sources
4252 * This parameter can be one of the following values:
4253 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4254 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4255 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4256 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4257 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4258 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4259 * @param BurstBuffer The Buffer address.
4260 * @param BurstLength DMA Burst length. This parameter can be one value
4261 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4262 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4263 * @retval HAL status
4264 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4265 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4266 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
4267 {
4268 HAL_StatusTypeDef status;
4269
4270 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4271 ((BurstLength) >> 8U) + 1U);
4272
4273
4274
4275 return status;
4276 }
4277
4278 /**
4279 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4280 * @param htim TIM handle
4281 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4282 * This parameter can be one of the following values:
4283 * @arg TIM_DMABASE_CR1
4284 * @arg TIM_DMABASE_CR2
4285 * @arg TIM_DMABASE_SMCR
4286 * @arg TIM_DMABASE_DIER
4287 * @arg TIM_DMABASE_SR
4288 * @arg TIM_DMABASE_EGR
4289 * @arg TIM_DMABASE_CCMR1
4290 * @arg TIM_DMABASE_CCMR2
4291 * @arg TIM_DMABASE_CCER
4292 * @arg TIM_DMABASE_CNT
4293 * @arg TIM_DMABASE_PSC
4294 * @arg TIM_DMABASE_ARR
4295 * @arg TIM_DMABASE_CCR1
4296 * @arg TIM_DMABASE_CCR2
4297 * @arg TIM_DMABASE_CCR3
4298 * @arg TIM_DMABASE_CCR4
4299 * @arg TIM_DMABASE_OR
4300 * @param BurstRequestSrc TIM DMA Request sources
4301 * This parameter can be one of the following values:
4302 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4303 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4304 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4305 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4306 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4307 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4308 * @param BurstBuffer The Buffer address.
4309 * @param BurstLength DMA Burst length. This parameter can be one value
4310 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4311 * @param DataLength Data length. This parameter can be one value
4312 * between 1 and 0xFFFF.
4313 * @retval HAL status
4314 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4315 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4316 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4317 uint32_t BurstLength, uint32_t DataLength)
4318 {
4319 HAL_StatusTypeDef status = HAL_OK;
4320
4321 /* Check the parameters */
4322 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4323 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4324 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4325 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4326 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4327
4328 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4329 {
4330 return HAL_BUSY;
4331 }
4332 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4333 {
4334 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4335 {
4336 return HAL_ERROR;
4337 }
4338 else
4339 {
4340 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4341 }
4342 }
4343 else
4344 {
4345 /* nothing to do */
4346 }
4347
4348 switch (BurstRequestSrc)
4349 {
4350 case TIM_DMA_UPDATE:
4351 {
4352 /* Set the DMA Period elapsed callbacks */
4353 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4354 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4355
4356 /* Set the DMA error callback */
4357 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4358
4359 /* Enable the DMA channel */
4360 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4361 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4362 {
4363 /* Return error status */
4364 return HAL_ERROR;
4365 }
4366 break;
4367 }
4368 case TIM_DMA_CC1:
4369 {
4370 /* Set the DMA compare callbacks */
4371 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4372 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4373
4374 /* Set the DMA error callback */
4375 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4376
4377 /* Enable the DMA channel */
4378 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4379 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4380 {
4381 /* Return error status */
4382 return HAL_ERROR;
4383 }
4384 break;
4385 }
4386 case TIM_DMA_CC2:
4387 {
4388 /* Set the DMA compare callbacks */
4389 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4390 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4391
4392 /* Set the DMA error callback */
4393 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4394
4395 /* Enable the DMA channel */
4396 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4397 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4398 {
4399 /* Return error status */
4400 return HAL_ERROR;
4401 }
4402 break;
4403 }
4404 case TIM_DMA_CC3:
4405 {
4406 /* Set the DMA compare callbacks */
4407 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4408 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4409
4410 /* Set the DMA error callback */
4411 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4412
4413 /* Enable the DMA channel */
4414 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4415 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4416 {
4417 /* Return error status */
4418 return HAL_ERROR;
4419 }
4420 break;
4421 }
4422 case TIM_DMA_CC4:
4423 {
4424 /* Set the DMA compare callbacks */
4425 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4426 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4427
4428 /* Set the DMA error callback */
4429 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4430
4431 /* Enable the DMA channel */
4432 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4433 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4434 {
4435 /* Return error status */
4436 return HAL_ERROR;
4437 }
4438 break;
4439 }
4440 case TIM_DMA_TRIGGER:
4441 {
4442 /* Set the DMA trigger callbacks */
4443 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4444 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4445
4446 /* Set the DMA error callback */
4447 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4448
4449 /* Enable the DMA channel */
4450 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4451 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4452 {
4453 /* Return error status */
4454 return HAL_ERROR;
4455 }
4456 break;
4457 }
4458 default:
4459 status = HAL_ERROR;
4460 break;
4461 }
4462
4463 if (status == HAL_OK)
4464 {
4465 /* Configure the DMA Burst Mode */
4466 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4467 /* Enable the TIM DMA Request */
4468 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4469 }
4470
4471 /* Return function status */
4472 return status;
4473 }
4474
4475 /**
4476 * @brief Stops the TIM DMA Burst mode
4477 * @param htim TIM handle
4478 * @param BurstRequestSrc TIM DMA Request sources to disable
4479 * @retval HAL status
4480 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4481 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4482 {
4483 HAL_StatusTypeDef status = HAL_OK;
4484
4485 /* Check the parameters */
4486 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4487
4488 /* Abort the DMA transfer (at least disable the DMA channel) */
4489 switch (BurstRequestSrc)
4490 {
4491 case TIM_DMA_UPDATE:
4492 {
4493 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4494 break;
4495 }
4496 case TIM_DMA_CC1:
4497 {
4498 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4499 break;
4500 }
4501 case TIM_DMA_CC2:
4502 {
4503 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4504 break;
4505 }
4506 case TIM_DMA_CC3:
4507 {
4508 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4509 break;
4510 }
4511 case TIM_DMA_CC4:
4512 {
4513 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4514 break;
4515 }
4516 case TIM_DMA_TRIGGER:
4517 {
4518 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4519 break;
4520 }
4521 default:
4522 status = HAL_ERROR;
4523 break;
4524 }
4525
4526 if (status == HAL_OK)
4527 {
4528 /* Disable the TIM Update DMA request */
4529 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4530
4531 /* Change the DMA burst operation state */
4532 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4533 }
4534
4535 /* Return function status */
4536 return status;
4537 }
4538
4539 /**
4540 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4541 * @param htim TIM handle
4542 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4543 * This parameter can be one of the following values:
4544 * @arg TIM_DMABASE_CR1
4545 * @arg TIM_DMABASE_CR2
4546 * @arg TIM_DMABASE_SMCR
4547 * @arg TIM_DMABASE_DIER
4548 * @arg TIM_DMABASE_SR
4549 * @arg TIM_DMABASE_EGR
4550 * @arg TIM_DMABASE_CCMR1
4551 * @arg TIM_DMABASE_CCMR2
4552 * @arg TIM_DMABASE_CCER
4553 * @arg TIM_DMABASE_CNT
4554 * @arg TIM_DMABASE_PSC
4555 * @arg TIM_DMABASE_ARR
4556 * @arg TIM_DMABASE_CCR1
4557 * @arg TIM_DMABASE_CCR2
4558 * @arg TIM_DMABASE_CCR3
4559 * @arg TIM_DMABASE_CCR4
4560 * @arg TIM_DMABASE_OR
4561 * @param BurstRequestSrc TIM DMA Request sources
4562 * This parameter can be one of the following values:
4563 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4564 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4565 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4566 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4567 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4568 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4569 * @param BurstBuffer The Buffer address.
4570 * @param BurstLength DMA Burst length. This parameter can be one value
4571 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4572 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4573 * @retval HAL status
4574 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4575 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4576 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4577 {
4578 HAL_StatusTypeDef status;
4579
4580 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4581 ((BurstLength) >> 8U) + 1U);
4582
4583
4584 return status;
4585 }
4586
4587 /**
4588 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4589 * @param htim TIM handle
4590 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4591 * This parameter can be one of the following values:
4592 * @arg TIM_DMABASE_CR1
4593 * @arg TIM_DMABASE_CR2
4594 * @arg TIM_DMABASE_SMCR
4595 * @arg TIM_DMABASE_DIER
4596 * @arg TIM_DMABASE_SR
4597 * @arg TIM_DMABASE_EGR
4598 * @arg TIM_DMABASE_CCMR1
4599 * @arg TIM_DMABASE_CCMR2
4600 * @arg TIM_DMABASE_CCER
4601 * @arg TIM_DMABASE_CNT
4602 * @arg TIM_DMABASE_PSC
4603 * @arg TIM_DMABASE_ARR
4604 * @arg TIM_DMABASE_CCR1
4605 * @arg TIM_DMABASE_CCR2
4606 * @arg TIM_DMABASE_CCR3
4607 * @arg TIM_DMABASE_CCR4
4608 * @arg TIM_DMABASE_OR
4609 * @param BurstRequestSrc TIM DMA Request sources
4610 * This parameter can be one of the following values:
4611 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4612 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4613 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4614 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4615 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4616 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4617 * @param BurstBuffer The Buffer address.
4618 * @param BurstLength DMA Burst length. This parameter can be one value
4619 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4620 * @param DataLength Data length. This parameter can be one value
4621 * between 1 and 0xFFFF.
4622 * @retval HAL status
4623 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4624 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4625 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4626 uint32_t BurstLength, uint32_t DataLength)
4627 {
4628 HAL_StatusTypeDef status = HAL_OK;
4629
4630 /* Check the parameters */
4631 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4632 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4633 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4634 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4635 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4636
4637 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4638 {
4639 return HAL_BUSY;
4640 }
4641 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4642 {
4643 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4644 {
4645 return HAL_ERROR;
4646 }
4647 else
4648 {
4649 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4650 }
4651 }
4652 else
4653 {
4654 /* nothing to do */
4655 }
4656 switch (BurstRequestSrc)
4657 {
4658 case TIM_DMA_UPDATE:
4659 {
4660 /* Set the DMA Period elapsed callbacks */
4661 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4662 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4663
4664 /* Set the DMA error callback */
4665 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4666
4667 /* Enable the DMA channel */
4668 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4669 DataLength) != HAL_OK)
4670 {
4671 /* Return error status */
4672 return HAL_ERROR;
4673 }
4674 break;
4675 }
4676 case TIM_DMA_CC1:
4677 {
4678 /* Set the DMA capture callbacks */
4679 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4680 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4681
4682 /* Set the DMA error callback */
4683 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4684
4685 /* Enable the DMA channel */
4686 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4687 DataLength) != HAL_OK)
4688 {
4689 /* Return error status */
4690 return HAL_ERROR;
4691 }
4692 break;
4693 }
4694 case TIM_DMA_CC2:
4695 {
4696 /* Set the DMA capture callbacks */
4697 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4698 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4699
4700 /* Set the DMA error callback */
4701 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4702
4703 /* Enable the DMA channel */
4704 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4705 DataLength) != HAL_OK)
4706 {
4707 /* Return error status */
4708 return HAL_ERROR;
4709 }
4710 break;
4711 }
4712 case TIM_DMA_CC3:
4713 {
4714 /* Set the DMA capture callbacks */
4715 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4716 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4717
4718 /* Set the DMA error callback */
4719 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4720
4721 /* Enable the DMA channel */
4722 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4723 DataLength) != HAL_OK)
4724 {
4725 /* Return error status */
4726 return HAL_ERROR;
4727 }
4728 break;
4729 }
4730 case TIM_DMA_CC4:
4731 {
4732 /* Set the DMA capture callbacks */
4733 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4734 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4735
4736 /* Set the DMA error callback */
4737 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4738
4739 /* Enable the DMA channel */
4740 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4741 DataLength) != HAL_OK)
4742 {
4743 /* Return error status */
4744 return HAL_ERROR;
4745 }
4746 break;
4747 }
4748 case TIM_DMA_TRIGGER:
4749 {
4750 /* Set the DMA trigger callbacks */
4751 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4752 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4753
4754 /* Set the DMA error callback */
4755 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4756
4757 /* Enable the DMA channel */
4758 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4759 DataLength) != HAL_OK)
4760 {
4761 /* Return error status */
4762 return HAL_ERROR;
4763 }
4764 break;
4765 }
4766 default:
4767 status = HAL_ERROR;
4768 break;
4769 }
4770
4771 if (status == HAL_OK)
4772 {
4773 /* Configure the DMA Burst Mode */
4774 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4775
4776 /* Enable the TIM DMA Request */
4777 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4778 }
4779
4780 /* Return function status */
4781 return status;
4782 }
4783
4784 /**
4785 * @brief Stop the DMA burst reading
4786 * @param htim TIM handle
4787 * @param BurstRequestSrc TIM DMA Request sources to disable.
4788 * @retval HAL status
4789 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4790 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4791 {
4792 HAL_StatusTypeDef status = HAL_OK;
4793
4794 /* Check the parameters */
4795 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4796
4797 /* Abort the DMA transfer (at least disable the DMA channel) */
4798 switch (BurstRequestSrc)
4799 {
4800 case TIM_DMA_UPDATE:
4801 {
4802 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4803 break;
4804 }
4805 case TIM_DMA_CC1:
4806 {
4807 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4808 break;
4809 }
4810 case TIM_DMA_CC2:
4811 {
4812 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4813 break;
4814 }
4815 case TIM_DMA_CC3:
4816 {
4817 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4818 break;
4819 }
4820 case TIM_DMA_CC4:
4821 {
4822 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4823 break;
4824 }
4825 case TIM_DMA_TRIGGER:
4826 {
4827 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4828 break;
4829 }
4830 default:
4831 status = HAL_ERROR;
4832 break;
4833 }
4834
4835 if (status == HAL_OK)
4836 {
4837 /* Disable the TIM Update DMA request */
4838 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4839
4840 /* Change the DMA burst operation state */
4841 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4842 }
4843
4844 /* Return function status */
4845 return status;
4846 }
4847
4848 /**
4849 * @brief Generate a software event
4850 * @param htim TIM handle
4851 * @param EventSource specifies the event source.
4852 * This parameter can be one of the following values:
4853 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
4854 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
4855 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
4856 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
4857 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
4858 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
4859 * @note Basic timers can only generate an update event.
4860 * @retval HAL status
4861 */
4862
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)4863 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
4864 {
4865 /* Check the parameters */
4866 assert_param(IS_TIM_INSTANCE(htim->Instance));
4867 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
4868
4869 /* Process Locked */
4870 __HAL_LOCK(htim);
4871
4872 /* Change the TIM state */
4873 htim->State = HAL_TIM_STATE_BUSY;
4874
4875 /* Set the event sources */
4876 htim->Instance->EGR = EventSource;
4877
4878 /* Change the TIM state */
4879 htim->State = HAL_TIM_STATE_READY;
4880
4881 __HAL_UNLOCK(htim);
4882
4883 /* Return function status */
4884 return HAL_OK;
4885 }
4886
4887 /**
4888 * @brief Configures the OCRef clear feature
4889 * @param htim TIM handle
4890 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
4891 * contains the OCREF clear feature and parameters for the TIM peripheral.
4892 * @param Channel specifies the TIM Channel
4893 * This parameter can be one of the following values:
4894 * @arg TIM_CHANNEL_1: TIM Channel 1
4895 * @arg TIM_CHANNEL_2: TIM Channel 2
4896 * @arg TIM_CHANNEL_3: TIM Channel 3
4897 * @arg TIM_CHANNEL_4: TIM Channel 4
4898 * @retval HAL status
4899 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)4900 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
4901 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
4902 uint32_t Channel)
4903 {
4904 HAL_StatusTypeDef status = HAL_OK;
4905
4906 /* Check the parameters */
4907 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
4908 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
4909
4910 /* Process Locked */
4911 __HAL_LOCK(htim);
4912
4913 htim->State = HAL_TIM_STATE_BUSY;
4914
4915 switch (sClearInputConfig->ClearInputSource)
4916 {
4917 case TIM_CLEARINPUTSOURCE_NONE:
4918 {
4919 /* Clear the OCREF clear selection bit and the the ETR Bits */
4920 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
4921 break;
4922 }
4923 case TIM_CLEARINPUTSOURCE_OCREFCLR:
4924 {
4925 /* Clear the OCREF clear selection bit */
4926 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
4927 break;
4928 }
4929
4930 case TIM_CLEARINPUTSOURCE_ETR:
4931 {
4932 /* Check the parameters */
4933 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
4934 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
4935 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
4936
4937 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
4938 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
4939 {
4940 htim->State = HAL_TIM_STATE_READY;
4941 __HAL_UNLOCK(htim);
4942 return HAL_ERROR;
4943 }
4944
4945 TIM_ETR_SetConfig(htim->Instance,
4946 sClearInputConfig->ClearInputPrescaler,
4947 sClearInputConfig->ClearInputPolarity,
4948 sClearInputConfig->ClearInputFilter);
4949
4950 /* Set the OCREF clear selection bit */
4951 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
4952 break;
4953 }
4954
4955 default:
4956 status = HAL_ERROR;
4957 break;
4958 }
4959
4960 if (status == HAL_OK)
4961 {
4962 switch (Channel)
4963 {
4964 case TIM_CHANNEL_1:
4965 {
4966 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4967 {
4968 /* Enable the OCREF clear feature for Channel 1 */
4969 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4970 }
4971 else
4972 {
4973 /* Disable the OCREF clear feature for Channel 1 */
4974 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4975 }
4976 break;
4977 }
4978 case TIM_CHANNEL_2:
4979 {
4980 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4981 {
4982 /* Enable the OCREF clear feature for Channel 2 */
4983 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4984 }
4985 else
4986 {
4987 /* Disable the OCREF clear feature for Channel 2 */
4988 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4989 }
4990 break;
4991 }
4992 case TIM_CHANNEL_3:
4993 {
4994 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4995 {
4996 /* Enable the OCREF clear feature for Channel 3 */
4997 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4998 }
4999 else
5000 {
5001 /* Disable the OCREF clear feature for Channel 3 */
5002 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5003 }
5004 break;
5005 }
5006 case TIM_CHANNEL_4:
5007 {
5008 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5009 {
5010 /* Enable the OCREF clear feature for Channel 4 */
5011 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5012 }
5013 else
5014 {
5015 /* Disable the OCREF clear feature for Channel 4 */
5016 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5017 }
5018 break;
5019 }
5020 default:
5021 break;
5022 }
5023 }
5024
5025 htim->State = HAL_TIM_STATE_READY;
5026
5027 __HAL_UNLOCK(htim);
5028
5029 return status;
5030 }
5031
5032 /**
5033 * @brief Configures the clock source to be used
5034 * @param htim TIM handle
5035 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5036 * contains the clock source information for the TIM peripheral.
5037 * @retval HAL status
5038 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5039 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5040 {
5041 HAL_StatusTypeDef status = HAL_OK;
5042 uint32_t tmpsmcr;
5043
5044 /* Process Locked */
5045 __HAL_LOCK(htim);
5046
5047 htim->State = HAL_TIM_STATE_BUSY;
5048
5049 /* Check the parameters */
5050 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5051
5052 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5053 tmpsmcr = htim->Instance->SMCR;
5054 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5055 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5056 htim->Instance->SMCR = tmpsmcr;
5057
5058 switch (sClockSourceConfig->ClockSource)
5059 {
5060 case TIM_CLOCKSOURCE_INTERNAL:
5061 {
5062 assert_param(IS_TIM_INSTANCE(htim->Instance));
5063 break;
5064 }
5065
5066 case TIM_CLOCKSOURCE_ETRMODE1:
5067 {
5068 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5069 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5070
5071 /* Check ETR input conditioning related parameters */
5072 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5073 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5074 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5075
5076 /* Configure the ETR Clock source */
5077 TIM_ETR_SetConfig(htim->Instance,
5078 sClockSourceConfig->ClockPrescaler,
5079 sClockSourceConfig->ClockPolarity,
5080 sClockSourceConfig->ClockFilter);
5081
5082 /* Select the External clock mode1 and the ETRF trigger */
5083 tmpsmcr = htim->Instance->SMCR;
5084 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5085 /* Write to TIMx SMCR */
5086 htim->Instance->SMCR = tmpsmcr;
5087 break;
5088 }
5089
5090 case TIM_CLOCKSOURCE_ETRMODE2:
5091 {
5092 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5093 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5094
5095 /* Check ETR input conditioning related parameters */
5096 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5097 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5098 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5099
5100 /* Configure the ETR Clock source */
5101 TIM_ETR_SetConfig(htim->Instance,
5102 sClockSourceConfig->ClockPrescaler,
5103 sClockSourceConfig->ClockPolarity,
5104 sClockSourceConfig->ClockFilter);
5105 /* Enable the External clock mode2 */
5106 htim->Instance->SMCR |= TIM_SMCR_ECE;
5107 break;
5108 }
5109
5110 case TIM_CLOCKSOURCE_TI1:
5111 {
5112 /* Check whether or not the timer instance supports external clock mode 1 */
5113 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5114
5115 /* Check TI1 input conditioning related parameters */
5116 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5117 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5118
5119 TIM_TI1_ConfigInputStage(htim->Instance,
5120 sClockSourceConfig->ClockPolarity,
5121 sClockSourceConfig->ClockFilter);
5122 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5123 break;
5124 }
5125
5126 case TIM_CLOCKSOURCE_TI2:
5127 {
5128 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5129 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5130
5131 /* Check TI2 input conditioning related parameters */
5132 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5133 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5134
5135 TIM_TI2_ConfigInputStage(htim->Instance,
5136 sClockSourceConfig->ClockPolarity,
5137 sClockSourceConfig->ClockFilter);
5138 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5139 break;
5140 }
5141
5142 case TIM_CLOCKSOURCE_TI1ED:
5143 {
5144 /* Check whether or not the timer instance supports external clock mode 1 */
5145 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5146
5147 /* Check TI1 input conditioning related parameters */
5148 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5149 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5150
5151 TIM_TI1_ConfigInputStage(htim->Instance,
5152 sClockSourceConfig->ClockPolarity,
5153 sClockSourceConfig->ClockFilter);
5154 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5155 break;
5156 }
5157
5158 case TIM_CLOCKSOURCE_ITR0:
5159 case TIM_CLOCKSOURCE_ITR1:
5160 case TIM_CLOCKSOURCE_ITR2:
5161 case TIM_CLOCKSOURCE_ITR3:
5162 {
5163 /* Check whether or not the timer instance supports internal trigger input */
5164 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5165
5166 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5167 break;
5168 }
5169
5170 default:
5171 status = HAL_ERROR;
5172 break;
5173 }
5174 htim->State = HAL_TIM_STATE_READY;
5175
5176 __HAL_UNLOCK(htim);
5177
5178 return status;
5179 }
5180
5181 /**
5182 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5183 * or a XOR combination between CH1_input, CH2_input & CH3_input
5184 * @param htim TIM handle.
5185 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5186 * output of a XOR gate.
5187 * This parameter can be one of the following values:
5188 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5189 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5190 * pins are connected to the TI1 input (XOR combination)
5191 * @retval HAL status
5192 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5193 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5194 {
5195 uint32_t tmpcr2;
5196
5197 /* Check the parameters */
5198 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5199 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5200
5201 /* Get the TIMx CR2 register value */
5202 tmpcr2 = htim->Instance->CR2;
5203
5204 /* Reset the TI1 selection */
5205 tmpcr2 &= ~TIM_CR2_TI1S;
5206
5207 /* Set the TI1 selection */
5208 tmpcr2 |= TI1_Selection;
5209
5210 /* Write to TIMxCR2 */
5211 htim->Instance->CR2 = tmpcr2;
5212
5213 return HAL_OK;
5214 }
5215
5216 /**
5217 * @brief Configures the TIM in Slave mode
5218 * @param htim TIM handle.
5219 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5220 * contains the selected trigger (internal trigger input, filtered
5221 * timer input or external trigger input) and the Slave mode
5222 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5223 * @retval HAL status
5224 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5225 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5226 {
5227 /* Check the parameters */
5228 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5229 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5230 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5231
5232 __HAL_LOCK(htim);
5233
5234 htim->State = HAL_TIM_STATE_BUSY;
5235
5236 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5237 {
5238 htim->State = HAL_TIM_STATE_READY;
5239 __HAL_UNLOCK(htim);
5240 return HAL_ERROR;
5241 }
5242
5243 /* Disable Trigger Interrupt */
5244 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5245
5246 /* Disable Trigger DMA request */
5247 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5248
5249 htim->State = HAL_TIM_STATE_READY;
5250
5251 __HAL_UNLOCK(htim);
5252
5253 return HAL_OK;
5254 }
5255
5256 /**
5257 * @brief Configures the TIM in Slave mode in interrupt mode
5258 * @param htim TIM handle.
5259 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5260 * contains the selected trigger (internal trigger input, filtered
5261 * timer input or external trigger input) and the Slave mode
5262 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5263 * @retval HAL status
5264 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5265 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5266 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5267 {
5268 /* Check the parameters */
5269 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5270 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5271 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5272
5273 __HAL_LOCK(htim);
5274
5275 htim->State = HAL_TIM_STATE_BUSY;
5276
5277 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5278 {
5279 htim->State = HAL_TIM_STATE_READY;
5280 __HAL_UNLOCK(htim);
5281 return HAL_ERROR;
5282 }
5283
5284 /* Enable Trigger Interrupt */
5285 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5286
5287 /* Disable Trigger DMA request */
5288 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5289
5290 htim->State = HAL_TIM_STATE_READY;
5291
5292 __HAL_UNLOCK(htim);
5293
5294 return HAL_OK;
5295 }
5296
5297 /**
5298 * @brief Read the captured value from Capture Compare unit
5299 * @param htim TIM handle.
5300 * @param Channel TIM Channels to be enabled
5301 * This parameter can be one of the following values:
5302 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5303 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5304 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5305 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5306 * @retval Captured value
5307 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)5308 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5309 {
5310 uint32_t tmpreg = 0U;
5311
5312 switch (Channel)
5313 {
5314 case TIM_CHANNEL_1:
5315 {
5316 /* Check the parameters */
5317 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5318
5319 /* Return the capture 1 value */
5320 tmpreg = htim->Instance->CCR1;
5321
5322 break;
5323 }
5324 case TIM_CHANNEL_2:
5325 {
5326 /* Check the parameters */
5327 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5328
5329 /* Return the capture 2 value */
5330 tmpreg = htim->Instance->CCR2;
5331
5332 break;
5333 }
5334
5335 case TIM_CHANNEL_3:
5336 {
5337 /* Check the parameters */
5338 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5339
5340 /* Return the capture 3 value */
5341 tmpreg = htim->Instance->CCR3;
5342
5343 break;
5344 }
5345
5346 case TIM_CHANNEL_4:
5347 {
5348 /* Check the parameters */
5349 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5350
5351 /* Return the capture 4 value */
5352 tmpreg = htim->Instance->CCR4;
5353
5354 break;
5355 }
5356
5357 default:
5358 break;
5359 }
5360
5361 return tmpreg;
5362 }
5363
5364 /**
5365 * @}
5366 */
5367
5368 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5369 * @brief TIM Callbacks functions
5370 *
5371 @verbatim
5372 ==============================================================================
5373 ##### TIM Callbacks functions #####
5374 ==============================================================================
5375 [..]
5376 This section provides TIM callback functions:
5377 (+) TIM Period elapsed callback
5378 (+) TIM Output Compare callback
5379 (+) TIM Input capture callback
5380 (+) TIM Trigger callback
5381 (+) TIM Error callback
5382
5383 @endverbatim
5384 * @{
5385 */
5386
5387 /**
5388 * @brief Period elapsed callback in non-blocking mode
5389 * @param htim TIM handle
5390 * @retval None
5391 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5392 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5393 {
5394 /* Prevent unused argument(s) compilation warning */
5395 UNUSED(htim);
5396
5397 /* NOTE : This function should not be modified, when the callback is needed,
5398 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5399 */
5400 }
5401
5402 /**
5403 * @brief Period elapsed half complete callback in non-blocking mode
5404 * @param htim TIM handle
5405 * @retval None
5406 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5407 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5408 {
5409 /* Prevent unused argument(s) compilation warning */
5410 UNUSED(htim);
5411
5412 /* NOTE : This function should not be modified, when the callback is needed,
5413 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5414 */
5415 }
5416
5417 /**
5418 * @brief Output Compare callback in non-blocking mode
5419 * @param htim TIM OC handle
5420 * @retval None
5421 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5422 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5423 {
5424 /* Prevent unused argument(s) compilation warning */
5425 UNUSED(htim);
5426
5427 /* NOTE : This function should not be modified, when the callback is needed,
5428 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5429 */
5430 }
5431
5432 /**
5433 * @brief Input Capture callback in non-blocking mode
5434 * @param htim TIM IC handle
5435 * @retval None
5436 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5437 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5438 {
5439 /* Prevent unused argument(s) compilation warning */
5440 UNUSED(htim);
5441
5442 /* NOTE : This function should not be modified, when the callback is needed,
5443 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5444 */
5445 }
5446
5447 /**
5448 * @brief Input Capture half complete callback in non-blocking mode
5449 * @param htim TIM IC handle
5450 * @retval None
5451 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5452 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5453 {
5454 /* Prevent unused argument(s) compilation warning */
5455 UNUSED(htim);
5456
5457 /* NOTE : This function should not be modified, when the callback is needed,
5458 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5459 */
5460 }
5461
5462 /**
5463 * @brief PWM Pulse finished callback in non-blocking mode
5464 * @param htim TIM handle
5465 * @retval None
5466 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5467 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5468 {
5469 /* Prevent unused argument(s) compilation warning */
5470 UNUSED(htim);
5471
5472 /* NOTE : This function should not be modified, when the callback is needed,
5473 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5474 */
5475 }
5476
5477 /**
5478 * @brief PWM Pulse finished half complete callback in non-blocking mode
5479 * @param htim TIM handle
5480 * @retval None
5481 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5482 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5483 {
5484 /* Prevent unused argument(s) compilation warning */
5485 UNUSED(htim);
5486
5487 /* NOTE : This function should not be modified, when the callback is needed,
5488 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5489 */
5490 }
5491
5492 /**
5493 * @brief Hall Trigger detection callback in non-blocking mode
5494 * @param htim TIM handle
5495 * @retval None
5496 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5497 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5498 {
5499 /* Prevent unused argument(s) compilation warning */
5500 UNUSED(htim);
5501
5502 /* NOTE : This function should not be modified, when the callback is needed,
5503 the HAL_TIM_TriggerCallback could be implemented in the user file
5504 */
5505 }
5506
5507 /**
5508 * @brief Hall Trigger detection half complete callback in non-blocking mode
5509 * @param htim TIM handle
5510 * @retval None
5511 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5512 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5513 {
5514 /* Prevent unused argument(s) compilation warning */
5515 UNUSED(htim);
5516
5517 /* NOTE : This function should not be modified, when the callback is needed,
5518 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5519 */
5520 }
5521
5522 /**
5523 * @brief Timer error callback in non-blocking mode
5524 * @param htim TIM handle
5525 * @retval None
5526 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5527 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5528 {
5529 /* Prevent unused argument(s) compilation warning */
5530 UNUSED(htim);
5531
5532 /* NOTE : This function should not be modified, when the callback is needed,
5533 the HAL_TIM_ErrorCallback could be implemented in the user file
5534 */
5535 }
5536
5537 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5538 /**
5539 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5540 * @param htim tim handle
5541 * @param CallbackID ID of the callback to be registered
5542 * This parameter can be one of the following values:
5543 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5544 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5545 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5546 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5547 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5548 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5549 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5550 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5551 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5552 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5553 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5554 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5555 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5556 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5557 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5558 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5559 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5560 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5561 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5562 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5563 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5564 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5565 * @param pCallback pointer to the callback function
5566 * @retval status
5567 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5568 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5569 pTIM_CallbackTypeDef pCallback)
5570 {
5571 HAL_StatusTypeDef status = HAL_OK;
5572
5573 if (pCallback == NULL)
5574 {
5575 return HAL_ERROR;
5576 }
5577
5578 if (htim->State == HAL_TIM_STATE_READY)
5579 {
5580 switch (CallbackID)
5581 {
5582 case HAL_TIM_BASE_MSPINIT_CB_ID :
5583 htim->Base_MspInitCallback = pCallback;
5584 break;
5585
5586 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5587 htim->Base_MspDeInitCallback = pCallback;
5588 break;
5589
5590 case HAL_TIM_IC_MSPINIT_CB_ID :
5591 htim->IC_MspInitCallback = pCallback;
5592 break;
5593
5594 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5595 htim->IC_MspDeInitCallback = pCallback;
5596 break;
5597
5598 case HAL_TIM_OC_MSPINIT_CB_ID :
5599 htim->OC_MspInitCallback = pCallback;
5600 break;
5601
5602 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5603 htim->OC_MspDeInitCallback = pCallback;
5604 break;
5605
5606 case HAL_TIM_PWM_MSPINIT_CB_ID :
5607 htim->PWM_MspInitCallback = pCallback;
5608 break;
5609
5610 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5611 htim->PWM_MspDeInitCallback = pCallback;
5612 break;
5613
5614 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5615 htim->OnePulse_MspInitCallback = pCallback;
5616 break;
5617
5618 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5619 htim->OnePulse_MspDeInitCallback = pCallback;
5620 break;
5621
5622 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5623 htim->Encoder_MspInitCallback = pCallback;
5624 break;
5625
5626 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5627 htim->Encoder_MspDeInitCallback = pCallback;
5628 break;
5629
5630 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5631 htim->PeriodElapsedCallback = pCallback;
5632 break;
5633
5634 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5635 htim->PeriodElapsedHalfCpltCallback = pCallback;
5636 break;
5637
5638 case HAL_TIM_TRIGGER_CB_ID :
5639 htim->TriggerCallback = pCallback;
5640 break;
5641
5642 case HAL_TIM_TRIGGER_HALF_CB_ID :
5643 htim->TriggerHalfCpltCallback = pCallback;
5644 break;
5645
5646 case HAL_TIM_IC_CAPTURE_CB_ID :
5647 htim->IC_CaptureCallback = pCallback;
5648 break;
5649
5650 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5651 htim->IC_CaptureHalfCpltCallback = pCallback;
5652 break;
5653
5654 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5655 htim->OC_DelayElapsedCallback = pCallback;
5656 break;
5657
5658 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5659 htim->PWM_PulseFinishedCallback = pCallback;
5660 break;
5661
5662 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5663 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5664 break;
5665
5666 case HAL_TIM_ERROR_CB_ID :
5667 htim->ErrorCallback = pCallback;
5668 break;
5669
5670 default :
5671 /* Return error status */
5672 status = HAL_ERROR;
5673 break;
5674 }
5675 }
5676 else if (htim->State == HAL_TIM_STATE_RESET)
5677 {
5678 switch (CallbackID)
5679 {
5680 case HAL_TIM_BASE_MSPINIT_CB_ID :
5681 htim->Base_MspInitCallback = pCallback;
5682 break;
5683
5684 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5685 htim->Base_MspDeInitCallback = pCallback;
5686 break;
5687
5688 case HAL_TIM_IC_MSPINIT_CB_ID :
5689 htim->IC_MspInitCallback = pCallback;
5690 break;
5691
5692 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5693 htim->IC_MspDeInitCallback = pCallback;
5694 break;
5695
5696 case HAL_TIM_OC_MSPINIT_CB_ID :
5697 htim->OC_MspInitCallback = pCallback;
5698 break;
5699
5700 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5701 htim->OC_MspDeInitCallback = pCallback;
5702 break;
5703
5704 case HAL_TIM_PWM_MSPINIT_CB_ID :
5705 htim->PWM_MspInitCallback = pCallback;
5706 break;
5707
5708 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5709 htim->PWM_MspDeInitCallback = pCallback;
5710 break;
5711
5712 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5713 htim->OnePulse_MspInitCallback = pCallback;
5714 break;
5715
5716 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5717 htim->OnePulse_MspDeInitCallback = pCallback;
5718 break;
5719
5720 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5721 htim->Encoder_MspInitCallback = pCallback;
5722 break;
5723
5724 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5725 htim->Encoder_MspDeInitCallback = pCallback;
5726 break;
5727
5728 default :
5729 /* Return error status */
5730 status = HAL_ERROR;
5731 break;
5732 }
5733 }
5734 else
5735 {
5736 /* Return error status */
5737 status = HAL_ERROR;
5738 }
5739
5740 return status;
5741 }
5742
5743 /**
5744 * @brief Unregister a TIM callback
5745 * TIM callback is redirected to the weak predefined callback
5746 * @param htim tim handle
5747 * @param CallbackID ID of the callback to be unregistered
5748 * This parameter can be one of the following values:
5749 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5750 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5751 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5752 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5753 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5754 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5755 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5756 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5757 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5758 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5759 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5760 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5761 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5762 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5763 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5764 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5765 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5766 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5767 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5768 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5769 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5770 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5771 * @retval status
5772 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)5773 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
5774 {
5775 HAL_StatusTypeDef status = HAL_OK;
5776
5777 if (htim->State == HAL_TIM_STATE_READY)
5778 {
5779 switch (CallbackID)
5780 {
5781 case HAL_TIM_BASE_MSPINIT_CB_ID :
5782 /* Legacy weak Base MspInit Callback */
5783 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
5784 break;
5785
5786 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5787 /* Legacy weak Base Msp DeInit Callback */
5788 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
5789 break;
5790
5791 case HAL_TIM_IC_MSPINIT_CB_ID :
5792 /* Legacy weak IC Msp Init Callback */
5793 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
5794 break;
5795
5796 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5797 /* Legacy weak IC Msp DeInit Callback */
5798 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
5799 break;
5800
5801 case HAL_TIM_OC_MSPINIT_CB_ID :
5802 /* Legacy weak OC Msp Init Callback */
5803 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
5804 break;
5805
5806 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5807 /* Legacy weak OC Msp DeInit Callback */
5808 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
5809 break;
5810
5811 case HAL_TIM_PWM_MSPINIT_CB_ID :
5812 /* Legacy weak PWM Msp Init Callback */
5813 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
5814 break;
5815
5816 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5817 /* Legacy weak PWM Msp DeInit Callback */
5818 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
5819 break;
5820
5821 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5822 /* Legacy weak One Pulse Msp Init Callback */
5823 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
5824 break;
5825
5826 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5827 /* Legacy weak One Pulse Msp DeInit Callback */
5828 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
5829 break;
5830
5831 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5832 /* Legacy weak Encoder Msp Init Callback */
5833 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
5834 break;
5835
5836 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5837 /* Legacy weak Encoder Msp DeInit Callback */
5838 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
5839 break;
5840
5841 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5842 /* Legacy weak Period Elapsed Callback */
5843 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
5844 break;
5845
5846 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5847 /* Legacy weak Period Elapsed half complete Callback */
5848 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
5849 break;
5850
5851 case HAL_TIM_TRIGGER_CB_ID :
5852 /* Legacy weak Trigger Callback */
5853 htim->TriggerCallback = HAL_TIM_TriggerCallback;
5854 break;
5855
5856 case HAL_TIM_TRIGGER_HALF_CB_ID :
5857 /* Legacy weak Trigger half complete Callback */
5858 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
5859 break;
5860
5861 case HAL_TIM_IC_CAPTURE_CB_ID :
5862 /* Legacy weak IC Capture Callback */
5863 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
5864 break;
5865
5866 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5867 /* Legacy weak IC Capture half complete Callback */
5868 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
5869 break;
5870
5871 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5872 /* Legacy weak OC Delay Elapsed Callback */
5873 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
5874 break;
5875
5876 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5877 /* Legacy weak PWM Pulse Finished Callback */
5878 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
5879 break;
5880
5881 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5882 /* Legacy weak PWM Pulse Finished half complete Callback */
5883 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
5884 break;
5885
5886 case HAL_TIM_ERROR_CB_ID :
5887 /* Legacy weak Error Callback */
5888 htim->ErrorCallback = HAL_TIM_ErrorCallback;
5889 break;
5890
5891 default :
5892 /* Return error status */
5893 status = HAL_ERROR;
5894 break;
5895 }
5896 }
5897 else if (htim->State == HAL_TIM_STATE_RESET)
5898 {
5899 switch (CallbackID)
5900 {
5901 case HAL_TIM_BASE_MSPINIT_CB_ID :
5902 /* Legacy weak Base MspInit Callback */
5903 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
5904 break;
5905
5906 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5907 /* Legacy weak Base Msp DeInit Callback */
5908 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
5909 break;
5910
5911 case HAL_TIM_IC_MSPINIT_CB_ID :
5912 /* Legacy weak IC Msp Init Callback */
5913 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
5914 break;
5915
5916 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5917 /* Legacy weak IC Msp DeInit Callback */
5918 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
5919 break;
5920
5921 case HAL_TIM_OC_MSPINIT_CB_ID :
5922 /* Legacy weak OC Msp Init Callback */
5923 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
5924 break;
5925
5926 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5927 /* Legacy weak OC Msp DeInit Callback */
5928 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
5929 break;
5930
5931 case HAL_TIM_PWM_MSPINIT_CB_ID :
5932 /* Legacy weak PWM Msp Init Callback */
5933 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
5934 break;
5935
5936 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5937 /* Legacy weak PWM Msp DeInit Callback */
5938 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
5939 break;
5940
5941 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5942 /* Legacy weak One Pulse Msp Init Callback */
5943 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
5944 break;
5945
5946 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5947 /* Legacy weak One Pulse Msp DeInit Callback */
5948 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
5949 break;
5950
5951 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5952 /* Legacy weak Encoder Msp Init Callback */
5953 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
5954 break;
5955
5956 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5957 /* Legacy weak Encoder Msp DeInit Callback */
5958 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
5959 break;
5960
5961 default :
5962 /* Return error status */
5963 status = HAL_ERROR;
5964 break;
5965 }
5966 }
5967 else
5968 {
5969 /* Return error status */
5970 status = HAL_ERROR;
5971 }
5972
5973 return status;
5974 }
5975 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5976
5977 /**
5978 * @}
5979 */
5980
5981 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
5982 * @brief TIM Peripheral State functions
5983 *
5984 @verbatim
5985 ==============================================================================
5986 ##### Peripheral State functions #####
5987 ==============================================================================
5988 [..]
5989 This subsection permits to get in run-time the status of the peripheral
5990 and the data flow.
5991
5992 @endverbatim
5993 * @{
5994 */
5995
5996 /**
5997 * @brief Return the TIM Base handle state.
5998 * @param htim TIM Base handle
5999 * @retval HAL state
6000 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6001 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6002 {
6003 return htim->State;
6004 }
6005
6006 /**
6007 * @brief Return the TIM OC handle state.
6008 * @param htim TIM Output Compare handle
6009 * @retval HAL state
6010 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6011 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6012 {
6013 return htim->State;
6014 }
6015
6016 /**
6017 * @brief Return the TIM PWM handle state.
6018 * @param htim TIM handle
6019 * @retval HAL state
6020 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6021 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6022 {
6023 return htim->State;
6024 }
6025
6026 /**
6027 * @brief Return the TIM Input Capture handle state.
6028 * @param htim TIM IC handle
6029 * @retval HAL state
6030 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6031 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6032 {
6033 return htim->State;
6034 }
6035
6036 /**
6037 * @brief Return the TIM One Pulse Mode handle state.
6038 * @param htim TIM OPM handle
6039 * @retval HAL state
6040 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6041 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6042 {
6043 return htim->State;
6044 }
6045
6046 /**
6047 * @brief Return the TIM Encoder Mode handle state.
6048 * @param htim TIM Encoder Interface handle
6049 * @retval HAL state
6050 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6051 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6052 {
6053 return htim->State;
6054 }
6055
6056 /**
6057 * @brief Return the TIM Encoder Mode handle state.
6058 * @param htim TIM handle
6059 * @retval Active channel
6060 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6061 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6062 {
6063 return htim->Channel;
6064 }
6065
6066 /**
6067 * @brief Return actual state of the TIM channel.
6068 * @param htim TIM handle
6069 * @param Channel TIM Channel
6070 * This parameter can be one of the following values:
6071 * @arg TIM_CHANNEL_1: TIM Channel 1
6072 * @arg TIM_CHANNEL_2: TIM Channel 2
6073 * @arg TIM_CHANNEL_3: TIM Channel 3
6074 * @arg TIM_CHANNEL_4: TIM Channel 4
6075 * @arg TIM_CHANNEL_5: TIM Channel 5
6076 * @arg TIM_CHANNEL_6: TIM Channel 6
6077 * @retval TIM Channel state
6078 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6079 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6080 {
6081 HAL_TIM_ChannelStateTypeDef channel_state;
6082
6083 /* Check the parameters */
6084 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6085
6086 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6087
6088 return channel_state;
6089 }
6090
6091 /**
6092 * @brief Return actual state of a DMA burst operation.
6093 * @param htim TIM handle
6094 * @retval DMA burst state
6095 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6096 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6097 {
6098 /* Check the parameters */
6099 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6100
6101 return htim->DMABurstState;
6102 }
6103
6104 /**
6105 * @}
6106 */
6107
6108 /**
6109 * @}
6110 */
6111
6112 /** @defgroup TIM_Private_Functions TIM Private Functions
6113 * @{
6114 */
6115
6116 /**
6117 * @brief TIM DMA error callback
6118 * @param hdma pointer to DMA handle.
6119 * @retval None
6120 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6121 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6122 {
6123 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6124
6125 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6126 {
6127 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6128 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6129 }
6130 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6131 {
6132 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6133 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6134 }
6135 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6136 {
6137 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6138 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6139 }
6140 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6141 {
6142 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6143 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6144 }
6145 else
6146 {
6147 htim->State = HAL_TIM_STATE_READY;
6148 }
6149
6150 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6151 htim->ErrorCallback(htim);
6152 #else
6153 HAL_TIM_ErrorCallback(htim);
6154 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6155
6156 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6157 }
6158
6159 /**
6160 * @brief TIM DMA Delay Pulse complete callback.
6161 * @param hdma pointer to DMA handle.
6162 * @retval None
6163 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6164 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6165 {
6166 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6167
6168 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6169 {
6170 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6171
6172 if (hdma->Init.Mode == DMA_NORMAL)
6173 {
6174 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6175 }
6176 }
6177 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6178 {
6179 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6180
6181 if (hdma->Init.Mode == DMA_NORMAL)
6182 {
6183 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6184 }
6185 }
6186 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6187 {
6188 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6189
6190 if (hdma->Init.Mode == DMA_NORMAL)
6191 {
6192 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6193 }
6194 }
6195 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6196 {
6197 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6198
6199 if (hdma->Init.Mode == DMA_NORMAL)
6200 {
6201 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6202 }
6203 }
6204 else
6205 {
6206 /* nothing to do */
6207 }
6208
6209 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6210 htim->PWM_PulseFinishedCallback(htim);
6211 #else
6212 HAL_TIM_PWM_PulseFinishedCallback(htim);
6213 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6214
6215 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6216 }
6217
6218 /**
6219 * @brief TIM DMA Delay Pulse half complete callback.
6220 * @param hdma pointer to DMA handle.
6221 * @retval None
6222 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6223 static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6224 {
6225 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6226
6227 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6228 {
6229 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6230 }
6231 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6232 {
6233 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6234 }
6235 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6236 {
6237 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6238 }
6239 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6240 {
6241 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6242 }
6243 else
6244 {
6245 /* nothing to do */
6246 }
6247
6248 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6249 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6250 #else
6251 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6252 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6253
6254 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6255 }
6256
6257 /**
6258 * @brief TIM DMA Capture complete callback.
6259 * @param hdma pointer to DMA handle.
6260 * @retval None
6261 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6262 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6263 {
6264 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6265
6266 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6267 {
6268 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6269
6270 if (hdma->Init.Mode == DMA_NORMAL)
6271 {
6272 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6273 }
6274 }
6275 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6276 {
6277 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6278
6279 if (hdma->Init.Mode == DMA_NORMAL)
6280 {
6281 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6282 }
6283 }
6284 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6285 {
6286 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6287
6288 if (hdma->Init.Mode == DMA_NORMAL)
6289 {
6290 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6291 }
6292 }
6293 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6294 {
6295 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6296
6297 if (hdma->Init.Mode == DMA_NORMAL)
6298 {
6299 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6300 }
6301 }
6302 else
6303 {
6304 /* nothing to do */
6305 }
6306
6307 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6308 htim->IC_CaptureCallback(htim);
6309 #else
6310 HAL_TIM_IC_CaptureCallback(htim);
6311 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6312
6313 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6314 }
6315
6316 /**
6317 * @brief TIM DMA Capture half complete callback.
6318 * @param hdma pointer to DMA handle.
6319 * @retval None
6320 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6321 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6322 {
6323 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6324
6325 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6326 {
6327 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6328 }
6329 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6330 {
6331 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6332 }
6333 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6334 {
6335 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6336 }
6337 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6338 {
6339 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6340 }
6341 else
6342 {
6343 /* nothing to do */
6344 }
6345
6346 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6347 htim->IC_CaptureHalfCpltCallback(htim);
6348 #else
6349 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6350 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6351
6352 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6353 }
6354
6355 /**
6356 * @brief TIM DMA Period Elapse complete callback.
6357 * @param hdma pointer to DMA handle.
6358 * @retval None
6359 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6360 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6361 {
6362 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6363
6364 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6365 {
6366 htim->State = HAL_TIM_STATE_READY;
6367 }
6368
6369 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6370 htim->PeriodElapsedCallback(htim);
6371 #else
6372 HAL_TIM_PeriodElapsedCallback(htim);
6373 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6374 }
6375
6376 /**
6377 * @brief TIM DMA Period Elapse half complete callback.
6378 * @param hdma pointer to DMA handle.
6379 * @retval None
6380 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6381 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6382 {
6383 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6384
6385 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6386 htim->PeriodElapsedHalfCpltCallback(htim);
6387 #else
6388 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6389 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6390 }
6391
6392 /**
6393 * @brief TIM DMA Trigger callback.
6394 * @param hdma pointer to DMA handle.
6395 * @retval None
6396 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6397 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6398 {
6399 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6400
6401 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6402 {
6403 htim->State = HAL_TIM_STATE_READY;
6404 }
6405
6406 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6407 htim->TriggerCallback(htim);
6408 #else
6409 HAL_TIM_TriggerCallback(htim);
6410 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6411 }
6412
6413 /**
6414 * @brief TIM DMA Trigger half complete callback.
6415 * @param hdma pointer to DMA handle.
6416 * @retval None
6417 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6418 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6419 {
6420 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6421
6422 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6423 htim->TriggerHalfCpltCallback(htim);
6424 #else
6425 HAL_TIM_TriggerHalfCpltCallback(htim);
6426 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6427 }
6428
6429 /**
6430 * @brief Time Base configuration
6431 * @param TIMx TIM peripheral
6432 * @param Structure TIM Base configuration structure
6433 * @retval None
6434 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)6435 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
6436 {
6437 uint32_t tmpcr1;
6438 tmpcr1 = TIMx->CR1;
6439
6440 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6441 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6442 {
6443 /* Select the Counter Mode */
6444 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6445 tmpcr1 |= Structure->CounterMode;
6446 }
6447
6448 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6449 {
6450 /* Set the clock division */
6451 tmpcr1 &= ~TIM_CR1_CKD;
6452 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6453 }
6454
6455 /* Set the auto-reload preload */
6456 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6457
6458 TIMx->CR1 = tmpcr1;
6459
6460 /* Set the Autoreload value */
6461 TIMx->ARR = (uint32_t)Structure->Period ;
6462
6463 /* Set the Prescaler value */
6464 TIMx->PSC = Structure->Prescaler;
6465
6466 /* Generate an update event to reload the Prescaler
6467 and the repetition counter (only for advanced timer) value immediately */
6468 TIMx->EGR = TIM_EGR_UG;
6469 }
6470
6471 /**
6472 * @brief Timer Output Compare 1 configuration
6473 * @param TIMx to select the TIM peripheral
6474 * @param OC_Config The output configuration structure
6475 * @retval None
6476 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6477 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6478 {
6479 uint32_t tmpccmrx;
6480 uint32_t tmpccer;
6481 uint32_t tmpcr2;
6482
6483 /* Get the TIMx CCER register value */
6484 tmpccer = TIMx->CCER;
6485
6486 /* Disable the Channel 1: Reset the CC1E Bit */
6487 TIMx->CCER &= ~TIM_CCER_CC1E;
6488
6489 /* Get the TIMx CR2 register value */
6490 tmpcr2 = TIMx->CR2;
6491
6492 /* Get the TIMx CCMR1 register value */
6493 tmpccmrx = TIMx->CCMR1;
6494
6495 /* Reset the Output Compare Mode Bits */
6496 tmpccmrx &= ~TIM_CCMR1_OC1M;
6497 tmpccmrx &= ~TIM_CCMR1_CC1S;
6498 /* Select the Output Compare Mode */
6499 tmpccmrx |= OC_Config->OCMode;
6500
6501 /* Reset the Output Polarity level */
6502 tmpccer &= ~TIM_CCER_CC1P;
6503 /* Set the Output Compare Polarity */
6504 tmpccer |= OC_Config->OCPolarity;
6505
6506 /* Write to TIMx CR2 */
6507 TIMx->CR2 = tmpcr2;
6508
6509 /* Write to TIMx CCMR1 */
6510 TIMx->CCMR1 = tmpccmrx;
6511
6512 /* Set the Capture Compare Register value */
6513 TIMx->CCR1 = OC_Config->Pulse;
6514
6515 /* Write to TIMx CCER */
6516 TIMx->CCER = tmpccer;
6517 }
6518
6519 /**
6520 * @brief Timer Output Compare 2 configuration
6521 * @param TIMx to select the TIM peripheral
6522 * @param OC_Config The output configuration structure
6523 * @retval None
6524 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6525 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6526 {
6527 uint32_t tmpccmrx;
6528 uint32_t tmpccer;
6529 uint32_t tmpcr2;
6530
6531 /* Get the TIMx CCER register value */
6532 tmpccer = TIMx->CCER;
6533
6534 /* Disable the Channel 2: Reset the CC2E Bit */
6535 TIMx->CCER &= ~TIM_CCER_CC2E;
6536
6537 /* Get the TIMx CR2 register value */
6538 tmpcr2 = TIMx->CR2;
6539
6540 /* Get the TIMx CCMR1 register value */
6541 tmpccmrx = TIMx->CCMR1;
6542
6543 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6544 tmpccmrx &= ~TIM_CCMR1_OC2M;
6545 tmpccmrx &= ~TIM_CCMR1_CC2S;
6546
6547 /* Select the Output Compare Mode */
6548 tmpccmrx |= (OC_Config->OCMode << 8U);
6549
6550 /* Reset the Output Polarity level */
6551 tmpccer &= ~TIM_CCER_CC2P;
6552 /* Set the Output Compare Polarity */
6553 tmpccer |= (OC_Config->OCPolarity << 4U);
6554
6555 /* Write to TIMx CR2 */
6556 TIMx->CR2 = tmpcr2;
6557
6558 /* Write to TIMx CCMR1 */
6559 TIMx->CCMR1 = tmpccmrx;
6560
6561 /* Set the Capture Compare Register value */
6562 TIMx->CCR2 = OC_Config->Pulse;
6563
6564 /* Write to TIMx CCER */
6565 TIMx->CCER = tmpccer;
6566 }
6567
6568 /**
6569 * @brief Timer Output Compare 3 configuration
6570 * @param TIMx to select the TIM peripheral
6571 * @param OC_Config The output configuration structure
6572 * @retval None
6573 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6574 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6575 {
6576 uint32_t tmpccmrx;
6577 uint32_t tmpccer;
6578 uint32_t tmpcr2;
6579
6580 /* Get the TIMx CCER register value */
6581 tmpccer = TIMx->CCER;
6582
6583 /* Disable the Channel 3: Reset the CC2E Bit */
6584 TIMx->CCER &= ~TIM_CCER_CC3E;
6585
6586 /* Get the TIMx CR2 register value */
6587 tmpcr2 = TIMx->CR2;
6588
6589 /* Get the TIMx CCMR2 register value */
6590 tmpccmrx = TIMx->CCMR2;
6591
6592 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6593 tmpccmrx &= ~TIM_CCMR2_OC3M;
6594 tmpccmrx &= ~TIM_CCMR2_CC3S;
6595 /* Select the Output Compare Mode */
6596 tmpccmrx |= OC_Config->OCMode;
6597
6598 /* Reset the Output Polarity level */
6599 tmpccer &= ~TIM_CCER_CC3P;
6600 /* Set the Output Compare Polarity */
6601 tmpccer |= (OC_Config->OCPolarity << 8U);
6602
6603 /* Write to TIMx CR2 */
6604 TIMx->CR2 = tmpcr2;
6605
6606 /* Write to TIMx CCMR2 */
6607 TIMx->CCMR2 = tmpccmrx;
6608
6609 /* Set the Capture Compare Register value */
6610 TIMx->CCR3 = OC_Config->Pulse;
6611
6612 /* Write to TIMx CCER */
6613 TIMx->CCER = tmpccer;
6614 }
6615
6616 /**
6617 * @brief Timer Output Compare 4 configuration
6618 * @param TIMx to select the TIM peripheral
6619 * @param OC_Config The output configuration structure
6620 * @retval None
6621 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6622 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6623 {
6624 uint32_t tmpccmrx;
6625 uint32_t tmpccer;
6626 uint32_t tmpcr2;
6627
6628 /* Get the TIMx CCER register value */
6629 tmpccer = TIMx->CCER;
6630
6631 /* Disable the Channel 4: Reset the CC4E Bit */
6632 TIMx->CCER &= ~TIM_CCER_CC4E;
6633
6634 /* Get the TIMx CR2 register value */
6635 tmpcr2 = TIMx->CR2;
6636
6637 /* Get the TIMx CCMR2 register value */
6638 tmpccmrx = TIMx->CCMR2;
6639
6640 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6641 tmpccmrx &= ~TIM_CCMR2_OC4M;
6642 tmpccmrx &= ~TIM_CCMR2_CC4S;
6643
6644 /* Select the Output Compare Mode */
6645 tmpccmrx |= (OC_Config->OCMode << 8U);
6646
6647 /* Reset the Output Polarity level */
6648 tmpccer &= ~TIM_CCER_CC4P;
6649 /* Set the Output Compare Polarity */
6650 tmpccer |= (OC_Config->OCPolarity << 12U);
6651
6652 /* Write to TIMx CR2 */
6653 TIMx->CR2 = tmpcr2;
6654
6655 /* Write to TIMx CCMR2 */
6656 TIMx->CCMR2 = tmpccmrx;
6657
6658 /* Set the Capture Compare Register value */
6659 TIMx->CCR4 = OC_Config->Pulse;
6660
6661 /* Write to TIMx CCER */
6662 TIMx->CCER = tmpccer;
6663 }
6664
6665 /**
6666 * @brief Slave Timer configuration function
6667 * @param htim TIM handle
6668 * @param sSlaveConfig Slave timer configuration
6669 * @retval None
6670 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)6671 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
6672 const TIM_SlaveConfigTypeDef *sSlaveConfig)
6673 {
6674 HAL_StatusTypeDef status = HAL_OK;
6675 uint32_t tmpsmcr;
6676 uint32_t tmpccmr1;
6677 uint32_t tmpccer;
6678
6679 /* Get the TIMx SMCR register value */
6680 tmpsmcr = htim->Instance->SMCR;
6681
6682 /* Reset the Trigger Selection Bits */
6683 tmpsmcr &= ~TIM_SMCR_TS;
6684 /* Set the Input Trigger source */
6685 tmpsmcr |= sSlaveConfig->InputTrigger;
6686
6687 /* Reset the slave mode Bits */
6688 tmpsmcr &= ~TIM_SMCR_SMS;
6689 /* Set the slave mode */
6690 tmpsmcr |= sSlaveConfig->SlaveMode;
6691
6692 /* Write to TIMx SMCR */
6693 htim->Instance->SMCR = tmpsmcr;
6694
6695 /* Configure the trigger prescaler, filter, and polarity */
6696 switch (sSlaveConfig->InputTrigger)
6697 {
6698 case TIM_TS_ETRF:
6699 {
6700 /* Check the parameters */
6701 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
6702 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
6703 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6704 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6705 /* Configure the ETR Trigger source */
6706 TIM_ETR_SetConfig(htim->Instance,
6707 sSlaveConfig->TriggerPrescaler,
6708 sSlaveConfig->TriggerPolarity,
6709 sSlaveConfig->TriggerFilter);
6710 break;
6711 }
6712
6713 case TIM_TS_TI1F_ED:
6714 {
6715 /* Check the parameters */
6716 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6717 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6718
6719 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
6720 {
6721 return HAL_ERROR;
6722 }
6723
6724 /* Disable the Channel 1: Reset the CC1E Bit */
6725 tmpccer = htim->Instance->CCER;
6726 htim->Instance->CCER &= ~TIM_CCER_CC1E;
6727 tmpccmr1 = htim->Instance->CCMR1;
6728
6729 /* Set the filter */
6730 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6731 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
6732
6733 /* Write to TIMx CCMR1 and CCER registers */
6734 htim->Instance->CCMR1 = tmpccmr1;
6735 htim->Instance->CCER = tmpccer;
6736 break;
6737 }
6738
6739 case TIM_TS_TI1FP1:
6740 {
6741 /* Check the parameters */
6742 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6743 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6744 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6745
6746 /* Configure TI1 Filter and Polarity */
6747 TIM_TI1_ConfigInputStage(htim->Instance,
6748 sSlaveConfig->TriggerPolarity,
6749 sSlaveConfig->TriggerFilter);
6750 break;
6751 }
6752
6753 case TIM_TS_TI2FP2:
6754 {
6755 /* Check the parameters */
6756 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6757 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6758 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6759
6760 /* Configure TI2 Filter and Polarity */
6761 TIM_TI2_ConfigInputStage(htim->Instance,
6762 sSlaveConfig->TriggerPolarity,
6763 sSlaveConfig->TriggerFilter);
6764 break;
6765 }
6766
6767 case TIM_TS_ITR0:
6768 case TIM_TS_ITR1:
6769 case TIM_TS_ITR2:
6770 case TIM_TS_ITR3:
6771 {
6772 /* Check the parameter */
6773 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6774 break;
6775 }
6776
6777 default:
6778 status = HAL_ERROR;
6779 break;
6780 }
6781
6782 return status;
6783 }
6784
6785 /**
6786 * @brief Configure the TI1 as Input.
6787 * @param TIMx to select the TIM peripheral.
6788 * @param TIM_ICPolarity The Input Polarity.
6789 * This parameter can be one of the following values:
6790 * @arg TIM_ICPOLARITY_RISING
6791 * @arg TIM_ICPOLARITY_FALLING
6792 * @arg TIM_ICPOLARITY_BOTHEDGE
6793 * @param TIM_ICSelection specifies the input to be used.
6794 * This parameter can be one of the following values:
6795 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
6796 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
6797 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
6798 * @param TIM_ICFilter Specifies the Input Capture Filter.
6799 * This parameter must be a value between 0x00 and 0x0F.
6800 * @retval None
6801 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
6802 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
6803 * protected against un-initialized filter and polarity values.
6804 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6805 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6806 uint32_t TIM_ICFilter)
6807 {
6808 uint32_t tmpccmr1;
6809 uint32_t tmpccer;
6810
6811 /* Disable the Channel 1: Reset the CC1E Bit */
6812 tmpccer = TIMx->CCER;
6813 TIMx->CCER &= ~TIM_CCER_CC1E;
6814 tmpccmr1 = TIMx->CCMR1;
6815
6816 /* Select the Input */
6817 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
6818 {
6819 tmpccmr1 &= ~TIM_CCMR1_CC1S;
6820 tmpccmr1 |= TIM_ICSelection;
6821 }
6822 else
6823 {
6824 tmpccmr1 |= TIM_CCMR1_CC1S_0;
6825 }
6826
6827 /* Set the filter */
6828 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6829 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
6830
6831 /* Select the Polarity and set the CC1E Bit */
6832 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6833 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
6834
6835 /* Write to TIMx CCMR1 and CCER registers */
6836 TIMx->CCMR1 = tmpccmr1;
6837 TIMx->CCER = tmpccer;
6838 }
6839
6840 /**
6841 * @brief Configure the Polarity and Filter for TI1.
6842 * @param TIMx to select the TIM peripheral.
6843 * @param TIM_ICPolarity The Input Polarity.
6844 * This parameter can be one of the following values:
6845 * @arg TIM_ICPOLARITY_RISING
6846 * @arg TIM_ICPOLARITY_FALLING
6847 * @arg TIM_ICPOLARITY_BOTHEDGE
6848 * @param TIM_ICFilter Specifies the Input Capture Filter.
6849 * This parameter must be a value between 0x00 and 0x0F.
6850 * @retval None
6851 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6852 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6853 {
6854 uint32_t tmpccmr1;
6855 uint32_t tmpccer;
6856
6857 /* Disable the Channel 1: Reset the CC1E Bit */
6858 tmpccer = TIMx->CCER;
6859 TIMx->CCER &= ~TIM_CCER_CC1E;
6860 tmpccmr1 = TIMx->CCMR1;
6861
6862 /* Set the filter */
6863 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6864 tmpccmr1 |= (TIM_ICFilter << 4U);
6865
6866 /* Select the Polarity and set the CC1E Bit */
6867 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6868 tmpccer |= TIM_ICPolarity;
6869
6870 /* Write to TIMx CCMR1 and CCER registers */
6871 TIMx->CCMR1 = tmpccmr1;
6872 TIMx->CCER = tmpccer;
6873 }
6874
6875 /**
6876 * @brief Configure the TI2 as Input.
6877 * @param TIMx to select the TIM peripheral
6878 * @param TIM_ICPolarity The Input Polarity.
6879 * This parameter can be one of the following values:
6880 * @arg TIM_ICPOLARITY_RISING
6881 * @arg TIM_ICPOLARITY_FALLING
6882 * @arg TIM_ICPOLARITY_BOTHEDGE
6883 * @param TIM_ICSelection specifies the input to be used.
6884 * This parameter can be one of the following values:
6885 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
6886 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
6887 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
6888 * @param TIM_ICFilter Specifies the Input Capture Filter.
6889 * This parameter must be a value between 0x00 and 0x0F.
6890 * @retval None
6891 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
6892 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
6893 * protected against un-initialized filter and polarity values.
6894 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6895 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6896 uint32_t TIM_ICFilter)
6897 {
6898 uint32_t tmpccmr1;
6899 uint32_t tmpccer;
6900
6901 /* Disable the Channel 2: Reset the CC2E Bit */
6902 tmpccer = TIMx->CCER;
6903 TIMx->CCER &= ~TIM_CCER_CC2E;
6904 tmpccmr1 = TIMx->CCMR1;
6905
6906 /* Select the Input */
6907 tmpccmr1 &= ~TIM_CCMR1_CC2S;
6908 tmpccmr1 |= (TIM_ICSelection << 8U);
6909
6910 /* Set the filter */
6911 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6912 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
6913
6914 /* Select the Polarity and set the CC2E Bit */
6915 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6916 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
6917
6918 /* Write to TIMx CCMR1 and CCER registers */
6919 TIMx->CCMR1 = tmpccmr1 ;
6920 TIMx->CCER = tmpccer;
6921 }
6922
6923 /**
6924 * @brief Configure the Polarity and Filter for TI2.
6925 * @param TIMx to select the TIM peripheral.
6926 * @param TIM_ICPolarity The Input Polarity.
6927 * This parameter can be one of the following values:
6928 * @arg TIM_ICPOLARITY_RISING
6929 * @arg TIM_ICPOLARITY_FALLING
6930 * @arg TIM_ICPOLARITY_BOTHEDGE
6931 * @param TIM_ICFilter Specifies the Input Capture Filter.
6932 * This parameter must be a value between 0x00 and 0x0F.
6933 * @retval None
6934 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6935 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6936 {
6937 uint32_t tmpccmr1;
6938 uint32_t tmpccer;
6939
6940 /* Disable the Channel 2: Reset the CC2E Bit */
6941 tmpccer = TIMx->CCER;
6942 TIMx->CCER &= ~TIM_CCER_CC2E;
6943 tmpccmr1 = TIMx->CCMR1;
6944
6945 /* Set the filter */
6946 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6947 tmpccmr1 |= (TIM_ICFilter << 12U);
6948
6949 /* Select the Polarity and set the CC2E Bit */
6950 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6951 tmpccer |= (TIM_ICPolarity << 4U);
6952
6953 /* Write to TIMx CCMR1 and CCER registers */
6954 TIMx->CCMR1 = tmpccmr1 ;
6955 TIMx->CCER = tmpccer;
6956 }
6957
6958 /**
6959 * @brief Configure the TI3 as Input.
6960 * @param TIMx to select the TIM peripheral
6961 * @param TIM_ICPolarity The Input Polarity.
6962 * This parameter can be one of the following values:
6963 * @arg TIM_ICPOLARITY_RISING
6964 * @arg TIM_ICPOLARITY_FALLING
6965 * @arg TIM_ICPOLARITY_BOTHEDGE
6966 * @param TIM_ICSelection specifies the input to be used.
6967 * This parameter can be one of the following values:
6968 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
6969 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
6970 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
6971 * @param TIM_ICFilter Specifies the Input Capture Filter.
6972 * This parameter must be a value between 0x00 and 0x0F.
6973 * @retval None
6974 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
6975 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6976 * protected against un-initialized filter and polarity values.
6977 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6978 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6979 uint32_t TIM_ICFilter)
6980 {
6981 uint32_t tmpccmr2;
6982 uint32_t tmpccer;
6983
6984 /* Disable the Channel 3: Reset the CC3E Bit */
6985 tmpccer = TIMx->CCER;
6986 TIMx->CCER &= ~TIM_CCER_CC3E;
6987 tmpccmr2 = TIMx->CCMR2;
6988
6989 /* Select the Input */
6990 tmpccmr2 &= ~TIM_CCMR2_CC3S;
6991 tmpccmr2 |= TIM_ICSelection;
6992
6993 /* Set the filter */
6994 tmpccmr2 &= ~TIM_CCMR2_IC3F;
6995 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
6996
6997 /* Select the Polarity and set the CC3E Bit */
6998 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
6999 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7000
7001 /* Write to TIMx CCMR2 and CCER registers */
7002 TIMx->CCMR2 = tmpccmr2;
7003 TIMx->CCER = tmpccer;
7004 }
7005
7006 /**
7007 * @brief Configure the TI4 as Input.
7008 * @param TIMx to select the TIM peripheral
7009 * @param TIM_ICPolarity The Input Polarity.
7010 * This parameter can be one of the following values:
7011 * @arg TIM_ICPOLARITY_RISING
7012 * @arg TIM_ICPOLARITY_FALLING
7013 * @arg TIM_ICPOLARITY_BOTHEDGE
7014 * @param TIM_ICSelection specifies the input to be used.
7015 * This parameter can be one of the following values:
7016 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7017 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7018 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7019 * @param TIM_ICFilter Specifies the Input Capture Filter.
7020 * This parameter must be a value between 0x00 and 0x0F.
7021 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7022 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7023 * protected against un-initialized filter and polarity values.
7024 * @retval None
7025 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7026 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7027 uint32_t TIM_ICFilter)
7028 {
7029 uint32_t tmpccmr2;
7030 uint32_t tmpccer;
7031
7032 /* Disable the Channel 4: Reset the CC4E Bit */
7033 tmpccer = TIMx->CCER;
7034 TIMx->CCER &= ~TIM_CCER_CC4E;
7035 tmpccmr2 = TIMx->CCMR2;
7036
7037 /* Select the Input */
7038 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7039 tmpccmr2 |= (TIM_ICSelection << 8U);
7040
7041 /* Set the filter */
7042 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7043 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7044
7045 /* Select the Polarity and set the CC4E Bit */
7046 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7047 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7048
7049 /* Write to TIMx CCMR2 and CCER registers */
7050 TIMx->CCMR2 = tmpccmr2;
7051 TIMx->CCER = tmpccer ;
7052 }
7053
7054 /**
7055 * @brief Selects the Input Trigger source
7056 * @param TIMx to select the TIM peripheral
7057 * @param InputTriggerSource The Input Trigger source.
7058 * This parameter can be one of the following values:
7059 * @arg TIM_TS_ITR0: Internal Trigger 0
7060 * @arg TIM_TS_ITR1: Internal Trigger 1
7061 * @arg TIM_TS_ITR2: Internal Trigger 2
7062 * @arg TIM_TS_ITR3: Internal Trigger 3
7063 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7064 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7065 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7066 * @arg TIM_TS_ETRF: External Trigger input
7067 * @retval None
7068 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7069 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7070 {
7071 uint32_t tmpsmcr;
7072
7073 /* Get the TIMx SMCR register value */
7074 tmpsmcr = TIMx->SMCR;
7075 /* Reset the TS Bits */
7076 tmpsmcr &= ~TIM_SMCR_TS;
7077 /* Set the Input Trigger source and the slave mode*/
7078 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7079 /* Write to TIMx SMCR */
7080 TIMx->SMCR = tmpsmcr;
7081 }
7082 /**
7083 * @brief Configures the TIMx External Trigger (ETR).
7084 * @param TIMx to select the TIM peripheral
7085 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7086 * This parameter can be one of the following values:
7087 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7088 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7089 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7090 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7091 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7092 * This parameter can be one of the following values:
7093 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7094 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7095 * @param ExtTRGFilter External Trigger Filter.
7096 * This parameter must be a value between 0x00 and 0x0F
7097 * @retval None
7098 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7099 static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7100 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7101 {
7102 uint32_t tmpsmcr;
7103
7104 tmpsmcr = TIMx->SMCR;
7105
7106 /* Reset the ETR Bits */
7107 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7108
7109 /* Set the Prescaler, the Filter value and the Polarity */
7110 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7111
7112 /* Write to TIMx SMCR */
7113 TIMx->SMCR = tmpsmcr;
7114 }
7115
7116 /**
7117 * @brief Enables or disables the TIM Capture Compare Channel x.
7118 * @param TIMx to select the TIM peripheral
7119 * @param Channel specifies the TIM Channel
7120 * This parameter can be one of the following values:
7121 * @arg TIM_CHANNEL_1: TIM Channel 1
7122 * @arg TIM_CHANNEL_2: TIM Channel 2
7123 * @arg TIM_CHANNEL_3: TIM Channel 3
7124 * @arg TIM_CHANNEL_4: TIM Channel 4
7125 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7126 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7127 * @retval None
7128 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7129 static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7130 {
7131 uint32_t tmp;
7132
7133 /* Check the parameters */
7134 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7135 assert_param(IS_TIM_CHANNELS(Channel));
7136
7137 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7138
7139 /* Reset the CCxE Bit */
7140 TIMx->CCER &= ~tmp;
7141
7142 /* Set or reset the CCxE Bit */
7143 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7144 }
7145
7146 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7147 /**
7148 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7149 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7150 * the configuration information for TIM module.
7151 * @retval None
7152 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7153 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7154 {
7155 /* Reset the TIM callback to the legacy weak callbacks */
7156 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
7157 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
7158 htim->TriggerCallback = HAL_TIM_TriggerCallback;
7159 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
7160 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
7161 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
7162 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
7163 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
7164 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7165 htim->ErrorCallback = HAL_TIM_ErrorCallback;
7166 }
7167 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7168
7169 /**
7170 * @}
7171 */
7172
7173 #endif /* HAL_TIM_MODULE_ENABLED */
7174 /**
7175 * @}
7176 */
7177
7178 /**
7179 * @}
7180 */
7181
