1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32l0xx_ll_spi.h"
22 #include "stm32l0xx_ll_bus.h"
23 #include "stm32l0xx_ll_rcc.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32L0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (SPI1) || defined (SPI2)
36
37 /** @addtogroup SPI_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
46 * @{
47 */
48 /* SPI registers Masks */
49 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
50 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
51 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
52 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
53 SPI_CR1_BIDIMODE)
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
60 * @{
61 */
62 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
63 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
64 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
66
67 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
68 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
69
70 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
71 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
72
73 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
74 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
75
76 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
77 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
78
79 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
80 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
81 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
82
83 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
84 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
85 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
86 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
87 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
88 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
89 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
90 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
91
92 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
93 || ((__VALUE__) == LL_SPI_MSB_FIRST))
94
95 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
96 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
97
98 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
99
100 /**
101 * @}
102 */
103
104 /* Private function prototypes -----------------------------------------------*/
105
106 /* Exported functions --------------------------------------------------------*/
107 /** @addtogroup SPI_LL_Exported_Functions
108 * @{
109 */
110
111 /** @addtogroup SPI_LL_EF_Init
112 * @{
113 */
114
115 /**
116 * @brief De-initialize the SPI registers to their default reset values.
117 * @param SPIx SPI Instance
118 * @retval An ErrorStatus enumeration value:
119 * - SUCCESS: SPI registers are de-initialized
120 * - ERROR: SPI registers are not de-initialized
121 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)122 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
123 {
124 ErrorStatus status = ERROR;
125
126 /* Check the parameters */
127 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
128
129 #if defined(SPI1)
130 if (SPIx == SPI1)
131 {
132 /* Force reset of SPI clock */
133 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
134
135 /* Release reset of SPI clock */
136 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
137
138 status = SUCCESS;
139 }
140 #endif /* SPI1 */
141 #if defined(SPI2)
142 if (SPIx == SPI2)
143 {
144 /* Force reset of SPI clock */
145 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
146
147 /* Release reset of SPI clock */
148 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
149
150 status = SUCCESS;
151 }
152 #endif /* SPI2 */
153
154 return status;
155 }
156
157 /**
158 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
159 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
160 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
161 * @param SPIx SPI Instance
162 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
163 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
164 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)165 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
166 {
167 ErrorStatus status = ERROR;
168
169 /* Check the SPI Instance SPIx*/
170 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
171
172 /* Check the SPI parameters from SPI_InitStruct*/
173 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
174 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
175 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
176 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
177 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
178 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
179 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
180 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
181 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
182
183 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
184 {
185 /*---------------------------- SPIx CR1 Configuration ------------------------
186 * Configure SPIx CR1 with parameters:
187 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
188 * - Master/Slave Mode: SPI_CR1_MSTR bit
189 * - DataWidth: SPI_CR1_DFF bit
190 * - ClockPolarity: SPI_CR1_CPOL bit
191 * - ClockPhase: SPI_CR1_CPHA bit
192 * - NSS management: SPI_CR1_SSM bit
193 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
194 * - BitOrder: SPI_CR1_LSBFIRST bit
195 * - CRCCalculation: SPI_CR1_CRCEN bit
196 */
197 MODIFY_REG(SPIx->CR1,
198 SPI_CR1_CLEAR_MASK,
199 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
200 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
201 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
202 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
203
204 /*---------------------------- SPIx CR2 Configuration ------------------------
205 * Configure SPIx CR2 with parameters:
206 * - NSS management: SSOE bit
207 */
208 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
209
210 /*---------------------------- SPIx CRCPR Configuration ----------------------
211 * Configure SPIx CRCPR with parameters:
212 * - CRCPoly: CRCPOLY[15:0] bits
213 */
214 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
215 {
216 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
217 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
218 }
219 status = SUCCESS;
220 }
221
222 #if defined (SPI_I2S_SUPPORT)
223 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
224 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
225 #endif /* SPI_I2S_SUPPORT */
226 return status;
227 }
228
229 /**
230 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
231 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
232 * whose fields will be set to default values.
233 * @retval None
234 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)235 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
236 {
237 /* Set SPI_InitStruct fields to default values */
238 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
239 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
240 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
241 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
242 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
243 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
244 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
245 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
246 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
247 SPI_InitStruct->CRCPoly = 7U;
248 }
249
250 /**
251 * @}
252 */
253
254 /**
255 * @}
256 */
257
258 /**
259 * @}
260 */
261
262 #if defined(SPI_I2S_SUPPORT)
263 /** @addtogroup I2S_LL
264 * @{
265 */
266
267 /* Private types -------------------------------------------------------------*/
268 /* Private variables ---------------------------------------------------------*/
269 /* Private constants ---------------------------------------------------------*/
270 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
271 * @{
272 */
273 /* I2S registers Masks */
274 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
275 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
276 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
277
278 #define I2S_I2SPR_CLEAR_MASK 0x0002U
279 /**
280 * @}
281 */
282 /* Private macros ------------------------------------------------------------*/
283 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
284 * @{
285 */
286
287 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
288 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
289 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
290 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
291
292 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
293 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
294
295 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
296 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
297 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
298 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
299 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
300
301 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
302 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
303 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
304 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
305
306 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
307 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
308
309 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
310 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
311 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
312
313 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
314
315 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
316 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
317 /**
318 * @}
319 */
320
321 /* Private function prototypes -----------------------------------------------*/
322
323 /* Exported functions --------------------------------------------------------*/
324 /** @addtogroup I2S_LL_Exported_Functions
325 * @{
326 */
327
328 /** @addtogroup I2S_LL_EF_Init
329 * @{
330 */
331
332 /**
333 * @brief De-initialize the SPI/I2S registers to their default reset values.
334 * @param SPIx SPI Instance
335 * @retval An ErrorStatus enumeration value:
336 * - SUCCESS: SPI registers are de-initialized
337 * - ERROR: SPI registers are not de-initialized
338 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)339 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
340 {
341 return LL_SPI_DeInit(SPIx);
342 }
343
344 /**
345 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
346 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
347 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
348 * @param SPIx SPI Instance
349 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
350 * @retval An ErrorStatus enumeration value:
351 * - SUCCESS: SPI registers are Initialized
352 * - ERROR: SPI registers are not Initialized
353 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)354 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
355 {
356 uint32_t i2sdiv = 2U;
357 uint32_t i2sodd = 0U;
358 uint32_t packetlength = 1U;
359 uint32_t tmp;
360 LL_RCC_ClocksTypeDef rcc_clocks;
361 uint32_t sourceclock;
362 ErrorStatus status = ERROR;
363
364 /* Check the I2S parameters */
365 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
366 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
367 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
368 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
369 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
370 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
371 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
372
373 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
374 {
375 /*---------------------------- SPIx I2SCFGR Configuration --------------------
376 * Configure SPIx I2SCFGR with parameters:
377 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
378 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
379 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
380 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
381 */
382
383 /* Write to SPIx I2SCFGR */
384 MODIFY_REG(SPIx->I2SCFGR,
385 I2S_I2SCFGR_CLEAR_MASK,
386 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
387 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
388 SPI_I2SCFGR_I2SMOD);
389
390 /*---------------------------- SPIx I2SPR Configuration ----------------------
391 * Configure SPIx I2SPR with parameters:
392 * - MCLKOutput: SPI_I2SPR_MCKOE bit
393 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
394 */
395
396 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
397 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
398 */
399 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
400 {
401 /* Check the frame length (For the Prescaler computing)
402 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
403 */
404 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
405 {
406 /* Packet length is 32 bits */
407 packetlength = 2U;
408 }
409
410 /* I2S Clock source is System clock: Get System Clock frequency */
411 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
412
413 /* Get the source clock value: based on System Clock value */
414 sourceclock = rcc_clocks.SYSCLK_Frequency;
415
416 /* Compute the Real divider depending on the MCLK output state with a floating point */
417 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
418 {
419 /* MCLK output is enabled */
420 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
421 }
422 else
423 {
424 /* MCLK output is disabled */
425 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
426 }
427
428 /* Remove the floating point */
429 tmp = tmp / 10U;
430
431 /* Check the parity of the divider */
432 i2sodd = (tmp & (uint16_t)0x0001U);
433
434 /* Compute the i2sdiv prescaler */
435 i2sdiv = ((tmp - i2sodd) / 2U);
436
437 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
438 i2sodd = (i2sodd << 8U);
439 }
440
441 /* Test if the divider is 1 or 0 or greater than 0xFF */
442 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
443 {
444 /* Set the default values */
445 i2sdiv = 2U;
446 i2sodd = 0U;
447 }
448
449 /* Write to SPIx I2SPR register the computed value */
450 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
451
452 status = SUCCESS;
453 }
454 return status;
455 }
456
457 /**
458 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
459 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
460 * whose fields will be set to default values.
461 * @retval None
462 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)463 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
464 {
465 /*--------------- Reset I2S init structure parameters values -----------------*/
466 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
467 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
468 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
469 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
470 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
471 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
472 }
473
474 /**
475 * @brief Set linear and parity prescaler.
476 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
477 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
478 * @param SPIx SPI Instance
479 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
480 * @param PrescalerParity This parameter can be one of the following values:
481 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
482 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
483 * @retval None
484 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)485 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
486 {
487 /* Check the I2S parameters */
488 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
489 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
490 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
491
492 /* Write to SPIx I2SPR */
493 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
494 }
495
496 /**
497 * @}
498 */
499
500 /**
501 * @}
502 */
503
504 /**
505 * @}
506 */
507 #endif /* SPI_I2S_SUPPORT */
508
509 #endif /* defined (SPI1) || defined (SPI2) */
510
511 /**
512 * @}
513 */
514
515 #endif /* USE_FULL_LL_DRIVER */
516
517
