1 /**
2 ******************************************************************************
3 * @file stm32l0xx_hal_cryp.c
4 * @author MCD Application Team
5 * @brief CRYP HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Cryptography (CRYP) peripheral:
9 * + Initialization and de-initialization functions
10 * + Processing functions by algorithm using polling mode
11 * + Processing functions by algorithm using interrupt mode
12 * + Processing functions by algorithm using DMA mode
13 * + Peripheral State functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 The CRYP HAL driver can be used as follows:
21
22 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
23 (##) Enable the CRYP interface clock using __HAL_RCC_AES_CLK_ENABLE()
24 (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
25 (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
26 (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
27 (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
28 (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
29 (+) Enable the DMA1 interface clock using
30 (++) __HAL_RCC_DMA1_CLK_ENABLE()
31 (+) Configure and enable two DMA Channels one for managing data transfer from
32 memory to peripheral (input channel) and another channel for managing data
33 transfer from peripheral to memory (output channel)
34 (+) Associate the initialized DMA handle to the CRYP DMA handle
35 using __HAL_LINKDMA()
36 (+) Configure the priority and enable the NVIC for the transfer complete
37 interrupt on the two DMA Streams. The output stream should have higher
38 priority than the input stream.
39 (++) HAL_NVIC_SetPriority()
40 (++) HAL_NVIC_EnableIRQ()
41
42 (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
43 (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
44 (##) The encryption/decryption key.
45 (##) The initialization vector (counter). It is not used ECB mode.
46
47 (#)Three processing (encryption/decryption) functions are available:
48 (##) Polling mode: encryption and decryption APIs are blocking functions
49 i.e. they process the data and wait till the processing is finished
50 e.g. HAL_CRYP_AESCBC_Encrypt()
51 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
52 i.e. they process the data under interrupt
53 e.g. HAL_CRYP_AESCBC_Encrypt_IT()
54 (##) DMA mode: encryption and decryption APIs are not blocking functions
55 i.e. the data transfer is ensured by DMA
56 e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
57
58 (#)When the processing function is called for the first time after HAL_CRYP_Init()
59 the CRYP peripheral is initialized and processes the buffer in input.
60 At second call, the processing function performs an append of the already
61 processed buffer.
62 When a new data block is to be processed, call HAL_CRYP_Init() then the
63 processing function.
64
65 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
66
67 @endverbatim
68 ******************************************************************************
69 * @attention
70 *
71 * Copyright (c) 2016 STMicroelectronics.
72 * All rights reserved.
73 *
74 * This software is licensed under terms that can be found in the LICENSE file
75 * in the root directory of this software component.
76 * If no LICENSE file comes with this software, it is provided AS-IS.
77 *
78 ******************************************************************************
79 */
80
81 #if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
82 /* Includes ------------------------------------------------------------------*/
83 #include "stm32l0xx_hal.h"
84
85 #ifdef HAL_CRYP_MODULE_ENABLED
86 /** @addtogroup STM32L0xx_HAL_Driver
87 * @{
88 */
89
90 /** @addtogroup CRYP
91 * @brief CRYP HAL module driver.
92 * @{
93 */
94
95
96 /* Private typedef -----------------------------------------------------------*/
97 /* Private define ------------------------------------------------------------*/
98
99 /** @addtogroup CRYP_Private CRYP Private
100 * @{
101 */
102
103 #define CRYP_ALGO_CHAIN_MASK (AES_CR_MODE | AES_CR_CHMOD)
104
105 /**
106 * @}
107 */
108
109 /* Private macro -------------------------------------------------------------*/
110 /* Private variables ---------------------------------------------------------*/
111 /* Private function prototypes -----------------------------------------------*/
112
113 /** @addtogroup CRYP_Private
114 * @{
115 */
116
117 static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp);
118 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
119 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key);
120 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
121 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
122 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
123 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
124 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
125
126 /**
127 * @}
128 */
129
130 /* Private functions ---------------------------------------------------------*/
131
132 /** @addtogroup CRYP_Exported_Functions
133 * @{
134 */
135
136 /** @addtogroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
137 * @brief Initialization and Configuration functions.
138 *
139 @verbatim
140 ==============================================================================
141 ##### Initialization and de-initialization functions #####
142 ==============================================================================
143 [..] This section provides functions allowing to:
144 (+) Initialize the CRYP according to the specified parameters
145 in the CRYP_InitTypeDef and creates the associated handle
146 (+) DeInitialize the CRYP peripheral
147 (+) Initialize the CRYP MSP
148 (+) DeInitialize CRYP MSP
149
150 @endverbatim
151 * @{
152 */
153
154 /**
155 * @brief Initializes the CRYP according to the specified
156 * parameters in the CRYP_InitTypeDef and creates the associated handle.
157 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
158 * the configuration information for CRYP module
159 * @retval HAL status
160 */
HAL_CRYP_Init(CRYP_HandleTypeDef * hcryp)161 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
162 {
163 /* Check the CRYP handle allocation */
164 if(hcryp == NULL)
165 {
166 return HAL_ERROR;
167 }
168
169 /* Check the parameters */
170 assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));
171 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
172
173 if(hcryp->State == HAL_CRYP_STATE_RESET)
174 {
175 /* Allocate lock resource and initialize it */
176 hcryp->Lock = HAL_UNLOCKED;
177
178 /* Init the low level hardware */
179 HAL_CRYP_MspInit(hcryp);
180 }
181
182 /* Check if AES already enabled */
183 if (HAL_IS_BIT_CLR(hcryp->Instance->CR, AES_CR_EN))
184 {
185 /* Change the CRYP state */
186 hcryp->State = HAL_CRYP_STATE_BUSY;
187
188 /* Set the data type*/
189 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
190
191 /* Reset CrypInCount and CrypOutCount */
192 hcryp->CrypInCount = 0U;
193 hcryp->CrypOutCount = 0U;
194
195 /* Change the CRYP state */
196 hcryp->State = HAL_CRYP_STATE_READY;
197
198 /* Set the default CRYP phase */
199 hcryp->Phase = HAL_CRYP_PHASE_READY;
200
201 /* Return function status */
202 return HAL_OK;
203 }
204 else
205 {
206 /* The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is */
207 /* enabled is forbidden to avoid unpredictable AES behavior.*/
208
209 /* Return function status */
210 return HAL_ERROR;
211 }
212
213 }
214
215 /**
216 * @brief DeInitializes the CRYP peripheral.
217 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
218 * the configuration information for CRYP module
219 * @retval HAL status
220 */
HAL_CRYP_DeInit(CRYP_HandleTypeDef * hcryp)221 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
222 {
223 /* Check the CRYP handle allocation */
224 if(hcryp == NULL)
225 {
226 return HAL_ERROR;
227 }
228
229 /* Change the CRYP state */
230 hcryp->State = HAL_CRYP_STATE_BUSY;
231
232 /* Set the default CRYP phase */
233 hcryp->Phase = HAL_CRYP_PHASE_READY;
234
235 /* Reset CrypInCount and CrypOutCount */
236 hcryp->CrypInCount = 0U;
237 hcryp->CrypOutCount = 0U;
238
239 /* Disable the CRYP Peripheral Clock */
240 __HAL_CRYP_DISABLE(hcryp);
241
242 /* DeInit the low level hardware: CLOCK, NVIC.*/
243 HAL_CRYP_MspDeInit(hcryp);
244
245 /* Change the CRYP state */
246 hcryp->State = HAL_CRYP_STATE_RESET;
247
248 /* Release Lock */
249 __HAL_UNLOCK(hcryp);
250
251 /* Return function status */
252 return HAL_OK;
253 }
254
255 /**
256 * @brief Initializes the CRYP MSP.
257 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
258 * the configuration information for CRYP module
259 * @retval None
260 */
HAL_CRYP_MspInit(CRYP_HandleTypeDef * hcryp)261 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
262 {
263 /* Prevent unused argument(s) compilation warning */
264 UNUSED(hcryp);
265
266 /* NOTE : This function should not be modified; when the callback is needed,
267 the HAL_CRYP_MspInit can be implemented in the user file */
268 }
269
270 /**
271 * @brief DeInitializes CRYP MSP.
272 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
273 * the configuration information for CRYP module
274 * @retval None
275 */
HAL_CRYP_MspDeInit(CRYP_HandleTypeDef * hcryp)276 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
277 {
278 /* Prevent unused argument(s) compilation warning */
279 UNUSED(hcryp);
280
281 /* NOTE : This function should not be modified; when the callback is needed,
282 the HAL_CRYP_MspDeInit can be implemented in the user file */
283 }
284
285 /**
286 * @}
287 */
288
289 /** @addtogroup CRYP_Exported_Functions_Group2
290 * @brief processing functions.
291 *
292 @verbatim
293 ==============================================================================
294 ##### AES processing functions #####
295 ==============================================================================
296 [..] This section provides functions allowing to:
297 (+) Encrypt plaintext using AES algorithm in different chaining modes
298 (+) Decrypt ciphertext using AES algorithm in different chaining modes
299 [..] Three processing functions are available:
300 (+) Polling mode
301 (+) Interrupt mode
302 (+) DMA mode
303
304 @endverbatim
305 * @{
306 */
307
308 /**
309 * @brief Initializes the CRYP peripheral in AES ECB encryption mode
310 * then encrypt pPlainData. The cypher data are available in pCypherData
311 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
312 * the configuration information for CRYP module
313 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
314 * @param Size Length of the plaintext buffer, must be a multiple of 16.
315 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
316 * @param Timeout Specify Timeout value
317 * @retval HAL status
318 */
HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData,uint32_t Timeout)319 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
320 {
321 /* Process Locked */
322 __HAL_LOCK(hcryp);
323
324 /* Check that data aligned on u32 and Size multiple of 16*/
325 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
326 {
327 /* Process Locked */
328 __HAL_UNLOCK(hcryp);
329
330 /* Return function status */
331 return HAL_ERROR;
332 }
333
334 /* Check if HAL_CRYP_Init has been called */
335 if(hcryp->State != HAL_CRYP_STATE_RESET)
336 {
337 /* Change the CRYP state */
338 hcryp->State = HAL_CRYP_STATE_BUSY;
339
340 /* Check if initialization phase has already been performed */
341 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
342 {
343 /* Set the key */
344 CRYP_SetKey(hcryp, hcryp->Init.pKey);
345
346 /* Reset the CHMOD & MODE bits */
347 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
348
349 /* Set the CRYP peripheral in AES ECB mode */
350 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
351
352 /* Enable CRYP */
353 __HAL_CRYP_ENABLE(hcryp);
354
355 /* Set the phase */
356 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
357 }
358
359 /* Write Plain Data and Get Cypher Data */
360 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
361 {
362 return HAL_TIMEOUT;
363 }
364
365 /* Change the CRYP state */
366 hcryp->State = HAL_CRYP_STATE_READY;
367
368 /* Process Unlocked */
369 __HAL_UNLOCK(hcryp);
370
371 /* Return function status */
372 return HAL_OK;
373 }
374 else
375 {
376 /* Process Locked */
377 __HAL_UNLOCK(hcryp);
378
379 /* Return function status */
380 return HAL_ERROR;
381 }
382 }
383
384 /**
385 * @brief Initializes the CRYP peripheral in AES CBC encryption mode
386 * then encrypt pPlainData. The cypher data are available in pCypherData
387 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
388 * the configuration information for CRYP module
389 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
390 * @param Size Length of the plaintext buffer, must be a multiple of 16.
391 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
392 * @param Timeout Specify Timeout value
393 * @retval HAL status
394 */
HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData,uint32_t Timeout)395 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
396 {
397 /* Process Locked */
398 __HAL_LOCK(hcryp);
399
400 /* Check that data aligned on u32 */
401 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
402 {
403 /* Process Locked */
404 __HAL_UNLOCK(hcryp);
405
406 /* Return function status */
407 return HAL_ERROR;
408 }
409
410 /* Check if HAL_CRYP_Init has been called */
411 if(hcryp->State != HAL_CRYP_STATE_RESET)
412 {
413 /* Change the CRYP state */
414 hcryp->State = HAL_CRYP_STATE_BUSY;
415
416 /* Check if initialization phase has already been performed */
417 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
418 {
419 /* Set the key */
420 CRYP_SetKey(hcryp, hcryp->Init.pKey);
421
422 /* Reset the CHMOD & MODE bits */
423 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
424
425 /* Set the CRYP peripheral in AES CBC mode */
426 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
427
428 /* Set the Initialization Vector */
429 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
430
431 /* Enable CRYP */
432 __HAL_CRYP_ENABLE(hcryp);
433
434 /* Set the phase */
435 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
436 }
437
438 /* Write Plain Data and Get Cypher Data */
439 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
440 {
441 return HAL_TIMEOUT;
442 }
443
444 /* Change the CRYP state */
445 hcryp->State = HAL_CRYP_STATE_READY;
446
447 /* Process Unlocked */
448 __HAL_UNLOCK(hcryp);
449
450 /* Return function status */
451 return HAL_OK;
452 }
453 else
454 {
455 /* Process Locked */
456 __HAL_UNLOCK(hcryp);
457
458 /* Return function status */
459 return HAL_ERROR;
460 }
461 }
462
463 /**
464 * @brief Initializes the CRYP peripheral in AES CTR encryption mode
465 * then encrypt pPlainData. The cypher data are available in pCypherData
466 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
467 * the configuration information for CRYP module
468 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
469 * @param Size Length of the plaintext buffer, must be a multiple of 16.
470 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
471 * @param Timeout Specify Timeout value
472 * @retval HAL status
473 */
HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData,uint32_t Timeout)474 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
475 {
476 /* Process Locked */
477 __HAL_LOCK(hcryp);
478
479 /* Check that data aligned on u32 */
480 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
481 {
482 /* Process Locked */
483 __HAL_UNLOCK(hcryp);
484
485 /* Return function status */
486 return HAL_ERROR;
487 }
488
489 /* Check if HAL_CRYP_Init has been called */
490 if(hcryp->State != HAL_CRYP_STATE_RESET)
491 {
492 /* Change the CRYP state */
493 hcryp->State = HAL_CRYP_STATE_BUSY;
494
495 /* Check if initialization phase has already been performed */
496 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
497 {
498 /* Set the key */
499 CRYP_SetKey(hcryp, hcryp->Init.pKey);
500
501 /* Reset the CHMOD & MODE bits */
502 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
503
504 /* Set the CRYP peripheral in AES CTR mode */
505 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
506
507 /* Set the Initialization Vector */
508 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
509
510 /* Enable CRYP */
511 __HAL_CRYP_ENABLE(hcryp);
512
513 /* Set the phase */
514 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
515 }
516
517 /* Write Plain Data and Get Cypher Data */
518 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
519 {
520 return HAL_TIMEOUT;
521 }
522
523 /* Change the CRYP state */
524 hcryp->State = HAL_CRYP_STATE_READY;
525
526 /* Process Unlocked */
527 __HAL_UNLOCK(hcryp);
528
529 /* Return function status */
530 return HAL_OK;
531 }
532 else
533 {
534 /* Release Lock */
535 __HAL_UNLOCK(hcryp);
536
537 /* Return function status */
538 return HAL_ERROR;
539 }
540 }
541
542 /**
543 * @brief Initializes the CRYP peripheral in AES ECB decryption mode
544 * then decrypted pCypherData. The cypher data are available in pPlainData
545 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
546 * the configuration information for CRYP module
547 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
548 * @param Size Length of the plaintext buffer, must be a multiple of 16.
549 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
550 * @param Timeout Specify Timeout value
551 * @retval HAL status
552 */
HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData,uint32_t Timeout)553 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
554 {
555 /* Process Locked */
556 __HAL_LOCK(hcryp);
557
558 /* Check that data aligned on u32 */
559 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
560 {
561 /* Process Locked */
562 __HAL_UNLOCK(hcryp);
563
564 /* Return function status */
565 return HAL_ERROR;
566 }
567
568 /* Check if HAL_CRYP_Init has been called */
569 if(hcryp->State != HAL_CRYP_STATE_RESET)
570 {
571 /* Change the CRYP state */
572 hcryp->State = HAL_CRYP_STATE_BUSY;
573
574 /* Check if initialization phase has already been performed */
575 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
576 {
577 /* Set the key */
578 CRYP_SetKey(hcryp, hcryp->Init.pKey);
579
580 /* Reset the CHMOD & MODE bits */
581 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
582
583 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
584 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
585
586 /* Enable CRYP */
587 __HAL_CRYP_ENABLE(hcryp);
588
589 /* Set the phase */
590 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
591 }
592
593 /* Write Cypher Data and Get Plain Data */
594 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
595 {
596 return HAL_TIMEOUT;
597 }
598
599 /* Change the CRYP state */
600 hcryp->State = HAL_CRYP_STATE_READY;
601
602 /* Process Unlocked */
603 __HAL_UNLOCK(hcryp);
604
605 /* Return function status */
606 return HAL_OK;
607 }
608 else
609 {
610 /* Release Lock */
611 __HAL_UNLOCK(hcryp);
612
613 /* Return function status */
614 return HAL_ERROR;
615 }
616 }
617
618 /**
619 * @brief Initializes the CRYP peripheral in AES ECB decryption mode
620 * then decrypted pCypherData. The cypher data are available in pPlainData
621 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
622 * the configuration information for CRYP module
623 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
624 * @param Size Length of the plaintext buffer, must be a multiple of 16.
625 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
626 * @param Timeout Specify Timeout value
627 * @retval HAL status
628 */
HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData,uint32_t Timeout)629 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
630 {
631 /* Process Locked */
632 __HAL_LOCK(hcryp);
633
634 /* Check that data aligned on u32 */
635 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
636 {
637 /* Process Locked */
638 __HAL_UNLOCK(hcryp);
639
640 /* Return function status */
641 return HAL_ERROR;
642 }
643
644 /* Check if HAL_CRYP_Init has been called */
645 if(hcryp->State != HAL_CRYP_STATE_RESET)
646 {
647 /* Change the CRYP state */
648 hcryp->State = HAL_CRYP_STATE_BUSY;
649
650 /* Check if initialization phase has already been performed */
651 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
652 {
653 /* Set the key */
654 CRYP_SetKey(hcryp, hcryp->Init.pKey);
655
656 /* Reset the CHMOD & MODE bits */
657 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
658
659 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
660 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
661
662 /* Set the Initialization Vector */
663 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
664
665 /* Enable CRYP */
666 __HAL_CRYP_ENABLE(hcryp);
667
668 /* Set the phase */
669 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
670 }
671
672 /* Write Cypher Data and Get Plain Data */
673 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
674 {
675 return HAL_TIMEOUT;
676 }
677
678 /* Change the CRYP state */
679 hcryp->State = HAL_CRYP_STATE_READY;
680
681 /* Process Unlocked */
682 __HAL_UNLOCK(hcryp);
683
684 /* Return function status */
685 return HAL_OK;
686 }
687 else
688 {
689 /* Release Lock */
690 __HAL_UNLOCK(hcryp);
691
692 /* Return function status */
693 return HAL_ERROR;
694 }
695 }
696
697 /**
698 * @brief Initializes the CRYP peripheral in AES CTR decryption mode
699 * then decrypted pCypherData. The cypher data are available in pPlainData
700 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
701 * the configuration information for CRYP module
702 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
703 * @param Size Length of the plaintext buffer, must be a multiple of 16.
704 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
705 * @param Timeout Specify Timeout value
706 * @retval HAL status
707 */
HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData,uint32_t Timeout)708 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
709 {
710 /* Process Locked */
711 __HAL_LOCK(hcryp);
712
713 /* Check that data aligned on u32 */
714 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
715 {
716 /* Process Locked */
717 __HAL_UNLOCK(hcryp);
718
719 /* Return function status */
720 return HAL_ERROR;
721 }
722
723 /* Check if initialization phase has already been performed */
724 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->Phase == HAL_CRYP_PHASE_READY))
725 {
726 /* Change the CRYP state */
727 hcryp->State = HAL_CRYP_STATE_BUSY;
728
729 /* Set the key */
730 CRYP_SetKey(hcryp, hcryp->Init.pKey);
731
732 /* Reset the CHMOD & MODE bits */
733 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
734
735 /* Set the CRYP peripheral in AES CTR decryption mode */
736 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
737
738 /* Set the Initialization Vector */
739 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
740
741 /* Enable CRYP */
742 __HAL_CRYP_ENABLE(hcryp);
743
744 /* Set the phase */
745 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
746 }
747
748 /* Write Cypher Data and Get Plain Data */
749 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
750 {
751 return HAL_TIMEOUT;
752 }
753
754 /* Change the CRYP state */
755 hcryp->State = HAL_CRYP_STATE_READY;
756
757 /* Process Unlocked */
758 __HAL_UNLOCK(hcryp);
759
760 /* Return function status */
761 return HAL_OK;
762 }
763
764 /**
765 * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
766 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
767 * the configuration information for CRYP module
768 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
769 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
770 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
771 * @retval HAL status
772 */
HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)773 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
774 {
775 uint32_t inputaddr = 0U;
776
777 /* Check that data aligned on u32 */
778 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
779 {
780 /* Process Locked */
781 __HAL_UNLOCK(hcryp);
782
783 /* Return function status */
784 return HAL_ERROR;
785 }
786
787 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
788 {
789 /* Process Locked */
790 __HAL_LOCK(hcryp);
791
792 /* Get the buffer addresses and sizes */
793 hcryp->CrypInCount = Size;
794 hcryp->pCrypInBuffPtr = pPlainData;
795 hcryp->pCrypOutBuffPtr = pCypherData;
796 hcryp->CrypOutCount = Size;
797
798 /* Change the CRYP state */
799 hcryp->State = HAL_CRYP_STATE_BUSY;
800
801 /* Check if initialization phase has already been performed */
802 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
803 {
804 /* Set the key */
805 CRYP_SetKey(hcryp, hcryp->Init.pKey);
806
807 /* Reset the CHMOD & MODE bits */
808 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
809
810 /* Set the CRYP peripheral in AES ECB mode */
811 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
812
813 /* Set the phase */
814 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
815 }
816
817 /* Enable Interrupts */
818 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
819
820 /* Enable CRYP */
821 __HAL_CRYP_ENABLE(hcryp);
822
823 /* Get the last input data address */
824 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
825
826 /* Write the Input block in the Data Input register */
827 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
828 inputaddr+=4U;
829 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
830 inputaddr+=4U;
831 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
832 inputaddr+=4U;
833 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
834 hcryp->pCrypInBuffPtr += 16U;
835 hcryp->CrypInCount -= 16U;
836
837 /* Return function status */
838 return HAL_OK;
839 }
840 else
841 {
842 /* Release Lock */
843 __HAL_UNLOCK(hcryp);
844
845 /* Return function status */
846 return HAL_ERROR;
847 }
848 }
849
850 /**
851 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
852 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
853 * the configuration information for CRYP module
854 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
855 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
856 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
857 * @retval HAL status
858 */
HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)859 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
860 {
861 uint32_t inputaddr = 0U;
862
863 /* Check that data aligned on u32 */
864 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
865 {
866 /* Process Locked */
867 __HAL_UNLOCK(hcryp);
868
869 /* Return function status */
870 return HAL_ERROR;
871 }
872
873 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
874 {
875 /* Process Locked */
876 __HAL_LOCK(hcryp);
877
878 /* Get the buffer addresses and sizes */
879 hcryp->CrypInCount = Size;
880 hcryp->pCrypInBuffPtr = pPlainData;
881 hcryp->pCrypOutBuffPtr = pCypherData;
882 hcryp->CrypOutCount = Size;
883
884 /* Change the CRYP state */
885 hcryp->State = HAL_CRYP_STATE_BUSY;
886
887 /* Check if initialization phase has already been performed */
888 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
889 {
890 /* Set the key */
891 CRYP_SetKey(hcryp, hcryp->Init.pKey);
892
893 /* Reset the CHMOD & MODE bits */
894 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
895
896 /* Set the CRYP peripheral in AES CBC mode */
897 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
898
899 /* Set the Initialization Vector */
900 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
901
902 /* Set the phase */
903 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
904 }
905
906 /* Enable Interrupts */
907 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
908
909 /* Enable CRYP */
910 __HAL_CRYP_ENABLE(hcryp);
911
912 /* Get the last input data address */
913 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
914
915 /* Write the Input block in the Data Input register */
916 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
917 inputaddr+=4U;
918 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
919 inputaddr+=4U;
920 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
921 inputaddr+=4U;
922 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
923 hcryp->pCrypInBuffPtr += 16U;
924 hcryp->CrypInCount -= 16U;
925
926 /* Return function status */
927 return HAL_OK;
928 }
929 else
930 {
931 /* Release Lock */
932 __HAL_UNLOCK(hcryp);
933
934 /* Return function status */
935 return HAL_ERROR;
936 }
937 }
938
939 /**
940 * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
941 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
942 * the configuration information for CRYP module
943 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
944 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
945 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
946 * @retval HAL status
947 */
HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)948 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
949 {
950 uint32_t inputaddr = 0U;
951
952 /* Check that data aligned on u32 */
953 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
954 {
955 /* Process Locked */
956 __HAL_UNLOCK(hcryp);
957
958 /* Return function status */
959 return HAL_ERROR;
960 }
961
962 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
963 {
964 /* Process Locked */
965 __HAL_LOCK(hcryp);
966
967 /* Get the buffer addresses and sizes */
968 hcryp->CrypInCount = Size;
969 hcryp->pCrypInBuffPtr = pPlainData;
970 hcryp->pCrypOutBuffPtr = pCypherData;
971 hcryp->CrypOutCount = Size;
972
973 /* Change the CRYP state */
974 hcryp->State = HAL_CRYP_STATE_BUSY;
975
976 /* Check if initialization phase has already been performed */
977 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
978 {
979 /* Set the key */
980 CRYP_SetKey(hcryp, hcryp->Init.pKey);
981
982 /* Reset the CHMOD & MODE bits */
983 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
984
985 /* Set the CRYP peripheral in AES CTR mode */
986 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
987
988 /* Set the Initialization Vector */
989 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
990
991 /* Set the phase */
992 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
993 }
994
995 /* Enable Interrupts */
996 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
997
998 /* Enable CRYP */
999 __HAL_CRYP_ENABLE(hcryp);
1000
1001 /* Get the last input data address */
1002 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1003
1004 /* Write the Input block in the Data Input register */
1005 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1006 inputaddr+=4U;
1007 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1008 inputaddr+=4U;
1009 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1010 inputaddr+=4U;
1011 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1012 hcryp->pCrypInBuffPtr += 16U;
1013 hcryp->CrypInCount -= 16U;
1014
1015 /* Return function status */
1016 return HAL_OK;
1017 }
1018 else
1019 {
1020 /* Release Lock */
1021 __HAL_UNLOCK(hcryp);
1022
1023 /* Return function status */
1024 return HAL_ERROR;
1025 }
1026 }
1027
1028 /**
1029 * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
1030 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1031 * the configuration information for CRYP module
1032 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
1033 * @param Size Length of the plaintext buffer, must be a multiple of 16.
1034 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1035 * @retval HAL status
1036 */
HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1037 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1038 {
1039 uint32_t inputaddr = 0U;
1040
1041 /* Check that data aligned on u32 */
1042 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
1043 {
1044 /* Process Locked */
1045 __HAL_UNLOCK(hcryp);
1046
1047 /* Return function status */
1048 return HAL_ERROR;
1049 }
1050
1051 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1052 {
1053 /* Process Locked */
1054 __HAL_LOCK(hcryp);
1055
1056 /* Get the buffer addresses and sizes */
1057 hcryp->CrypInCount = Size;
1058 hcryp->pCrypInBuffPtr = pCypherData;
1059 hcryp->pCrypOutBuffPtr = pPlainData;
1060 hcryp->CrypOutCount = Size;
1061
1062 /* Change the CRYP state */
1063 hcryp->State = HAL_CRYP_STATE_BUSY;
1064
1065 /* Check if initialization phase has already been performed */
1066 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1067 {
1068 /* Set the key */
1069 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1070
1071 /* Reset the CHMOD & MODE bits */
1072 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
1073
1074 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
1075 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
1076
1077 /* Set the phase */
1078 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1079 }
1080
1081 /* Enable Interrupts */
1082 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
1083
1084 /* Enable CRYP */
1085 __HAL_CRYP_ENABLE(hcryp);
1086
1087 /* Get the last input data address */
1088 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1089
1090 /* Write the Input block in the Data Input register */
1091 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1092 inputaddr+=4U;
1093 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1094 inputaddr+=4U;
1095 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1096 inputaddr+=4U;
1097 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1098 hcryp->pCrypInBuffPtr += 16U;
1099 hcryp->CrypInCount -= 16U;
1100
1101 /* Return function status */
1102 return HAL_OK;
1103 }
1104 else
1105 {
1106 /* Release Lock */
1107 __HAL_UNLOCK(hcryp);
1108
1109 /* Return function status */
1110 return HAL_ERROR;
1111 }
1112 }
1113
1114 /**
1115 * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
1116 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1117 * the configuration information for CRYP module
1118 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
1119 * @param Size Length of the plaintext buffer, must be a multiple of 16
1120 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1121 * @retval HAL status
1122 */
HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1123 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1124 {
1125 uint32_t inputaddr = 0U;
1126
1127 /* Check that data aligned on u32 */
1128 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
1129 {
1130 /* Process Locked */
1131 __HAL_UNLOCK(hcryp);
1132
1133 /* Return function status */
1134 return HAL_ERROR;
1135 }
1136
1137 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1138 {
1139 /* Process Locked */
1140 __HAL_LOCK(hcryp);
1141
1142 /* Get the buffer addresses and sizes */
1143 hcryp->CrypInCount = Size;
1144 hcryp->pCrypInBuffPtr = pCypherData;
1145 hcryp->pCrypOutBuffPtr = pPlainData;
1146 hcryp->CrypOutCount = Size;
1147
1148 /* Change the CRYP state */
1149 hcryp->State = HAL_CRYP_STATE_BUSY;
1150
1151 /* Check if initialization phase has already been performed */
1152 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1153 {
1154 /* Set the key */
1155 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1156
1157 /* Reset the CHMOD & MODE bits */
1158 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
1159
1160 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
1161 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
1162
1163 /* Set the Initialization Vector */
1164 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1165
1166 /* Set the phase */
1167 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1168 }
1169
1170 /* Enable Interrupts */
1171 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
1172
1173 /* Enable CRYP */
1174 __HAL_CRYP_ENABLE(hcryp);
1175
1176 /* Get the last input data address */
1177 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1178
1179 /* Write the Input block in the Data Input register */
1180 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1181 inputaddr+=4U;
1182 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1183 inputaddr+=4U;
1184 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1185 inputaddr+=4U;
1186 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1187 hcryp->pCrypInBuffPtr += 16U;
1188 hcryp->CrypInCount -= 16U;
1189
1190 /* Return function status */
1191 return HAL_OK;
1192 }
1193 else
1194 {
1195 /* Release Lock */
1196 __HAL_UNLOCK(hcryp);
1197
1198 /* Return function status */
1199 return HAL_ERROR;
1200 }
1201 }
1202
1203 /**
1204 * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
1205 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1206 * the configuration information for CRYP module
1207 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
1208 * @param Size Length of the plaintext buffer, must be a multiple of 16
1209 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1210 * @retval HAL status
1211 */
HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1212 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1213 {
1214 uint32_t inputaddr = 0U;
1215
1216 /* Check that data aligned on u32 */
1217 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
1218 {
1219 /* Process Locked */
1220 __HAL_UNLOCK(hcryp);
1221
1222 /* Return function status */
1223 return HAL_ERROR;
1224 }
1225
1226 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1227 {
1228 /* Process Locked */
1229 __HAL_LOCK(hcryp);
1230
1231 /* Get the buffer addresses and sizes */
1232 hcryp->CrypInCount = Size;
1233 hcryp->pCrypInBuffPtr = pCypherData;
1234 hcryp->pCrypOutBuffPtr = pPlainData;
1235 hcryp->CrypOutCount = Size;
1236
1237 /* Change the CRYP state */
1238 hcryp->State = HAL_CRYP_STATE_BUSY;
1239
1240 /* Check if initialization phase has already been performed */
1241 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1242 {
1243 /* Set the key */
1244 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1245
1246 /* Reset the CHMOD & MODE bits */
1247 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
1248
1249 /* Set the CRYP peripheral in AES CTR decryption mode */
1250 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
1251
1252 /* Set the Initialization Vector */
1253 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1254
1255 /* Set the phase */
1256 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1257 }
1258
1259 /* Enable Interrupts */
1260 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
1261
1262 /* Enable CRYP */
1263 __HAL_CRYP_ENABLE(hcryp);
1264
1265 /* Get the last input data address */
1266 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1267
1268 /* Write the Input block in the Data Input register */
1269 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1270 inputaddr+=4U;
1271 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1272 inputaddr+=4U;
1273 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1274 inputaddr+=4U;
1275 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1276 hcryp->pCrypInBuffPtr += 16U;
1277 hcryp->CrypInCount -= 16U;
1278
1279 /* Return function status */
1280 return HAL_OK;
1281 }
1282 else
1283 {
1284 /* Release Lock */
1285 __HAL_UNLOCK(hcryp);
1286
1287 /* Return function status */
1288 return HAL_ERROR;
1289 }
1290 }
1291
1292 /**
1293 * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
1294 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1295 * the configuration information for CRYP module
1296 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1297 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
1298 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
1299 * @retval HAL status
1300 */
HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)1301 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1302 {
1303 uint32_t inputaddr = 0U, outputaddr = 0U;
1304
1305 /* Check that data aligned on u32 */
1306 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
1307 {
1308 /* Process Locked */
1309 __HAL_UNLOCK(hcryp);
1310
1311 /* Return function status */
1312 return HAL_ERROR;
1313 }
1314
1315 /* Check if HAL_CRYP_Init has been called */
1316 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1317 {
1318 /* Process Locked */
1319 __HAL_LOCK(hcryp);
1320
1321 inputaddr = (uint32_t)pPlainData;
1322 outputaddr = (uint32_t)pCypherData;
1323
1324 /* Change the CRYP state */
1325 hcryp->State = HAL_CRYP_STATE_BUSY;
1326
1327 /* Check if initialization phase has already been performed */
1328 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1329 {
1330 /* Set the key */
1331 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1332
1333 /* Set the CRYP peripheral in AES ECB mode */
1334 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
1335
1336 /* Set the phase */
1337 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1338 }
1339 /* Set the input and output addresses and start DMA transfer */
1340 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1341
1342 /* Process Unlocked */
1343 __HAL_UNLOCK(hcryp);
1344
1345 /* Return function status */
1346 return HAL_OK;
1347 }
1348 else
1349 {
1350 /* Release Lock */
1351 __HAL_UNLOCK(hcryp);
1352
1353 return HAL_ERROR;
1354 }
1355 }
1356
1357 /**
1358 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
1359 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1360 * the configuration information for CRYP module
1361 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1362 * @param Size Length of the plaintext buffer, must be a multiple of 16.
1363 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
1364 * @retval HAL status
1365 */
HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)1366 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1367 {
1368 uint32_t inputaddr = 0U, outputaddr = 0U;
1369
1370 /* Check that data aligned on u32 */
1371 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
1372 {
1373 /* Process Locked */
1374 __HAL_UNLOCK(hcryp);
1375
1376 /* Return function status */
1377 return HAL_ERROR;
1378 }
1379
1380 /* Check if HAL_CRYP_Init has been called */
1381 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1382 {
1383 /* Process Locked */
1384 __HAL_LOCK(hcryp);
1385
1386 inputaddr = (uint32_t)pPlainData;
1387 outputaddr = (uint32_t)pCypherData;
1388
1389 /* Change the CRYP state */
1390 hcryp->State = HAL_CRYP_STATE_BUSY;
1391
1392 /* Check if initialization phase has already been performed */
1393 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1394 {
1395 /* Set the key */
1396 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1397
1398 /* Set the CRYP peripheral in AES CBC mode */
1399 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
1400
1401 /* Set the Initialization Vector */
1402 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1403
1404 /* Set the phase */
1405 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1406 }
1407 /* Set the input and output addresses and start DMA transfer */
1408 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1409
1410 /* Process Unlocked */
1411 __HAL_UNLOCK(hcryp);
1412
1413 /* Return function status */
1414 return HAL_OK;
1415 }
1416 else
1417 {
1418 /* Release Lock */
1419 __HAL_UNLOCK(hcryp);
1420
1421 return HAL_ERROR;
1422 }
1423 }
1424
1425 /**
1426 * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
1427 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1428 * the configuration information for CRYP module
1429 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1430 * @param Size Length of the plaintext buffer, must be a multiple of 16.
1431 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
1432 * @retval HAL status
1433 */
HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)1434 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1435 {
1436 uint32_t inputaddr = 0U, outputaddr = 0U;
1437
1438 /* Check that data aligned on u32 */
1439 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
1440 {
1441 /* Process Locked */
1442 __HAL_UNLOCK(hcryp);
1443
1444 /* Return function status */
1445 return HAL_ERROR;
1446 }
1447
1448 /* Check if HAL_CRYP_Init has been called */
1449 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1450 {
1451 /* Process Locked */
1452 __HAL_LOCK(hcryp);
1453
1454 inputaddr = (uint32_t)pPlainData;
1455 outputaddr = (uint32_t)pCypherData;
1456
1457 /* Change the CRYP state */
1458 hcryp->State = HAL_CRYP_STATE_BUSY;
1459
1460 /* Check if initialization phase has already been performed */
1461 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1462 {
1463 /* Set the key */
1464 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1465
1466 /* Set the CRYP peripheral in AES CTR mode */
1467 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
1468
1469 /* Set the Initialization Vector */
1470 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1471
1472 /* Set the phase */
1473 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1474 }
1475
1476 /* Set the input and output addresses and start DMA transfer */
1477 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1478
1479 /* Process Unlocked */
1480 __HAL_UNLOCK(hcryp);
1481
1482 /* Return function status */
1483 return HAL_OK;
1484 }
1485 else
1486 {
1487 /* Release Lock */
1488 __HAL_UNLOCK(hcryp);
1489
1490 return HAL_ERROR;
1491 }
1492 }
1493
1494 /**
1495 * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
1496 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1497 * the configuration information for CRYP module
1498 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
1499 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
1500 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1501 * @retval HAL status
1502 */
HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1503 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1504 {
1505 uint32_t inputaddr = 0U, outputaddr = 0U;
1506
1507 /* Check that data aligned on u32 */
1508 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
1509 {
1510 /* Process Locked */
1511 __HAL_UNLOCK(hcryp);
1512
1513 /* Return function status */
1514 return HAL_ERROR;
1515 }
1516
1517 /* Check if HAL_CRYP_Init has been called */
1518 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1519 {
1520 /* Process Locked */
1521 __HAL_LOCK(hcryp);
1522
1523 inputaddr = (uint32_t)pCypherData;
1524 outputaddr = (uint32_t)pPlainData;
1525
1526 /* Change the CRYP state */
1527 hcryp->State = HAL_CRYP_STATE_BUSY;
1528
1529 /* Check if initialization phase has already been performed */
1530 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1531 {
1532 /* Set the key */
1533 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1534
1535 /* Reset the CHMOD & MODE bits */
1536 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
1537
1538 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
1539 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
1540
1541 /* Set the phase */
1542 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1543 }
1544
1545 /* Set the input and output addresses and start DMA transfer */
1546 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1547
1548 /* Process Unlocked */
1549 __HAL_UNLOCK(hcryp);
1550
1551 /* Return function status */
1552 return HAL_OK;
1553 }
1554 else
1555 {
1556 /* Release Lock */
1557 __HAL_UNLOCK(hcryp);
1558
1559 return HAL_ERROR;
1560 }
1561 }
1562
1563 /**
1564 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
1565 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1566 * the configuration information for CRYP module
1567 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
1568 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
1569 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1570 * @retval HAL status
1571 */
HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1572 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1573 {
1574 uint32_t inputaddr = 0U, outputaddr = 0U;
1575
1576 /* Check that data aligned on u32 */
1577 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
1578 {
1579 /* Process Locked */
1580 __HAL_UNLOCK(hcryp);
1581
1582 /* Return function status */
1583 return HAL_ERROR;
1584 }
1585
1586 /* Check if HAL_CRYP_Init has been called */
1587 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1588 {
1589 /* Process Locked */
1590 __HAL_LOCK(hcryp);
1591
1592 inputaddr = (uint32_t)pCypherData;
1593 outputaddr = (uint32_t)pPlainData;
1594
1595 /* Change the CRYP state */
1596 hcryp->State = HAL_CRYP_STATE_BUSY;
1597
1598 /* Check if initialization phase has already been performed */
1599 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1600 {
1601 /* Set the key */
1602 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1603
1604 /* Reset the CHMOD & MODE bits */
1605 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
1606
1607 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
1608 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
1609
1610 /* Set the Initialization Vector */
1611 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1612
1613 /* Set the phase */
1614 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1615 }
1616
1617 /* Set the input and output addresses and start DMA transfer */
1618 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1619
1620 /* Process Unlocked */
1621 __HAL_UNLOCK(hcryp);
1622
1623 /* Return function status */
1624 return HAL_OK;
1625 }
1626 else
1627 {
1628 /* Release Lock */
1629 __HAL_UNLOCK(hcryp);
1630
1631 return HAL_ERROR;
1632 }
1633 }
1634
1635 /**
1636 * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
1637 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1638 * the configuration information for CRYP module
1639 * @param pCypherData Pointer to the ciphertext buffer (aligned on u32)
1640 * @param Size Length of the plaintext buffer, must be a multiple of 16
1641 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1642 * @retval HAL status
1643 */
HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1644 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1645 {
1646 uint32_t inputaddr = 0U, outputaddr = 0U;
1647
1648 /* Check that data aligned on u32 */
1649 if((((uint32_t)pPlainData & 0x00000003UL) != 0U) || (((uint32_t)pCypherData & 0x00000003UL) != 0U) || ((Size & 0x000FU) != 0U))
1650 {
1651 /* Process Locked */
1652 __HAL_UNLOCK(hcryp);
1653
1654 /* Return function status */
1655 return HAL_ERROR;
1656 }
1657
1658 /* Check if HAL_CRYP_Init has been called */
1659 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1660 {
1661 /* Process Locked */
1662 __HAL_LOCK(hcryp);
1663
1664 inputaddr = (uint32_t)pCypherData;
1665 outputaddr = (uint32_t)pPlainData;
1666
1667 /* Change the CRYP state */
1668 hcryp->State = HAL_CRYP_STATE_BUSY;
1669
1670 /* Check if initialization phase has already been performed */
1671 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1672 {
1673 /* Set the key */
1674 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1675
1676 /* Set the CRYP peripheral in AES CTR mode */
1677 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
1678
1679 /* Set the Initialization Vector */
1680 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1681
1682 /* Set the phase */
1683 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1684 }
1685
1686 /* Set the input and output addresses and start DMA transfer */
1687 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1688
1689 /* Process Unlocked */
1690 __HAL_UNLOCK(hcryp);
1691
1692 /* Return function status */
1693 return HAL_OK;
1694 }
1695 else
1696 {
1697 /* Release Lock */
1698 __HAL_UNLOCK(hcryp);
1699
1700 return HAL_ERROR;
1701 }
1702 }
1703
1704 /**
1705 * @}
1706 */
1707
1708 /** @addtogroup CRYP_Exported_Functions_Group3
1709 * @brief DMA callback functions.
1710 *
1711 @verbatim
1712 ==============================================================================
1713 ##### DMA callback functions #####
1714 ==============================================================================
1715 [..] This section provides DMA callback functions:
1716 (+) DMA Input data transfer complete
1717 (+) DMA Output data transfer complete
1718 (+) DMA error
1719
1720 @endverbatim
1721 * @{
1722 */
1723
1724 /**
1725 * @brief CRYP error callback.
1726 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1727 * the configuration information for CRYP module
1728 * @retval None
1729 */
HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef * hcryp)1730 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
1731 {
1732 /* Prevent unused argument(s) compilation warning */
1733 UNUSED(hcryp);
1734
1735 /* NOTE : This function should not be modified; when the callback is needed,
1736 the HAL_CRYP_ErrorCallback can be implemented in the user file
1737 */
1738 }
1739
1740 /**
1741 * @brief Input transfer completed callback.
1742 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1743 * the configuration information for CRYP module
1744 * @retval None
1745 */
HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef * hcryp)1746 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
1747 {
1748 /* Prevent unused argument(s) compilation warning */
1749 UNUSED(hcryp);
1750
1751 /* NOTE : This function should not be modified; when the callback is needed,
1752 the HAL_CRYP_InCpltCallback can be implemented in the user file
1753 */
1754 }
1755
1756 /**
1757 * @brief Output transfer completed callback.
1758 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1759 * the configuration information for CRYP module
1760 * @retval None
1761 */
HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef * hcryp)1762 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
1763 {
1764 /* Prevent unused argument(s) compilation warning */
1765 UNUSED(hcryp);
1766
1767 /* NOTE : This function should not be modified; when the callback is needed,
1768 the HAL_CRYP_OutCpltCallback can be implemented in the user file
1769 */
1770 }
1771
1772 /**
1773 * @}
1774 */
1775
1776 /** @addtogroup CRYP_Exported_Functions_Group4
1777 * @brief CRYP IRQ handler.
1778 *
1779 @verbatim
1780 ==============================================================================
1781 ##### CRYP IRQ handler management #####
1782 ==============================================================================
1783 [..] This section provides CRYP IRQ handler function.
1784
1785 @endverbatim
1786 * @{
1787 */
1788
1789 /**
1790 * @brief This function handles CRYP interrupt request.
1791 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1792 * the configuration information for CRYP module
1793 * @retval None
1794 */
HAL_CRYP_IRQHandler(CRYP_HandleTypeDef * hcryp)1795 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
1796 {
1797 /* Check if error occurred*/
1798 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERR) != RESET)
1799 {
1800 if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_RDERR) != RESET)
1801 {
1802 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_RDERR);
1803 }
1804
1805 if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_WRERR) != RESET)
1806 {
1807 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_WRERR);
1808 }
1809
1810 if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_CCF) != RESET)
1811 {
1812 __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CLEARFLAG_CCF);
1813 }
1814
1815 hcryp->State= HAL_CRYP_STATE_ERROR;
1816 /* Disable Computation Complete Interrupt */
1817 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC);
1818 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR);
1819
1820 HAL_CRYP_ErrorCallback(hcryp);
1821
1822 /* Process Unlocked */
1823 __HAL_UNLOCK(hcryp);
1824
1825 return;
1826 }
1827
1828 /* Check if computation complete interrupt was enabled*/
1829 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CC) != RESET)
1830 {
1831 /* Clear CCF Flag */
1832 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
1833
1834 CRYP_EncryptDecrypt_IT(hcryp);
1835 }
1836 }
1837
1838 /**
1839 * @}
1840 */
1841
1842 /** @addtogroup CRYP_Exported_Functions_Group5
1843 * @brief Peripheral State functions.
1844 *
1845 @verbatim
1846 ==============================================================================
1847 ##### Peripheral State functions #####
1848 ==============================================================================
1849 [..]
1850 This subsection permits to get in run-time the status of the peripheral.
1851
1852 @endverbatim
1853 * @{
1854 */
1855
1856 /**
1857 * @brief Returns the CRYP state.
1858 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1859 * the configuration information for CRYP module
1860 * @retval HAL state
1861 */
HAL_CRYP_GetState(CRYP_HandleTypeDef * hcryp)1862 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
1863 {
1864 return hcryp->State;
1865 }
1866
1867 /**
1868 * @}
1869 */
1870
1871 /**
1872 * @}
1873 */
1874
1875 /** @addtogroup CRYP_Private
1876 * @{
1877 */
1878
1879 /**
1880 * @brief IT function called under interruption context to continue encryption or decryption
1881 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1882 * the configuration information for CRYP module
1883 * @retval HAL status
1884 */
CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef * hcryp)1885 static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp)
1886 {
1887 uint32_t inputaddr = 0U, outputaddr = 0U;
1888
1889 /* Get the last Output data address */
1890 outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
1891
1892 /* Read the Output block from the Output Register */
1893 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
1894 outputaddr+=4U;
1895 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
1896 outputaddr+=4U;
1897 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
1898 outputaddr+=4U;
1899 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
1900
1901 hcryp->pCrypOutBuffPtr += 16U;
1902 hcryp->CrypOutCount -= 16U;
1903
1904 /* Check if all input text is encrypted or decrypted */
1905 if(hcryp->CrypOutCount == 0U)
1906 {
1907 /* Disable Computation Complete Interrupt */
1908 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC);
1909 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR);
1910
1911 /* Process Unlocked */
1912 __HAL_UNLOCK(hcryp);
1913
1914 /* Change the CRYP state */
1915 hcryp->State = HAL_CRYP_STATE_READY;
1916
1917 /* Call computation complete callback */
1918 HAL_CRYPEx_ComputationCpltCallback(hcryp);
1919 }
1920 else /* Process the rest of input text */
1921 {
1922 /* Get the last Input data address */
1923 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1924
1925 /* Write the Input block in the Data Input register */
1926 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1927 inputaddr+=4U;
1928 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1929 inputaddr+=4U;
1930 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1931 inputaddr+=4U;
1932 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1933 hcryp->pCrypInBuffPtr += 16U;
1934 hcryp->CrypInCount -= 16U;
1935 }
1936 return HAL_OK;
1937 }
1938 /**
1939 * @brief DMA CRYP Input Data process complete callback.
1940 * @param hdma DMA handle
1941 * @retval None
1942 */
CRYP_DMAInCplt(DMA_HandleTypeDef * hdma)1943 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
1944 {
1945 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1946
1947 /* Disable the DMA transfer for input request */
1948 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
1949
1950 /* Call input data transfer complete callback */
1951 HAL_CRYP_InCpltCallback(hcryp);
1952 }
1953
1954 /**
1955 * @brief DMA CRYP Output Data process complete callback.
1956 * @param hdma DMA handle
1957 * @retval None
1958 */
CRYP_DMAOutCplt(DMA_HandleTypeDef * hdma)1959 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
1960 {
1961 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1962
1963 /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit
1964 in the DMACR register */
1965 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
1966
1967 /* Clear CCF Flag */
1968 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
1969
1970 /* Disable CRYP */
1971 __HAL_CRYP_DISABLE(hcryp);
1972
1973 /* Change the CRYP state to ready */
1974 hcryp->State = HAL_CRYP_STATE_READY;
1975
1976 /* Call output data transfer complete callback */
1977 HAL_CRYP_OutCpltCallback(hcryp);
1978 }
1979
1980 /**
1981 * @brief DMA CRYP communication error callback.
1982 * @param hdma DMA handle
1983 * @retval None
1984 */
CRYP_DMAError(DMA_HandleTypeDef * hdma)1985 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
1986 {
1987 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1988 hcryp->State= HAL_CRYP_STATE_ERROR;
1989 HAL_CRYP_ErrorCallback(hcryp);
1990 }
1991
1992 /**
1993 * @brief Writes the Key in Key registers.
1994 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1995 * the configuration information for CRYP module
1996 * @param Key Pointer to Key buffer
1997 * @note Key must be written as little endian.
1998 * If Key pointer points at address n,
1999 * n[15:0] contains key[96:127],
2000 * (n+4)[15:0] contains key[64:95],
2001 * (n+8)[15:0] contains key[32:63] and
2002 * (n+12)[15:0] contains key[0:31]
2003 * @retval None
2004 */
CRYP_SetKey(CRYP_HandleTypeDef * hcryp,uint8_t * Key)2005 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key)
2006 {
2007 uint32_t keyaddr = (uint32_t)Key;
2008
2009 hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
2010 keyaddr+=4U;
2011 hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
2012 keyaddr+=4U;
2013 hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
2014 keyaddr+=4U;
2015 hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
2016 }
2017
2018 /**
2019 * @brief Writes the InitVector/InitCounter in IV registers.
2020 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
2021 * the configuration information for CRYP module
2022 * @param InitVector Pointer to InitVector/InitCounter buffer
2023 * @note Init Vector must be written as little endian.
2024 * If Init Vector pointer points at address n,
2025 * n[15:0] contains Vector[96:127],
2026 * (n+4)[15:0] contains Vector[64:95],
2027 * (n+8)[15:0] contains Vector[32:63] and
2028 * (n+12)[15:0] contains Vector[0:31]
2029 * @retval None
2030 */
CRYP_SetInitVector(CRYP_HandleTypeDef * hcryp,uint8_t * InitVector)2031 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
2032 {
2033 uint32_t ivaddr = (uint32_t)InitVector;
2034
2035 hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
2036 ivaddr+=4U;
2037 hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
2038 ivaddr+=4U;
2039 hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
2040 ivaddr+=4U;
2041 hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
2042 }
2043
2044 /**
2045 * @brief Process Data: Writes Input data in polling mode and reads the output data
2046 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
2047 * the configuration information for CRYP module
2048 * @param Input Pointer to the Input buffer
2049 * @param Ilength Length of the Input buffer, must be a multiple of 16.
2050 * @param Output Pointer to the returned buffer
2051 * @param Timeout Specify Timeout value
2052 * @retval None
2053 */
CRYP_ProcessData(CRYP_HandleTypeDef * hcryp,uint8_t * Input,uint16_t Ilength,uint8_t * Output,uint32_t Timeout)2054 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
2055 {
2056 uint32_t tickstart = 0U;
2057
2058 uint32_t index = 0U;
2059 uint32_t inputaddr = (uint32_t)Input;
2060 uint32_t outputaddr = (uint32_t)Output;
2061
2062 for(index=0U; (index < Ilength); index += 16U)
2063 {
2064 /* Write the Input block in the Data Input register */
2065 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
2066 inputaddr+=4U;
2067 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
2068 inputaddr+=4U;
2069 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
2070 inputaddr+=4U;
2071 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
2072 inputaddr+=4U;
2073
2074 /* Get timeout */
2075 tickstart = HAL_GetTick();
2076
2077 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
2078 {
2079 /* Check for the Timeout */
2080 if(Timeout != HAL_MAX_DELAY)
2081 {
2082 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
2083 {
2084 /* Change state */
2085 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
2086
2087 /* Process Unlocked */
2088 __HAL_UNLOCK(hcryp);
2089
2090 return HAL_TIMEOUT;
2091 }
2092 }
2093 }
2094 /* Clear CCF Flag */
2095 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
2096
2097 /* Read the Output block from the Data Output Register */
2098 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
2099 outputaddr+=4U;
2100 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
2101 outputaddr+=4U;
2102 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
2103 outputaddr+=4U;
2104 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
2105 outputaddr+=4U;
2106 }
2107 /* Return function status */
2108 return HAL_OK;
2109 }
2110
2111 /**
2112 * @brief Set the DMA configuration and start the DMA transfer
2113 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
2114 * the configuration information for CRYP module
2115 * @param inputaddr address of the Input buffer
2116 * @param Size Size of the Input buffer, must be a multiple of 16.
2117 * @param outputaddr address of the Output buffer
2118 * @retval None
2119 */
CRYP_SetDMAConfig(CRYP_HandleTypeDef * hcryp,uint32_t inputaddr,uint16_t Size,uint32_t outputaddr)2120 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
2121 {
2122 /* Set the CRYP DMA transfer complete callback */
2123 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
2124 /* Set the DMA error callback */
2125 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
2126
2127 /* Set the CRYP DMA transfer complete callback */
2128 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
2129 /* Set the DMA error callback */
2130 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
2131
2132 /* Enable the DMA In DMA Stream */
2133 HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
2134
2135 /* Enable the DMA Out DMA Stream */
2136 HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
2137
2138 /* Enable In and Out DMA requests */
2139 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
2140
2141 /* Enable CRYP */
2142 __HAL_CRYP_ENABLE(hcryp);
2143 }
2144
2145 /**
2146 * @}
2147 */
2148
2149 /**
2150 * @}
2151 */
2152
2153 /**
2154 * @}
2155 */
2156
2157 #endif /* HAL_CRYP_MODULE_ENABLED */
2158 #endif /* STM32L021xx || STM32L041xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
2159
